R1LP0108E Series 1Mb Advanced LPSRAM (128k word x 8bit) R10DS0151EJ0100 Rev.1.00 2013.6.21 Description The R1LP0108E Series is a family of low voltage 1-Mbit static RAMs organized as 131,072-word by 8-bit, fabricated by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1LP0108E Series has realized higher density, higher performance and low power consumption. The R1LP0108E Series is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. It has been packaged in 32-pin SOP,32-pin TSOP and 32-pin sTSOP. Features Single 4.5~5.5V power supply Small stand-by current: 0.6µA (5.0V, typical) No clocks, No refresh All inputs and outputs are TTL compatible. Easy memory expansion by CS1# and CS2 Common Data I/O Three-state outputs: OR-tie Capability OE# prevents data contention on the I/O bus R10DS0151EJ0100 Rev.1.00 2013.6.21 Page 1 of 12 R1LP0108E Series Ordering Information Orderable Part Name R1LP0108ESN-5SR#B* R1LP0108ESN-5SI#B* R1LP0108ESN-7SR#B* R1LP0108ESN-7SI#B* R1LP0108ESN-5SR#S* R1LP0108ESN-5SI#S* R1LP0108ESN-7SR#S* R1LP0108ESN-7SI#S* R1LP0108ESA-5SR#B* R1LP0108ESA-5SI#B* R1LP0108ESA-7SR#B* R1LP0108ESA-7SI#B* R1LP0108ESA-5SR#S* R1LP0108ESA-5SI#S* R1LP0108ESA-7SR#S* R1LP0108ESA-7SI#S* R1LP0108ESF-5SR#B* R1LP0108ESF-5SI#B* R1LP0108ESF-7SR#B* R1LP0108ESF-7SI#B* R1LP0108ESF-5SR#S* R1LP0108ESF-5SI#S* R1LP0108ESF-7SR#S* R1LP0108ESF-7SI#S* Access time 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns R10DS0151EJ0100 Rev.1.00 2013.6.21 Temperature Range Package Shipping Container Quantity Tube Max. 25pcs/Tube Max. 225pcs/Inner Bag Max. 900pcs/Inner Box Embossed tape 1000pcs/Reel Tray Max. 234pcs/Tray Max. 1872pcs/Inner Box Embossed tape 1000pcs/Reel Tray Max. 156pcs/Tray Max. 1248pcs/Inner Box Embossed tape 1000pcs/Reel 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 525-mil 32-pin plastic SOP PRSP0032DF-A (32P2S-A) 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 8mm×13.4mm 32-pin plastic sTSOP (normal-bend type) 0 ~ +70°C -40 ~ +85°C PTSA0032KB-A (32P3K-B) 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 8mm×20mm 32-pin plastic TSOP (normal-bend type) 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C PTSA0032KA-A (32P3H-E) -40 ~ +85°C Page 2 of 12 R1LP0108E Series Pin Arrangement NC A16 A14 A12 A7 A6 A5 A4 32 Vcc 2 31 A15 3 30 CS2 4 29 WE# 5 28 A13 6 27 A8 7 26 A9 25 A11 9 24 OE# 10 23 A10 11 22 CS1# 12 21 DQ7 13 20 DQ6 14 19 DQ5 15 18 DQ4 16 17 DQ3 8 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND R10DS0151EJ0100 Rev.1.00 2013.6.21 1 32-pin SOP A11 1 32 OE# A9 2 31 A10 A8 3 30 CS1# A13 4 29 DQ7 WE# 5 28 DQ6 CS2 6 27 DQ5 A15 7 26 DQ4 Vcc 8 25 DQ3 NC 9 24 GND A16 10 23 DQ2 A14 11 22 DQ1 A12 12 21 DQ0 A7 13 20 A0 A6 14 19 A1 A5 15 18 A2 A4 16 17 A3 32-pin sTSOP A11 1 32 OE# A9 2 31 A10 A8 3 30 CS1# A13 4 29 DQ7 WE# 5 28 DQ6 CS2 6 27 DQ5 A15 7 26 DQ4 Vcc 8 25 DQ3 NC 9 24 GND A16 10 23 DQ2 A14 11 22 DQ1 A12 12 21 DQ0 A7 13 20 A0 A6 14 19 A1 A5 15 18 A2 A4 16 17 A3 32-pin TSOP Page 3 of 12 R1LP0108E Series Pin Description Pin name Function Vcc Power supply Vss A0 to A16 DQ0 to DQ7 CS1# CS2 WE# OE# NC Ground Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Non connection Block Diagram A0 A1 ADDRESS ROW MEMORY ARRAY BUFFER DECODER 128k-word x8-bit A16 DQ0 DQ DQ1 BUFFER SENSE / WRITE AMPLIFIER DQ7 COLUMN DECODER CLOCK GENERATOR WE# Vcc Vss CS1# CS2 OE# R10DS0151EJ0100 Rev.1.00 2013.6.21 Page 4 of 12 R1LP0108E Series Operation Table CS1# CS2 WE# OE# DQ0~7 Operation X L X X High-Z Stand-by H X X X High-Z Stand-by L H L X Din Write L H H L Dout Read L H H H High-Z Output disable Note 1. H: VIH L:VIL X: VIH or VIL Absolute Maximum Parameter Power supply voltage relative to Vss Terminal voltage on any pin relative to Vss Power dissipation Operation temperature Storage temperature range Storage temperature range under bias Note Symbol Vcc VT PT Topr*3 Value -0.3 to +7 -0.3*1 to Vcc+0.3*2 0.7 R Ver. I Ver. Tstg Tbias*3 0 to +70 -40 to +85 -65 to 150 R Ver. I Ver. unit V V W °C °C 0 to +70 -40 to +85 °C 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Maximum voltage is +7V. 3. Ambient temperature range depends on R/I-version. Please see table on page 1. R10DS0151EJ0100 Rev.1.00 2013.6.21 Page 5 of 12 R1LP0108E Series DC Operating Conditions Parameter Symbol Min. Typ. Max. Unit Vcc 4.5 5.0 5.5 V Supply voltage Note Vss 0 0 0 V Input high voltage VIH 2.2 - Vcc+0.3 V Input low voltage VIL -0.3 - 0.8 V 1 0 - +70 °C 2 -40 - +85 °C 2 Ambient temperature range Note R Ver. Ta I Ver. 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Ambient temperature range depends on R/I-version. Please see table on page 1. DC Characteristics Parameter Input leakage current Output leakage current Average operating current Symbol Min. Typ. Max. Unit | ILI | - - 1 A | ILO | - - 1 A ICC1 - 25 35 mA ICC2 - 2 5 mA ISB - - 3 mA - 0.6*1 2 A ~+25°C - - 3 A ~+40°C - - 8 A ~+70°C - - 10 A ~+85°C VOH 2.4 - - V IOH = -1mA VOH2 Vcc - 0.5 - - V IOH = -0.1mA VOL - - 0.4 V IOL = 2mA Standby current Standby current Test conditions Vin = Vss to Vcc CS1# =VIH or CS2 =VIL or OE# =VIH, VI/O =Vss to Vcc Min. cycle, duty =100%, II/O = 0mA CS1# =VIL, CS2 =VIH, Others = VIH/VIL Cycle =1s, duty =100%, II/O = 0mA CS1# ≤ 0.2V, CS2 ≥ Vcc-0.2V, VIH ≥ Vcc-0.2V, VIL ≤ 0.2V “CS2 =VIL” or “CS2 = VIH and CS1# =VIH”, Others = Vss to Vcc ISB1 Output high voltage Output low voltage Note Vin = Vss to Vcc (1) CS2 ≤ 0.2 or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V 1. Typical parameter indicates the value for the center of distribution at 5.0V (Ta= 25ºC), and not 100% tested. Capacitance (Vcc = 4.5V ~ 5.5V, f = 1MHz, Ta = 0 ~ +70°C / -40 ~ +85°C*2) Parameter Symbol Min. Typ. Max. Unit Test conditions Input capacitance C in 8 pF Vin =0V Input / output capacitance C I/O 10 pF VI/O =0V Note 1. This parameter is sampled and not 100% tested. 2. Ambient temperature range depends on R/I-version. Please see table on page 1. R10DS0151EJ0100 Rev.1.00 2013.6.21 Note 1 1 Page 6 of 12 R1LP0108E Series AC Characteristics Test Conditions (Vcc = 4.5V ~ 5.5V, Ta = 0 ~ +70°C / -40 ~ +85°C*1) Input pulse levels: VIL = 0.6V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.5V Output load: See figures (Including scope and jig) 1.5V RL = 500 ohm DQ Note CL = 30 pF ( -5SI, -5SR) CL = 100 pF ( -7SI, -7SR) 1. Ambient temperature range depends on R/I-version. Please see table on page 1. R10DS0151EJ0100 Rev.1.00 2013.6.21 Page 7 of 12 R1LP0108E Series Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Symbol tRC tAA tACS1 tACS2 tOE tOH tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ R1LP0108E**-5** R1LP0108E**-7** Min. 55 5 5 5 5 0 0 0 Min. 70 10 10 10 5 0 0 0 Max. 55 55 55 30 20 20 20 Max. 70 70 70 35 25 25 25 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns 2,3 2,3 2,3 1,2,3 1,2,3 1,2,3 Write Cycle Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z Write to output in high-Z Note Symbol tWC tAW tCW tWP tAS tWR tDW tDH tOW tOHZ tWHZ R1LP0108E**-5** R1LP0108E**-7** Min. 55 50 50 45 0 0 25 0 5 0 0 Min. 70 55 55 50 0 0 30 0 5 0 0 Max. 20 20 Max. 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns Note 5 4 6 7 2 1,2 1,2 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE#. A write begins at the latest transition among CS1# going low, CS2 going high and WE# going low. A write ends at the earliest transition among CS1# going high, CS2 going low and WE# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. 8. Don’t apply inverted phase signal externally when DQ pin is output mode. R10DS0151EJ0100 Rev.1.00 2013.6.21 Page 8 of 12 R1LP0108E Series Timing Waveforms Read Cycle tRC A0~16 tOH tAA tACS1 CS1# tCLZ1 CS2 tCHZ1 tACS2 tCLZ2 WE# tCHZ2 VIH WE# = “H” level tOE OE# tOLZ tOHZ High impedance DQ0~7 R10DS0151EJ0100 Rev.1.00 2013.6.21 Valid Data Page 9 of 12 R1LP0108E Series Write Cycle (1) (WE# CLOCK) tWC A0~16 tCW CS1# tCW CS2 tAW tAS tWP tWR WE# OE# tWHZ tOLZ tOHZ DQ0~7 tOW Valid Data tDW R10DS0151EJ0100 Rev.1.00 2013.6.21 tDH Page 10 of 12 R1LP0108E Series Write Cycle (2) (CS1#, CS2 CLOCK) tWC A0~16 tAW tAS tCW tWR tAS tCW tWR CS1# CS2 tWP WE# OE# VIH OE# = “H” level tDW DQ0~7 R10DS0151EJ0100 Rev.1.00 2013.6.21 tDH Valid Data Page 11 of 12 R1LP0108E Series Low Vcc Data Retention Characteristics Parameter Symbol VCC for data retention VDR Min. Typ. Max. Test conditions*2 Unit 2.0 - 5.5 V Vin ≥ 0V (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V - 0.6*1 2 A ~+25°C Vcc=3.0V, Vin ≥ 0V Data retention current - - 3 A ~+40°C - - 8 A ~+70°C - - 10 A ~+85°C ICCDR (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V Chip deselect time to data retention tCDR 0 ns See retention waveform. Operation recovery time tR 5 ms Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE# ,OE#, DQ) can be in the high impedance state. Low Vcc Data Retention Timing Waveforms (1) CS1# Controlled Vcc tCDR 4.5V 4.5V tR VDR 2.2V 2.2V CS1# ≥ Vcc - 0.2V CS1# (2) CS2 Controlled Vcc tCDR CS2 4.5V 4.5V tR VDR 0.2V 0.2V 0V ≤ CS2 ≤ 0.2V R10DS0151EJ0100 Rev.1.00 2013.6.21 Page 12 of 12 Revision History R1LP0108E Series Data Sheet Description Rev. Date 1.00 2013.6.21 Page - Summary First Edition issued All trademarks and registered trademarks are the property of their respective owners. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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