AIE Adaptive Image Enhancer Series Video Encoders built-in Image Correction No.10060ECT03 BU6520KV,BU6521KV ●Description BU6520KV, BU6521KV are video encoders with built-in AIE image correcting function. Also, BU6521KV has the image correcting function of the fog reduction, too. Fog Reduction, the brightness correction, the backlight correction and the chroma emphasis can improve the visibility of the input image of the camera. * AIE and Fog Reduction function are image processing technology by ROHM’s hardware. ●Features 1) Format of video output is compatible with NTSC/PAL composite video format (CVBS). Built-in DAC with direct 75Ω drive capability. *1 2) Built-in Fog Reduction function , dynamic range correction, edge-emphasizing filter and gamma filter. 3) Input/output data format is compatible with ITU-R BT.656 and YCbCr=4:2:2 with synchronization signal. 4) Compatible with NTSC (27MHz, 28.63636MHz and 19.06993MHz)/ *2 PAL(27MHz, 28.375MHz, 35.46895MHz and 18.9375MHz) . 5) Registers can be set up with a 2-line serial interface. 6) Registers can be automatically set up by reading from external EEPROM, when after resetting or changing mode. *1 As for the Fog Reduction feature, it loads only BU6521KV. *2 NTSC 19,06993 MHz and PAL 18,9375 MHz support only BU6521KV. ●Applications Security camera, camera for automotive, drive recorder etc. ●Line up matrix Part No. Power Sopply Image size Voltage(V) Input Interface Control Interface Output Interface 2 1.4 to 1.6 I C, 8bit, 8bit, 720x480, Serial (VDDCore) BU6520KV YUV=4:2:2, YUV=4:2:2, 2.7 to 3.6 SD size EEPROM ITU-R BT.656 ITU-R BT.656 (VDDI/O, AVDD) interface Feature Temperature Operating Range(℃) Package AIE, Video output -40 ~ +85 VQFP48C -40 ~ +85 VQFP48C 2 1.4 to 1.6 I C, AIE, 8bit, 8bit, 720x480, Serial (VDDCore) Fog reduction, BU6521KV YUV=4:2:2, YUV=4:2:2, SD size 2.7 to 3.6 EEPROM Video output ITU-R BT.656 ITU-R BT.656 (VDDI/O, AVDD) interface I2C BUS is a registered trademark of Philips www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV ●Absolute maximum ratings Parameter Symbol Rating Unit Supply voltage1 (IO) VDDIO -0.3～+4.2 V Supply voltage2 (IO) VDDI2C -0.3～+4.2 V Supply voltage3 (DAC) AVDD -0.3～+4.2 V Supply voltage4 (CORE) VDD -0.3～+2.1 Input voltage range VIN Storage temperature range Tstg Power dissipation PD *1 *2 *3 * * V -0.3～IO_LVL+0.3 *1 -40～+125 400 *2, V ℃ 900 *3 mW IO_LVL is a generic name of VDDIO, VDDI2C, and AVDD. IC only. In the case exceeding 25ºC, 4.0mW should be reduced at the rating 1ºC. When packaging a glass epoxy board of 70x70x1.6mm. If exceeding 25ºC, 9.0mW should be reduced at the rating 1ºC. Has not been designed to withstand radiation. Operation is not guaranteed at absolute maximum ratings. ●Operating conditions Parameter Symbol Ratings Unit Supply voltage 1 (IO) VDDIO 2.70 ~ 3.60 (Typ.: 3.30) V Supply voltage 2 (IO) VDDI2C 2.70 ~ 3.60 (Typ.: 3.30) V Supply voltage 3 (DAC) AVDD 2.70 ~ 3.60 (Typ.: 3.30) V Supply voltage 4 (CORE) VDD 1.40 ~ 1.60 (Typ.: 1.50) V Input voltage range VIN Operating temperature range Topr 0.00 ~ IO_LVL -40 ~ +85 *1 V ºC *1 IO_LVL is a generic name of VDDIO, VDDI2C, and AVDD. * Please supply power source in order of VDD→(VDDIO, VDDI2C, and AVDD). www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV ●Block Diagram [BU6520KV] CAMDI0 ―CAMDI7 8 8 AIE CAMHSI CAMVSI CAMCKI Timing Generator Video Encoder CAMDO0 ―CAMDO7 10bit DAC VOUT IREF CAMHSO CAMVSO CAMCKO Register Serial Interface (SPI) 2-line Serial Interface (I2 C) SDA SDC SDI SDO SCK SCEB WPB RESETB TEST AUTO MODE0 MODE1 Fig.1 BU6520KV Block Diagram [BU6521KV] CAMDI0 ―CAMDI7 8 8 AIE Fog reduction CAMHSI CAMVSI CAMCKI Timing Generator Video Encoder CAMDO0 ―CAMDO7 10bit DAC VOUT IREF CAMHSO CAMVSO CAMCKO Register Serial Interface (SPI) 2-line Serial Interface (I2 C) SDA SDC SDI SDO SCK SCEB WPB RESETB TEST AUTO MODE0 MODE1 Fig.2 BU6521KV Block Diagram www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV ●Pin functional descriptions・Equivalent circuit Power Source System I/O *1 type SPI-bus data input 1 A - Data input bit 7 1 C DATA - Data input bit 6 1 C In DATA - Data input bit 5 1 C CAMDI4 In DATA - Data input bit 4 1 C 6 GND - GND - Common GROUND 1,2,4 - 7 VDD - PWR - CORE power source 4 - 8 CAMDI3 In DATA - Data input bit 3 1 C 9 CAMDI2 In DATA - Data input bit 2 1 C 10 CAMDI1 In DATA - Data input bit 1 1 C 11 CAMDI0 In DATA - Data input bit 0 1 C 12 CAMHSI In * - Horizontal timing input 1 C 13 CAMVSI In * - Vertical timing input 1 C 14 CAMCKI In CLK - Clock input 1 E 15 GND - GND - Common GROUND 1,2,4 - 16 VDDIO - PWR - Digital IO power source 1 - 17 CAMDO0 Out DATA Low Data output bit 0 1 F 18 CAMDO1 Out DATA Low Data output bit 1 1 F 19 CAMDO2 Out DATA Low Data output bit 2 1 F 20 CAMDO3 Out DATA Low Data output bit 3 1 F 21 CAMDO4 Out DATA Low Data output bit 4 1 F 22 CAMDO5 Out DATA Low Data output bit 5 1 F 23 CAMDO6 Out DATA Low Data output bit 6 1 F 24 CAMDO7 Out DATA Low Data output bit 7 1 F PIN No. PIN Name In/Out Active Level Init 1 SDI In DATA - 2 CAMDI7 In DATA 3 CAMDI6 In 4 CAMDI5 5 Function explanation ※ ” * ” in the Active Level column indicates that it may be changed during set-up of the register. ※ Init column indicates pin status when released from reset. ※ In the power system column, ” 1 ” stands for VDDIO, ” 2 ” stands for VDDI2C, ” 3 ” stands for AVDD, ” 4 ” stands for VDD. *1 Fig.3 Equivalent Circuit Structures of input / output pins reference www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 4/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV Power Source System I/O *1 type Horizontal timing output 1 F Low Vertical timing output 1 F CLK Low Clock output 1 F - GND - Common GROUND 1,2,4 - - PWR - PIN No. PIN Name In/Out Active Level Init 25 CAMHSO Out * Low 26 CAMVSO Out * 27 CAMCKO Out 28 GND 29 VDD 30 31 AUTO MODE0 In In High DATA Function explanation CORE power source 4 - PD *2 Auto register setting enable signal 1 D PD *2 Auto register setting mode select bit 0 1 D *2 Auto register setting mode select bit 1 1 D 32 MODE1 In DATA PD 33 VOUT Out Analog - Analog composite output 3 H 34 AVSS - GND - Analog GROUND for DAC 3 - 35 IREF Out Analog - Reference voltage for DAC 3 I 36 AVDD - PWR - Analog power source for DAC 3 - 37 GND - GND - Common GROUND 1,2,4 - 38 VDDI2C - PWR - Digital IO power source (For 2-line serial interface input/output) 2 - 39 SDA In/Out DATA In 2-line serial interface data input/output 2 G 40 SDC In/Out CLK In 2-line serial interface clock input 2 G 41 RESETB In Low - System reset signal 1 B Test mode terminal (Connect to GND) 1 D 1,2,4 - *2 42 TEST In High PD 43 GND - GND - Common GROUND 44 VDDIO - PWR - Digital IO power source 1 - 45 WPB Out Low Low Write protect signal to EEPROM 1 F 46 SCEB Out Low High Chip select signal to EEPROM 1 F 47 SCK Out CLK Low SPI-bus clock 1 F 48 SDO Out DATA Low SPI-bus data output 1 F ※ ” * ” in the Active Level column indicates that it may be changed during set-up of the register. ※ Init column indicates pin status when released from reset. ※ In the power system column, ” 1 ” stands for VDDIO, ” 2 ” stands for VDDI2C, ” 3 ” stands for AVDD, ” 4 ” stands for VDD. *1 Fig.3 Equivalent Circuit Structures of input / output pins reference *2 Pull-down status. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 5/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV Type Equivalent circuit configuration VDDIO Typ Equivalent circuit configuration VDDIO VDDIO To internal circuit A B To internal circuit GND Input terminal GND GND Internal signal Input terminal with hysteresis VDDIO VDDIO VDDIO VDDIO To internal circuit C To internal circuit D GND GND Input terminal with suspend GND Internal signal GND GND Input terminal with pull down VDDIO VDDIO VDDIO To internal circuit Internal signal E F Internal signal GND GND VDDI2C VDDI2C To internal circuit AVDD VDDI2C AVDD Internal signal GND G Internal signal Internal signal H Internal signal GND GND Output terminal Input terminal with hysteresis and suspend Internal signal GND VOUT Input/Output terminal AVSS AVDD Internal signal AVDD Internal signal I Internal signal To internal circuit AVSS IREF Fig.3 Equivalent Circuit Structures of input / output pins www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV SDO SCK SCEB WPB VDDIO GND TEST RESETB SDC SDA VDDI2C GND ●Pin configrations 48 47 46 45 44 43 42 41 40 39 38 37 SDI 1 36 AVDD CAMDI7 2 35 IREF CAMDI6 3 34 AVSS CAMDI5 4 33 VOUT CAMDI4 5 32 MODE1 GND 6 31 MODE0 VDD 7 30 AUTO CAMDI3 8 29 VDD CAMDI2 9 28 GND CAMDI1 10 27 CAMCKO CAMDI0 11 26 CAMVSO CAMHSI 12 25 CAMHSO 13 14 15 16 17 18 19 20 21 22 23 24 CAMVSI CAMCKI GND VDDIO CAMDO0 CAMDO1 CAMDO2 CAMDO3 CAMDO4 CAMDO5 CAMDO6 CAMDO7 VQFP48C Fig.4 Pin configrations www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 7/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV ●Electrical characteristics(common) (Unless otherwise specified VDD=1.50V, VDDIO=3.3V, VDDI2C=3.3V, AVDD=3.3V, GND=0.0V, Ta=25℃,fIN=35.5MHz) Limits Parameter Symbol Unit Condition MIN. TYP. MAX. Input frequency Supply current (CORE) fIN 2 - 35.5 BU6520KV IDD1 - 30 - mA 35.5MHz operational setting*1 BU6521KV IDD1 - 40 62 mA 35.5MHz operational setting*2 IDDst1 - - 50 µA At sleep mode setting, input terminal = GND setting BU6520KV IDD2 - 38 - mA RL=37.5Ω, RIREF=2.4kΩ BU6521KV IDD2 - 38 56 mA RL=37.5Ω, RIREF=2.4kΩ IDDst2 - - 5 µA input terminal=GND and DAC power down mode setting Leakage current (CORE) Supply current (DAC) Leakage current (DAC) *1 *2 MHz CAMCKI(DUTY45%～55%) Supply current(Total value of current of VDD, VDDIO, and VDDI2C) at color-bar image input in AIE enable and Digital output disable settings. Supply current(VDD) at color-bar image input in Fog-Reduction enable, AIE enable and Digital output disable settings. ●Electrical characteristics(DC characteristics) 1. DC characteristics (IO) (Unless otherwise specified VDD=1.50V, VDDIO=3.3V, VDDI2C=3.3V, AVDD=3.3V, GND=0.0V, Ta=25℃) Limits Parameter Symbol Unit Condition MIN. TYP. MAX. Input ”H” current IIH -10 - 10 µA VIH=IO_LVL Input ”L” current IIL -10 - 10 µA VIL=GND Pull-down current IPD 25 50 100 µA VIH=IO_LVL Input ”H” voltage 1 VIH1 IO_LVL x0.8 - Input ”L” voltage 1 VIL1 -0.3 - Input ”H” voltage 2 VIH2 IO_LVL x0.85 - Input ”L” voltage 2 VIL2 -0.3 - Output ”H” voltage VOH IO_LVL -0.4 - IO_LVL V Output ”L” voltage VOL 0.0 - 0.4 V * IO_LVL +0.3 IO_LVL x0.2 IO_LVL +0.3 IO_LVL x0.15 V V V V Normal input (Including input mode of I/O terminal) Normal input (Including input mode of I/O terminal) Hysteresis input (RESETB,CAMCKI,AUTO,MODE0,MODE1) Hysteresis input (RESETB,CAMCKI,AUTO,MODE0,MODE1) IOH=-1.0mA(DC) (including output mode of I/O terminal) IOL=1.0mA(DC) (including output mode of I/O terminal) IO_LVL is a generic name of VDDIO, VDDI2C and AVDD. 2. DC characteristics (DAC) (Unless otherwise specified VDD=1.50V, VDDIO=3.3V, VDDI2C=3.3V, AVDD=3.3V, GND=0.0V, Ta=25℃) Limits Parameter Symbol Unit Condition MIN. TYP. MAX. RL=37.5Ω, RIREF=2.4kΩ, Integral Non-linearity INL ±4.0 ±8.0 LSB DAC resolution=10bit RL=37.5Ω, RIREF=2.4kΩ, ±1.0 ±2.0 Differential Non-linearity DNL LSB DAC resolution=10bit RL=37.5Ω, RIREF=2.4kΩ, Output Voltage (full scale) VFS 1.1 1.25 1.4 V DAC resolution=10bit www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV ●Electrical characteristics(AC characteristics) 1. Data Input Interface Timing CAMVSI CAMHSI CAMDI0 －CAMDI7 CAMCKI (CKPOL=“0”) CAMCKI (CKPOL=“1”) tCMH tCMS Fig.5 Data Input Interface Timing Symbol Description MIN TYP MAX Unit tCAMCKI CAMCKI Clock Cycle 27.8 - - ns dCAMCKI CAMCKI Clock Duty 45 50 55 % tCMS CAMCKI Rise / Fall Camera Setup Time 8 - - ns tCMH CAMCKI Rise / Fall Camera Hold Time BU6520KV 6 - - ns BU6521KV 5 - - ns * CKPOL selects the CAMCKI polarity. (CKPOL is register at BU6520KV/BU6521KV) 2. Data Output Interface Timing tPCLK CAMCKO (CKPOL="1") tPHH CAMVSO CAMHSO tPHL tPDV CAMDO0 －CAMDO7 Fig.6 Data Output Interface Timing Symbol Description MIN TYP MAX Unit tPCLK CAMCKO Clock Cycle 27.8 - - ns dPCLK CAMCKO Clock Duty 40 50 60 % tPDV Decision of CAMDO from CAMCKO - - 7 ns tPHL, tPHH Decision of CAMVSO or CAMHSO from CAMCKO - - 7 ns * This figure shows CKPOL setting is ” 1 ” In case of CKPOL= ” 0 ”, CAMVSO, CAMHSO and CAMDO0-CAMCO7 change based on CAMCKO fall edge. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 9/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV 3. 2-line Serial Interface Timing SDA t SU;DAT t LOW t BUF t HD;ST SDC t HD;STA t HD;DAT t SU;STA t HIGH t SU;STO Fig.7 2-line Serial Interface Timing Symbol Description MIN TYP MAX Unit 0 - 400 kHz fSCL SDC Clock Frequency tHD;STA Hold Time (repetition) ”START” conditions. The first clock pulse is generated after this period. 0.6 - - µs fLOW The ”L” period of SDC clock 1.3 - - µs tHIGH The ”H” period of SDC clock 0.6 - - µs tSU;STA Setup Time of repetitive ”START” conditions 0.6 - - µs tHD;DAT Data Hold Time 0 tSU;DAT Data Setup Time 100 - - ns tSU;STO Setup Time of the ”STOP” conditions 0.6 - - µs tBUF Bus free Time between ”STOP” conditions and the ”START” conditions 1.3 - - µs www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 10/18 µs 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV 4. SPI-bus Interface Timing ｔSPCS ｔSPDV ｔSPCH SCK SCEB SDO SDI ｔSPS ｔSPH Fig.8 SPI-bus Interface Timing Symbol Description MIN TYP MAX Unit 736*1 8192 tCAMCKI tSPCLK Clock Cycle 2 dSPCLK Clock Duty 45 50 55 % 12289 tCAMCKI tSPCS SCK Rise SCEB Setup Time 4 738～ *1 1105 tSPCH SCEB Rise after SCK Rise Time 2 751*1 8319 tCAMCKI tSPDV Decision of SDO from SCK Fall - - 28 ns tSPS SCK Rise SDI Setup Time - - 28 ns tSPH SCK Rise SDI Hold Time - - 28 ns *1 Default status right after reset When the automatic reading function with the AUTO pin is used, it becomes timing of SCEB to SCK as above. It is possible to access from the register of BU6520KV/BU6521KV to EEPROM.In that case, SCEB is controlled by the register. After the value is set to the register, the SCEB pin is changed into the logic set at once. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV ●Functional descriptions 1. Analog Composite Output Waveform 1.1. Output waveform in NTSC 130.8 IRE 130.8 IRE 100.0 IRE 116.4 IRE 100.3 IRE 93.6 IRE 59.4 IRE VOUT 48.1 IRE 0.0 IRE 13.9 IRE 40.0 IRE 7.5 IRE 7.2 IRE -8.9 IRE -40.0 IRE White Yellow Cyan Green Magenta -23.3 IRE -23.3 IRE Red Blue Black Fig.9 Color-bar corrugation in NTSC setting 1.2. Output waveform in PAL 133.3 IRE 133.3 IRE 100.0 IRE 117.7 IRE 100.3 IRE 93.2 IRE 56.1 IRE VOUT 43.9 IRE 0.0 IRE 6.9 IRE 42.9 IRE 0.0 IRE -0.3 IRE -17.7 IRE -43.0 IRE White Yellow Cyan Green Magenta -33.3 IRE -33.3 IRE Red Blue Black Fig.10 Color-bar corrugation in PAL setting www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 12/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV 2. The 2 line formula serial interface format Slave address is 70h. The sub-address is incremented automatically when accessing it (read / write) continuously 2 times or more. SDI SDA SDC SCLK 1-7 S START Slave condition address 8 9 R/W ACK 1-7 9 8 Sub address 1-7 ACK 8 Data 9 P ACK STOP condition Fig.11 Waveform of date transmission part Fig.10 データ送受信波形 Write sequence S Slave address (70h) W A(S) (0) Sub address A(S) Read sequence S Slave address (70h) W A(S) (0) Sub address A(S) Data A(S) Slave address (70h) S Data R A(S) (1) A(S) Data S = START condition A(S) = Acknowledge by slave NA(S) = Not acknowledge by slave P = STOP condition A(M) = Acknowledge by master NA(M) = Not acknowledge by master Data A(M) A(S)/ NA(S) Data P A(M)/ NA(M) P Fig.12 2-line serial interface format 3. SPI-bus format WPB H'/'L' level is set by the REG_WPB register. SCEB H'/'L' level is set by the REG_SCEB register. SCK SDO W7 W6 W5 W4 W3 W2 W1 W0 SDI R7 R6 R5 R4 R3 R2 R1 R0 The data written in the SWDATA register is set. It is possible to read it from the SRDATA register. Fig.13 SPI-bus interface wave form * REG_WPB, REG_SCEB, SWDATA, and SRDATA in figure are the register names, and the each function is as follows. REG_WPB ：Set WP Terminal logic. Register value is output directly. REG_SCEB ：Set SCEB Terminal logic. Register value is output directly. SWDATA[7:0]：Write data to EEPROM. Transfers MSB the first. SRDATA[7:0] ：Read data from EEPROM. Converts MSB the first. The SCK clock frequency is as follows. (SPIPREDIV+1) ÷ (SPIDIV+1) SCK frequency = CAMCKI frequency ÷ 2 Register range : SPIPREDIV = 0 to 7, SPIDIV = 0 to 31 When CAMCKI is 27MHz, SCK becomes 3.3 kHz from 13.5 MHz. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV ●Application example 2 <When registers are controlled by both of the automatic reading from EEPROM and the I C controller > BU6520KV/BU6521KV 8 Camera Module 8 CAMDO0 -CAMDO7 CAMDI0 -CAMDI7 CAMHSI CAMVSI CAMHSO CAMVSO CAMCKI CAMCKO Image Processor R1 : 2.4kΩ IREF I2C Controller SDA SDC VOUT EEPROM WPB SCEB LPF R2 : 75Ω SCK SDO VDD SDI C1,C2 : 0.1uF *1 C3,C4 : 0.1uF *2 VDDIO Switch AUTO MODE0 MODE1 Reset Controller VDDI2C *3 C6 : 0.1uF *4 RESETB AVDD AVSS TEST *1 *2 *3 *4 C5 : 0.1uF GND Please arrange a capacitor each near two VDD pin. Please arrange a capacitor each near two VDDIO pin. Please arrange a capacitor near VDDI2C pin. Please arrange a capacitor near AVDD pin. Fig.14 Application example 1 Fig.14 is a reference example when the system is connected, and the operation is not guaranteed. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 14/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV 2 <When registers are controlled only by the I C controller> BU6520KV/BU6521KV 8 8 CAMDI0 -CAMDI7 Camera Module CAMDO0 -CAMDO7 CAMHSI CAMVSI CAMHSO CAMVSO CAMCKI CAMCKO Image Processor R1 : 2.4kΩ IREF I2C Controller SDA SDC VOUT OPEN WPB SCEB SCK SDO LPF R2 : 75Ω SDI VDD *1 C3,C4 : 0.1uF *2 VDDIO AUTO MODE0 MODE1 Reset Controller C1,C2 : 0.1uF VDDI2C C5 : 0.1uF *3 C6 : 0.1uF *4 GND RESETB AVDD TEST *1 *2 *3 *4 AVSS Please arrange a capacitor each near two VDD pin. Please arrange a capacitor each near two VDDIO pin. Please arrange a capacitor near VDDI2C pin. Please arrange a capacitor near AVDD pin. Fig.15 Application example 2 Fig.15 is a reference example when the system is connected, and the operation is not guaranteed. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 15/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV <When registers are controlled only by the automatic reading from EEPROM > BU6520KV/BU6521KV 8 Camera Module 8 CAMDI0 -CAMDI7 CAMDO0 -CAMDO7 CAMHSI CAMVSI CAMHSO CAMVSO CAMCKI CAMCKO Image Processor R1 : 2.4kΩ IREF SDA SDC VOUT EEPROM WPB SCEB SCK SDO SDI LPF R2 : 75Ω VDD Switch AUTO MODE0 C1,C2 : 0.1uF *1 C3,C4 : 0.1uF *2 VDDIO MODE1 VDDI2C Reset Controller C5 : 0.1uF *3 C6 : 0.1uF *4 GND RESETB AVDD TEST *1 *2 *3 *4 AVSS Please arrange a capacitor each near two VDD pin. Please arrange a capacitor each near two VDDIO pin. Please arrange a capacitor near VDDI2C pin. Please arrange a capacitor near AVDD pin. Fig.16 Application example 3 Fig.16 is a reference example when the system is connected, and the operation is not guaranteed. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 16/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV ●Note for use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9) Input terminals} In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (12) Rush current For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and delays. Therefore, give special consideration to power coupling capacitance, power wiring, width of GND wiring, and routing of wiring. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 17/18 2010.02 - Rev.C Technical Note BU6520KV,BU6521KV ●Ordering part number B U 6 Part No. 5 2 0 K Part No. 6520 6521 V - Package KV:VQFP48C E 2 Packaging and forming specification E2: Embossed tape and reel VQFP48C <Tape and Reel information> 9.0 ± 0.2 7.0 ± 0.1 36 25 Embossed carrier tape Quantity 1500pcs 0.5±0.15 0.75 48 13 1 1PIN MARK Direction of feed E2 direction is the 1pin of product is at the upper left when you hold ( The ) reel on the left hand and you pull out the tape on the right hand +0.05 0.145 -0.03 1.6MAX 0.75 12 1.0±0.2 24 7.0±0.1 9.0±0.2 37 Tape 0.1±0.05 1.4±0.05 4 +6 -4 0.5 ± 0.1 0.08 S +0.05 0.22 -0.04 0.08 1pin M (Unit : mm) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Reel Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 18/18 2010.02 - Rev.C Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. 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