RAiO RA0086A 80 CH Segment/Common Driver For Dot Matrix LCD Specification Simplify Version 1.1 December 29, 2009 RAiO Technology Inc. ©Copyright RAiO Technology Inc. 2009 瑞佑科技 RAiO TECHNOLOGY INC. 1/6 www.raio.com.tw RA0086A Version 1.1 80CH Common / Segment Driver For DOT Matrix LCD 1. Introduction The RA0086A is an 80 channels LCD driver LSI which is fabricated by low power CMOS high voltage process technology. It can be used either as a COMMON driver or as a SEGMENT driver, by connecting its CS input to VDD or VSS. In segment driver mode, it can be interfaced in 1-bit serial or 4-bit parallel method by the controller. In common driver mode, dual type mode is applicable. And in segment mode application, the power down function reduces power consumption. 2. Features Interface Power supply voltage: + 5V±10 %, + 3V± 10% Supply voltage for display: 6 to 30V (VDDVEE) In 80-SEGMENT driver or 80-COMMON driver selection, to set CS-pin voltage is VSS or VDD 4-bit parallel / 1-bit serial data processing (in segment mode) Single mode / dual mode operation (in common mode) Power down function (in segment mode) Applicable LCD duty: 1/64 – 1/256 COM(Cascade) RA0086A Drivers SEG(Cascade) RA0086A High voltage CMOS process Available package Type: LQFP-100 pin, Die Parts Number RA0086A RA0086AL3N Package Die LQFP-100 pin 3. Block Diagram SC1 SC2 SC3 SC78 SC79 SC80 V0 V12 80-bit 4-level Driver V43 V5 VEE M DISP0FFB 80-bit Driver Output Level Selector D1-SID D2-DL LCK SCK CL1 CL2 80-bitData Latch/Common Data Bi-direction Shift Register D3-DM D4-DR 20 x 4-bit Segment Data Bi-direction Shift Register Data Latch Control Clock Control CS AMS Power Down Function ERB VDD VSS ELB 瑞佑科技 RAiO TECHNOLOGY INC. 2/6 www.raio.com.tw RA0086A Version 1.1 80CH Common / Segment Driver For DOT Matrix LCD 4. Signal Description 4-1 Block Description Name Clock control Function COM / SEG Generates latch clock (LCK), shift clock (SCK) and control clock timing according to the input of CL1, CL2 and control inputs (CS, AMS). In COM / SEG common driver application mode, this block generates the shift clock (LCK) for the common data Bi-directional shift register. Data latch control Determines the direction of segment data shift, and input data of each Bi-directional shift register. In 4-bit segment data parallel transfer mode, data is shifted by a 4-bit unit. In common driver application mode, data is transferred to the common data shift register directly, which disables this block. SEG Power down function Controls the clock enable state of the current driver according to the input value of enable pin (ELB or ERB). If enable input value is “Low”, every clock of the current driver is enabled and the clock control block works. But if enable input is “High”, current driver is disabled and the input data value has no effect on the output level. So power consumption can be lowered. SEG Output level selector Controls the output voltage level according to the input control pin (M COM / SEG and DISPOFFB). 20x4-bit segment data BI-directional shift register Stores output data value by shifting the input values. In 1-bit serial interface mode application, all 80 shift clocks (SCK) are needed to store all the display data. But in 4-bit parallel transfer mode application, only 20 clocks are needed. In common driver application mode, this block does not work. 80-bit data latch / common data BI-directional shift register In segment driver application mode, the data from the 20x4-bit segment data shift register are latched for segment driver output. In single-type common driver application,1-bit input data (from DL or DR pin) is shifted COM / SEG and latched by the direction according to the SHL signal input. In dualtype common application mode, 80-bit registers are divided by two blocks and controlled independently. SEG 80-bit level shifter Voltage level shifter block for high voltage part. The inputs of this block are of logical voltage level and the outputs of this block are at high voltage level value. These values are input in to the driver. SEG 80-bit 4-level driver Selects the output voltage level according to M and latched data value. If the data value is "High" the driver output is at selected voltage level (V0 or V5), and in the reverse case the driver output value is at the nonselected level (V12 or V43). In segment driver application mode, nonselected output value is V2 or V3. and when in common driver application, this value becomes V1 or V4. SEG 瑞佑科技 RAiO TECHNOLOGY INC. 3/6 www.raio.com.tw RA0086A Version 1.1 80CH Common / Segment Driver For DOT Matrix LCD 4-2 Pin Description Pin I/O Name P Power supply VDD VSS VEE V0, V12, V43, V5 I SC1 SC80 O CL2 I M I CL1 I DISPOFFB I CS I Description Function Logical "High" input port (+5V ± 10%, +3V ± 10%) Interface 0V (GND) Power Logical "Low" for high voltage part LCD driver Bias supply voltage input to drive the LCD. Bias voltage output divided by the resistance is usually used as a supply voltage voltage source. level Display data output pin which corresponds to the LCD driver respective latch contents. One of V0, V12, V34 and V5 is selected as a display driving voltage source according to output the combination of the latched data level and M signal. Clock pulse input for the bi-directional shift register. – In segment driver application mode, the data is shifted to 20 x 4-bit segment data shift. Data shift The clock pulse, which was input when the enable bit (ELB/ERB) is in not active condition, is invalid. clock – In common driver application mode, the data is shifted to 80-bit common data bi-directional shift register by the CL1 clock.Hence, this clock pin is not used (Open or connect this pin to VDD). AC signal for LCD Alternate signal input pin for LCD driving. driver Normal frame inversion signal is input in to this pin. output – In segment driver application mode, this signal is used for latching the shift register contents at the falling edge of Data latch this clock pulse. CL1 pulse "High" level initializes powerdown function block. clock – In common driver application mode, CL1 is used as a shifting clock of common output data. Control input pin to fix the driver output (SC1~SC80) to V0 Display OFF level,during "Low" value input. LCD becomes non-selected by V0 level output from every output of segment drivers and control every output of common drivers. COM / SEG When CS = "Low", RA0086A is used as an 80-bit segment driver. mode When CS = "High", RA0086A is set to an 80-bit common control driver Power LCD Controller Controller Controller Controller VDD/ VSS According to the input value of the AMS and the CS pin, application mode of RA0086A is differs as shown below. AMS I Application mode select 瑞佑科技 RAiO TECHNOLOGY INC. CS AMS Application mode 0 0 4-bit parallel interface mode. 0 1 1 0 1-bit serial interface mode. Single type application mode 1 1 Dual type application mode 4/6 COM /SEG SEG VDD/ VSS COM www.raio.com.tw RA0086A Version 1.1 80CH Common / Segment Driver For DOT Matrix LCD D1_SID, D2_DL, D3_DM, D4_DR. I/O SHL I ELB,ERB I/O - In segment driver application mode, these pins are used as 4-bit data input pin (when 4-bit parallel interface mode : AMS = "Low"), or D1_SID is used as serial data input pin Display data and other pins are not used (connect these to VDD) (when input / 1-bit serial interface mode : AMS = "High"). Serial input data / – In common driver application mode, the data is shifted from D2_DL(D4_DR) to D4_DR(D2_DL), when in single left,right data input type interface mode (AMS = "Low"). In dual type application case, the data are shifted from D2_DL and output D3_DM (D4_DR and D3_DM) to D4_DR(D2_DL). In each case the direction of the data shift and the connection of data pins are determined by SHL input. Shift When SHL = "Low", data is shifted from left to right. direction When SHL = "High", the direction is reversed. control – In segment driver application mode, the internal operation is enabled only when enable input (ELB or ERB) is “Low” (power down function). When several drivers are serially connected, the enable state of each driver is shifted according to the SHL input. Connect Enable data these pins as below. input/output SHL L H Controller VDD/ VSS Segment Driver ELB ERB Output Input Input Output - In common driver application mode, power down function is not used. Open these pins. 5. System Block Diagram STN STN Controller Controller RA0086A RA8822 RA8822 RA8803 RA8803 RA8806 RA8806 RA8835 RA8835 RA0086A STN LCD Panel RA6963 RA6963 瑞佑科技 RAiO TECHNOLOGY INC. 5/6 www.raio.com.tw RA0086A Version 1.1 80CH Common / Segment Driver For DOT Matrix LCD 6. Application Information SC2 SC1 ELB CL1 AMS CL2 D1_SID D2_DL D3_DM D4_DR VSS SHL VDD DISPOFFB M CS V0 V12 V34 V5 VEE ERB SC80 SC79 SC78 7. Package 75 SC3 SC4 SC5 SC6 SC7 SC8 SC9 SC10 SC11 SC12 SC13 SC14 SC15 SC16 SC17 SC18 SC19 SC20 SC21 SC22 SC23 SC24 SC25 SC26 SC27 70 65 60 55 50 80 45 85 90 RAiO TM 40 RA0086AL3N 35 09XX-N MXTS01 95 PIN#1. 5 10 15 30 20 25 SC28 SC29 SC30 SC31 SC32 SC33 SC34 SC35 SC36 SC37 SC38 SC39 SC40 SC41 SC42 SC43 SC44 SC45 SC46 SC47 SC48 SC49 SC50 SC51 SC52 100 Date code (Year 2009) SC77 SC76 SC75 SC74 SC73 SC72 SC71 SC70 SC69 SC68 SC67 SC66 SC65 SC64 SC63 SC62 SC61 SC60 SC59 SC58 SC57 SC56 SC55 SC54 SC53 瑞佑科技 RAiO TECHNOLOGY INC. 6/6 www.raio.com.tw