HD74SSTV16859
1:2 13-bit SSTL_2 Registered Buffer
REJ03D0832-0900
(Previous: ADE-205-337H)
Rev.9.00
Apr 07, 2006
Description
The HD74SSTV16859 is a 1:2 13-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset
(RESET) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to QA, QB is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on
the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins.
When RESET is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low
state during power up.
Features
•
•
•
•
Supports LVCMOS reset (RESET)) input / SSTL_2 data (D) inputs and CLK input
Differential SSTL_2 (Stub series terminated logic) CLK signal
Flow through architecture optimizes PCB layout
Ordering Information
Part Name
HD74SSTV16859TEL
Package Type
TSSOP-64 pin
Package Code
(Previous code)
PTSP0064KA-A
(TTP-64DV)
Package
Abbreviation
Taping Abbreviation
(Quantity)
T
EL (1,000 pcs / Reel)
Function Table
Inputs
RESET
L
H
H
CL
CLK
LK
LK
X
↓
↓
Outputs
CLK
X
↑
↑
D
X
H
L
QA
L
H
L
H
L or H
H or L
X
Q0
H:
High level
L:
Low level
X:
Immaterial
↑:
Low to high transition
↓:
High to low transition
Note: 1. Output level before the indicated steady state input conditions were established.
Rev.9.00 Apr 07, 2006 page 1 of 10
*1
QB
L
H
L
Q0
*1
HD74SSTV16859
Pin Arrangement
Q12A 1
64 VDDQ
Q11A 2
63 GND
Q10A 3
62 D12
Q09A 4
61 D11
Q08A 5
60 VCC
VDDQ 6
59 VDDQ
GND 7
58 GND
Q07A 8
57 D10
Q06A 9
56 D9
Q05A 10
55 D8
Q04A 11
54 GND
Q03A 12
53 D7
Q02A 13
Q01A 14
52 D6
51 RESET
RESE
GND 15
50 GND
Q00A 16
49 CLK
Q12B 17
48 CLK
VDDQ 18
47 VDDQ
Q11B 19
46 VCC
Q10B 20
45 VREF
Q09B 21
44 D5
Q08B 22
43 GND
Q07B 23
42 D4
Q06B 24
41 D3
Q05B 25
40 D2
GND 26
39 GND
VDDQ 27
38 VDDQ
Q04B 28
37 VCC
Q03B 29
36 D1
Q02B 30
35 D0
Q01B 31
34 GND
Q00B 32
33 VDDQ
(Top view)
Rev.9.00 Apr 07, 2006 page 2 of 10
HD74SSTV16859
Absolute Maximum Ratings
Item
Supply voltage
Input voltage *1
Output voltage *1
Input clamp current
Output clamp current
Continuous output current
VCC, VDDQ or GND current / pin
Symbol
VCC or VDDQ
VI
VO
IIK
IOK
IO
ICC, IDDQ or IGND
Maximum power dissipation
at Ta = 55°C (in still air)
Storage temperature
Notes:
PT
Ratings
–0.5 to 3.6
–0.5 to VDDQ+0.5
–0.5 to VDDQ+0.5
±50
±50
±50
±100
1
Unit
V
V
V
mA
mA
mA
mA
W
Tstg
–65 to +150
°C
Conditions
VI < 0 or VI > VCC
VO < 0 or VO > VDDQ
VO = 0 to VDDQ
TSSOP
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
Recommended Operating Conditions
Item
Supply voltage
Output supply voltage
Reference voltage
Termination voltage
Input voltage
AC high level input voltage
AC low level input voltage
DC high level input voltage
DC low level input voltage
High level input voltage
Low level input voltage
Differential (Common mode range)
input voltage (Minimum peak to
Symbol
VCC
VDDQ
VREF
VTT
VI
VIH
VIL
VIH
VIL
VIH
VIL
VCMR
VPP
Min
VDDQ
2.3
1.15
VREF–40 mV
0
VREF+310 mV
—
VREF+150 mV
—
1.7
–0.3
0.97
360
Typ
2.5
2.5
1.25
VREF
—
—
—
—
—
—
—
—
—
Max
2.7
2.7
1.35
VREF+40 mV
VCC
—
VREF–310 mV
—
VREF–150 mV
VDDQ+0.3
0.7
1.53
—
Unit
V
V
V
V
V
V
V
V
V
V
V
V
mV
IOH
IOL
Ta
—
—
0
—
—
—
–20
20
70
mA
mA
°C
Conditions
VREF = 0.5 × VDDQ
D
D
D
D
RESET
RESET
CLK, CLK
CLK, CLK
peak input)
High level output current
Low level output current
Operating temperature
Note: The RESET input of the device must be held at VDDQ or GND to ensure proper device operation. The differential
inputs must not be floating, unless RESET is low.
Rev.9.00 Apr 07, 2006 page 3 of 10
HD74SSTV16859
Logic Diagram
*1
RESET
51
CLK
CLK
48
49
D0
VREF
35
16
1D
C1
32
R
45
Q00A
Q00B
To twelve other channels
Note:
1. RESET input gate is connected to VDDQ.
Electrical Characteristics
Item
Input diode voltage
Output voltage
Symbol
VIK
VOH
VOL
Input current
(All inputs)
Quiescent supply current
Standby current
Dynamic operating clock only
IIN
ICC *2
ICC (stdy)
ICCD *2
VCC (V)
2.3
Min
—
2.3 to 2.7 VCC–0.2
2.3
1.95
2.3 to 2.7
—
2.3
0
2.7
—
2.7
—
2.7
—
2.7
—
Typ
—
Max
–1.2
Unit
V
—
—
—
—
—
—
—
—
—
VDDQ
0.2
0.35
±5
45
10
90
V
µA
mA
µA
µA/
clock
MHz
Test Conditions
IIN = –18 mA
IOH = –100 µA
IOH = –16 mA
IOL = 100 µA
IOL = 16 mA
VIN = 2.7 V or 0
VIN = VIH(AC) or VIL(AC), IO = 0
RESET = GND
RESET = VCC,
VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50%
duty cycle
Dynamic operating per each
data input
ICCD
—
20
µA/
clock
MHz/
data
input
rO(∆)
—
—
—
22 *4
22 *4
4
Ω
Ω
Ω
CIN
2.5 *1
2.5
2.5
—
—
—
3.0
3.5
3.5
—
pF
rOH – rOL each
*3
separate bit
CLK and CLK
RESET
Notes: 1.
2.
3.
4.
—
7
7
—
rOH
rOL
Data inputs
2.7
2.3 to 2.7
2.3 to 2.7
2.5
Output high *3
Output low *3
Input
capacitance
*2
All typical values are at VCC = 2.5 V, Ta = 25°C.
Total ICC (max) = ICC + {ICCD (clock)×f(clock)} + {ICCD (Data)×1/2f(clock)×13}
This is effective in the case that it did terminate by resistance.
See figure. 1, 2
Rev.9.00 Apr 07, 2006 page 4 of 10
RESET = VCC,
VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50%
duty cycle. One data input
switching at half clock
frequency, 50% duty cycle.
IOH = –20 mA
IOL = 20 mA
IO = 20 mA, Ta = 25°C
VI = VREF±310 mV
VCMR = 1.25 V, VPP = 360 mV
VI = VCC or GND
HD74SSTV16859
Switching Characteristics
Item
Symbol
VCC = 2.5 ± 0.2 V
Min
Max
—
200
0.75
—
0.9
—
0.75
—
0.9
—
22
—
Clock frequency *1
Setup time
Fast slew rate *4, 6
Slow slew rate *5, 6
Hold time
Fast slew rate *4, 6
Slow slew rate *5, 6
Differential inputs active time
fclock
tsu
Differential inputs inactive time
tinact
22
Pulse width
Output slew *3
tw
tSL
2.5
1
th
tact
Unit
MHz
ns
Test Condition
Data before CLK↑, CLK↓
ns
Data after CLK↑, CLK↓
ns
Data inputs must be low after RESET
high.
—
ns
—
4
ns
volt/ns
Data and clock inputs must be held at
valid levels (not floating) after RESET
low.
CLK, CLK “H” or “L”
(CL = 30 pF, RL = 50 Ω, VREF = VTT = VDDQ × 0.5)
Item
Symbol
Maximum clock frequency
4.
5.
6.
Min
200
Typ
—
Max
—
Unit
FROM
(Input)
TO
(Output)
MHz
tPLH, tPHL
1.1
—
2.8
ns
CLK, CLK
QA, QB
tPHL
—
—
5.0
RESET
QA, QB
Although the clock is differential, all timing is relative
lative to CLK going high and CLK going low.
This timing relationship is specified into test load (see waveforms – 3, 4) with all of the outputs switching.
Assumes into an equivalent, distributed load to the address net structure def
defined in the application
information provided in this specification.
For data signal input slew rate ≥ 1 V/ns.
For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns.
CLK, CLK signals input slew rates are ≥ 1 V/ns.
Propagation delay time
Notes: 1.
2.
3.
fmax
VCC = 2.5 ± 0.2 V
*2
Rev.9.00 Apr 07, 2006 page 5 of 10
HD74SSTV16859
Test Circuit
VTT
*2
50 Ω
Test point
*1
C L = 30 pF
Notes:
1. CL includes probe and jig capacitance.
2. VTT = VREF = VDDQ × 0.5
Waveforms – 1
LVCMOS
RESET
Input
VCC
VCC /2
VCC /2
0V
tinact
tact
*1
I CC
I CCH
90 %
10 %
I CCL
Waveforms – 2
tw
VIH
Input
VREF
VREF
VIL
Timing input
VCMR
tsu
VPP
th
VIH
Input
VREF
VREF
VIL
Rev.9.00 Apr 07, 2006 page 6 of 10
HD74SSTV16859
Waveforms – 3
Timing input
VCMR
VCMR
tPLH
VPP
tPHL
V OH
Output
VTT
VTT
VOL
Waveforms – 4
LVCMOS
RESET
Input
VIH
VCC /2
VIL
tPHL
VOH
Output
VTT
VOL
Notes:
1. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
2. All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, Zo = 50 Ω,, input slew rate = 1 V/ns ±20% (unless otherwise specified).
3. The outputs are measured one at a time with one transition per measurement.
4. VTT = VREF = VDDQ/2
5. VIH = VREF+310 mV (AC voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
6. VIL = VREF–310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
7. tPLH and tPHL are the same as tpd
Rev.9.00 Apr 07, 2006 page 7 of 10
HD74SSTV16859
Application Data
• Pull-down
100
Current (Amps)
80
60
40
Min
Max
20
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2.0
2.5
3.0
Voltage (V)
Figure 1
• Pull-up
Voltage (V)
0.0
0
0.5
1.0
1.5
Min
Max
Current (Amps)
-20
-40
-60
-80
-100
Figure 2
Rev.9.00 Apr 07, 2006 page 8 of 10
HD74SSTV16859
Curve Data
Pull-down
Pull-up
Voltage (V)
I (mA)
I (mA)
I (mA)
I (mA)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Min
0
6
10
15
19
23
27
30.5
34
36.5
38.5
40
42
43
44
44
45
45
45
45
45
46
46
46
46
46
46
46
Max
0
7
15
22
29
35.5
41.5
48
54
59
65
70
75
79
82
84.5
87
89
90
90
91
91
91
91
91.5
92
92
92
Min
0
–5
–10
–15
–19
–23.5
–28
–31.5
–35
–38
–41
–44
–46
–48
–50
–51
–52
–52
–52.5
–53
–53
–53.5
–54
–54
–54
–54.5
–55
–55
Max
0
–7
–13
–19
–25
–31
–37
–42
–47
–53
–58
–62
–66
–71
–74
–77
–81
–84
–86
–89
–91
–92
–93
–94
–95
–96.5
–98
–99
Rev.9.00 Apr 07, 2006 page 9 of 10
HD74SSTV16859
Package Dimensions
JEITA Package Code
P-TSSOP64-6.1x17-0.50
RENESAS Code
PTSP0064KA-A
Previous Code
TTP-64DV
*1
MASS[Typ.]
0.47g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
D
F
64
33
HE
Terminal cross section
( Ni/Pd/Au plating )
*2
E
c
bp
Index mark
1
Z
Reference Dimension in Millimeters
Symbol
32
e
*3
bp
Min
x
M
A
L1
y
A1
θ
L
Detail F
Rev.9.00 Apr 07, 2006 page 10 of 10
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Nom Max
17.0 17.2
6.10
0.00 0.05 0.10
1.20
0.15 0.20 0.25
0.10 0.15 0.20
0°
8°
7.90 8.10 8.30
0.50
0.08
0.08
0.90
0.4 0.5 0.6
1.0
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
Technology Corp. or a third party.
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas T
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information
on products at the time of
i
improvements or other reasons. It is
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvement
distributor for the latest product
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distrib
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Technology Corp. Semiconductor
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Techn
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances
in which human life
ci
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
aerospace, nuclear, or undersea repeater
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
materi
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license
from the Japanese government and
lic
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network"
http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .6.0