Delay Lines - Rhombus

Rhombus
Industries Inc.
2002
Transformers & Magnetic Products
Delay Lines
Electromagnetic
∆t
Logic Buffered
Delay
Low Distortion
Buffered Input / Output
Fast Rise Times
5V FAST/TTL &
Advanced CMOS
Single Output
5 Taps
10 Taps
16 Taps
20 Taps
3V Logic,
Low Voltage CMOS
10K & 10KH ECL
Single Output
5 Taps
Wide Range of
Standard Family
Impedances
10 Taps
50 Ω
Triple
75 Ω
Quad
93 Ω
Programmables
100 Ω
Special Function
Pulse Width Control
200 Ω
Dual
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15801 Chemical Lane, Huntington Beach, CA 92649-1595 z Tel: 714-898-0960 z FAX: 714-896-0971 z sales@rhombus-ind.com
June 2001
Founded in 1970, Rhombus Industries
Incorporated is a privately owned corporation
and a leading designer and manufacturer of
transformers and magnetic products. Our
headquarters is located in Huntington Beach,
California and includes engineering, research
and development, complete manufacturing capabilities,
marketing and extensive in-house environmental testing
capabilities. Supporting the Huntington Beach facility is our
privately owned and operated sub-assembly operation located in
Thailand.
Insuring the accuracy, consistency, and overall quality of
Rhombus products is of primary concern. All of our products are
designed and built to meet the most demanding reliability
requirements. We have an extensive quality control program
which incorporates statistical process control and is also in strict
compliance with MIL-I-45208.
For over 30 years, Rhombus has gained unique experience in
providing quality components and innovative designs for users of
magnetic products. Rhombus welcomes custom designs tailored
to unique customer requirements. Our dedicated employees look
forward to proving to you that Rhombus offers the price, delivery
and application support advantages that can address your most
critical needs.
Delay Lines
Passive & Logic Buffered
Description
Page
Passive Delay Line Application Notes ............................... 2
Logic Buffered Delay Line Application Notes ..................... 3
Passive Delay Lines:
Mini 6-Pin SMD .............................. SH6G .................... 4
Single 16-Pin SOIC ........................ AML1 .................... 4
5 Tap 8-Pin DIP/SMD ...................... AMZ ..................... 5
10 Tap 14-Pin DIP/SMD ................... AIZ ...................... 6
10 Tap 14-Pin DIL ........................... TZB ..................... 7
5 Tap 7-Pin SIP ............................... SIP4 ..................... 8
10 Tap 14-Pin SIP ........................... SIP5 ..................... 8
Single Delay 8-Pin SIP .............. SIP8, SL7T ................ 9
Mini SIP 3-Pin ................................. SIL2 ................... 10
10 Tap 28-Pin DIL ............................ TF ..................... 11
Mini SIP 3-Pin ................................. SP3 ................... 11
20 Tap 24-Pin DIP/SMD ................ SP24A ................. 12
For Downloadable Catalogs and Data Sheets, as
well as Complete On-line Magnetic Product
resources please visit us on the web at
High BW, 24-Pin DIP/SMD ............ SP24L .................. 13
Logic Buffered Delay Lines (TTL/FAST, LVC, ACT):
5V, 5 Tap 8-Pin DIP/SMD ............. FAMDM ................ 14
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Cross Reference
Application Notes
5V, 5 Tap 14-Pin DIP/SMD ............ FAIDM ................. 15
5V, 5 Tap 8-Pin SIP ....................... FSIDM ................. 15
5V, 10 Tap 14-Pin DIP/SMD .......... FAITD .................. 16
5V, 5 Tap 8-Pin DIP/SMD ............. ACMDM ................ 17
Part Index
3V, 5 Tap 8-Pin DIP/SMD ............. LVMDM................. 18
with links to data sheets
3V, 10 Tap 14-Pin DIP/SMD .......... LVITD .................. 19
I.C. Guide
Single, Dual, Triple DIP/SMD .......... misc ................... 20
Triple, Quad DIP/SMD ............... FAI3D & 4D ............. 21
Inductor Selction Guide
5V, 5 Tap Wide DIP ....................... DTZM .................. 22
CM Choke Guide
Pulse Width Generator ................ TTLPWG ............... 23
Sales Representatives
Pulse Width Discriminator ............. TTLPD ................. 23
Catalogs
Transformers (Datacomm) Catalog
Mag. Compontents (Power/SMPS) Catalog
Audio Magnetics Catalog
Delay Line Catalog
Gated Oscillators ........................... TTLOS ................. 23
Programmables .............................. PLDM .................. 24
ECL 10K, 10KH Delays:
5 Tap, Single & Triple ......... DECL, FECL, MECL ....... 26
Programmables ............................. PECL3 ................. 27
Test Circuit & Waveform Parameters .............................. 28
P/N Index / Glossary ....................................................... 28
15801 Chemical Lane, Huntington Beach, CA 92649-1595
Phone: (714) 898-0960 z FAX: (714) 896-0971 z www.rhombus-ind.com
Passive Delay Line Design Considerations
A Passive Delay Line is a special purpose Low Pass Filter designed to delay (phase shift) the input signal by a specified
increment of time, and is composed of series inductors and shunt capacitors with values dictated by the line impedance.
Design: This LC network may be used to pass either analog or digital
signals whose bandwidth is compatible with the intended range of
operation for the delay line. A specific delay and impedance, determine
the required LC values of the network:
Reflections, continued: :There are three basic rules relating to reflections in passive delay line applications:
Rt = Zo
1) No reflections at either terminal
of a line which is terminated with
its characteristic impedance.
Lt/N
Ct/2N
Figure 2A.
Ct/2N
Ct/N
2) A reflection, equal in amplitude and of same polarity to the impinging
signal, will occur at the input of a line which is open circuited.
( Rt = infinite, see figures below.)
Figure 1A. Passive Delay Line Schematic Diagram.
Td =
ZO =
Td = Total Delay ( ns )
ZO = Impedance ( Ohms )
Lt = Total Line Inductance ( µH )
Ct = Total Line Capacitance ( pF )
( Lt x Ct )
( Lt / Ct )
PW > 2xTd
Open: Rt =
PW < Td
2xTd
Rise Time: The rise time of a delay line is typically measured from the
10% to 90% points of the leading edge of the output pulse. The measured
output risetime ( tr o ) is a function of the input rise time ( tr i ) and the true
rise time of the delay line ( tr ):
tr =
3) A reflection, equal in amplitude and of opposite polarity to the
impinging signal, will occur at the input of a line which is short
circuited. ( Rt = 0, see figures below.)
tr o2 - tr i2
.35 / tr
N
PW > 2xTd
Short: Rt = 0
2xTd
(Td / tr)1.36
Circuit Considerations: To assure delay accuracy and prevent signal
distortion, care should be taken to properly integrate the passive delay line
into the circuit design. A board trace can load a tap with several picofarads
of capacitance which will increase delay, rise time, distortion and attenuation. The designer should calculate inductance and capacitance values
of the delay line ( Lt , Ct ) to determine if anticipated board loading is
significant. For typical passive delay line applications, the following
design criteria provide optimum performance:
1.
2.
3.
4.
5.
When the delay line is minimally loaded, properly terminated and the input
pulse widths are significantly greater than the line's rise time, attenuation
is given by:
Attenuation (%) = 1 - (Zo / (Zo + DCR))
Operating Specifications - Passive Delay Lines
tr i2 + tr 12 + tr 22 + ... tr N2
Pulse Overshoot (Pos) ................................... 5% to 10%, typical
Pulse Distortion (S) ..................................................... 3% typical
Working Voltage ............................................. 25 VDC maximum
Dielectric Strength ........................................... 100VDC minimum
Insulation Resistance ........................ 1,000 MΩ min. @ 100VDC
Temperature Coefficient ................................. 70 ppm/OC, typical
Bandwidth (fC) ....................................................... 0.35/tr approx.
Operating Temperature Range ............................. -55O to +125OC
Storage Temperature Range ................................ -65O to +150OC
Reflections: Loading at taps should be at least 10 times the characteristic impedance to minimize reflections due to transmission line effects.
The reflected voltage due to a tap loaded by a resistance, RL, is given by
Reflection (%) = 1 - (1 / (1 + Zo/2RL))
In certain applications, mismatches can be used to achieve pulseshaping requirements.
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The line should be properly terminated.
Minimize tap loading. 10 x ZO min. recommended.
Minimize trace lengths to delay line.
Circuit should have massive ground plane.
All common connections should be used.
We encourage you to call and discuss the details of your design with one
of our application engineers. We offer quick turnaround on samples, and
custom versions are available, generally at no cost for existing package
configurations.
Series Connection: Passive delay lines of the same impedance can
be connected input-to-output (cascaded) to optimize rise time and/or
obtain specific delay values. Termination is required only at the output of
the final stage. The rise time of the grouped lines is given by
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2xTd
Figure 4A.
Internal D.C. resistance (DCR)
Dielectric and ground plane losses
Loading effects at taps
Impedance mismatches at terminations
Frequency limitations (BW) of delay line
tro =
PW < Td
2xTd
Attenuation: The output voltage attenuation of a delay line has several
contributing factors:
1.
2.
3.
4.
5.
2xTd
Figure 3A.
An analog delay line's bandwidth (-3dB attenuation) is related to the
network's rise time which is dependent upon the total number (N) of LC
sections. The delay-to-rise time ratio is the figure of merit, or Quality
Factor, used to characterize delay lines. Generally, the greater figure of
merit implies higher number of sections, and therefore higher cost. The
bandwidth for the network, and number of sections follow these approximations:
BW
Rt
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APP1_PAS 2001-01
Logic Buffered Delay Module Design Considerations
Delays up to 1000ns
5V -- TTL / FAST, ACT CMOS
3V -- Low Voltage CMOS, LVC, AC
10K & 10KH ECL
5 & 10 Tap Modules
Single / Dual / Triple / Quad
Programmables 3, 4, 5 & 6 Bit
Pulse Width Control
General: To avoid the difficulties associated with interfacing passive
delay lines with digital integrated circuits, active delay lines have been
developed to provide design flexibility and circuit simplification. Logic
buffered input and outputs prevent the designer from having to contend
with the loading issues of passive circuity, and the related output
waveform transients. Unlike a passive delay line whose output rise time
is proportional to its delay, the active line's output has the edge rate
characteristic of the respective logic family. Similarly, the active delay
modules will have the fan-in & fan-out ratings of that logic family. Thus,
active delay lines can be used to drive a higher number of gates of a
more complicated topology with minimal effect on signal quality or delay
accuracy.
T
1
T
2
T
N-1
T
Gated Oscillator Modules
DIP, Gullwing & J Bend SMD
Military Grade Versions Available
Customs available ... Quick Delivery
Min. PW and BW Limitations, continued: The most significant
attenuation occurs at outputs with higher delay. Some degradation of
the delay accuracy may occur near these limiting conditions, and we
recommend that Delay Modules be evaluated under the intended
operating conditions. There are options for increasing the effective
bandwidth, and we encourage you to contact us regarding designs
where minimum width is an issue.
INPUT
#1
T
Active
Multi-Delay
Schematic
N
INPUT
#N
INPUT
These devices will provide the Digital Design Engineer with simple
modular solutions to a variety of timing requirements which commonly
arise. Buffered Logic delay modules are ideally suited for situtations
where the interval being considered is less than the period of the system
clock, or where a precise timing adjustment is required. Also, by
incorporating the functions of multiplexers or logic gates, active lines
can perform as programmable delays, logic control delays, pulse-width
control units and gated oscillators that will, in many applications, be
capable of completely replacing complex gate arrangements.
These devices are of hybrid construction, combining Integrated Circuitry with Passive Networks utilizing inductive, capacitive, and resistive
elements. Inputs & outputs are internally buffered and compensated for
propagation delays and require no external components to perform their
intended timing function (for ECL devices standard termination of Open
Emitter-Follower Outputs is required).
Delay
IN
N
D0
D1
Delay
Active 3-Bit
Programmable
Delay Line
Schematic
D2
8 to 1
MUX
OUT
Delay
All modules are designed to meet or exceed all applicable environmental requirements of MIL-D-83532, MIL-STD-883, and MIL-STD-202.
Certain families available as MIL-GRADE by adding "M" suffix. Active
delay lines are available in a wide variety of standard package configurations, for both through-hole and surface mount applications: “J” Style
Surface Mount, Auto Insertable (DIP), Gull Wing Style Surface Mount,
and Single-In-Line (SIP).
D7
Minimum Pulse Width and BW Limitations: Although the output rise
time of an active delay line is characteristic of its logic family, the
bandwidth limitation is chiefly due to the rise and fall times of the internal
delay network (see Rise time / BW notes for Passive Delays, pg. 2). This
Low Pass Filter frequency limitation for active delay lines is expressed
as a minimum pulse width that the delay line is guaranteed to pass.
Reducing the input pulse width beneath this minimum typically results
in shrinking output widths and eventually complete suppression.
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T
Edge-to-Edge Relationship: Typically, active delay lines are specified for leading edge delay accuracy. This is a result of the physical
switching properties of integrated circuits. For example, the logic “1”
threshold of TTL devices is 2.0 Vdc minimum, at approximately 50% of
the margin between the typical TTL low and high levels. However, to
reach the TTL logic “0” threshold the negative-going pulse must drop
down to 0.8 Vdc, or about 80% of the total signal amplitude. Because
of this inherent asymmetry and its effect driving the internal delay circuit,
the delay lines output pulse width will typically be less (2 to 3 ns) than
the input pulse width. Rhombus has design variations that control
delays for Leading and/or Trailing edges, and combinations of pulse
polarity, width, and period.
_
P1 P2 P3 E
Active Tapped Delay Line Schematic
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1
Special Requirements: The listings in this catalog are necessarily
limited to the most popular versions; intermediate values are readily
available, simply contact the factory for data sheets and ordering
information. Designs customized to your specific requirements and/or
slight modifications to the existing products are welcome. Rhombus
customarily provides most engineering services for first article samples
at no charge. Please call one of our Applications Engineers today to
discuss your requirement.
sales@rhombus-ind.com
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TEL: (714) 898-0960
FAX: (714) 896-0971
APP1_LOG 2001-01
SH6G Series Mini 6-Pin SMD Passive Delay Modules
IN
1
6
COM
Stable Delay vs.
Temperature: 100 ppm/OC
Operating Temperature
Range -55OC to +125OC
2
5
COM
OUT 3
4
COM
1
6
2
5
3
4
.315
(8.00)
MAX.
.170
(4.32)
MAX.
.010
(0.25)
.020
(0.38)
TYP.
TYP.
.425 (10.80)
.405 (10.29)
DIP version available: SH6D Series
Electrical Specifications at 25OC 1, 2, 3, 4
Dimensions in
Inches (mm)
.270
(6.86)
.286
(7.27)
Standard Impedances: 50, 75, 100 Ω
For other impedances (up to 500Ω)
visit web page or contact factory
Low Distortion LC Network
SH6G Schematic
.100
(2.54)
TYP.
Delay
(ns)
Rise Time
10%-90%
max. (ns)
DCR
max.
(Ohms)
50 Ohm
Part Number
75 Ohm
Part Number
100 Ohm
Part Number
1.0 ± .20
1.5 ± .20
2.0 ± .20
2.5 ± .25
3.0 ± .30
4.0 ± .40
5.0 ± .40
6.0 ± .40
7.0 ± .40
7.5 ± .40
8.0 ± .40
9.0 ± .50
10.0 ± .60
12.0 ± .60
0.70
0.80
0.90
1.00
1.20
1.50
1.80
2.20
2.40
2.50
2.60
2.80
3.00
3.30
0.35
0.35
0.35
0.40
0.40
0.45
0.50
0.55
0.55
0.60
0.75
0.75
0.80
0.85
SH6G-0105
SH6G-0155
SH6G-0205
SH6G-0255
SH6G-0305
SH6G-0405
SH6G-0505
SH6G-0605
SH6G-0705
SH6G-0755
SH6G-0805
SH6G-0905
SH6G-1005
SH6G-1105
SH6G-0107
SH6G-0157
SH6G-0207
SH6G-0257
SH6G-0307
SH6G-0407
SH6G-0507
SH6G-0607
SH6G-0707
SH6G-0757
SH6G-0807
SH6G-0907
SH6G-1007
SH6G-1107
SH6G-0101
SH6G-0151
SH6G-0201
SH6G-0251
SH6G-0301
SH6G-0401
SH6G-0501
SH6G-0601
SH6G-0701
SH6G-0751
SH6G-0801
SH6G-0901
SH6G-1001
SH6G-1101
1. Rise Times are measured 20% to 80% points.
2. Delay Times measured at 50% points of leading edge.
3. Impedance, ZO, tolerance + 10 %
4. Output terminated to ground through RL= ZO
.038
(0.96)
TYP.
AML1 Series Mini 16-Pin 50-mil SMD Passive Delay Modules
Low Distortion LC Network
Stable Delay vs. Temperature: 100 ppm/OC
O
Dimensions in Inches (mm)
.285
(7.24)
.505
(12.83)
MAX.
MAX.
O
Operating Temp. Range -55 C to +125 C
MAX.
TYP.
TYP.
COM
COM
16 15 14 13 12 11 10
3
4
5
6
7
IN
9
8
100%
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TYP.
.025
(0.64)
TYP.
.010
(0.25)
TYP.
.380 (9.65)
.360 (9.14)
Electrical Specifications at 25OC 1, 2, 3, 4 (refer to Notes 1-4 above)
AML1 Schematic
2
.015
(0.38)
.050
(1.27)
.016
(0.41)
1
.205
(5.21)
AML1 Series
Standard Impedances: 50, 75, 100 Ω
For other impedances (up to 500Ω)
visit web page or contact factory
Delay
(ns)
Rise Time
20% - 80%
max. (ns)
DCR
max.
(Ohms)
50 Ohm
Part Number
75 Ohm
Part Number
100 Ohm
Part Number
200 Ohm
Part Number
1.0 ± .20
1.5 ± .20
2.0 ± .20
2.5 ± .20
3.0 ± .20
4.0 ± .20
5.0 ± .25
6.0 ± .30
7.0 ± .30
8.0 ± .30
9.0 ± .30
10 ± .30
12 ± .50
15 ± .70
20 ± 1.0
1.6
1.6
1.6
1.6
1.7
1.7
1.8
2.0
2.2
2.4
2.6
2.8
3.2
3.8
4.8
.20
.30
.40
.50
.60
.70
.80
.85
.90
.95
1.10
1.20
1.50
1.70
2.00
AML1-1-50
AML1-1P5-50
AML1-2-50
AML1-2P5-50
AML1-3-50
AML1-4-50
AML1-5-50
AML1-6-50
AML1-7-50
AML1-8-50
AML1-9-50
AML1-10-50
AML1-12-50
AML1-15-50
AML1-20-50
AML1-1-75
AML1-1P5-75
AML1-2-75
AML1-2P5-75
AML1-3-75
AML1-4-75
AML1-5-75
AML1-6-75
AML1-7-75
AML1-8-75
AML1-9-75
AML1-10-75
AML1-12-75
AML1-15-75
AML1-20-75
AML1-1-10
AML1-1P5-10
AML1-2-10
AML1-2P5-10
AML1-3-10
AML1-4-10
AML1-5-10
AML1-6-10
AML1-7-10
AML1-8-10
AML1-9-10
AML1-10-10
AML1-12-10
AML1-15-10
AML1-20-10
AML1-1-20
AML1-1P5-20
AML1-2-20
AML1-2P5-20
AML1-3-20
AML1-4-20
AML1-5-20
AML1-6-20
AML1-7-20
AML1-8-20
AML1-9-20
AML1-10-20
AML1-12-20
AML1-15-20
AML1-20-20
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SH6G 2001-01
AMZ & AMY Series Passive 5-Tap DIP/SMD Delay Modules
Operating Specifications - Passive Delay Lines
Low Profile 8-Pin Package
for Surface Mount Applications
Pulse Overshoot (Pos) ................................... 5% to 10%, typical
Pulse Distortion (S) ..................................................... 3% typical
Working Voltage .............................................. 25 VDC maximum
Dielectric Strength ........................................... 100VDC minimum
Insulation Resistance ........................ 1,000 MΩ min. @ 100VDC
Temperature Coefficient ................................. 70 ppm/OC, typical
Bandwidth (fC) ....................................................... 0.35/tr approx.
Operating Temperature Range ............................. -55O to +125OC
Storage Temperature Range ................................ -65O to +150OC
Low Distortion LC Network
5 Equal Delay Taps
Fast Rise Time -- BW
0.35 / tr
Standard Impedances: 50 - 75 - 100 - 200 Ω
Stable Delay vs. Temperature: 100 ppm/OC
Operating Temperature Range -55OC to +125OC
Electrical Specifications at 25OC
Delay Tolerances
Note: For SMD Package add "G" of "J" as below to P/N in Table
50 Ohm
Part Number
Rise
Time
(ns)
DCR
max.
(Ohms)
75 Ohm
Part Number
Rise
Time
(ns)
DCR
max.
(Ohms)
100 Ohm
Part Number
Rise
Time
(ns)
DCR
max.
(Ohms)
200 Ohm
Part Number
Rise
Time
(ns)
DCR
max.
(Ohms)
0.5 ± 0.2 AMZ-2.55
AMZ-55
1.0 ± 0.3
AMZ-65
1.2 ± 0.4
AMZ-75
1.4 ± 0.4
1.5 ± 0.5 AMZ-7.55
AMZ-85
1.6 ± 0.5
AMZ-95
1.8 ± 0.5
2.0 ± 0.5 AMZ-105
3.0 ± 0.6 AMZ-155
4.0 ± 1.0 AMZ-205
5.0 ± 1.0 AMZ-255
6.0 ± 1.5 AMZ-305
7.0 ± 1.5 AMZ-355
8.0 ± 1.8 AMZ-405
10.0 ± 2.0 AMZ-505
12.0 ± 2.5 AMZ-605
15.0 ± 3.0 AMZ-755
16.0 ± 3.0 AMZ-805
20.0 ± 3.0 AMZ-1005
1.5
2.0
2.3
2.6
2.8
3.0
3.3
3.4
5.2
6.8
8.5
10.2
11.9
13.6
17.0
20.4
25.5
27.2
34.0
0.4
0.5
0.5
0.6
0.6
0.6
0.7
0.7
0.9
1.0
1.3
1.4
1.5
1.6
2.0
2.2
2.5
2.6
3.0
AMZ-2.57
AMZ-57
AMZ-67
AMZ-77
AMZ-7.57
AMZ-87
AMZ-97
AMZ-107
AMZ-157
AMZ-207
AMZ-257
AMZ-307
AMZ-357
AMZ-407
AMZ-507
AMZ-607
AMZ-757
AMZ-807
AMZ-1007
1.5
2.0
2.3
2.6
2.8
3.0
3.4
3.5
5.2
6.8
8.5
10.2
11.9
13.6
17.0
20.4
25.5
27.2
34.0
0.6
0.6
0.6
0.6
0.8
0.9
0.9
0.9
1.7
1.9
2.1
2.2
2.4
2.7
2.9
3.3
3.6
3.4
3.7
AMZ-2.51
AMZ-51
AMZ-61
AMZ-71
AMZ-7.51
AMZ-81
AMZ-91
AMZ-101
AMZ-151
AMZ-201
AMZ-251
AMZ-301
AMZ-351
AMZ-401
AMZ-501
AMZ-601
AMZ-751
AMZ-801
AMZ-1001
1.5
2.0
2.4
2.8
2.9
3.0
3.4
3.6
5.2
6.8
8.5
10.2
11.9
13.6
17.0
20.4
25.5
27.2
34.0
0.6
0.6
0.7
0.8
0.8
0.8
0.8
0.9
1.8
2.0
2.2
2.4
2.6
2.8
3.1
3.3
3.6
5.0
5.8
AMZ-2.52
AMZ-52
AMZ-62
AMZ-72
AMZ-7.52
AMZ-82
AMZ-92
AMZ-102
AMZ-152
AMZ-202
AMZ-252
AMZ-302
AMZ-352
AMZ-402
AMZ-502
AMZ-602
AMZ-752
AMZ-802
AMZ-1002
1.5
2.0
2.6
2.8
2.9
3.1
3.4
3.6
5.2
6.8
8.5
10.2
11.9
13.6
17.0
20.4
25.5
27.2
34.0
0.9
1.1
1.1
1.1
1.4
1.4
1.4
1.6
2.7
2.8
3.0
3.2
3.4
3.6
5.5
6.2
6.8
7.0
7.8
Total
(ns)
Tap-to-Tap
(ns)
2.5 ± 0.3
5 ± 0.5
6 ± 0.5
7 ± 0.5
7.5 ± 0.5
8 ± 0.5
9 ± 0.5
10 ± 1.0
15 ± 1.0
20 ± 1.0
25 ± 1.25
30 ± 1.5
35 ± 1.75
40 ± 2.0
50 ± 2.5
60 ± 3.0
75 ± 3.75
80 ± 4.0
100 ± 5.0
1, 2, 3
1. Rise Times are measured from 10% to 90% points.
2. Delay Times measured at 50% point of leading edge.
3. Output (100% Tap) terminated to ground through RL=ZO
AMZ Style Schematic
Recommended
for New Designs
COM 20%
8
60%
COM
6
5
7
Dimensions in Inches (mm)
COM 100%
8
7
80%
60%
6
5
.285
(7.24)
MAX.
.505
(12.83)
MAX.
AMY Style Schematic
Per table, substitute
AMY for AMZ in P/N
.020
(0.51) .205
TYP. (5.21)
MAX.
.120
(3.05)
MIN.
1
2
3
4
1
2
3
4
IN
40%
80%
100%
COM
IN
20%
40%
.020
(0.51)
TYP.
.050
(1.27)
TYP.
To Specify SMD: Add Suffix "G" to P/N
.505
(12.83)
MAX.
.020
(0.51)
TYP.
.050
(1.27)
TYP.
.100
(2.54)
TYP.
.205
(5.21)
MAX.
.015
(0.38)
TYP.
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UKRPEXV LQGXVWULHV LQF
G-SMD
.030
(0.76)
TYP.
.300
(7.62)
.365
(9.27)
MAX.
.100
(2.54)
TYP.
To Specify SMD: Add Suffix "J" to P/N
.505
(12.83)
MAX.
.285
(7.24)
MAX.
G-SMD
.010
(0.25)
TYP.
.285
(7.24)
MAX.
.215
(5.46)
MAX.
J-SMD
.008 R
(0.20)
.010
(0.25)
TYP.
.020
(0.51)
TYP.
.430 (10.92)
.400 (10.16)
.050
(1.27)
TYP.
.100
(2.54)
TYP.
.030
(0.76)
TYP.
J-SMD
.285 (7.24)
.260 (6.60)
.020 R
(0.51)
.330 (8.38)
MAX.
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AMZ 2001-01
AIZ Series Passive 10-Tap DIP/SMD Delay Modules
Operating Specifications - Passive Delay Lines
Low Profile 14-Pin Package
DIP & Surface Mount Versions
Low Distortion LC Network
10 Equal Delay Taps, Variety of Footprints
Fast Rise Time -- BW
0.35 / tr
Standard Impedances: 50 - 75 - 100 - 200 Ω
Stable Delay vs. Temperature: 100 ppm/ OC
Operating Temperature Range -55 OC to +125OC
Electrical Specifications at 25OC
Delay Tolerances
Total
(ns)
Tap-to-Tap
(ns)
1, 2, 3
Pulse Overshoot (Pos) ................................... 5% to 10%, typical
Pulse Distortion (S) ..................................................... 3% typical
Working Voltage .............................................. 25 VDC maximum
Dielectric Strength ........................................... 100VDC minimum
Insulation Resistance ........................ 1,000 MΩ min. @ 100VDC
Temperature Coefficient .................................. 70 ppm/OC, typical
Bandwidth (fC) ....................................................... 0.35/tr approx.
Operating Temperature Range ............................. -55O to +125OC
Storage Temperature Range ................................ -65O to +150OC
Note: For Gullwing SMD Package add "G" to P/N in Table
50 Ohm Impedance
Part
Number
Rise
Time
max.
(ns)
DCR
max.
(Ohms)
75 Ohm Impedance
Part
Number
Rise
Time
max.
(ns)
DCR
max.
(Ohms)
100 Ohm Impedance
Part
Number
Rise
Time
max.
(ns)
DCR
max.
(Ohms)
200 Ohm Impedance
Part
Number
Rise
Time
max.
(ns)
DCR
max.
(Ohms)
5 ± 0.50
0.5 ± 0.2
AIZ-55
1.5
0.8
AIZ-57
1.5
0.8
AIZ-51
1.5
0.8
AIZ-52
1.5
0.8
10 ± 1.00
1.0 ± 0.3
AIZ-105
2.0
0.8
AIZ-107
2.0
1.1
AIZ-101
2.0
1.2
AIZ-102
2.0
1.7
15 ± 1.00
1.5 ± 0.5
AIZ-155
3.0
1.0
AIZ-157
3.0
1.3
AIZ-151
3.0
1.4
AIZ-152
3.3
1.9
20 ± 1.00
2.0 ± 0.5
AIZ-205
4.0
1.2
AIZ-207
4.0
1.5
AIZ-201
4.0
1.6
AIZ-202
4.5
2.4
25 ± 1.25
2.5 ± 0.5
AIZ-255
5.0
1.3
AIZ-257
5.0
1.6
AIZ-251
5.0
1.8
AIZ-252
2.6
3.4
30 ± 1.50
3.0 ± 0.6
AIZ-305
6.0
1.4
AIZ-307
6.0
1.9
AIZ-301
6.0
2.0
AIZ-302
7.2
3.7
35 ± 1.75
3.5 ± 1.0
AIZ-355
7.0
1.5
AIZ-357
7.0
2.6
AIZ-351
7.0
2.9
AIZ-352
8.0
4.0
40 ± 2.00
4.0 ± 1.0
AIZ-405
8.0
1.6
AIZ-407
8.0
2.9
AIZ-401
8.0
3.1
AIZ-402
9.1
4.3
50 ± 2.50
5.0 ± 1.0
AIZ-505
10.0
1.8
AIZ-507
10.0
3.2
AIZ-501
10.0
3.5
AIZ-502
11.0
5.6
60 ± 3.00
6.0 ± 1.5
AIZ-605
12.0
2.0
AIZ-607
12.0
3.5
AIZ-601
12.0
3.8
AIZ-602
12.9
6.1
70 ± 3.50
7.0 ± 1.5
AIZ-705
14.0
2.8
AIZ-707
14.0
4.1
AIZ-701
14.0
4.6
AIZ-702
14.8
6.6
75 ± 3.75
7.5 ± 1.5
AIZ-755
15.0
2.9
AIZ-757
15.0
4.5
AIZ-751
15.0
4.8
AIZ-752
15.7
6.8
80 ± 4.00
8.0 ± 1.8
AIZ-805
16.0
3.0
AIZ-807
16.0
4.8
AIZ-801
16.0
5.0
AIZ-802
16.7
7.0
100 ± 5.00
10.0 ± 2.0
AIZ-1005
20.0
3.4
AIZ-1007
20.0
4.9
AIZ-1001
20.0
5.6
AIZ-1002
21.0
8.2
125 ± 6.25
12.5 ± 2.5
AIZ-1255
25.0
3.8
AIZ-1257
25.0
5.6
AIZ-1251
25.0
6.2
AIZ-1252
25.0
9.5
150 ± 7.50
15.0 ± 3.0
AIZ-1505
30.0
4.8
AIZ-1507
30.0
6.3
AIZ-1501
30.0
6.8
AIZ-1502
30.0
9.8
200 ± 10.00 20.0 ± 3.0
AIZ-2005
40.0
5.7
AIZ-2007
40.0
7.3
AIZ-2001
40.0
7.9
AIZ-2002
40.0
9.9
1. Rise Times are measured from 10% to 90% points.
2. Delay Times measured at 50% point of leading edge.
3. Output (100% Tap) terminated to ground through RL=ZO
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AIZ Style Schematic
Dimensions in Inches (mm)
Most Popular Footprint
COM 10%
14
13
30%
50%
70%
12
11
10
.285
(7.24)
MAX.
.785
(19.94)
MAX.
90% COM
9
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.205
.020 (5.21)
(0.51) MAX.
.120
(3.05)
MIN.
1
2
3
4
5
IN
N/C
20%
40%
60%
6
7
80% 100%
.020
(0.51)
TYP.
AIU Style Schematic
14
100% 90%
13
12
80%
70%
60%
50%
11
10
9
8
1
2
3
4
5
6
7
COM
IN
10%
20%
30%
40%
50%
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.365
(9.27)
MAX.
.100
(2.54)
TYP.
.285
(7.24)
.785
(19.94)
MAX.
MAX.
.205
(5.21)
MAX.
G-SMD
www.rhombus-ind.com
.010
(0.25)
TYP.
.300
(7.62)
To Specify G-SMD, Add "G" Suffix to P/N
Examples: AIZ-51G, AIZ-1505G etc.
Per table above,
substitute AIU for AIZ in P/N
COM
.050
(1.27)
TYP.
.008 R
(0.20)
.020
(0.51)
TYP.
.050
(1.27)
TYP.
.100
(2.54)
TYP.
.015
(0.38)
TYP.
.030
(0.76)
TYP.
G-SMD
.008 R
(0.20)
.010
(0.25)
TYP.
.430 (10.92)
.400 (10.16)
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AIZ-01 2001-01
TZB-TYB-TUB Series 10-Tap High Performance Passive Delays
Operating Specifications - Passive Delay Lines
Fast Rise Time, Low DCR
High Bandwidth
Pulse Overshoot (Pos) .................................... 5% to 10%, typical
Pulse Distortion (S) ...................................................... 3% typical
Working Voltage ............................................. 25 VDC maximum
Dielectric Strength .......................................... 100VDC minimum
Insulation Resistance ......................... 1,000 MΩ min. @ 100VDC
Temperature Coefficient ............................... 100 ppm/ OC, typical
Bandwidth (fC) ....................................................... 0.35/tr approx.
Operating Temperature Range ............................ -55O to +125OC
Storage Temperature Range ............................... -65 O to +150OC
0.35 / tr
Low Distortion LC Network
10 Equal Delay Taps
Standard Impedances: 50 - 75 - 100 - 200 Ω
Stable Delay vs. Temperature: 100 ppm/OC
Operating Temperature Range -55OC to +125OC
TZB Style Schematic
TYB Style Schematic
TUB Style Schematic
Most Popular Footprint
Substitute TYB for TZB in P/N
Substitute TUB for TZB in P/N
COM 10%
14
13
30%
50%
70%
12
11
10
1
2
3
4
5
IN
N/C
20%
40%
60%
N/C
90% COM
9
8
6
7
80% 100%
Total
(ns)
Tap-to-Tap
(ns)
5 ± 0.5
10 ± 0.7
20 ± 1.0
25 ± 1.25
30 ± 1.5
40 ± 2.0
50 ± 2.5
60 ± 3.0
70 ± 3.5
80 ± 4.0
90 ± 4.5
100 ± 5.0
150 ± 7.50
200 ± 10.0
250 ± 12.5
300 ± 15.0
400 ± 20.0
500 ± 25.0
0.5 ± 0.2
1.0 ± 0.4
2.0 ± 0.5
2.5 ± 0.5
3.0 ± 0.5
4.0 ± 1.0
5.0 ± 1.0
6.0 ± 1.5
7.0 ± 1.5
8.0 ± 1.8
9.0 ± 2.0
10.0 ± 2.0
15.0 ± 3.0
20.0 ± 3.0
25.0 ± 3.0
30.0 ± 3.0
40.0 ± 5.0
50.0 ± 5.0
13
12
80%
70%
60%
50%
COM
11
10
9
8
14
100% 90%
13
80%
70%
60%
50%
11
10
9
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
IN
10%
20%
30%
40%
COM
COM
IN
10%
20%
30%
40%
50%
Low-profile DIP/SMD versions refer to AIZ Series !!!
50 Ohm
Part Number
Rise
Time
(ns)
DCR
max.
(Ohms)
75 Ohm
Part Number
Rise
Time
(ns)
DCR
max.
(Ohms)
100 Ohm
Part Number
Rise
Time
(ns)
DCR
max.
(Ohms)
200 Ohm
Part Number
Rise
Time
(ns)
DCR
max.
(Ohms)
TZB1-5
TZB6-5
TZB12-5
TZB18-5
TZB24-5
TZB30-5
TZB36-5
TZB42-5
TZB48-5
TZB54-5
TZB60-5
TZB66-5
TZB72-5
TZB78-5
TZB84-5
TZB90-5
TZB94-5
TZB98-5
2.0
3.2
4.0
4.5
5.5
7.0
8.5
10.5
11.0
12.0
14.0
18.0
24.0
34.0
41.0
48.0
65.0
75.0
0.7
0.7
0.7
0.9
1.0
1.2
1.3
1.6
1.7
1.9
2.0
2.1
2.2
2.4
2.4
2.5
2.8
3.3
TZB1-7
TZB6-7
TZB12-7
TZB18-7
TZB24-7
TZB30-7
TZB36-7
TZB42-7
TZB48-7
TZB54-7
TZB60-7
TZB66-7
TZB72-7
TZB78-7
TZB84-7
TZB90-7
TZB94-7
TZB98-7
2.1
3.6
4.4
5.3
5.8
7.5
8.5
11.4
13.0
15.3
17.3
19.5
26.0
38.0
45.0
53.0
66.0
84.0
0.8
0.8
1.3
1.5
1.7
2.0
2.1
2.3
2.5
3.8
3.0
3.1
3.3
3.4
3.5
3.5
3.6
3.7
TZB1-10
TZB6-10
TZB12-10
TZB18-10
TZB24-10
TZB30-10
TZB36-10
TZB42-10
TZB48-10
TZB54-10
TZB60-10
TZB66-10
TZB72-10
TZB78-10
TZB84-10
TZB90-10
TZB94-10
TZB98-10
2.2
3.8
4.6
5.5
5.8
7.5
8.5
11.5
13.0
15.5
17.5
20.0
26.0
39.0
46.0
54.0
67.0
86.0
0.8
0.8
1.5
1.7
2.0
2.2
2.3
2.5
2.8
3.0
3.1
3.2
3.5
3.5
4.0
4.2
4.5
5.0
TZB1-20
TZB6-20
TZB12-20
TZB18-20
TZB24-20
TZB30-20
TZB36-20
TZB42-20
TZB48-20
TZB54-20
TZB60-20
TZB66-20
TZB72-20
TZB78-20
TZB84-20
TZB90-20
−−−−
−−−−
2.4
5.5
8.5
9.0
10.0
13.0
15.5
16.0
17.0
19.0
20.0
24.0
35.0
44.0
56.0
68.0
−−−−
−−−−
0.9
1.0
1.5
1.8
2.0
2.2
2.4
2.5
2.5
2.5
2.5
2.5
3.6
4.8
5.2
5.8
−−−−
−−−−
1. Rise Times are measured from 10% to 90% points.
2. Delay Times measured at 50% points of leading edge.
3. Output (100% Tap) terminated to ground through RL=ZO
P/N Description
Dimensions
in inches (mm)
.300
(7.62)
MAX.
.030
.275
(0.76) (6.99)
TYP. MAX.
Delay Coding Number
Per Table above
Impedance Specifier:
50 Ohms = 5
75 Ohms = 7
100 Ohms = 10
200 Ohms = 20
.120
(3.05)
MIN.
Part Number Examples:
TZB6-10 = 10 ns, 1 ns / tap , 100 Ω, 14-pin
TZB18-7 = 25 ns, 2.5 ns / tap , 75 Ω, 14-pin
TZB98-5 = 500 ns, 50 ns / tap , 50 Ω, 14-pin
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.320 (8.13)
.290 (7.37)
.750
(19.05)
MAX.
TZB XX - XX
Passive 10 Tap Thru-hole
14-pin Delay Module Series
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12
COM
Electrical Specifications at 25OC
Delay Tolerances
100% 90%
14
.050
(1.27)
TYP.
.020
(0.51)
TYP.
.100
(2.54)
TYP.
.010
(0.25)
TYP.
.350 (8.89)
.310 (7.87)
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FAX: (714) 896-0971
TZB 2001-01
SIP4 & SIP5 Series High Performance Passive Delay Modules
Operating Specifications - Passive Delay Lines
Fast Rise Time, Low DCR
High Bandwidth
Pulse Overshoot (Pos) ................................... 5% to 10%, typical
Pulse Distortion (S) ..................................................... 3% typical
Working Voltage ............................................. 25 VDC maximum
Dielectric Strength .......................................... 100VDC minimum
Insulation Resistance ......................... 1,000 MΩ min. @ 100VDC
Temperature Coefficient ............................... 100 ppm/ OC, typical
Bandwidth (fC) ....................................................... 0.35/tr approx.
Operating Temperature Range ............................ -55O to +125OC
Storage Temperature Range ............................... -65 O to +150OC
0.35 / tr
Low Distortion LC Network
5 or 10 Equal Delay Taps
Standard Impedances: 50 - 75 - 100 - 200 Ω
Stable Delay vs. Temperature: 100 ppm/OC
Operating Temperature Range -55OC to +125OC
Electrical Specifications at 25OC
Delay Tolerances
Total
(ns)
SIP4-55
5 ± 0.5 1.0 ± 0.4
10 ± 1.0 2.0 ± 0.5 SIP4-105
15 ± 1.0 3.0 ± 0.6 SIP4-155
20 ± 1.0 4.0 ± 0.8 SIP4-205
25 ± 1.25 5.0 ± 1.0 SIP4-255
30 ± 1.5 6.0 ± 1.5 SIP4-305
40 ± 2.0 8.0 ± 2.0 SIP4-405
50 ± 2.5 10.0 ± 2.0 SIP4-505
75 ± 3.75 15.0 ± 3.5 SIP4-755
100 ± 5.0 20.0 ± 4.0 SIP4-1005
Delay Tolerances
Total
(ns)
Rise
Time
(ns)
DCR
max.
(Ohms)
75 Ohm
5-Tap P/N
Rise
Time
(ns)
DCR
max.
(Ohms)
100 Ohm
5-Tap P/N
Rise
Time
(ns)
DCR
max.
(Ohms)
200 Ohm
5-Tap P/N
Rise
Time
(ns)
DCR
max.
(Ohms)
2.0
4.0
5.5
6.4
8.0
9.0
11.0
14.0
23.0
33.0
0.7
0.7
1.0
1.2
1.3
1.6
1.9
2.1
2.2
2.4
SIP4-57
SIP4-107
SIP4-157
SIP4-207
SIP4-257
SIP4-307
SIP4-407
SIP4-507
SIP4-757
SIP4-1007
2.7
4.4
5.8
7.3
8.0
8.5
15.5
17.8
25.7
34.0
0.8
1.3
1.6
1.7
1.9
2.2
2.7
2.9
3.3
3.6
SIP4-51
SIP4-101
SIP4-151
SIP4-201
SIP4-251
SIP4-301
SIP4-401
SIP4-501
SIP4-751
SIP4-1001
3.0
4.6
5.8
7.5
8.0
8.5
15.5
18.0
26.0
34.0
0.8
1.3
1.6
1.7
1.9
2.2
2.8
3.1
3.4
3.7
SIP4-52
SIP4-102
SIP4-152
SIP4-202
SIP4-252
SIP4-302
SIP4-402
SIP4-502
−
−
3.0
6.3
7.7
9.8
15.5
16.0
17.0
19.0
−
−
0.9
1.5
2.0
2.2
2.4
2.8
3.4
4.0
−
−
Rise
Time
(ns)
DCR
max.
(Ohms)
75 Ohm
10-Tap P/N
Rise
Time
(ns)
DCR
max.
(Ohms)
100 Ohm
10-Tap P/N
Rise
Time
(ns)
DCR
max.
(Ohms)
200 Ohm
10-Tap P/N
Rise
Time
(ns)
DCR
max.
(Ohms)
2.1
3.6
4.1
4.4
5.3
5.8
7.5
8.5
11.4
15.0
19.5
0.8
0.8
1.2
1.3
1.5
1.7
2.0
2.1
2.3
2.8
3.1
SIP5-51
SIP5-101
SIP5-151
SIP5-201
SIP5-251
SIP5-301
SIP5-401
SIP5-501
SIP5-601
SIP5-751
SIP5-1001
2.2
3.8
4.1
4.6
5.5
5.8
7.5
8.5
11.5
15.3
20.0
0.8
0.8
1.3
1.5
1.7
2.0
2.2
2.3
2.5
3.0
3.2
SIP5-52
SIP5-102
SIP5-152
SIP5-202
SIP5-252
SIP5-302
SIP5-402
SIP5-502
SIP5-602
SIP5-752
SIP5-1002
2.4
5.5
6.3
8.5
9.0
10.0
13.4
15.5
16.2
19.1
24.0
0.9
1.0
1.5
1.5
2.2
2.4
3.0
3.3
3.6
3.8
4.4
50 Ohm
5-Tap P/N
Tap-to-Tap
(ns)
50 Ohm
10-Tap P/N
Tap-to-Tap
(ns)
SIP5-57
5 ± 0.5
0.5 ± 0.2 SIP5-55
2.0
0.7
SIP5-107
10 ± 0.7
1.0 ± 0.4 SIP5-105
3.2
0.7
SIP5-157
15 ± 1.0
1.5 ± 0.5 SIP5-155
3.4
0.8
SIP5-207
20 ± 1.0
2.0 ± 0.5 SIP5-205
4.0
0.8
SIP5-257
25 ± 1.25 2.5 ± 0.5 SIP5-255
4.5
0.9
SIP5-307
30 ± 1.5
3.0 ± 0.6 SIP5-305
5.5
1.0
SIP5-407
40 ± 2.0
4.0 ± 1.0 SIP5-405
7.0
1.2
SIP5-507
50 ± 2.5
5.0 ± 1.0 SIP5-505
8.5
1.3
SIP5-607
60 ± 3.0
6.0 ± 1.5 SIP5-605
10.5
1.6
SIP5-757
75 ± 3.75 7.5 ± 1.5 SIP5-755
11.6
1.9
100 ± 5.0 10.0 ± 2.0 SIP5-1005 18.0
2.1 SIP5-1007
1. Rise Times are measured from 10% to 90% points.
2. Delay Times measured at 50% points of leading edge.
3. Output (100% Tap) terminated to ground through RL=ZO
Low-profile DIP/SMD versions
refer to AIZ & AMZ Series !!!
5-Tap SIP4 Style Schematic
1
2
3
4
5
COM
IN
20%
40%
60%
7
6
1
80% 100%
COM
2
3
4
N/C
IN
10%
5
SIP4-101 0102
.100
(2.54)
TYP.
.030
(0.76)
TYP.
.120
(3.05)
MIN.
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7
8
9
50% 60%
10
11
70% 80%
12
SIP5-101
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8
TEL: (714) 898-0960
14
.190
(4.83)
MAX.
.275
(6.99)
MAX.
0102
.020
(0.51)
TYP.
13
90% 100% COM
1.455
(36.96)
MAX.
.275
(6.99)
MAX.
.010
(0.25)
TYP.
6
20% 30% 40%
.200
(5.08)
MAX.
.800
(20.32)
MAX.
.020
(0.51)
TYP.
10-Tap SIP5 Style Schematic
.100
(2.54)
TYP.
.030
(0.76)
TYP.
.010
(0.25)
TYP.
FAX: (714) 896-0971
SIP4-5 2001-01
Electrical Specifications @ 25OC (1, 2, 3)
SIP8 Series
High Performance
Passive Delays
Fast Rise Time, Low DCR
High Bandwidth
0.35 / tr
Low Distortion LC Network
SIngle Precise Delay Output
Standard Impedances: 50 - 75 - 100 - 200 Ω
Stable Delay vs. Temperature: 100 ppm/OC
Operating Temperature Range -55OC to +125OC
SIP8 Style Schematic
Delay
(ns)
Rise Time
max.
(ns)
DCR
max.
(Ohms)
1.0 ± .20
1.5 ± .30
2.0 ± .30
2.5 ± .30
3.0 ± .30
4.0 ± .30
5.0 ± .30
10 ± .50
15 ± .70
20 ± 1.0
25 ± 1.2
30 ± 0.5
50 ± 2.0
100 ± 5.0
200 ± 10
0.8
0.9
1.1
1.1
1.3
1.6
1.8
2.5
3.7
4.6
5.4
6.5
10.0
20.0
44.0
0.8
1.1
1.2
1.3
1.4
1.5
1.5
1.7
2.1
2.4
3.1
4.5
4.5
6.2
7.6
50 Ohm
Impedance
75 Ohm
Impedance
93 Ohm
Impedance
100 Ohm
Impedance
Part Number
Part Number
Part Number
Part Number
SIP8-15
SIP8-1.55
SIP8-25
SIP8-2.55
SIP8-35
SIP8-45
SIP8-55
SIP8-105
SIP8-155
SIP8-205
SIP8-255
SIP8-305
SIP8-505
SIP8-1005
SIP8-2005
SIP8-17
SIP8-1.57
SIP8-27
SIP8-2.57
SIP8-37
SIP8-47
SIP8-57
SIP8-107
SIP8-157
SIP8-207
SIP8-257
SIP8-307
SIP8-507
SIP8-1007
SIP8-2007
SIP8-19
SIP8-1.59
SIP8-29
SIP8-2.59
SIP8-39
SIP8-49
SIP8-59
SIP8-109
SIP8-159
SIP8-209
SIP8-259
SIP8-309
SIP8-509
SIP8-1009
SIP8-2009
SIP8-11
SIP8-1.51
SIP8-21
SIP8-2.51
SIP8-31
SIP8-41
SIP8-51
SIP8-101
SIP8-151
SIP8-201
SIP8-251
SIP8-301
SIP8-501
SIP8-1001
SIP8-2001
Dimensions inches (mm)
1
2
7
8
COM
IN
OUT
COM
.800
(20.32)
MAX.
.200
(5.08)
MAX.
Operating Specifications - Passive Delay Lines
6,3
Pulse Overshoot (Pos) ................................... 5% to 10%, typical
Pulse Distortion (S) ..................................................... 3% typical
Working Voltage .............................................. 25 VDC maximum
Dielectric Strength ........................................... 100VDC minimum
Insulation Resistance ........................ 1,000 MΩ min. @ 100VDC
Temperature Coefficient ............................... 100 ppm/ OC, typical
Bandwidth (fC) ....................................................... 0.35/tr approx.
Operating Temperature Range ............................. -55O to +125OC
Storage Temperature Range ................................ -65O to +150OC
High Performance Delays
SL7T Schematic Diagram
1
2
6
7
IN
COM
COM
OUT
Dimensions inches (mm)
.810
(20.57)
.120
(3.05)
MAX.
MAX.
6/7
.400
(10.16)
.025 MAX.
(0.64)
TYP.
.120
(3.05)
MIN.
.100
(2.54)
.400
(10.16)
TYP.
.020
(0.51)
TYP.
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UKRPEXV LQGXVWULHV LQF
.030
(0.76)
TYP.
.010
(0.25)
TYP.
.010
(0.25)
TYP.
.060
(1.52)
TYP.
.500
(12.70)
MAX.
.
.020
(0.51)
TYP.
Electrical Specifications at 25OC
SL7T Series Thin SIP
Passive Single Output
.275
(6.99)
MAX.
.120
(3.05)
MIN.
.100
(2.54)
TYP.
1, 2, 3
Delay
(ns)
Rise Time
10%-90%
max. (ns)
DCR
max.
(Ohms)
50 Ohm
Impedance
Part Number
75 Ohm
Impedance
Part Number
100 Ohm
Impedance
Part Number
1.0 ± .20
1.5 ± .25
2.0 ± .30
2.5 ± .30
3.0 ± .30
3.5 ± .50
4.0 ± .50
5.0 ± .50
6.0 ± .60
7.0 ± .70
7.5 ± .75
8.0 ± .75
10.0 ± .75
12.5 ± .75
15.0 ± .75
20.0 ± 1.0
25.0 ± 1.25
30.0 ± 1.5
40.0 ± 2.0
50.0 ± 2.5
75.0 ± 3.75
100 ± 5.0
0.8
0.9
1.1
1.1
1.3
1.5
1.6
1.8
1.9
2.1
2.2
2.2
2.5
2.5
2.7
4.6
5.4
6.5
8.5
10.0
15.0
20.0
0.8
1.1
1.2
1.3
1.4
1.5
1.5
1.5
1.5
1.5
1.6
1.6
1.7
1.9
2.1
2.4
2.9
3.0
3.3
3.5
4.8
5.6
SL7T-15
SL7T-1P55
SL7T-25
SL7T-2P55
SL7T-35
SL7T-3P55
SL7T-45
SL7T-55
SL7T-65
SL7T-75
SL7T-7P55
SL7T-85
SL7T-105
SL7T-12P55
SL7T-155
SL7T-205
SL7T-255
SL7T-305
SL7T-405
SL7T-505
SL7T-755
SL7T-1005
SL7T-17
SL7T-1P57
SL7T-27
SL7T-2P57
SL7T-37
SL7T-3P57
SL7T-47
SL7T-57
SL7T-67
SL7T-77
SL7T-7P57
SL7T-87
SL7T-107
SL7T-12P57
SL7T-157
SL7T-207
SL7T-257
SL7T-307
SL7T-407
SL7T-507
SL7T-757
SL7T-1007
SL7T-11
SL7T-1P51
SL7T-21
SL7T-2P51
SL7T-31
SL7T-3P51
SL7T-41
SL7T-51
SL7T-61
SL7T-71
SL7T-7P51
SL7T-81
SL7T-101
SL7T-12P51
SL7T-151
SL7T-201
SL7T-251
SL7T-301
SL7T-401
SL7T-501
SL7T-751
SL7T-1001
1. Rise Times are measured from 10% to 90% points.
2. Delay Times measured at 50% points of leading edge.
3. Output terminated to ground through RL=ZO
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TEL: (714) 898-0960
FAX: (714) 896-0971
SIP8-SL7 2001-01
SIL2 Series Mini-SIP Passive Delay Modules
Operating Specifications - Passive Delay Lines
Fast Rise Time, Low DCR
High Bandwidth
0.35 / tr
Low Distortion LC Network
Tight Delay Tolerance
Standard Impedances: 50 to 200 Ω
Stable Delay vs. Temperature: 100 ppm/OC
Operating Temperature Range -55OC to +125OC
Pulse Overshoot (Pos) ................................... 5% to 10%, typical
Pulse Distortion (S) ..................................................... 3% typical
Working Voltage .............................................. 25 VDC maximum
Dielectric Strength ........................................... 100VDC minimum
Insulation Resistance ........................ 1,000 MΩ min. @ 100VDC
Temperature Coefficient ............................... 100 ppm/ OC, typical
Bandwidth (fC) ....................................................... 0.35/tr approx.
Operating Temperature Range ............................. -55O to +125OC
Storage Temperature Range ................................ -65O to +150OC
Electrical Specifications at 25OC
Delay
(ns)
Rise
Time max.
(ns)
DCR
max.
(Ohms)
50 Ohm
Impedance
Part Number
55 Ohm
Impedance
Part Number
60 Ohm
Impedance
Part Number
75 Ohm
Impedance
Part Number
93 Ohm
Impedance
Part Number
100 Ohm
Impedance
Part Number
200 Ohm
Impedance
Part Number
0.0
1.0 ± .20
1.5 ± .20
2.0 ± .20
2.5 ± .20
3.0 ± .20
4.0 ± .20
5.0 ± .25
6.0 ± .30
7.0 ± .30
8.0 ± .30
9.0 ± .30
10 ± .30
11 ± .40
12 ± .50
13 ± .60
14 ± .70
15 ± .70
16 ± .80
20 ± 1.0
−−
1.6
1.6
1.6
1.6
1.7
1.7
1.8
2.0
2.3
2.7
2.9
3.3
3.8
4.1
4.6
4.9
5.3
5.6
7.0
.10
.20
.30
.40
.50
.60
.70
.80
.85
.90
.95
1.10
1.20
1.40
1.50
1.60
1.60
1.70
1.70
2.00
SIL2-0
SIL2-1-50
SIL2-1.5-50
SIL2-2-50
SIL2-2.5-50
SIL2-3-50
SIL2-4-50
SIL2-5-50
SIL2-6-50
SIL2-7-50
SIL2-8-50
SIL2-9-50
SIL2-10-50
SIL2-11-50
SIL2-12-50
SIL2-13-50
SIL2-14-50
SIL2-15-50
SIL2-16-50
SIL2-20-50
SIL2-0
SIL2-1-55
SIL2-1.5-55
SIL2-2-55
SIL2-2.5-55
SIL2-3-55
SIL2-4-55
SIL2-5-55
SIL2-6-55
SIL2-7-55
SIL2-8-55
SIL2-9-55
SIL2-10-55
SIL2-11-55
SIL2-12-55
SIL2-13-55
SIL2-14-55
SIL2-15-55
SIL2-16-55
SIL2-20-55
SIL2-0
SIL2-1-60
SIL2-1.5-60
SIL2-2-60
SIL2-2.5-60
SIL2-3-60
SIL2-4-60
SIL2-5-60
SIL2-6-60
SIL2-7-60
SIL2-8-60
SIL2-9-60
SIL2-10-60
SIL2-11-60
SIL2-12-60
SIL2-13-60
SIL2-14-60
SIL2-15-60
SIL2-16-60
SIL2-20-60
SIL2-0
SIL2-1-75
SIL2-1.5-75
SIL2-2-75
SIL2-2.5-75
SIL2-3-75
SIL2-4-75
SIL2-5-75
SIL2-6-75
SIL2-7-75
SIL2-8-75
SIL2-9-75
SIL2-10-75
SIL2-11-75
SIL2-12-75
SIL2-13-75
SIL2-14-75
SIL2-15-75
SIL2-16-75
SIL2-20-75
SIL2-0
SIL2-1-93
SIL2-1.5-93
SIL2-2-93
SIL2-2.5-93
SIL2-3-93
SIL2-4-93
SIL2-5-93
SIL2-6-93
SIL2-7-93
SIL2-8-93
SIL2-9-93
SIL2-10-93
SIL2-11-93
SIL2-12-93
SIL2-13-93
SIL2-14-93
SIL2-15-93
SIL2-16-93
SIL2-20-93
SIL2-0
SIL2-1-10
SIL2-1.5-10
SIL2-2-10
SIL2-2.5-10
SIL2-3-10
SIL2-4-10
SIL2-5-10
SIL2-6-10
SIL2-7-10
SIL2-8-10
SIL2-9-10
SIL2-10-10
SIL2-11-10
SIL2-12-10
SIL2-13-10
SIL2-14-10
SIL2-15-10
SIL2-16-10
SIL2-20-10
SIL2-0
SIL2-1-20
SIL2-1.5-20
SIL2-2-20
SIL2-2.5-20
SIL2-3-20
SIL2-4-20
SIL2-5-20
SIL2-6-20
SIL2-7-20
SIL2-8-20
SIL2-9-20
SIL2-10-20
SIL2-11-20
SIL2-12-20
SIL2-13-20
SIL2-14-20
SIL2-15-20
SIL2-16-20
SIL2-20-20
1. Rise Times are measured from 20% to 80% points.
2. Delay Times measured at 50% points of leading edge.
3. Output terminated to ground through RL=ZO
SIL2 Single Output Schematic
"SL2T" Part Number
Examples:
SL2T 2-tap Schematic
SL2T2-50
2 ns (1ns Tap) 50 Ω
1
2
3
IN
COM
OUT
SL2T1.5-55
2.5 ns (1.25ns Tap) 55 Ω
SL2T12-10
12 ns (6ns Tap) 100 Ω
1
2
COM
IN
3
4
Tap1 Tap2
Dimensions in inches (mm)
.120
(3.05)
MAX.
.490
(12.45)
MAX.
SIL2-1-55
0102
.030
(0.76)
TYP.
.100
(2.54)
.200
(5.08)
.120
(3.05)
MIN.
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SL2T-10-20
0102
.375
(9.53)
MAX.
.020
(0.51)
TYP.
.120
(3.05)
MAX.
.490
(12.45)
MAX.
.010
(0.25)
TYP.
.020
(0.51)
TYP.
.060
(1.52)
TYP.
.375
(9.53)
MAX.
.030
(0.76)
TYP.
.100
(2.54)
.120
(3.05)
MIN.
.010
(0.25)
TYP.
.060
(1.52)
TYP.
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SIL2-2T 2001-01
TF Series High Performance 20 Section 10-Tap Delay Lines
Fast Rise Time ( td / tr 10 )
High Bandwidth
0.35 / tr
TF Schematic Diagram
COM
28
27
Stable Delay vs. Temperature: 100 ppm/OC
1
2
Operating Temperature Range -55OC to +125OC
IN
26
25
24
23
22
21
20
3
4
5
6
7
8
9
COM
19
18
17
16
15
10
11
12
13
14
Low Distortion LC Network
10 Equal Delay Taps
Standard Impedances: 50 - 75 - 100 Ω
Electrical Specifications at 25OC
Delay Tolerances
Total
(ns)
Tap-to-Tap
(ns)
50 ± 2.5
75 ± 3.7
80 ± 4.0
100 ± 5.0
120 ± 6.0
150 ± 15.0
200 ± 10.0
250 ± 12.5
300 ± 15.0
400 ± 20.0
500 ± 25.0
5.0 ± 1.0
7.5 ± 2.0
8.0 ± 2.0
10.0 ± 2.0
12.0 ± 2.0
15.0 ± 2.5
20.0 ± 3.0
25.0 ± 3.0
30.0 ± 3.5
40.0 ± 4.0
50.0 ± 5.0
10% 20% 30% 40% 50%
60% 70% 80% 90% 100%
1, 2, 3
50 Ohm
Part Number
Rise
Time
(ns)
DCR
max.
(Ohms)
75 Ohm
Part Number
Rise
Time
(ns)
DCR
max.
(Ohms)
100 Ohm
Part Number
Rise
Time
(ns)
DCR
max.
(Ohms)
TF50-5
TF75-5
TF80-5
TF100-5
TF120-5
TF150-5
TF200-5
TF250-5
TF300-5
TF400-5
TF500-5
6.2
9.2
9.5
11.2
13.4
15.7
21.3
27.2
31.1
41.0
50.8
1.9
2.1
2.2
2.3
2.3
2.4
2.5
2.6
2.7
2.8
2.9
TF50-7
TF75-7
TF80-7
TF100-7
TF120-7
TF150-7
TF200-7
TF250-7
TF300-7
TF400-7
TF500-7
6.2
9.2
9.6
11.7
13.7
16.1
21.5
27.3
31.4
41.3
53.1
2.0
2.2
2.3
2.5
2.7
3.1
3.3
3.5
3.6
3.7
3.9
TF50-10
TF75-10
TF80-10
TF100-10
TF120-10
TF150-10
TF200-10
TF250-10
TF300-10
TF400-10
TF500-10
6.4
9.4
9.9
12.5
13.8
16.4
21.6
27.5
32.3
41.7
54.2
2.2
2.3
2.4
2.7
3.1
3.5
3.8
4.3
4.6
4.8
5.1
1. Rise Times are measured
from 10% to 90% points.
1.450
(36.83)
MAX.
2. Delay Times measured at 50%
points of leading edge.
.030 .275
(0.76) (6.99)
TYP. MAX.
Dimensions
in Inches (mm)
3. Output (100% Tap) terminated
through ZO to ground.
.120
(3.05)
MIN.
.050
(1.27)
TYP.
SP3 Style
Schematic
3-Pin Mini-SIP
Passive Delays
Refer to SIL2 Series
.120
(3.05)
MAX.
63
.375
(9.53)
MAX.
.020
(0.51)
TYP.
.030
(0.76)
TYP.
.100
(2.54)
.120
(3.05)
MIN.
.020
(0.51)
TYP.
.100
(2.54)
TYP.
.010
(0.25)
TYP.
.350 (8.89)
.310 (7.87)
Electrical Specifications at 25OC
SP3 Series
.490
(12.45)
MAX.
.320 (8.13)
.290 (7.37)
.300
(7.62)
MAX.
.010
(0.25)
TYP.
1
2
IN
COM
3
OUT
Part Number Examples:
SP3-2-50 = 2 ns 50 Ω
SP3-2.5-93 = 2.5 ns 93 Ω
SP3-5-10 = 5 ns 100 Ω
SP3-10-20 = 10 ns 200 Ω
.060
(1.52)
TYP.
Delay
(ns)
Rise Time
20% - 80%
max. (ns)
DCR
max.
(Ohms)
1.0 ± .20
1.5 ± .20
2.0 ± .20
2.5 ± .20
3.0 ± .20
3.5 ± .20
4.0 ± .20
4.5 ± .20
5.0 ± .25
6.0 ± .30
7.0 ± .30
7.5 ± .30
8.0 ± .30
10 ± .30
1.6
1.6
1.6
1.6
1.7
1.7
1.7
1.7
1.8
2.0
2.2
2.4
2.4
2.8
.20
.30
.40
.50
.60
.60
.70
.70
.80
.85
.90
.95
.95
1.20
Part Number
Zo: XX= 50, 55,
75, 93, 10 or 20
SP3-1 - XX
SP3-1.5 - XX
SP3-2 - XX
SP3-2.5 - XX
SP3-3 - XX
SP3-3.5 - XX
SP3-4 - XX
SP3-4.5 - XX
SP3-5 - XX
SP3-6 - XX
SP3-7 - XX
SP3-7.5 - XX
SP3-8 - XX
SP3-10 - XX
1. Rise Times are measured from 20% to 80% points.
2. Delay Times measured at 50% points of leading edge.
3. Output (100% Tap) terminated through ZO to ground.
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TF-SP3 2001-01
SP24A Series 20-Tap High Performance Passive Delay Modules
Operating Specifications - Passive Delay Lines
Fast Rise Time, Low DCR
High Bandwidth
Pulse Overshoot (Pos) ................................... 5% to 10%, typical
Pulse Distortion (S) ...................................................... 3% typical
Working Voltage ............................................. 25 VDC maximum
Dielectric Strength .......................................... 100VDC minimum
Insulation Resistance ........................ 1,000 MΩ min. @ 100VDC
Temperature Coefficient ................................. 70 ppm/OC, typical
Bandwidth (fC) ....................................................... 0.35/tr approx.
Operating Temperature Range ............................ -55O to +125OC
Storage Temperature Range ............................... -65 O to +150OC
0.35 / tr
Low Distortion LC Network
20 Equal Delay Taps
Standard Impedances: 50 - 75 - 100 - 200 Ω
Stable Delay vs. Temperature: 100 ppm/OC
Operating Temperature Range -55OC to +125OC
Electrical Specifications 1, 2, 3 at 25OC
Total
(ns)
Tap-to-Tap
(ns)
50 Ohm
Part Number
Note: For SMD Package Add "G" to end of P/N in Table Below
Rise
Time
max. (ns)
DCR
max.
(Ohms)
75 Ohm
Part Number
2.5
1.0
SP24A-107
10 ± 0.50
0.5 ± 0.2 SP24A-105
3.7
1.7
SP24A-207
20 ± 1.00
1.0 ± 0.4 SP24A-205
4.0
1.8
SP24A-257
25 ± 1.25 1.25 ± 0.5 SP24A-255
4.8
1.9
SP24A-307
30 ± 1.50
1.5 ± 0.5 SP24A-305
5.5
2.1
SP24A-407
40 ± 2.00
2.0 ± 0.5 SP24A-405
6.0
2.2
SP24A-507
50 ± 2.50
2.5 ± 0.5 SP24A-505
7.0
2.4
SP24A-607
60 ± 3.00
3.0 ± 0.6 SP24A-605
7.9
2.6
SP24A-707
70 ± 3.50
3.5 ± 0.8 SP24A-705
8.7
2.6
SP24A-757
75 ± 3.75 3.75 ± 0.8 SP24A-755
9.4
2.8
SP24A-807
80 ± 4.00
4.0 ± 1.0 SP24A-805
3.0
SP24A1007
100 ± 5.00
5.0 ± 1.0 SP24A1005 11.8
3.4
SP24A1507
150 ± 7.50
7.5 ± 2.0 SP24A1505 15.5
3.6
SP24A2007
200 ± 10.0 10.0 ± 2.0 SP24A2005 20.0
3.8
SP24A2507
250 ± 12.5 12.5 ± 3.0 SP24A2505 26.0
4.4
SP24A3007
300 ± 15.0 15.0 ± 3.0 SP24A3005 32.0
4.5
SP24A4007
400 ± 20.0 20.0 ± 4.0 SP24A4005 38.0
4.8
SP24A5007
500 ± 25.0 25.0 ± 5.0 SP24A5005 46.0
1. Rise Times are measured from 10% to 90% points.
2. Delay Times measured at 50% points of leading edge.
3. Output (100% Tap) terminated to ground through RL=ZO
Rise
Time
max. (ns)
DCR
max.
(Ohms)
100 Ohm
Part Number
Rise
Time
max. (ns)
DCR
max.
(Ohms)
200 Ohm
Part Number
Rise
Time
max. (ns)
DCR
max.
(Ohms)
2.5
3.7
4.0
4.8
5.5
6.0
7.0
7.9
8.8
9.4
11.9
16.0
18.9
24.5
29.0
38.0
46.0
1.0
1.7
1.8
1.9
2.1
2.2
2.4
2.6
2.6
2.8
3.3
3.7
4.1
4.2
4.5
4.7
4.9
SP24A-101
SP24A-201
SP24A-251
SP24A-301
SP24A-401
SP24A-501
SP24A-601
SP24A-701
SP24A-751
SP24A-801
SP24A1001
SP24A1501
SP24A2001
SP24A2501
SP24A3001
SP24A4001
SP24A5001
2.8
3.7
4.0
4.8
5.5
6.2
7.1
8.1
8.8
9.5
11.9
16.0
18.9
24.5
29.0
38.0
46.0
1.3
1.8
2.1
2.3
2.4
2.6
2.7
2.8
2.9
3.0
3.3
3.7
4.1
4.3
4.8
4.9
5.2
SP24A-102
SP24A-202
SP24A-252
SP24A-302
SP24A-402
SP24A-502
SP24A-602
SP24A-702
SP24A-752
SP24A-802
SP24A1002
SP24A1502
SP24A2002
SP24A2502
SP24A3002
-------
3.5
4.0
4.5
5.0
7.5
9.0
10.0
11.0
11.5
12.0
15.0
23.0
31.0
38.0
46.0
-------
2.5
3.9
4.4
4.8
5.0
5.2
5.3
5.4
5.5
5.7
6.0
7.0
8.1
9.2
9.9
-------
Dimensions in Inches (mm)
Default Thru-hole 24-Pin Package. Example: SP24A-105
SP24A Style 20-Tap Schematic
COM 100% 95% 90% 85% 80% 75% 70% 65% 60% 55% N/C
24
23
22
21
20
19
18
17
16
15
14
13
1.270
(32.30)
.590
(14.99)
MAX.
MAX.
.020 .295
(0.51) (7.49)
TYP.
MAX.
.010
(0.25)
.120
(3.05)
MIN.
1
IN
2
8
9
3
4
10
5
6
7
11 12
5% 10% 15% 20% 25% 30% 35% 40% 45% 50% COM
.018
(0.46)
.040
(1.02)
.100
(2.54)
TYP.
TYP.
TYP.
TYP.
.600
(15.24)
1.270
(32.30)
.590
(14.99)
MAX.
MAX.
Alternate Pinout, Similar 20 Tap
Electricals, refer to Series SP24
.295
(7.49)
MAX.
Also, for same 24-Pin package and
Single Output refer to Series SP24L
.018
(0.46)
.040
(1.02)
.100
(2.54)
TYP.
TYP.
TYP.
.022
(0.56)
TYP.
.080
(2.03)
.737
(18.72)
.010
(0.25)
TYP.
Gull wing SMD Package Add suffix "G" to P/N. Example: SP24A-105G
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SP24A 2001-01
SP24L Series 24-Pin Single Output Passive Delay Modules
Optimized for Fastest Rise times and Lowest DCR in single configuration
Fast Rise Time, Low DCR
Operating Specifications - Passive Delay Lines
Better than 10/1 Td/tr typical
Pulse Overshoot (Pos) ................................... 5% to 10%, typical
Pulse Distortion (S) ..................................................... 3% typical
Working Voltage .............................................. 25 VDC maximum
Dielectric Strength ........................................... 100VDC minimum
Insulation Resistance ........................ 1,000 MΩ min. @ 100VDC
Temperature Coefficient ................................. 70 ppm/OC, typical
Bandwidth (fC) ....................................................... 0.35/tr approx.
Operating Temperature Range ............................. -55O to +125OC
Storage Temperature Range ................................ -65O to +150OC
High Bandwidth
0.35 / tr
Low Distortion LC Network
Standard Impedances: 50 - 75 - 100 Ω
Stable Delay vs. Temperature: 100 ppm/ OC
Operating Temperature Range -55 OC to +125OC
Electrical Specifications 1, 2, 3 at 25OC
Note: For SMD Package Add "G" to end of P/N in Table Below
50 Ohm
Part Number
Rise
Time
max. (ns)
DCR
max.
(Ohms)
75 Ohm
Part Number
Rise
Time
max. (ns)
DCR
max.
(Ohms)
100 Ohm
Part Number
Rise
Time
max. (ns)
DCR
max.
(Ohms)
50 ± 2.50
SP24L-505
5.2
1.5
SP24L-507
5.2
1.8
SP24L-501
5.2
2.0
75 ± 3.75
SP24L-755
7.1
1.9
SP24L-757
7.1
2.2
SP24L-751
7.3
2.3
100 ± 5.00
SP24L1005
9.2
2.4
SP24L1007
9.3
2.6
SP24L1001
9.4
2.6
150 ± 7.50
SP24L1505
13.8
2.5
SP24L1507
14.0
2.7
SP24L1501
14.0
2.7
200 ± 10.0
SP24L2005
16.5
2.6
SP24L2007
16.5
2.9
SP24L2001
16.5
2.9
250 ± 12.5
SP24L2505
22.0
2.9
SP24L2507
22.0
3.4
SP24L2501
22.0
3.5
300 ± 15.0
SP24L3005
22.4
3.1
SP24L3007
22.6
3.7
SP24L3001
22.8
3.9
400 ± 20.0
SP24L4005
34.0
3.8
SP24L4007
35.0
4.8
SP24L4001
36.0
4.9
500 ± 25.0
SP24L5005
42.0
4.8
SP24L5007
42.0
5.8
SP24L5001
42.0
6.2
750 ± 37.5
SP24L7505
69.0
6.4
SP24L7507
69.0
7.1
SP24L7501
69.0
7.2
1000 ± 50.0
SP24L10005
94.0
7.2
SP24L10007
94.0
8.8
SP24L10001
94.0
9.6
1200 ± 60.0
SP24L12005
110.0
8.3
SP24L12007
111.0
9.8
SP24L12001
112.0
10.4
Delay (ns)
1. Rise Times are measured from 10% to 90% points.
2. Delay Times measured at 50% points of leading edge.
3. Output (100% Tap) terminated to ground through RL=ZO
Dimensions in Inches (mm)
SP24L Style Single Output Schematic
Default Thru-hole 24-Pin Package Example: SP24L1001
COM OUT
24
23
22
21
20
19
18
17
16
15
14
13
1.270
(32.30)
.590
(14.99)
MAX.
MAX.
.020 .295
(0.51) (7.49)
TYP.
1
2
N/C
IN
3
4
5
6
7
8
9
10
11
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.010
(0.25)
.120
(3.05)
12
COM
MIN.
.018
(0.46)
.040
(1.02)
.100
(2.54)
TYP.
TYP.
TYP.
For similar package, alternate
schematic style with only one
common connection (pin 24 = N/C)
at pin 12, refer to Series SP241
For 20 Tap versions in the same
24-Pin package, refer to Series
SP24A & SP24A
MAX.
TYP.
.600
(15.24)
1.270
(32.30)
.590
(14.99)
MAX.
MAX.
.295
(7.49)
MAX.
.018
(0.46)
.040
(1.02)
.100
(2.54)
TYP.
TYP.
TYP.
.022
(0.56)
TYP.
.080
(2.03)
.737
(18.72)
.010
(0.25)
TYP.
Gull wing SMD Package Add suffix "G" to P/N. Example: SP24L1001G
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SP24L 2001-01
FAMDM Series FAST / TTL Buffered 5-Tap Delay Modules
Low Profile 8-Pin Package
Two Surface Mount Versions
Electrical Specifications at 25OC
FAST/TTL Logic Buffered
5 Equal Delay Taps
Operating Temperature
Range 0OC to +70OC
14-Pin Versions: FAMDM Series
SIP Versions: FSIDM Series
Low Voltage CMOS Versions
refer to LVMDM / LVIDM Series
FAMDM 8-Pin Schematic
Vcc
8
1
IN
Tap1 Tap3 Tap5
7
6
2
3
5
4
Tap2 Tap4
GND
Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns)
FAST 5 Tap
8-Pin DIP P/N
Tap 1
Tap 2
Tap 3
Tap 4
Total - Tap 5
FAMDM-7
FAMDM-9
FAMDM-11
FAMDM-13
FAMDM-15
FAMDM-20
FAMDM-25
FAMDM-30
FAMDM-35
FAMDM-40
FAMDM-50
FAMDM-60
FAMDM-75
FAMDM-100
FAMDM-125
FAMDM-150
FAMDM-200
FAMDM-250
FAMDM-350
FAMDM-500
3.0
3.0
3.0
3.0
3.0
4.0
5.0
6.0
7.0
8.0
10.0
12.0
15.0
20.0
25.0
30.0
40.0
50.0
70.0
100.0
4.0
4.5
5.0
5.5
6.0
8.0
10.0
12.0
14.0
16.0
20.0
24.0
30.0
40.0
50.0
60.0
80.0
100.0
140.0
200.0
5.0
6.0
7.0
8.0
9.0
12.0
15.0
18.0
21.0
24.0
30.0
36.0
45.0
60.0
75.0
90.0
120.0
150.0
210.0
300.0
6.0
7.5
9.0
10.5
12.0
16.0
20.0
24.0
28.0
32.0
40.0
48.0
60.0
80.0
100.0
120.0
160.0
200.0
280.0
400.0
7 ± 1.0
9 ± 1.0
11 ± 1.0
13 ± 1.5
15 ± 1.5
20 ± 2.0
25 ± 2.0
30 ± 2.0
35 ± 2.0
40 ± 2.0
50 ± 2.5
60 ± 3.0
75 ± 3.75
100 ± 5.0
125 ± 6.25
150 ± 7.5
200 ± 10.0
250 ± 12.5
350 ± 17.5
500 ± 25.0
Tap-to-Tap
(ns)
∗∗ 1 ± 0.5
∗∗ 1.5 ± 0.5
∗∗ 2 ± 0.7
∗∗ 2.5 ± 1.0
3 ± 1.0
4 ± 1.5
5 ± 2.0
6 ± 2.0
7 ± 2.0
8 ± 2.0
10 ± 2.0
12 ± 2.0
15 ± 2.5
20 ± 3.0
25 ± 3.0
30 ± 3.0
40 ± 4.0
50 ± 5.0
70 ± 5.0
100 ± 10.0
** These part numbers do not have 5 equal taps. Tap-to-Tap Delays reference Tap 1.
TEST CONDITIONS -- FAST / TTL
VCC Supply Voltage ................................................ 5.00VDC
Input Pulse Voltage ................................................... 3.20V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25OC
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 10pf probe and fixture load on output under test.
Dimensions in Inches (mm)
.020
(0.51) .250
TYP. (6.35)
MAX.
DIP
.120
(3.05)
MIN.
OPERATING SPECIFICATIONS
VCC Supply Voltage ................................... 5.00 ± 0.25 VDC
ICC Supply Current .................................... 48 mA Maximum
Logic “1” Input: VIH ....................... 2.00 V min., 5.50 V max.
IIH .............................. 20 µA max. @ 2.70V
Logic “0” Input: VIL .......................................... 0.80 V max.
IIL ............................................. -0.6 mA mA
VOH Logic “1” Voltage Out .................................. 2.40 V min.
VOL Logic “0” Voltage Out ............................... 0.50 V max.
PWI Input Pulse Width ............................. 40% of Delay min.
Operating Temperature Range ............................ 0O to 70OC
Storage Temperature Range ...................... -65O to +150OC
P/N Description
.020 .050
(0.51) (1.27)
TYP. TYP.
G-SMD
.020 .050
(0.51) (1.27)
TYP. TYP.
FAMDM - XXX X
J-SMD
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.020 .050
(0.51) (1.27)
TYP. TYP.
.100
(2.54)
TYP.
.300
(7.62)
.010
(0.25)
TYP.
.285
(7.24)
MAX.
.250
(6.35)
MAX.
.015
(0.38)
TYP.
G-SMD
.030
(0.76)
TYP.
.430 (10.92)
.400 (10.16)
.008 R
(0.20)
.010
(0.25)
TYP.
.285
(7.24)
MAX.
.505
(12.83)
MAX.
Examples: FAMDM-25G = 25ns (5ns per tap)
74F, 8-Pin G-SMD
FAMDM-100 = 100ns (20ns per tap)
74F, 8-Pin DIP
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.100
(2.54)
TYP.
DIP
.365
(9.27)
MAX.
.100
(2.54)
TYP.
.505
(12.83)
MAX.
Buffered 5 Tap Delay
Molded Package Series:
8-pin DIP: FAMDM
Total Delay in nanoseconds (ns)
Lead Style: Blank = Thru-hole
G = “Gull Wing” SMD
J = “J” Bend SMD
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.285
(7.24)
MAX.
.505
(12.83)
MAX.
.265
(6.73)
MAX.
.030
(0.76)
TYP.
J-SMD
.285 (7.24)
.260 (6.60)
.330 (8.38)
MAX.
.020 R
(0.51)
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FAMDM 2001-01
FAIDM / FSIDM Series FAST / TTL Buffered 5-Tap Delay Modules
Electrical Specifications at 25OC
FAIDM 14-Pin Schematic
Vcc
Tap1
Tap3
Tap5
14
12
10
8
1
4
6
7
IN
Tap2
Tap4
GND
FSIDM 8-Pin SIP Schematic
1
2
Vcc
IN
3
4
6
5
7
8
Tap1 Tap2 Tap3 Tap4 Tap5 GND
P/N Description
FXIDM - XXX X
Logic 5 Tap Delay
Molded Package Series:
14-pin DIP: FAIDM
8-pin SIP: FSIDM
Total Delay in nanoseconds (ns)
Lead Style: Blank = Thru-hole
G = “Gull Wing” SMD (FAIDM Only)
Tap Delay Tolerances +/- 5% or 2ns
74F 5-Tap
14-Pin DIP
74F 5-Tap
8-Pin SIP
Tap 1
Tap 2
Tap 3
Tap 4
Tap 5
FAIDM-7
FAIDM-9
FAIDM-11
FAIDM-13
FAIDM-15
FAIDM-20
FAIDM-25
FAIDM-30
FAIDM-35
FAIDM-40
FAIDM-45
FAIDM-50
FAIDM-60
FAIDM-75
FAIDM-80
FAIDM-100
FAIDM-125
FAIDM-150
FAIDM-200
FAIDM-250
FAIDM-300
FAIDM-350
FAIDM-400
FAIDM-500
FSIDM-7
FSIDM-9
FSIDM-11
FSIDM-13
FSIDM-15
FSIDM-20
FSIDM-25
FSIDM-30
FSIDM-35
FSIDM-40
FSIDM-45
FSIDM-50
FSIDM-60
FSIDM-75
FSIDM-80
FSIDM-100
FSIDM-125
FSIDM-150
FSIDM-200
FSIDM-250
FSIDM-300
FSIDM-350
---------
3.0
3.0
3.0
3.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
12.0
15.0
16.0
20.0
25.0
30.0
40.0
50.0
60.0
70.0
80.0
100.0
4.0
4.5
5.0
5.5
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
24.0
30.0
32.0
40.0
50.0
60.0
80.0
100.0
120.0
140.0
160.0
200.0
5.0
6.0
7.0
8.0
9.0
12.0
15.0
18.0
21.0
24.0
27.0
30.0
36.0
45.0
48.0
60.0
75.0
90.0
120.0
150.0
180.0
210.0
240.0
300.0
6.0
7.5
9.0
10.5
12.0
16.0
20.0
24.0
28.0
32.0
36.0
40.0
48.0
60.0
64.0
80.0
100.0
120.0
160.0
200.0
240.0
280.0
160.0
400.0
7 ± 1.0
9 ± 1.0
11 ± 1.0
13 ± 1.5
15 ± 1.5
20 ± 2.0
25 ± 2.0
30 ± 2.0
35 ± 2.0
40 ± 2.0
45 ± 2.25
50 ± 2.50
60 ± 3.0
75 ± 3.75
80 ± 4.0
100 ± 5.0
125 ± 6.25
150 ± 7.5
200 ± 10.0
250 ± 12.5
300 ± 15.0
350 ± 17.5
400 ± 20.0
500 ± 25.0
Examples: FAIDM-25G = 25ns (5ns per tap)
74F, 14-Pin G-SMD
FAIDM-100 = 100ns (20ns per tap)
74F, 14-Pin DIP
FSIDM-50 =
50ns (10ns per tap)
74F, 8-Pin SIP
FSIDM Series
Molded 8-Pin SIP Package
.010
(0.25)
TYP.
.285
(7.24)
MAX.
.100
(2.54)
TYP.
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UKRPEXV LQGXVWULHV LQF
.015
(0.38)
TYP.
.020
(0.51)
TYP.
.050
(1.27)
TYP.
.100
(2.54)
TYP.
FAIDM Series 14-Pin Gullwing-SMD
per Table above add "G" suffix to P/N
.250
.020 (6.35)
(0.51) MAX.
.050
(1.27)
TYP.
.280
(7.11)
MAX.
.120
(3.05)
MIN.
.155 (3.94)
.145 (3.68)
FAIDM Series 14-Pin DIP Package
.785
(19.94)
MAX.
1.0 ± 0.4
1.5 ± 0.5
2.0 ± 0.7
2.5 ± 1.0
3 ± 1.0
4 ± 1.5
5 ± 2.0
6 ± 2.0
7 ± 2.0
8 ± 2.0
9 ± 2.0
10 ± 2.0
12 ± 2.0
15 ± 2.5
16 ± 2.5
20 ± 3.0
25 ± 3.0
30 ± 3.0
40 ± 4.0
50 ± 5.0
60 ± 6.0
70 ± 7.0
80 ± 8.0
100 ± 10
.810
(20.57)
MAX.
.180
(4.57)
MAX.
VCC Supply Voltage ................................... 5.00 ± 0.25 VDC
ICC Supply Current .................................... 48 mA Maximum
Logic “1” Input: VIH ....................... 2.00 V min., 5.50 V max.
IIH ............................... 20 µA max. @ 2.70V
Logic “0” Input: VIL ........................................... 0.80 V max.
IIL ............................................ -0.6 mA mA
VOH Logic “1” Voltage Out .................................. 2.40 V min.
VOL Logic “0” Voltage Out ................................ 0.50 V max.
PWI Input Pulse Width ............................. 40% of Delay min.
Operating Temperature Range ........................... 0O to 70OC
Storage Temperature Range ..................... -65O to +150OC
.020
(0.51)
TYP.
∗∗
∗∗
∗∗
∗∗
DImensions in Inches (mm)
OPERATING SPECIFICATIONS
.120
(3.05)
MIN.
Tap-to-Tap
(ns)
FAIDM-xxxG
.008 R
(0.20)
.300
(7.62)
.365
(9.27)
MAX.
.285
(7.24)
.785
(19.94)
MAX.
MAX.
.250
(6.35)
MAX.
G-SMD
.010
(0.25)
TYP.
.020
(0.51)
TYP.
.050
(1.27)
TYP.
.100
(2.54)
TYP.
.015
(0.38)
TYP.
G-SMD
.030
(0.76)
TYP.
.008 R
(0.20)
.010
(0.25)
TYP.
.430 (10.92)
.400 (10.16)
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F_IDM 2001-01
FAITD Series FAST / TTL Buffered 10-Tap Delay Modules
Electrical Specifications at 25OC
Low Profile 14-Pin Package
Two Surface Mount Versions
FAST 10 Tap
14-Pin P/N
FAST/TTL Logic Buffered
10 Equal Delay Taps
Operating Temperature
Range 0OC to +70OC
Low Voltage CMOS Versions
refer to LVITD Series
FAITD Schematic
Vcc
14
Tap1 Tap3 Tap5 Tap7 Tap9 Tap10
13
1
2
IN
N/C
12
11
10
9
8
3
4
5
6
7
Tap2 Tap4 Tap6 Tap8 GND
Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <15ns)
Tap 1
Tap 2
Tap 3
Tap 4
Tap 5
Tap 6
Tap 7
Tap 8
Tap 9
Total - Tap 10
Tap-to-Tap
(ns)
FAITD-12
3
4
5
6
7
8
9
10
11
12 ± 1.0 ∗∗ 1.0 ± 0.5
FAITD-15
3
3.5
4.5
6
7.5
9
10.5
12
13.5
15 ± 1.0 ∗∗ 1.5 ± 0.6
FAITD-20
3
4
6
8
10
12
14
16
18
20 ± 1.5 ∗∗ 2.0 ± 0.7
FAITD-25
3
5
7.5
10
12.5
15
17.5
20
22.5
25 ± 2.0 ∗∗ 2.5 ± 0.8
FAITD-30
3
6
9
12
15
18
21
24
27
30 ± 2.0
3.0 ± 1.0
FAITD-35
3.5
7
10.5
14
17.5
21
24.5
28
31.5
35 ± 2.0
3.5 ± 1.0
FAITD-40
4
8
12
16
20
24
28
32
36
40 ± 2.0
4.0 ± 1.0
FAITD-50
5
10
15
20
25
30
35
40
45
50 ± 2.5
5.0 ± 2.0
FAITD-60
6
12
18
24
30
36
42
48
54
60 ± 3.0
6.0 ± 2.0
FAITD-70
7
14
21
28
35
42
49
56
63
70 ± 3.5
7.0 ± 2.0
FAITD-75
7.5
15
22.5
30
37.5
45
52.5
60
67.5
75 ± 3.75
7.5 ± 2.0
FAITD-80
8
16
24
32
40
48
56
64
72
80 ± 4.0
8.0 ± 2.0
FAITD-100
10
20
30
40
50
60
70
80
90
100 ± 5.0
10 ± 2.0
FAITD-125 12.5
25
37.5
50
62.5
75
87.5
100 112.5 125 ± 6.25 12.5 ± 3.0
FAITD-150
15
30
45
60
75
90
105
120
135
150 ± 7.5
15 ± 3.0
FAITD-200
20
40
60
80
100
120
140
160
180 200 ± 10.0
20 ± 3.0
FAITD-250
25
50
75
100
125
150
175
200
225 250 ± 12.5
25 ± 3.0
FAITD-300
30
60
90
120
150
180
210
240
270 300 ± 15.0
30 ± 5.0
FAITD-500
50
100
150
200
250
300
350
400
450 500 ± 25.0
50 ± 6.0
** These part numbers do not have 5 equal taps. Tap-to-Tap Delays reference Tap 1.
TEST CONDITIONS -- FAST / TTL
VCC Supply Voltage ................................................ 5.00VDC
Input Pulse Voltage ................................................... 3.20V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25OC
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 10pf probe and fixture load on output under test.
Dimensions in Inches (mm)
.285
(7.24)
MAX.
.785
(19.94)
MAX.
.250
.020 (6.35)
(0.51) MAX.
DIP
.120
(3.05)
MIN.
OPERATING SPECIFICATIONS
VCC Supply Voltage ................................... 5.00 ± 0.25 VDC
ICC Supply Current ......................... 25mA typ., 50 mA Max.
Logic “1” Input: VIH ....................... 2.00 V min., 5.50 V max.
IIH .............................. 20 µA max. @ 2.70V
Logic “0” Input: VIL .......................................... 0.80 V max.
IIL ............................................. -0.6 mA mA
VOH Logic “1” Voltage Out .................................. 2.40 V min.
VOL Logic “0” Voltage Out ............................... 0.50 V max.
PWI Input Pulse Width ............................. 20% of Delay min.
Operating Temperature Range ............................ 0O to 70OC
Storage Temperature Range ...................... -65O to +150OC
P/N Description
FAITD - XXX X
.020
(0.51)
TYP.
FAITD-100 =
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UKRPEXV LQGXVWULHV LQF
.285
(7.24)
MAX.
.250
(6.35)
MAX.
.100
(2.54)
TYP.
.015
(0.38)
TYP.
.265
(6.73)
MAX.
J-SMD
.020
(0.51)
TYP.
.050
(1.27)
TYP.
.030
(0.76)
TYP.
G-SMD
.008 R
(0.20)
.010
(0.25)
TYP.
.430 (10.92)
.400 (10.16)
.285
(7.24)
MAX.
.785
(19.94)
MAX.
75ns (7.5ns per tap)
74F, 14-Pin G-SMD
100ns (10ns per tap)
74F, 14-Pin DIP
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.050
(1.27)
TYP.
.010
(0.25)
TYP.
.365
(9.27)
MAX.
.100
(2.54)
TYP.
G-SMD
.020
(0.51)
TYP.
.008 R
(0.20)
.300
(7.62)
.785
(19.94)
MAX.
Buffered 10 Tap Delay
Molded Package Series:
14-pin DIP: FAITD
Total Delay in nanoseconds (ns)
Lead Style: Blank = Thru-hole
G = “Gull Wing” SMD
J = “J” Bend SMD
Examples: FAITD-75G =
.050
(1.27)
TYP.
DIP
.100
(2.54)
TYP.
.030
(0.76)
TYP.
J-SMD
.285 (7.24)
.260 (6.60)
.020 R
(0.51)
.330 (8.38)
MAX.
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FAITD 2001-01
ACMDM Series Advanced CMOS Logic Buffered 5-Tap Delay Modules
74ACT type input is compatible with TTL
Low Profile 8-Pin Package
Two Surface Mount Versions
Available in Low Voltage CMOS
74LVC Logic version LVMDM Series
5 Equal Delay Taps
Operating Temp. -40OC to +85OC
ACMDM 8-Pin Schematic
Vcc
Tap1 Tap3 Tap5
8
7
6
5
1
2
3
4
IN
Tap2 Tap4
Outputs can Source / Sink 24 mA
Electrical Specifications at 25OC
Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns)
74ACT 5 Tap
8-Pin DIP P/N
Tap 1
Tap 2
Tap 3
Tap 4
Total - Tap 5
ACMDM-30
ACMDM-35
ACMDM-40
ACMDM-50
ACMDM-60
ACMDM-75
ACMDM-80
ACMDM-100
ACMDM-125
ACMDM-150
ACMDM-200
ACMDM-250
6.0
7.0
8.0
10.0
12.0
15.0
16.0
20.0
25.0
30.0
40.0
50.0
12.0
14.0
16.0
20.0
24.0
30.0
32.0
40.0
50.0
60.0
80.0
100.0
18.0
21.0
24.0
30.0
36.0
45.0
48.0
60.0
75.0
90.0
120.0
150.0
24.0
28.0
32.0
40.0
48.0
60.0
64.0
80.0
100.0
120.0
160.0
200.0
30 ± 2.0
35 ± 2.0
40 ± 2.0
50 ± 2.5
60 ± 3.0
75 ± 3.75
80 ± 4.0
100 ± 5.0
125 ± 6.25
150 ± 7.5
200 ± 10.0
250 ± 12.5
Tap-to-Tap
(ns)
6 ± 2.0
7 ± 2.0
8 ± 2.0
10 ± 2.0
12 ± 2.0
15 ± 2.5
16 ± 3.0
20 ± 3.0
25 ± 3.0
30 ± 3.0
40 ± 4.0
50 ± 5.0
GND
TEST CONDITIONS -- Advanced CMOS, 74ACT
Dimensions in Inches (mm)
VCC Supply Voltage ................................................ 5.00VDC
Input Pulse Voltage ................................................... 3.00V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25OC
2. Delay Times measured at 1.50V level of input to
+2.50V level of Output on leading edge.
3. Rise Times measured from 10% to 90% points.
4. 50pf probe and fixture load on output under test.
.120
(3.05)
MIN.
.020 .050
(0.51) (1.27)
TYP. TYP.
Supply Voltage, VCC ...................................... 5.00 ± 0.50 VDC
Supply Current, ICC ........................... 14 mA typ., 28 mA max.
ICCH, VIN = VCC, VCC = 5.5V ............................. 40 µA typ.
ICCL, VIN = 0V, VCC = 5.5V ............................. 25 mA typ.
Logic “1” Input: VIH ........................... 2.00 V min., 5.50V max.
Logic “0” Input: VIL .............................................. 0.80 V max.
Logic “1” Voltage Out, VOH ...................................... 3.8 V min.
Logic “0” Voltage Out, VOL ................................... 0.44 V max.
Max. Input Current, IIN ................................................ ± 1.0 µA
Minimum Input Pulse Width ........................ 40% of Delay min.
Operating Temperature Range ......................... -40O to +85OC
Storage Temperature Range ......................... -65O to +150OC
G-SMD
.020 .050
(0.51) (1.27)
TYP. TYP.
J-SMD
.020 .050
(0.51) (1.27)
TYP. TYP.
Examples: ACMDM-25G = 25ns (5ns per tap) 74ACT, 8-Pin G-SMD
ACMDM-100 = 100ns (20ns per tap) 74ACT, 8-Pin DIP
UKRPEXV LQGXVWULHV LQF
.100
(2.54)
TYP.
.300
(7.62)
.010
(0.25)
TYP.
.285
(7.24)
MAX.
.250
(6.35)
MAX.
.015
(0.38)
TYP.
G-SMD
.030
(0.76)
TYP.
.430 (10.92)
.400 (10.16)
.008 R
(0.20)
.010
(0.25)
TYP.
.285
(7.24)
MAX.
.505
(12.83)
MAX.
74ACT Buffered 5 Tap Delay
Molded Package Series:
8-pin DIP: ACMDM
Total Delay in nanoseconds (ns)
Lead Style: Blank = Thru-hole
G = “Gull Wing” SMD
J = “J” Bend SMD
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.100
(2.54)
TYP.
DIP
.365
(9.27)
MAX.
.100
(2.54)
TYP.
.505
(12.83)
MAX.
ACMDM - XXX X
6SHFLILFDWLRQV VXEMHFW WR FKDQJH ZLWKRXW QRWLFH
.020
(0.51) .250
TYP. (6.35)
MAX.
DIP
OPERATING SPECIFICATIONS
P/N Description
.285
(7.24)
MAX.
.505
(12.83)
MAX.
.265
(6.73)
MAX.
.030
(0.76)
TYP.
J-SMD
.285 (7.24)
.260 (6.60)
.330 (8.38)
MAX.
.020 R
(0.51)
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ACMDM 2001-01
LVMDM Series LVC Low Voltage Logic
Buffered 5-Tap Delay SMD Modules
Low Profile 8-Pin Package
Two Surface Mount Versions
Low Voltage CMOS 74LVC
Logic Buffered
5 Equal Delay Taps
Operating Temp. -40OC to +85OC
LVMDM 8-Pin Schematic
Vcc
8
1
IN
Tap1 Tap3 Tap5
7
6
2
3
Tap2 Tap4
5
4
GND
Inputs accept voltages up to 5.5 V
74LVC type input can be driven from either 3.3V or 5V
devices. This allows delay module to serve as a
translator in a mixed 3.3V / 5V system environment.
Electrical Specifications at 25OC
LVC 5 Tap
Tap 1
Tap 2
Tap 3
Tap 4
Tap 5
Tap-to-Tap
( ns )
( ns )
( ns )
( ns )
( ns )
(ns)
SMD P/N
LVMDM-7G
3.0 ± 1.0
4.0 ± 1.0
5.0 ± 1.0
6.0 ± 1.0
7 ± 1.0
1.0 ± 0.4
LVMDM-9G
3.0 ± 1.0
4.5 ± 1.0
6.0 ± 1.0
7.5 ± 1.0
9 ± 1.0
1.5 ± 0.5
LVMDM-11G
3.0 ± 1.0
5.0 ± 1.0
7.0 ± 1.0
9.0 ± 1.0
11 ± 1.5
2.0 ± 0.6
LVMDM-13G
3.0 ± 1.0
5.5 ± 1.0
8.0 ± 1.0
10.5 ± 1.0
13 ± 1.5
2.5 ± 0.8
LVMDM-15G
3.0 ± 1.0
6.0 ± 1.0
9.0 ± 1.0
12.0 ± 1.5
15 ± 1.5
3.0 ± 1.0
LVMDM-20G
4.0 ± 1.0
8.0 ± 1.2
12.0 ± 1.5
16.0 ± 1.5
20 ± 2.0
4.0 ± 1.0
LVMDM-25G
5.0 ± 1.0
10.0 ± 1.5
15.0 ± 1.5
20.0 ± 2.0
25 ± 2.0
5.0 ± 1.5
LVMDM-30G
6.0 ± 1.0
12.0 ± 1.5
18.0 ± 1.5
24.0 ± 2.0
30 ± 2.0
6.0 ± 1.5
LVMDM-35G
7.0 ± 1.0
14.0 ± 1.5
21.0 ± 2.0
28.0 ± 2.0
35 ± 2.0
7.0 ± 1.8
LVMDM-40G
8.0 ± 1.0
16.0 ± 1.5
24.0 ± 2.0
32.0 ± 2.0
40 ± 2.0
8.0 ± 2.0
LVMDM-45G
9.0 ± 1.0
18.0 ± 1.5
27.0 ± 2.0
36.0 ± 2.0
45 ± 2.25
9.0 ± 2.0
LVMDM-50G
10.0 ± 1.5
20.0 ± 2.0
30.0 ± 2.0
40.0 ± 2.0
50 ± 2.5
10 ± 2.0
LVMDM-60G
12.0 ± 1.5
24.0 ± 2.0
36.0 ± 2.0
48.0 ± 2.4
60 ± 3.0
12 ± 2.0
LVMDM-75G
15.0 ± 2.0
30.0 ± 2.0 45.0 ± 2.25 60.0 ± 3.0
75 ± 3.75
15 ± 2.5
LVMDM-80G
16.0 ± 2.0
32.0 ± 2.0
48.0 ± 2.4
64.0 ± 3.2
80 ± 4.0
16 ± 2.5
LVMDM-100G 20.0 ± 2.0
40.0 ± 2.0
60.0 ± 3.0
80.0 ± 2.0
100 ± 5.0
20 ± 3.0
** These part numbers do not have 5 equal taps. Tap-to-Tap Delays reference Tap 1.
TEST CONDITIONS -- Low Voltage CMOS, LVC
Dimensions in Inches (mm)
VCC Supply Voltage ................................................ 3.30VDC
Input Pulse Voltage ................................................... 2.70V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25OC
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 50pf probe and fixture load on output under test.
.020
(0.51) .250
TYP. (6.35)
MAX.
DIP
.120
(3.05)
MIN.
OPERATING SPECIFICATIONS
.020 .050
(0.51) (1.27)
TYP. TYP.
Supply Voltage, VCC .......................................... 3.3 ± 0.3 VDC
Supply Current, ICC ........................... 10 mA typ., 30 mA max.
Supply Current, ICCL : VIN = GND ......................... 22 mA max.
Supply Current, ICCH : VIN = VCC ............................. 10 µA max.
Input Voltage, VI ..................................... 0 V min., 5.5 V max.
Logic “1” Input, VIH .................................................. 2.0 V min.
Logic “0” Input, VIL ................................................. 0.8 V max.
Logic “1” Out, VOH: VCC = 3V & IOH = -24 mA ............ 2.0 V min.
Logic “0” Out, VOL: VCC = 3V & IOL = 24 mA ......... 0.55 V max.
Input Capacitance, CI ............................................. 5 pF, typ.
Input Pulse Width, PWI .............................. 40% of Delay min.
Operating Temperature Range ......................... -40O to +85OC
Storage Temperature Range ........................ -65O to +150OC
P/N Description
.285
(7.24)
MAX.
.505
(12.83)
MAX.
.100
(2.54)
TYP.
.250
(6.35)
MAX.
.015
(0.38)
TYP.
LVMDM - XXX X
J-SMD
.020 .050
(0.51) (1.27)
TYP. TYP.
.100
(2.54)
TYP.
G-SMD
.008 R
(0.20)
.030
(0.76)
TYP.
.430 (10.92)
.400 (10.16)
.010
(0.25)
TYP.
.285
(7.24)
MAX.
.505
(12.83)
MAX.
LVC Buffered 5 Tap Delay
Molded Package Series:
8-pin DIP: LVMDM
Total Delay in nanoseconds (ns)
Lead Style: Blank = Thru-hole
G = “Gull Wing” SMD
J = “J” Bend SMD
.300
(7.62)
.285
(7.24)
MAX.
.505
(12.83)
MAX.
.020 .050
(0.51) (1.27)
TYP. TYP.
.010
(0.25)
TYP.
.365
(9.27)
MAX.
.100
(2.54)
TYP.
G-SMD
DIP
.265
(6.73)
MAX.
.030
(0.76)
TYP.
J-SMD
.285 (7.24)
.260 (6.60)
.330 (8.38)
MAX.
.020 R
(0.51)
Examples: LVMDM-25G = 25ns (5ns per tap) 74LVC, 8-Pin G-SMD
LVMDM-100 = 100ns (20ns per tap) 74LVC, 8-Pin DIP
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LVMDM 2001-01
LVITD Series LVC Low Voltage Logic 10-Tap Delay Modules
Inputs accept voltages up to 5.5 V
LVITD Schematic
74LVC type input can be driven from either 3.3V or 5V
devices. This allows delay module to serve as a
translator in a mixed 3.3V / 5V system environment.
Vcc
Tap1 Tap3 Tap5 Tap7 Tap9 Tap10
14
13
12
11
10
9
8
3
4
5
6
7
Operating Temp. -40OC to +85OC
Low Profile 14-Pin Package
Two Surface Mount Versions
For 5-Tap 8-Pin Versions see LVMDM Series
1
2
IN
N/C
Tap2 Tap4 Tap6 Tap8 GND
Electrical Specifications at 25OC
Tap Delay Tolerances +/- 5% or 2ns (>15ns +/- 1.0ns)
LVC Logic
10 Tap P/N
Tap 1
Tap 2
Tap 3
Tap 4
LVITD-12
3
4
5
6
7
LVITD-21
3
5
7
9
11
LVITD-30
3
6
9
12
15
LVITD-50
5
10
15
20
LVITD-60
6
12
18
LVITD-75
7.5
15
LVITD-80
8
LVITD-100
Tap 5
Tap 6
Tap-to-Tap
(ns)
Tap 7
Tap 8
Tap 9
8
9
10
11
12 ± 2.5
1.0 ± 0.4
13
15
17
19
21 ± 2.5
2.0 ± 0.6
18
21
24
27
30 ± 2.5
3.0 ± 0.8
25
30
35
40
45
50 ± 2.5
5.0 ± 1.8
24
30
36
42
48
54
60 ± 3.0
6.0 ± 2.0
22.5
30
37.5
45
52.5
60
67.5
75 ± 3.75
7.5 ± 2.0
16
24
32
40
48
56
64
72
80 ± 4.0
8.0 ± 2.0
10
20
30
40
50
60
70
80
90
100 ± 5.0
10.0 ± 2.0
LVITD-125
12.5
25
37.5
50
62.5
75
87.5
100
112.5
125 ± 6.25
12.5 ± 3.0
LVITD-150
15
30
45
60
75
90
105
120
135
150 ± 7.5
15.0 ± 3.0
Dimensions in Inches (mm)
TEST CONDITIONS -- Low Voltage CMOS, LVC
VCC Supply Voltage ................................................ 3.30VDC
Input Pulse Voltage ................................................... 2.70V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25OC
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 50pf probe and fixture load on output under test.
OPERATING SPECIFICATIONS
Supply Voltage, VCC .......................................... 3.3 ± 0.3 VDC
Supply Current, ICC ........................... 10 mA typ., 30 mA max.
Supply Current, ICCL : VIN = GND ......................... 22 mA max.
Supply Current, ICCH : VIN = VCC ............................. 10 µA max.
Input Voltage, VI ..................................... 0 V min., 5.5 V max.
Logic “1” Input, VIH .................................................. 2.0 V min.
Logic “0” Input, VIL ................................................. 0.8 V max.
Logic “1” Out, VOH: VCC = 3V & IOH = -24 mA ............ 2.0 V min.
Logic “0” Out, VOL: VCC = 3V & IOL = 24 mA ......... 0.55 V max.
Input Capacitance, CI ............................................. 5 pF, typ.
Input Pulse Width, PWI .............................. 40% of Delay min.
Operating Temperature Range ......................... -40O to +85OC
Storage Temperature Range ........................ -65O to +150OC
P/N Description
Examples: LVITD-30G =
LVITD-100 =
.250
.020 (6.35)
(0.51) MAX.
DIP
DIP
.120
(3.05)
MIN.
.020
(0.51)
TYP.
.050
(1.27)
TYP.
.365
(9.27)
MAX.
.100
(2.54)
TYP.
.285
(7.24)
MAX.
G-SMD
.050
(1.27)
TYP.
.100
(2.54)
TYP.
.015
(0.38)
TYP.
.030
(0.76)
TYP.
.008 R
(0.20)
.010
(0.25)
TYP.
.430 (10.92)
.400 (10.16)
.285
(7.24)
MAX.
.265
(6.73)
MAX.
J-SMD
.050
(1.27)
TYP.
G-SMD
.250
(6.35)
MAX.
.785
(19.94)
MAX.
.020
(0.51)
TYP.
.010
(0.25)
TYP.
.300
(7.62)
.785
(19.94)
MAX.
.020
(0.51)
TYP.
.008 R
(0.20)
.100
(2.54)
TYP.
.030
(0.76)
TYP.
J-SMD
.285 (7.24)
.260 (6.60)
.020 R
(0.51)
.330 (8.38)
MAX.
30ns (3ns per tap) 74LVC, 14-Pin G-SMD
100ns (10ns per tap) 74LVC, 14-Pin DIP
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.285
(7.24)
MAX.
.785
(19.94)
MAX.
LVITD - XXX X
LVC Buffered 10 Tap Delay
Molded Package Series:
14-pin DIP: LVITD
Total Delay in nanoseconds (ns)
Lead Style: Blank = Thru-hole
G = “Gull Wing” SMD
J = “J” Bend SMD
Total - Tap 10
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LVITD 2001-01
• FAST / TTL •
Logic Buffered Single - Dual - Triple
Independent Delay Modules
Part Number
Description
Electrical Specifications at 25OC
FAST Buffered
Delay
Single
Dual
(ns)
GENERAL: For Operating Specifications and Test
Conditions refer to corresponding 5-Tap Series
FAMDM, ACMDM and LVMDM except Minimum
Pulse width and Supply current ratings as below.
Delays specified for the Leading Edge.
XXXXX - XXX X
74ACT -- ACMDL
ACM2D & ACM3D
74F -- FAMDL
FAM2D & FAM3D
74LVC -- LVMDL
LVM2D & LVM3D
Delay Per Line (ns)
Lead Style:
Blank = Auto-Insertable DIP
G = “Gull Wing” Surface Mount
J = “J” Bend Surface Mount
Dimensions in Inches (mm)
(ns)
Single 8-Pin "DL"
Schematic
.285
(7.24)
MAX.
Vcc
OUT
8
7
6
5
.020
(0.51) .250
TYP. (6.35)
MAX.
.120
(3.05)
MIN.
.020 .050
(0.51) (1.27)
TYP. TYP.
.300
(7.62)
.010
(0.25)
TYP.
1
.365
(9.27)
MAX.
.100
(2.54)
TYP.
2
3
4
GND
IN
Dual 8-Pin "2D"
Schematic
.285
(7.24)
MAX.
.505
(12.83)
MAX.
G-SMD
.020 .050
(0.51) (1.27)
TYP. TYP.
.100
(2.54)
TYP.
.250
(6.35)
MAX.
.015
(0.38)
TYP.
J-SMD
.020 .050
(0.51) (1.27)
TYP. TYP.
.100
(2.54)
TYP.
G-SMD
.030
(0.76)
TYP.
.430 (10.92)
.400 (10.16)
Vcc
OUT1
8
7
.265
(6.73)
MAX.
.030
(0.76)
TYP.
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Triple
8-Pin P/N
FAMDL-4
FAM2D-4
FAM3D-4
FAMDL-5
FAM2D-5
FAM3D-5
FAMDL-6
FAM2D-6
FAM3D-6
FAMDL-7
FAM2D-7
FAM3D-7
FAMDL-8
FAM2D-8
FAM3D-8
6
6 ± 1.00
7 ± 1.00
8 ± 1.00
9 ± 1.00
10 ± 1.50
12 ± 1.50
15 ± 1.50
16 ± 1.50
20 ± 2.00
25 ± 2.00
30 ± 2.00
50 ± 2.50
75 ± 3.75
100 ± 5.0
8-Pin P/N
8-Pin P/N
8-Pin P/N
ACMDL-6
ACM2D-6
ACM3D-6
ACMDL-7
ACM2D-7
ACM3D-7
ACMDL-8
ACM2D-8
ACM3D-8
ACMDL-9
ACM2D-9
ACM3D-9
ACMDL-10
ACM2D-10
ACM3D-10
ACMDL-12
ACM2D-12
ACM3D-12
ACMDL-15
ACM2D-15
ACM3D-15
ACMDL-16
ACM2D-16
ACM3D-16
ACMDL-20
ACM2D-20
ACM3D-20
ACMDL-25
ACM2D-25
ACM3D-25
ACMDL-30
ACM2D-30
ACM3D-30
ACMDL-50
---
---
ACMDL-75
---
---
ACMDL-100
---
---
5
• Low Voltage CMOS •
.010
(0.25)
TYP.
Electrical Specifications at 25OC
Low Voltage CMOS Buffered
Delay
Single
Dual
Triple
(ns)
1
2
IN 1
3
4
IN 2
GND
Triple 8-Pin "3D"
Schematic
Vcc OUT1 OUT2 OUT3
J-SMD
.285 (7.24)
.260 (6.60)
.330 (8.38)
MAX.
OUT2
.008 R
(0.20)
.285
(7.24)
MAX.
.505
(12.83)
MAX.
8-Pin P/N
Operating Temperature Range
FAMDL-9
FAM2D-9
FAM3D-9
FAST/TTL
..................................... 0OC to +70OC
FAMDL-10 FAM2D-10 FAM3D-10
O
O
74ACT
.................................. -40 C to +85 C
FAMDL-12 FAM2D-12 FAM3D-12
74LVC
.................................. -40OC to +85OC
FAMDL-15 FAM2D-15 FAM3D-15
Temp. Coefficient of Delay:
FAMDL-16 FAM2D-16 FAM3D-16
Single .................... 500ppm/OC typical
Dual/Triple ............ 800ppm/OC typical
FAMDL-20 FAM2D-20 FAM3D-20
Minimum Input Pulse Width:
FAMDL-25 FAM2D-25 FAM3D-25
Single ..................... 40% of total delay
FAMDL-30 FAM2D-30 FAM3D-30
Dual/Triple ........... 100% of total delay
FAMDL-50
----Supply Current, ICC :
FAMDL-75
----FAST/TTL FAMDL ........ 25 mA typ., 48 mA max.
FAMDL-100
----FAM2D ........ 32 mA typ., 65 mA max.
FAM3D ........ 45 mA typ., 95 mA max.
74ACT
ACMDL ........ 14 mA typ., 28 mA max.
ACM2D ......... 23 mA typ., 52 mA max.
ACM3D ........ 34 mA typ., 75 mA max.
• Advanced CMOS •
74LVC
LVMDL ......... 10 mA typ., 30 mA max. Electrical Specifications at 25OC
LVM2D ......... 15 mA typ., 44 mA max.
74ACT Adv. CMOS
Delay
LVM3D ......... 21 mA typ., 64 mA max.
Single
Dual
Triple
Examples:
FAMDL-4 = 4ns Single 74F, DIP
ACM2D-25G = 25ns Dual ACT, G-SMD
LVM3D-30G = 30ns Triple LVC, G-SMD
.505
(12.83)
MAX.
4 ± 1.00
5 ± 1.00
6 ± 1.00
7 ± 1.00
8 ± 1.00
9 ± 1.00
10 ± 1.50
12 ± 1.50
15 ± 1.50
16 ± 1.50
20 ± 2.00
25 ± 2.00
30 ± 2.00
50 ± 2.50
75 ± 3.75
100 ± 5.0
8-Pin P/N
8
7
6
5
.020 R
(0.51)
1
2
3
4
IN 1
IN 2
IN 3
GND
4 ± 1.00
5 ± 1.00
6 ± 1.00
7 ± 1.00
8 ± 1.00
9 ± 1.00
10 ± 1.50
12 ± 1.50
15 ± 1.50
16 ± 1.50
20 ± 2.00
25 ± 2.00
30 ± 2.00
50 ± 2.50
75 ± 3.75
100 ± 5.0
8-Pin P/N
8-Pin P/N
8-Pin P/N
LVMDL-4
LVM2D-4
LVM3D-4
LVMDL-5
LVM2D-5
LVM3D-5
LVMDL-6
LVM2D-6
LVM3D-6
LVMDL-7
LVM2D-7
LVM3D-7
LVMDL-8
LVM2D-8
LVM3D-8
LVMDL-9
LVM2D-9
LVM3D-9
LVMDL-10
LVM2D-10
LVM3D-10
LVMDL-12
LVM2D-12
LVM3D-12
LVMDL-15
LVM2D-15
LVM3D-15
LVMDL-16
LVM2D-16
LVM3D-16
LVMDL-20
LVM2D-20
LVM3D-20
LVMDL-25
LVM2D-25
LVM3D-25
LVMDL-30
LVM2D-30
LVM3D-30
LVMDL-50
---
---
LVMDL-75
---
---
LVMDL-100
---
---
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LOGBUF3D 2001-01
FAST / TTL Logic Buffered Triple & Quad Delays Modules
Uniform or Various Delays in 14-Pin DIP & SMD Packages
Electrical Specifications at 25OC
Triple 14-Pin Schematic
FAST Buffered Multi-Line
Delay
(ns)
4 ± 1.00
5 ± 1.00
6 ± 1.00
7 ± 1.00
8 ± 1.00
10 ± 1.50
15 ± 2.00
16 ± 2.00
20 ± 2.00
25 ± 2.00
30 ± 2.00
50 ± 2.50
Quad 14-Pin Schematic
Quadruple P/N
Vcc
OUT 1
OUT 2
OUT 3
Vcc
FAI3D-4
FAI4D-4
14
12
10
8
14
13
FAI3D-5
FAI4D-5
FAI3D-6
FAI4D-6
FAI3D-7
FAI4D-7
2
FAI3D-8
FAI4D-8
FAI3D-10
FAI4D-10
FAI3D-15
FAI4D-15
1
3
5
7
1
FAI3D-16
FAI4D-16
FAI4D-20
IN 2
IN 3
GND
FAI3D-20
IN 1
IN 1
FAI3D-25
FAI4D-25
FAI3D-30
FAI4D-30
FAI3D-50
FAI4D-50
FAI4D-M01
FAI4D-M02
FAI4D-M03
FAI4D-M04
FAI4D-M05
FAI4D-M06
FAI4D-M07
FAI4D-M08
FAI4D-M09
FAI4D-M10
FAI4D-M11
FAI4D-M12
4.0
4.0
5.0
4.0
6.0
5.0
7.5
8.0
10.0
5.0
10.0
4.0
5.0
4.0
5.0
6.0
6.0
7.5
7.5
8.0
10.0
5.0
10.0
8.0
Line 4 (ns)
Pin 5 to Pin 8
6.0
8.0
10.0
8.0
12.0
10.0
15.0
16.0
20.0
20.0
20.0
16.0
11
10
9
6
3
4
5
IN 2
IN 3
IN 4
8
7
GND
VCC Supply Voltage ........................................ 5.00 ± 0.25 VDC
ICC Supply Current (3D) ...................... 45 mA typ., 95 mA max.
ICC Supply Current (4D) .................... 65 mA typ., 130 mA max.
Logic “1” Input: VIH .......................... 2.00 V min., 5.50 V max.
IIH ................................. 20 µA max. @ 2.70V
Logic “0” Input: VIL ............................................. 0.80 V max.
IIL .............................................. -0.6 mA mA
VOH Logic “1” Voltage Out ....................................... 2.40 V min.
VOL Logic “0” Voltage Out .................................... 0.50 V max.
PWI Input Pulse Width ...................................... 100% of Delay
Operating Temperature Range ................................ 0O to 70OC
Storage Temperature Range .......................... -65O to +150OC
Refer to Delay tolerances for similar delays above
Line 1 (ns)
Line 2 (ns)
Line 3 (ns)
Pin 1 to Pin 12 Pin 3 to Pin 10 Pin 4 to Pin 9
12
OPERATING SPECIFICATIONS
To Specify G-SMD
add "G" suffix to P/N
FAI4D-M Series: Variety of Delays per Part
FAST Logic
Multi-Line /
Multi-Delay P/N
OUT 2 OUT 3 OUT 4
OUT 1
Triple P/N
7.0
8.0
10.0
10.0
12.0
12.5
15.0
16.0
20.0
20.0
20.0
32.0
TEST CONDITIONS
(Measurements made at 25OC)
VCC Supply Voltage ..................................................... 5.00VDC
Input Pulse Voltage ........................................................ 3.20V
Input Pulse Rise Time ............................................ 3.0 ns max.
Input Pulse Period ......................................................... 500 ns
Input Pulse Width ........................................................ 1000 ns
Dimensions in Inches (mm)
.285
(7.24)
MAX.
.785
(19.94)
MAX.
DIP (Default, FAI4D-XX)
.250
.020 (6.35)
(0.51) MAX.
.120
(3.05)
MIN.
.020
(0.51)
TYP.
.050
(1.27)
TYP.
UKRPEXV LQGXVWULHV LQF
.010
(0.25)
TYP.
.100
(2.54)
TYP.
.250
(6.35)
MAX.
.015
(0.38)
TYP.
.030
(0.76)
TYP.
.020
(0.51)
TYP.
.200
(5.08)
TYP.
.050
(1.27)
TYP.
.785
(19.94)
MAX.
G-SMD (FAI3D-XXG)
.008 R
(0.20)
.010
(0.25)
TYP.
.430 (10.92)
.400 (10.16)
.250
.020 (6.35)
(0.51) MAX.
.120
(3.05)
MIN.
MAX.
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.300
(7.62)
.285
(7.24)
G-SMD (FAI4D-XXG)
.050
(1.27)
TYP.
DIP (Default, FAI3D-XX)
.008 R
(0.20)
.365
(9.27)
MAX.
.100
(2.54)
TYP.
.785
(19.94)
MAX.
.020
(0.51)
TYP.
.785
(19.94)
MAX.
.020
(0.51)
TYP.
.050
(1.27)
TYP.
.200
(5.08)
TYP.
.250
(6.35)
MAX.
.015
(0.38)
TYP.
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FAI34D-M 2001-01
DTZM Series FAST / TTL Buffered 5-Tap Delay Modules
Electrical Specifications at 25OC
14-Pin Package Commercial
and Mil-Grade Versions
TTL Buffered 5 Tap Modules
FAST/TTL Logic Buffered
5 Equal Delay Taps
Operating Temperature Ranges
0OC to +70OC, or -55OC to +125OC
8-Pin Versions: FAMDM Series
SIP Versions: FSIDM Series
Low Voltage CMOS Versions
refer to LVMDM / LVIDM Series
DTZM 14-Pin Schematic
Vcc
Tap1
Tap3
Tap5
14
12
10
8
1
4
6
7
IN
Tap2
Tap4
GND
Mil-Grade P/N
Tap 1
Tap 2
Tap 3
Tap 4
Total - Tap 5
DTZM1-9
DTZM1-13
DTZM1-17
DTZM1-20
DTZM1-25
DTZM1-30
DTZM1-35
DTZM1-40
DTZM1-45
DTZM1-50
DTZM1-60
DTZM1-75
DTZM1-80
DTZM1-100
DTZM1-125
DTZM1-150
DTZM1-200
DTZM1-250
DTZM1-300
DTZM1-350
DTZM1-400
DTZM1-500
DTZM1-800
DTZM3-9M
DTZM3-13M
DTZM3-17M
DTZM3-20M
DTZM3-25M
DTZM3-30M
DTZM3-35M
DTZM3-40M
DTZM3-45M
DTZM3-50M
DTZM3-60M
DTZM3-75M
DTZM3-80M
DTZM3-100M
DTZM3-125M
DTZM3-150M
DTZM3-200M
DTZM3-250M
DTZM3-300M
DTZM3-350M
DTZM3-400M
DTZM3-500M
DTZM3-800M
5.0
5.0
5.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
12.0
15.0
16.0
20.0
25.0
30.0
40.0
50.0
60.0
70.0
80.0
100.0
160.0
6.0
7.0
8.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
24.0
30.0
32.0
40.0
50.0
60.0
80.0
100.0
120.0
140.0
160.0
200.0
320.0
7.0
9.0
11.0
12.0
15.0
18.0
21.0
24.0
27.0
30.0
36.0
45.0
48.0
60.0
75.0
90.0
120.0
150.0
180.0
210.0
240.0
300.0
480.0
8.0
11.0
14.0
16.0
20.0
24.0
28.0
32.0
36.0
40.0
48.0
60.0
64.0
80.0
100.0
120.0
160.0
200.0
240.0
280.0
320.0
400.0
640.0
9 ± 1.0
13 ± 1.5
17 ± 1.5
20 ± 1.5
25 ± 2.0
30 ± 2.0
35 ± 2.0
40 ± 2.0
45 ± 2.25
50 ± 2.5
60 ± 3.0
75 ± 3.75
80 ± 4.0
100 ± 5.0
125 ± 6.25
150 ± 7.5
200 ± 10.0
250 ± 12.5
300 ± 15.0
350 ± 17.5
400 ± 20.0
500 ± 25.0
800 ± 40.0
TEST CONDITIONS -- FAST / TTL
VCC Supply Voltage ............................................... 5.00VDC
Input Pulse Voltage .................................................... 3.20V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period .......................... 1000 / 2000 ns
1. Measurements made at 25OC
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 10pf probe and fixture load on output under test.
DTZM1 - XXX X
Buffered 5 Tap Delays:
14-pin Com'l: DTZM1
14-pin MIL: DTZM3
Total Delay in nanoseconds (ns)
Temp. Range Blank = Commercial
M = Mil-Grade
Examples: DTZM1-25 =
25ns (5ns per tap)
74F, 14-Pin Thru-hole
DTZM3-50M = 50ns (10ns per tap)
74F, 14-Pin, Mil-Grade
6SHFLILFDWLRQV VXEMHFW WR FKDQJH ZLWKRXW QRWLFH
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UKRPEXV LQGXVWULHV LQF
∗∗ 1.0 ± 0.5
∗∗ 2.0 ± 0.8
3.0 ± 1.0
4.0 ± 1.5
5.0 ± 2.0
6.0 ± 2.0
7.0 ± 2.0
8.0 ± 2.0
9.0 ± 2.0
10 ± 2.0
12 ± 2.0
15 ± 2.5
16 ± 2.5
20 ± 3.0
25 ± 3.0
30 ± 3.0
40 ± 4.0
50 ± 5.0
60 ± 6.0
70 ± 7.0
80 ± 8.0
100 ± 10.0
160 ± 16.0
Dimensions in Inches (mm)
Commercial Grade 14-Pin Package with Unused Leads Removed
as per Schematic. (For Mil-Grade DTZM3 the Height is 0.335")
.810
(20.57)
MAX.
VCC Supply Voltage .................................... 5.00 ± 0.25 VDC
ICC Supply Current .................................... 48 mA Maximum
Logic “1” Input: VIH ....................... 2.00 V min., 5.50 V max.
IIH ............................... 20 µA max. @ 2.70V
Logic “0” Input: VIL ........................................... 0.80 V max.
IIL ............................................ -0.6 mA mA
VOH Logic “1” Voltage Out .................................. 2.40 V min.
VOL Logic “0” Voltage Out ................................ 0.50 V max.
PWI Input Pulse Width ............................. 40% of Delay min.
Operating Temperature Range ........................... 0O to 70OC
Storage Temperature Range ..................... -65O to +150OC
Tap-to-Tap
(ns)
** These part numbers do not have 5 equal taps.
Tap-to-Tap Delays reference Tap 1.
OPERATING SPECIFICATIONS
P/N Description
Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns)
Part Number
.400
(10.16)
MAX.
.245 .275
(6.22) (6.99)
TYP. MAX.
.120
(3.05)
MIN.
.020
(0.51)
TYP.
.100
(2.54)
TYP.
.050
(1.27)
TYP.
.010
(0.25)
TYP.
.300
(7.62)
MIL-GRADE: DTZM3 Military Grade delay lines use integrated circuits screened to MIL-STD-883B with an operating
temperature range of -55 to +125OC. These devices have a
package height of .335"
Auto-Insertable DIP and Surface Mount Versions:
Refer to FAIDM Series, same 14-pin footprint.
For space saving, refer to FAMDM 8-pin Series
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DTZM13 2001-01
TTL Gated
Oscillators
TTL Pulse Width
Generator Modules
TTL Pulse Width
Discriminators
These gated oscillators permit synchronization of the output square wave with the highto-low transition of the enable input. When
the enable is high, the output is held high.
The output will start with a high-to-low transition one half-cycle after the input trigger.
The output frequency tolerance is ± 3%.
Triggered by the input's rising edge (input
pulse width 10 ns, min.), a pulse of specified
width will be generated at the output with a
propagation delay of 5 ± 2 ns (7 ± 2 ns, for
inverted output). High-to-low transitions will
not trigger the unit. Designed for output
duty-cycle less than 50%.
Input pulse widths greater than the Nominal
value (XX in ns from P/N TTLPD-XX) of the
module, will propagate with delay (XX + 5ns)
± 5% or 2 ns, whichever is greater. Output
pulse width equals input width ± 7% or 4 ns,
whichever is greater. Input pulse widths less
than Nominal value are suppressed.
E
Pin 8
IN
Pin 8
IN
Pin 8
OUT
Pin 1
OUT
Pin 1
OUT
Pin 1
TON
T OFF
TTLOS
Schematic
Vcc
ENABLE
14
8
T
D
PW
Vcc
OUT
14
13
SQUARE WAVE
OSCILLATOR
T
D
PW
OUT
TTLPWG
Schematic
PWIN > XX
PWIN < XX
T
D
PW
OUT
OUT
IN
Vcc
8
14
TTLPD
Schematic
IN
8
Pulse Width
Discriminator
Pulse Width
Control Circuit
1
7
1
7
1
7
OUT
GND
OUT
GND
OUT
GND
Electrical Specifications at 25OC
TTL Gated Oscillators
Part Number
Output Frequency
TTLOS-5
TTLOS-10
TTLOS-15
TTLOS-20
TTLOS-25
TTLOS-30
TTLOS-33
TTLOS-35
TTLOS-40
TTLOS-45
TTLOS-50
TTLOS-66
TTLOS-75
TTLOS-80
5 MHz
10 MHz
15 MHz
20 MHz
25 MHz
30 MHz
33 MHz
35 MHz
40 MHz
45 MHz
50 MHz
66 MHz
75 MHz
80 MHz
Electrical Specifications at 25OC
TTL Buffered Pulse Width Generator Modules
Output Pulse
Width (ns)
TTLPWG-5
5 ± 1.0
TTLPWG-7
7 ± 1.0
TTLPWG-10
10 ± 1.5
TTLPWG-15
15 ± 2.0
TTLPWG-20
20 ± 2.0
TTLPWG-25
25 ± 2.0
TTLPWG-30
30 ± 2.0
TTLPWG-35
35 ± 2.0
TTLPWG-40
40 ± 2.0
TTLPWG-45
45 ± 2.25
TTLPWG-50
50 ± 2.5
TTLPWG-60
60 ± 3.0
TTLPWG-80
80 ± 4.0
TTLPWG-100
100 ± 5.0
Part Number
OPERATING SPECIFICATIONS
Dimensions in Inches (mm)
14-Pin Package with Unused Leads Removed Per Schematic
VCC Supply Voltage ................................... 5.00 ± 0.25 VDC
Supply Current, ICC
TTLPWG .......................... 35 mA typ., 55 mA max.
TTLPD
.......................... 42 mA typ., 60 mA max.
TTLOS
.......................... 15 mA typ., 30 mA max.
Logic “1” Input: VIH ..................... 2.00 V min., 5.50 V max.
Logic “0” Input: VIL ........................................ 0.80 V max.
VOH Logic “1” Voltage Out .................................. 2.40 V min.
VOL Logic “0” Voltage Out ............................... 0.50 V max.
Operating Temperature Range ........................... 0O to 70OC
Storage Temperature Range ..................... -65O to +150OC
.810
(20.57)
MAX.
www.rhombus-ind.com
UKRPEXV LQGXVWULHV LQF
.400
(10.16)
MAX.
.245 .275
(6.22) (6.99)
TYP. MAX.
.020
(0.51)
TYP.
MIL-GRADE: Add "M" suffix. Integrated circuits screened to
MIL-STD-883B with -55 to +125OC operating temperature
range. These devices have a package height of .335"
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Maximum
Freq. (MHz)
63
53
42
32
22
19
15
13
11
10
9
8
6
5
Electrical Specifications at 25OC
TTL Pulse Width Discriminator Modules
Suppressed
Passed
Pulse Width, Pulse Width,
Part Number
Max. (ns)
Min. (ns)
TTLPD-10
< 8.5
> 11.5
TTLPD-15
< 13.5
> 16.5
TTLPD-20
< 18.5
> 21.5
TTLPD-25
< 23.5
> 26.5
TTLPD-30
< 28.5
> 31.5
TTLPD-40
< 38.0
> 42.0
TTLPD-50
< 47.5
> 52.5
TTLPD-60
< 57.0
> 63.0
TTLPD-75
< 71.0
> 79.0
TTLPD-100
< 95.0
> 105.0
TTLPD-120
< 114.0
> 126.0
TTLPD-125
< 118.7
> 131.3
TTLPD-150
< 142.5
> 157.5
TTLPD-200
< 190.0
> 210.0
.100
(2.54)
TYP.
.600
(15.24)
TYP.
.120
(3.05)
MIN.
.050
(1.27)
TYP.
.010
(0.25)
TYP.
.300
(7.62)
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TTLPW 2001-01
FAST/TTL 3-Bit Schematic
3-Bit Programmable Delay Modules
PLDM4 Series FAST/TTL Logic
Vcc
P1
P2
P3
16
11
10
9
Output
Buffer
3-Bit Programmable
Delay Line
7 Delay Steps -- 4 ns Inherent Delay
Available in Surface Mount
4
5
7
8
IN
OUT
E
GND
Electrical Specifications at 25OC
3-Bit FAST
Part Number
Delay per
Step (ns)
PLDM4-0.5
PLDM4-0.7
PLDM4-0.8
PLDM4-1
PLDM4-1.2
PLDM4-1.25
PLDM4-1.3
PLDM4-1.5
PLDM4-1.8
PLDM4-2
PLDM4-2.5
PLDM4-2.6
PLDM4-3
0.5 ± .25
0.7 ± .30
0.8 ± .30
1.0 ± .4
1.2 ± .4
1.25 ± .5
1.3 ± .5
1.5 ± .5
1.8 ± .6
2.0 ± .7
2.5 ± .7
2.6 ± .7
3.0 ± .7
Error ref.
to 000
(ns)
± .30
± .40
± .50
± .50
± .60
± .70
± .70
± .70
± .80
± .80
± .90
± .90
± 1.0
Initial
Delay (ns)
000
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1)
000
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
001
0.5
0.7
0.8
1.0
1.2
1.25
1.3
1.5
1.8
2.0
2.5
2.6
3.0
010
1.0
1.4
1.6
2.0
2.4
2.50
2.6
3.0
3.6
4.0
5.0
5.2
6.0
011
1.5
2.1
2.4
3.0
3.6
3.75
3.9
4.5
5.4
6.0
7.5
7.8
9.0
100
2.0
2.8
3.2
4.0
4.8
5.00
5.2
6.0
7.2
8.0
10.0
10.4
12.0
101
2.5
3.5
4.0
5.0
6.0
6.25
6.5
7.5
9.0
10.0
12.5
13.0
15.0
110
3.0
4.2
4.8
6.0
7.2
7.50
7.8
9.0
10.8
12.0
15.0
15.6
18.0
111
3.5
4.9
5.6
7.0
8.4
8.75
9.1
10.5
12.6
14.0
17.5
18.2
21.0
CUMULATIVE TOLERANCES: "Error" Tolerance is for Programmed Delays referenced to Initial Delay, Setting "000."
For example, the setting "111" delay of PLDM4-10 is 70.0 ± 3.0ns ref. to "000," and 74.0 ± 4.0ns referenced to the input.
_
ENABLE input (Pin 7) is active low. Output will be disabled ( low) when " E " is high.
INPUT FAN-IN: Input, pin 4, is loaded by the internal passive
network and 8 gate inputs (74F type). The source driving Pin 4
should be FAST/TTL (74S/74F) type or equivalent, and should not
be used to drive any load other than the delay line input.
Dimensions in Inches (mm)
.260 .300
(6.60) (7.62)
TYP. MAX.
.120
(3.05)
MIN.
.020
(0.51)
TYP.
TYP.
16-Pin SMD Pkg. Unused leads are NOT removed.
To Specify SMD Package, Add "G" Suffix to P/N
Examples: PLDM4-1.25G, PLDM4-2G
VCC Supply Voltage ................................... 5.00 ± 0.25 VDC
ICC Supply Current .......................... 60 mA typ., 80 mA max
Logic “1” Input *: VIH ..................... 2.00 V min., 5.50 V max.
IIH ............................... 50 µA max. @ 2.70V
Logic “0” Input *: VIL ....................................... 0.80 V max.
IIL ............................................ -0.6 mA mA
VOH Logic “1” Voltage Out ................................... 2.40 V min.
VOL Logic “0” Voltage Out ................................ 0.50 V max.
PWI Input Pulse Width ............................. 40% of Delay min.
Operating Temperature Range ......................... -0O to +70OC
Storage Temperature Range ...................... -65O to +150OC
1.02
(25.9)
.400
(10.16)
MAX.
.010
(0.25)
.285
(7.24)
TYP.
MAX.
* Refer to "INPUT FAN-IN" note above.
IIL/IIH specified for Programming pins 9, 10 & 11.
UKRPEXV LQGXVWULHV LQF
TYP.
.010
(0.25)
.300
(7.62)
.050 .100
(1.27) (2.54)
TYP.
OPERATING SPECIFICATIONS
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MAX.
MAX.
VCC Supply Voltage ............................................... 5.00VDC
Input Pulse Voltage ................................................... 3.20V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25OC
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 10pf probe and fixture load on output.
6SHFLILFDWLRQV VXEMHFW WR FKDQJH ZLWKRXW QRWLFH
.400
(10.16)
.810
(20.57)
TEST CONDITIONS -- FAST / TTL
.020
(0.51)
.040
(1.02)
.100
(2.54)
TYP.
TYP.
TYP.
.015
(0.38)
.025
(0.64)
.510 (12.95)
.480 (12.19)
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PLDM4-G 2001-01
FAST/TTL 3-Bit Schematic
3-Bit Programmable Delay Modules
PLDM7 Series FAST/TTL Logic
Vcc
P1
P2
P3
16
11
10
9
Output
Buffer
3-Bit Programmable
Delay Line
7 Delay Steps -- 7 ns Inherent Delay
Available in Surface Mount
Electrical Specifications at 25OC
Error ref.
3-Bit TTL
Delay per
to 000
Part Number Step (ns)
(ns)
PLDM7-1
1.0 ± .4
± .50
PLDM7-1.2
1.2 ± .4
± .60
PLDM7-1.25
1.25 ± .5
± .70
PLDM7-1.3
1.3 ± .5
± .70
PLDM7-1.5
1.5 ± .5
± .70
PLDM7-1.8
1.8 ± .6
± .80
PLDM7-1.9
1.9 ± .7
± .80
PLDM7-2
2.0 ± .7
± .80
PLDM7-2.5
2.5 ± .7
± .90
PLDM7-2.6
2.6 ± .7
± .90
PLDM7-3
3.0 ± .7
± 1.0
PLDM7-5
5.0 ± 1.0
± 1.5
PLDM7-8
8.0 ± 1.2
± 2.5
PLDM7-10
10.0 ± 1.5
± 3.0
Initial
Delay (ns)
000
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
7 ± 1.0
4
5
7
8
IN
OUT
E
GND
Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1)
000
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
001
1.0
1.2
1.25
1.3
1.5
1.8
1.9
2.0
2.5
2.6
3.0
5.0
8.0
10.0
010
2.0
2.4
2.5
2.6
3.0
3.6
3.8
4.0
5.0
5.2
6.0
10.0
16.0
20.0
011
3.0
3.6
3.75
3.9
4.5
5.4
5.7
6.0
7.5
7.8
9.0
15.0
24.0
30.0
100
4.0
4.8
5.0
5.2
6.0
7.2
7.6
8.0
10.0
10.4
12.0
20.0
32.0
40.0
101
5.0
6.0
6.25
6.5
7.5
9.0
9.5
10.0
12.5
13.0
15.0
25.0
40.0
50.0
110
6.0
7.2
7.5
7.8
9.0
10.8
11.4
12.0
15.0
15.6
18.0
30.0
48.0
60.0
111
7.0
8.4
8.75
9.1
10.5
12.6
13.3
14.0
17.5
18.2
21.0
35.0
56.0
70.0
CUMULATIVE TOLERANCES: "Error" Tolerance is for Programmed Delays referenced to Initial Delay, Setting "000."
For example, the setting "111" delay of PLDM7-10 is 70.0 ± 3.0ns ref. to "000," and 77.0 ± 4.0ns referenced to the input.
_
ENABLE input (Pin 7) is active low. Output will be disabled ( low) when " E " is high.
INPUT FAN-IN: Input, pin 4, is loaded by the internal passive
network and 8 gate inputs (74S type). The source driving Pin 4
should be FAST/TTL (74S/74F) type or equivalent, and should not
be used to drive any load other than the delay line input.
Dimensions in Inches (mm)
TEST CONDITIONS -- FAST / TTL
.260 .300
(6.60) (7.62)
TYP. MAX.
.120
(3.05)
MIN.
.020
(0.51)
TYP.
TYP.
16-Pin SMD Pkg. Unused leads are NOT removed.
To Specify SMD Package, Add "G" Suffix to P/N
Examples: PLDM7-1.25G, PLDM7-2G
VCC Supply Voltage ................................... 5.00 ± 0.25 VDC
ICC Supply Current ......................... 60 mA typ., 80 mA max
Logic “1” Input *: VIH ..................... 2.00 V min., 5.50 V max.
IIH ............................... 50 µA max. @ 2.70V
Logic “0” Input *: VIL ....................................... 0.80 V max.
IIL ............................................ -2.0 mA mA
VOH Logic “1” Voltage Out .................................. 2.40 V min.
VOL Logic “0” Voltage Out ............................... 0.50 V max.
PWI Input Pulse Width ............................. 40% of Delay min.
Operating Temperature Range ........................ -0O to +70OC
Storage Temperature Range ...................... -65O to +150OC
1.02
(25.9)
.400
(10.16)
MAX.
.010
(0.25)
.285
(7.24)
TYP.
MAX.
* Refer to "INPUT FAN-IN" note above.
IIL/IIH specified for Programming pins 9, 10 & 11.
UKRPEXV LQGXVWULHV LQF
TYP.
.010
(0.25)
.300
(7.62)
.050 .100
(1.27) (2.54)
TYP.
OPERATING SPECIFICATIONS
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MAX.
MAX.
VCC Supply Voltage ................................................ 5.00VDC
Input Pulse Voltage ................................................... 3.20V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25OC
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 10pf probe and fixture load on output.
6SHFLILFDWLRQV VXEMHFW WR FKDQJH ZLWKRXW QRWLFH
.400
(10.16)
.810
(20.57)
.020
(0.51)
.040
(1.02)
.100
(2.54)
TYP.
TYP.
TYP.
.015
(0.38)
.025
(0.64)
.510 (12.95)
.480 (12.19)
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PLDM7-G 2001-01
10K ECL Logic Buffered Delay 16-Pin Modules
5-Tap: DECL • Single: FECL • Triple: MECL
Electrical Specifications at 25OC
Delay
Single
Triple
(ns)
10K P/N
10K P/N
FECL-3
MECL-3
3 ± 0.5
FECL-4
MECL-4
4 ± 0.5
FECL-5
MECL-5
5 ± 0.5
FECL-6
MECL-6
6 ± 0.75
FECL-7
MECL-7
7 ± 0.75
FECL-8
MECL-8
8 ± 0.8
FECL-9
MECL-9
9 ± 1.0
FECL-10
MECL-10
10 ± 1.0
FECL-15
MECL-15
15 ± 1.5
FECL-20
MECL-20
20 ± 1.5
FECL-25
MECL-25
25 ± 1.5
FECL-50
MECL-50
50 ± 2.5
FECL-60
---60 ± 3.0
FECL-75
---75 ± 3.75
FECL-100
---100 ± 5.0
Electrical Specifications at 25OC
Tap Delay Tolerances +/- 5% or 1.5ns (+/- 0.8ns <10ns)
10K ECL
5 Tap P/N
Tap 1
Tap 2
Tap 3
Tap 4
Total - Tap 5
2.0
2.0
3.0
4.0
5.0
6.0
8.0
9.0
10.0
15.0
20.0
25.0
30.0
40.0
50.0
DECL-6
DECL-10
DECL-15
DECL-20
DECL-25
DECL-30
DECL-40
DECL-45
DECL-50
DECL-75
DECL-100
DECL-125
DECL-150
DECL-200
DECL-250
3.0
4.0
6.0
8.0
10.0
12.0
16.0
18.0
20.0
30.0
40.0
50.0
60.0
80.0
100.0
4.0
6.0
9.0
12.0
15.0
18.0
24.0
27.0
30.0
45.0
60.0
75.0
90.0
120.0
150.0
5.0
8.0
12.0
16.0
20.0
24.0
32.0
36.0
40.0
60.0
80.0
100.0
120.0
160.0
200.0
Tap-to-Tap
(ns)
6 ± 0.8
10 ± 1.0
15 ± 1.5
20 ± 1.5
25 ± 1.5
30 ± 1.5
40 ± 2.0
45 ± 2.25
50 ± 2.5
75 ± 3.75
100 ± 5.0
125 ± 6.25
150 ± 7.5
200 ± 10.0
250 ± 12.5
∗∗ 1 ± 0.4
2 ± 0.6
3 ± 0.8
4 ± 1.0
5 ± 1.0
6 ± 1.5
8 ± 2.0
9 ± 2.0
10 ± 2.0
15 ± 2.5
20 ± 3.0
25 ± 3.0
30 ± 3.0
40 ± 4.0
50 ± 5.0
** This part numbers does not have 5 equal taps.
Specified Tap-to-Tap Delays are referenced to Tap 1.
OPERATING SPECIFICATIONS (10K ECL)
VEE Supply Voltage .............................................. -5.20 ± 0.25 VDC
Supply Current, IEE , DECL .......................... 60 mA typ., 75 mA max.
Supply Current, IEE , FECL .......................... 40 mA typ., 65 mA max.
Supply Current, IEE , MECL ....................... 85 mA typ., 105 mA max.
Logic “1” Input:
VIH ................................................ -0.98 V min.
IIH .................................................. 265 µA max.
Logic “0” Input:
VIL ................................................. -1.63 V max.
IIL .................................................. 0.5 mA max.
VOH Logic “1” Voltage Out .............................................. -0.96 V min.
VOL Logic “0” Voltage Out .............................................. -1.65V max.
TRO Output Rise Time .................................................. < 3.00 ns typ.
Input Pulse Width, PWI (DECL,FECL) ......... 40% of total delay, min.
Input Pulse Width, PWI (MECL) ................ 100% of total delay, min.
Operating Temperature Range ................................... -30 O to +85OC
Storage Temperature Range ..................................... -65O to +150OC
TEST CONDITIONS
(Measurements made at 25OC)
VEE Supply Voltage ................................................................. -5.20VDC
Input Pulse Voltage ....................................................... -.80V to -1.80V
Input Pulse Rise Time ......................................................... 3.00ns max.
Input Pulse Period ....................................................... 4.0 x Total Delay
Input Pulse Duty Cycle .................................................................... 50%
Outputs terminated through 100 Ω to -2.00 Vdc.
Dimensions in Inches (mm) -- Unused Leads Removed Per Schematic
DECL Style Schematic
Vcc Tap1 Tap3 Tap5
16
15
1
Vcc
13
3
4
Tap2 Tap4
5
8
IN
Vee
FECL Style Schematic
Vcc
OUT
OUT
16
15
9
1
4
8
Vcc
IN
Vee
.400
(10.16)
MAX.
.810
(20.57)
MAX.
14
MECL Style Schematic
Vcc OUT1 OUT2 OUT3
16
.260 .300
(6.60) (7.62)
TYP. MAX.
.100
(2.54)
TYP.
.020
(0.51)
TYP.
14
13
.010
(0.25)
TYP.
.120
(3.05)
MIN.
.050
(1.27)
TYP.
15
.300
(7.62)
1
5
6
Vcc
IN 1
IN 2
7
8
IN 3 Vee
Also Available in 10KH ECL Versions: DECLH, FECLH & MECLH Series
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DECL_FM 2001-01
3-Bit Programmable Delay Modules
PECL3 Series 10K ECL Logic
3PECLH Series 10KH ECL Logic
Delay per
Step (ns)
Error ref.
to "000"
(ns)
OUT
16
15
ECL 3-Bit
Schematic
P2
P3
10
9
3-Bit Programmable
Delay Line
Output
Buffer
Available in Surface Mount
Electrical Specifications at 25OC
3Bit 10K ECL
3-Bit 10KH ECL
DIP Part Number DIP Part Number
"000"=3±0.5ns ** "000"=1.5±.5ns **
Vcc
1
2
6
Vcc
E
IN
8
7
P1 Vee
_
ENABLE input E , Pin 2, is active low.
Output is disabled (low) when Pin 2 is logic high.
Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1)
PECL3-0.5
3PECLH-0.5
0.5 ± .25
± .30
000
0.0
001
0.5
010
1.0
011
1.5
100
2.0
101
2.5
110
3.0
111
3.5
PECL3-0.75
3PECLH0.75
0.75 ± .3
± .50
0.0
0.75
1.50
2.25
3.00
3.75
4.50
5.25
PECL3-1
3PECLH-1
1.0 ± .4
± .50
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
PECL3-1.25
3PECLH1.25
1.25 ± .5
± .70
0.0
1.25
2.50
3.75
5.00
6.25
7.50
8.75
PECL3-1.5
3PECLH-1.5
1.5 ± .5
± .70
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
PECL3-2
3PECLH-2
2.0 ± .7
± .80
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
PECL3-2.5
3PECLH-2.5
2.5 ± .7
± .90
0.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
PECL3-3
3PECLH-3
3.0 ± .7
± 1.0
0.0
3.0
6.0
9.0
12.0
15.0
18.0
21.0
PECL3-5
3PECLH-5
5.0 ± 1.0
± 1.5
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
PECL3-10
3PECLH-10
10.0 ± 1.5
± 3.0
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
** INITIAL DELAY & CUMULATIVE TOLERANCES: "Error" Tolerance is for Programmed Delays Referenced to Initial Delay, Setting "000."
For example, the setting "111" delay of PECL3-2 is 14.0 ± 0.8 ns ref. to "000," and 17.0 ± 1.3 ns referenced to the input,
and the setting "111" delay of 3PECLH-2 is 14.0 ± 0.8 ns ref. to "000," and 15.5 ± 1.3 ns referenced to the input.
INPUT LOADING: Input, Pin 6, internally connected to eight ECL
gate inputs terminated by Thevenin equivalent of 100 Ohms to -2V.
Dimensions in Inches (mm)
VEESupply Voltage ........................................... -5.20 ± 0.25VDC
IEE Supply Current ............................................... 60 mA typical
Logic “1” Input:
VIH ................................................. -.98V min.
IIH .............................................. 265 µA max.
IIH (Pin 6) * ................................... -11mA typ.
Logic “0” Input:
VIL .............................................. -1.63V max.
IIL ................................................ 0.5 µA min.
IIL (Pin 6) * ...................................... -2mA typ.
VOH Logic “1” Voltage Out ......................................... -.96V min.
VOL Logic “0” Voltage Out ....................................... -1.65V max.
PWI Input Pulse Width .......................... 40% of Max. Delay min.
Operating Temp. Range (10K, PECL3) ................... -30 to +85OC
Storage Temperature Range ................................ -65 to +150OC
OPERATING SPECIFICATIONS (10KH, 3PECLH)
VEESupply Voltage ........................................... -5.20 ± 0.25VDC
IEE Supply Current ............................................... 75 mA typical
Logic “1” Input:
VIH ................................................. -.98V min.
IIH .............................................. 320 µA max.
IIH (Pin 6) * ................................... -11mA typ.
Logic “0” Input:
VIL .............................................. -1.63V max.
IIL ................................................ 0.7 µA min.
IIL (Pin 6) * ...................................... -2mA typ.
VOH Logic “1” Voltage Out ......................................... -.96V min.
VOL Logic “0” Voltage Out ....................................... -1.65V max.
PWI Input Pulse Width .......................... 40% of Max. Delay min.
Operating Temp. Range (10KH, 3PECLH) ................ -0 to +75OC
Storage Temperature Range ................................ -65 to +150OC
* Refer to Input (Pin 6) Loading note above.
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.400
(10.16)
.810
(20.57)
OPERATING SPECIFICATIONS (10K, PECL3)
MAX.
MAX.
.260 .300
(6.60) (7.62)
TYP. MAX.
.120
(3.05)
.010
(0.25)
MIN.
.020
(0.51)
TYP.
.300
(7.62)
.050 .100
(1.27) (2.54)
TYP.
TYP.
TYP.
16-Pin SMD Pkg. Unused leads are NOT removed.
To Specify SMD Package, Add "H" Suffix to P/N
Examples: PECL3-1.25H, 3PECLH-2H
.895
(22.73)
.590
(14.99)
MAX.
MAX.
.295
(7.49)
MAX.
.020
(0.51)
.045
(1.14)
.100
(2.54)
TYP.
TYP.
TYP.
.010
(0.25)
.070
(1.78)
.815
(20.70)
.010
(0.25)
TYP.
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PECL3-H 2001-02
Delay Line
Part Number
Index
Family
Page
ACM2D
20
ACM3D
20
ACMDL
20
ACMDM 17
AIDM
**
AIU
6
AIY
6
AIZ
6
AMDM
**
AML1
4
AMY
5
AMZ
5
D2ECL
**
DDECL
**
DECL
26
DSP-xxx
**
DTZM
22
ESP-xxx
**
FAI3D
21
FAI4D
21
FAIDM
15
FAITD
16
FAM2D
20
FAM3D
20
FAMDL
20
FAMDM
14
FECL
26
FSIDM
15
LVITD
19
LVM2D
20
LVM3D
20
LVMDL
20
LVMDM
18
MECL
26
PECL3
27
PLDM
24
SH6G
4
SIL2
10
SIL2T
10
SIP4
8
SIP5
8
SIP8
9
SL7T
9
SP24A
12
SP24L
13
SP3
11
SP-xxx
**
TF
11
TTLOS
23
TTLPD
23
TTLPW
23
TUB
7
TYA
**
TYB
7
TZA
**
TZB
7
** See Website
or Contact
Rhombus
for details.
Glossary of
Delay Line Parameters
Test Circuit & Waveform Parameters
Attenuation (At): the difference in peak
amplitude between input and output pulses.
R1
Rg
TEST
PROBE
TEST
PROBE
PULSE
GENERATOR
IN
HIGH BW
(350 MHz min.)
OSCILLOSCOPE
DELAY LINE
UNDER TEST
R2
OUT
CH
A
Rt = Zo
CH
B
TRIG
IN
EXTERNAL
TRIGGER
Rg = GENERATOR SOURCE IMPEDANCE = 50 OHMS
R1, R2 = INPUT MATCHING PAD RESISTORS
Rt = TERMINATING RESISTOR
Zo = DELAY LINES CHARACTERISTIC IMPEDANCE
DELAY TIME (Td): the elapsed time
between the respective 50% points on the
leading edges of the input and output pulses.
IMPEDANCE (Zo): the effective impedance
of the delay line which is equal to the value of
the terminating impedance which provides a
minimum reflection back to the input of the
delay line.
R1 = {Rg x Zo} / R2
(Rg2 x Zo)
(Zo - Rg)
R2 =
D.C. RESISTANCE (DCR): The D.C.
resistance, in ohms, measured between the
input and output of a delay line.
INPUT FALL TIME (Tfi): the elapsed time
between the 90% and the 10% points on the
trailing edge of the input pulse.
Figure 5A. Recommended test circuit for Passive Delay Lines
( For Logic Buffered devices no resistors are required)
INPUT RISE TIME (Tri): the elapsed time
between the 10% and the 90% points on the
leading edge of the input pulse.
Pos
90%
90%
At
Ei 50%
Eo
Pw
10%
INPUT VOLTAGE (Ei): the amplitude of the
input pulse.
S
LEADING EDGE: that portion of the pulse
which rises from zero to peak amplitude.
50%
OUTPUT RISE TIME (Tfo): the elapsed time
between the 10% and the 90% points on the
leading edge of the output pulse.
10%
Tri
Tfi
Tro
Tfo
Td
Figure 6A. Passive Delay Line Waveform Parameters
OUTPUT FALL TIME (Tfo): the elapsed
time between the 90% and the 10% points on
the trailing edge of the output pulse.
OUTPUT VOLTAGE (Eo): the amplitude of
the output pulse.
VOH
VTrh
Ei
VTrh
V Td
Eo V Td
Pw
VTrl
VOL
Tfi
Tri
Td
LH
Tro
Td
Tfo
PULSE OVERSHOOT (Pos): the peak
amplitude of overshoot occurring at the top of
the leading edge of the output pulse (for flat
input pulse top).
HL
Figure 7A. Active Delay Line Waveform Parameters
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PULSE DISTORTION (S): the magnitude of
the largest peak amplitude of all spurious
responses in either a positive or negative
direction occurring in the period after the top
of the leading edge of the output pulse and
before two time delays (for flat input pulse
top).
PULSE WIDTH (Pw): the elapsed time
between the 50% points on the leading and
trailing edge of a pulse.
TRAILING EDGE: that portion of the pulse
which falls from peak amplitude to zero.
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INDX-GLS 2001-01
Magnetic Product Families from Rhombus Industries
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1 Watt to 1 kW
Delay Lines
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Leaders in development, we
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Various Packaging Options:
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Rhombus Industries provides this
service with the option of either
customer, or Rhombus supplied
raw materials.
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Rhombus can cross reference your
current supplier part numbers.
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DLCAT-2002-01
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