Preliminary RMLV0408E Series 4Mb Advanced LPSRAM (512k word × 8bit) R10DS0217EJ0001 Rev.0.01 2013.09.10 Description The RMLV0408E Series is a family of 4-Mbit static RAMs organized 524,288-word × 8-bit, fabricated by Renesas’s high-performance Advanced LPSRAM technologies. The RMLV0408E Series has realized higher density, higher performance and low power consumption. The RMLV0408E Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is offered in 32-pin SOP, 32-pin TSOP II or 32-pin STSOP. Features Single 3V supply: 2.7V to 3.6V Access time: 45/55ns (max.) Current consumption: ── Standby: 0.4µA (typ.) Equal access and cycle times Common data input and output ── Three state output Directly TTL compatible ── All inputs and outputs Battery backup operation Part Name Information Part Name Access time RMLV0408EGSP-4S2 45 ns RMLV0408EGSP-5S2 55 ns RMLV0408EGSB-4S2 45 ns RMLV0408EGSB-5S2 55 ns RMLV0408EGSA-4S2 45 ns RMLV0408EGSA-5S2 55 ns R10DS0217EJ0001 Rev.0.01 2013.09.10 Temperature Range Package 525-mil 32-pin plastic SOP -40 ~ +85°C 400-mil 32-pin plastic TSOP II 8mm x 13.4mm STSOP Page 1 of 10 RMLV0408E Series Preliminary Pin Arrangement 32-pin SOP 32-pin TSOP II 32-pin STSOP A18 1 32 Vcc A11 1 32 OE# A16 2 31 A15 A9 2 31 A10 A14 3 30 A17 A8 3 30 CS# A12 4 29 WE# A13 4 29 I/O7 A7 5 28 A13 WE# 5 28 I/O6 A6 6 27 A8 A18 6 27 I/O5 A5 7 26 A9 A15 7 26 I/O4 A4 8 25 A11 Vcc 8 25 I/O3 A3 9 24 OE# A17 9 24 Vss A2 10 23 A10 A16 10 23 I/O2 A1 11 22 CS# A14 11 22 I/O1 A0 12 21 I/O7 A12 12 21 I/O0 I/O0 13 20 I/O6 A7 13 20 A0 I/O1 14 19 I/O5 A6 14 19 A1 I/O2 15 18 I/O4 A5 15 18 A2 Vss 16 17 I/O3 A4 16 17 A3 (Top view) (Top view) Pin Description Pin name VCC VSS A0 to A18 I/O0 to I/O7 CS# WE# OE# Function Power supply Ground Address input Data input/output Chip select Write enable Output enable R10DS0217EJ0001 Rev.0.01 2013.09.10 Page 2 of 10 RMLV0408E Series Preliminary Block Diagram VCC A0 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 VSS ・ ・ ・ ・ ・ Row Decoder I/O0 Memory Matrix 2,048 x 2,048 ・ ・ Column I/O ・ ・ Column Decoder Input Data Control I/O7 A1 A2 A3 A14 A15 A16 A17 A18 ・ ・ CS# Timing Pulse Generator WE# Read/Write Control OE# Operation Table CS# WE# OE# I/O0 to I/O7 Operation H X X High-Z Standby L H L Dout Read L L X Din Write L H H High-Z Output disable Note 1. H: VIH L:VIL X: VIH or VIL R10DS0217EJ0001 Rev.0.01 2013.09.10 Page 3 of 10 RMLV0408E Series Preliminary Absolute Maximum Ratings Parameter Power supply voltage relative to VSS Symbol VCC Terminal voltage on any pin relative to VSS VT Power dissipation PT Operation temperature Topr Storage temperature range Tstg Storage temperature range under bias Tbias Note 2. -3.0V for pulse ≤ 30ns (full width at half maximum) 3. Maximum voltage is +4.6V. Value -0.5 to +4.6 unit V -0.5*2 to VCC+0.3*3 0.7 -40 to +85 -65 to +150 -40 to +85 V W °C °C °C DC Operating Conditions Parameter Symbol VCC VSS Input high voltage VIH Input low voltage VIL Ambient temperature range Ta Note 4. -3.0V for pulse ≤ 30ns (full width at half maximum) Supply voltage Min. 2.7 0 2.2 -0.3 -40 Typ. 3.0 0 ─ ─ ─ Max. 3.6 0 VCC+0.3 0.6 +85 Unit V V V V °C Note 4 DC Characteristics Parameter Input leakage current Symbol Min. Typ. Max. Unit | ILI | ─ ─ 1 A | ILO | ─ ─ 1 A ICC ─ ─ 10 mA ICC1 ─ ─ 20 mA ICC2 ─ ─ 2.5 mA ISB ─ 0.1*5 0.3 mA ─ 0.4*5 2 A ~+25°C ─ ─ 3 A ~+40°C ─ ─ 5 A ~+70°C ─ ─ 7 A ~+85°C VOH 2.4 ─ ─ V IOH = -1mA VOH2 VCC-0.2 ─ ─ V IOH = -0.1mA VOL ─ ─ 0.4 V IOL = 2.1mA VOL2 ─ ─ 0.2 V IOL = 0.1mA Output leakage current Operating current Average operating current Standby current Standby current ISB1 Output high voltage Output low voltage Note Test conditions Vin = VSS to VCC CS# =VIH or OE# =VIH or WE#= VIL, VI/O = VSS to VCC CS# =VIL, Others = VIH/VIL, II/O = 0mA Min. cycle, duty =100%, II/O = 0mA CS# =VIL, Others = VIH/VIL Cycle =1s, duty =100%, II/O = 0mA CS# ≤ 0.2V, VIH ≥ Vcc-0.2V, VIL ≤ 0.2V CS# =VIH, Others = VSS to VCC Vin = VSS to VCC, CS# ≥ VCC-0.2V 5. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. Capacitance (Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = -40 ~ +85°C*2) Parameter Symbol Min. Input capacitance C in ─ Input / output capacitance C I/O ─ Note 6. This parameter is sampled and not 100% tested. R10DS0217EJ0001 Rev.0.01 2013.09.10 Typ. ─ ─ Max. 8 10 Unit pF pF Test conditions Vin =0V VI/O =0V Note 6 6 Page 4 of 10 RMLV0408E Series Preliminary AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C) 1.4V Input pulse levels: VIL = 0.4V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.4V Output load: See figures (Including scope and jig) RL = 500 ohm I/O CL = 30 pF (-4S2) CL = 50 pF (-5S2) Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Symbol tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ RMLV0408EG**-4S2 Min. 45 ─ ─ ─ 10 10 5 0 0 Max. ─ 45 45 22 ─ ─ ─ 18 18 RMLV0408EG**-5S2 Min. 55 ─ ─ ─ 10 10 5 0 0 Max. ─ 55 55 30 ─ ─ ─ 20 20 Unit Note ns ns ns ns ns ns ns ns ns 7,8 7,8 7,8,9 7,8,9 Write Cycle Parameter Symbol RMLV0408EG**-4S2 RMLV0408EG**-5S2 Unit Note Min. Max. Min. Max. Write cycle time tWC 45 ─ 55 ─ ns Address valid to write end tAW 35 ─ 50 ─ ns Chip select to write end tCW 35 ─ 50 ─ ns Write pulse width tWP 35 ─ 40 ─ ns 10 Address setup time to write start tAS 0 ─ 0 ─ ns Write recovery time from write end tWR 0 ─ 0 ─ ns Data to write time overlap tDW 25 ─ 25 ─ ns Data hold from write end tDH 0 ─ 0 ─ ns Output enable from write end tOW 5 ─ 5 ─ ns 7 Output disable to output in high-Z tOHZ 0 18 0 20 ns 7,9 Write to output in high-Z tWHZ 0 18 0 20 ns 7,9 Note 7. This parameter is sampled and not 100% tested. 8. At any given temperature and voltage condition, tCHZ max is less than tCLZ min, and tOHZ max is less than tOLZ min, for any device. 9. tCHZ, tOHZ and tWHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 10. tWP is the interval between write start and write end. A write starts when both of CS# and WE# become active A write is performed during the overlap of a low CS#, a low WE# A write ends when any of CS#, WE# becomes inactive. R10DS0217EJ0001 Rev.0.01 2013.09.10 Page 5 of 10 RMLV0408E Series Preliminary Timing Waveforms Read Cycle tRC Valid address A0~18 tAA tACS CS# tCHZ *11,12,13 tCLZ *12,13 WE# VIH WE# = “H” level tOHZ *11,12,13 tOE OE# tOLZ I/O0~7 High impedance tOH *12,13 Valid Data Note 11. tCHZ and tOHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 12. This parameter is sampled and not 100% tested. 13. At any given temperature and voltage condition, tCHZ max is less than tCLZ min, and tOHZ max is less than tOLZ min, for any device. R10DS0217EJ0001 Rev.0.01 2013.09.10 Page 6 of 10 RMLV0408E Series Preliminary Write Cycle (1) (WE# CLOCK, OE#=”H” while writing) tWC Valid address A0~18 tCW CS# tAW tWR tWP *14 WE# tAS OE# tWHZ *15,16 tOHZ *15,16 I/O0~7 *17 tDW tDH Valid Data Note 14. tWP is the interval between write start and write end. A write starts when both of CS# and WE# become active. A write is performed during the overlap of a low CS# and a low WE#. A write ends when any of CS# or WE# becomes inactive. 15. tOHZ and tWHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 16. This parameter is sampled and not 100% tested. 17. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins. R10DS0217EJ0001 Rev.0.01 2013.09.10 Page 7 of 10 RMLV0408E Series Preliminary Write Cycle (2) (WE# CLOCK, OE# Low Fixed) tWC Valid address A0~18 tCW CS# tAW tWP WE# OE# OE# = “L” level tWR *18, tAS VIL tWHZ I/O0~7 *21 *19,20 tOW Valid Data tDW *21 tDH Note 18. tWP is the interval between write start and write end. A write starts when both of CS# and WE# become active. A write is performed during the overlap of a low CS# and a low WE#. A write ends when any of CS# or WE# becomes inactive. 19. tWHZ is defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 20. This parameter is sampled and not 100% tested. 21. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins. R10DS0217EJ0001 Rev.0.01 2013.09.10 Page 8 of 10 RMLV0408E Series Preliminary Write Cycle (3) (CS# CLOCK) tWC Valid address A0~18 tAW tAS tWR tCW CS# tWP *22 WE# OE# VIH OE# = “H” level tDW I/O0~7 tDH Valid Data Note 22. tWP is the interval between write start and write end. A write starts when both of CS# and WE# become active. A write is performed during the overlap of a low CS# and a low WE#. A write ends when any of CS# or WE# becomes inactive. R10DS0217EJ0001 Rev.0.01 2013.09.10 Page 9 of 10 RMLV0408E Series Preliminary Low VCC Data Retention Characteristics Test conditions*24 Parameter Symbol Min. Typ. Max. Unit VCC for data retention VDR 1.5 ─ ─ V Vin ≥ 0V, CS# ≥ VCC-0.2V ─ 0.4*23 2 A ~+25°C ─ ─ 3 A ~+40°C ─ ─ 5 A ~+70°C ─ ─ 7 A ~+85°C Data retention current ICCDR VCC=3.0V, Vin ≥ 0V, CS# ≥ Vcc-0.2V Chip deselect time to data retention tCDR 0 ─ ─ ns See retention waveform. Operation recovery time tR 5 ─ ─ ms Note 23. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. 24. CS# controls address buffer, WE# buffer, OE# buffer, and I/O buffer. If CS# controls data retention mode, Vin levels (address, WE#, OE#, I/O) can be in the high-impedance state. Low Vcc Data Retention Timing Waveforms (CS# controlled) CS# Controlled VCC tCDR 2.2V 2.7V 2.7V VDR tR 2.2V CS# ≥ VCC - 0.2V CS# R10DS0217EJ0001 Rev.0.01 2013.09.10 Page 10 of 10 Revision History RMLV0408E Series Data Sheet Description Rev. Date 0.01 2013.09.10 Page ─ Summary Preliminary First Edition issued All trademarks and registered trademarks are the property of their respective owners. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. 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