SS542

SS542
Hall Latch - High Sensitivity
Features and Benefits
Application Examples
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CMOS Hall IC Technology
Bipolar Output CMOS Multi-purpose latch
Solid-State Reliability much better than reed
switch
Operation down to 2.5V
Supply current down to 45μA, very low power
consumption
CMOS inverter output (no pull-up resistance)
High sensitivity for direct reed switch replacement application
Solid state switch
Magneto-electric conversion switch
Magnet proximity sensor for reed switch replacement in low duty cycle applications
3 pin TSOT23 (suffix ST)
3 pin SIP (suffix UA)
Functional Block Diagram
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V3.10 Nov 1, 2013
SS542
Hall Latch - High Sensitivity
General Description
The SS542 Hall effect sensor IC is fabricated from mixed signal CMOS technology. It incorporates advanced
chopper-stabilization techniques to provide accurate and stable magnetic switch points.
The circuit design provides an internally controlled clocking mechanism to cycle power to the Hall element and
analog signal processing circuits. This serves to place the high current-consuming portions of the circuit into a
“Sleep” mode. Periodically the device is “Awakened” by this internal logic and the magnetic flux from the Hall
element is evaluated against the predefined thresholds. If the flux density is above or below the Bop/Brp thresholds
then the output transistor is driven to change states accordingly. While in the “Sleep” cycle the output transistor is
latched in its previous state. The design has been optimized for service in applications requiring extended operating
lifetime in battery powered systems.
The output transistor of the SS542 switches low (turns on) when a magnetic field perpendicular to the Hall sensor
exceeds the operate point threshold (BOP). After turn-on, the output voltage is VDS. The device remains on if the
south pole is removed (B→0). Thi s latching property defines the device as a magnetic memory. When the magnetic field is reduced below the release point, BRP, the Output transistor turns off (goes high). The difference in the
magnetic operate and release points is the hysteresis (BHYS) of the device. This built-in hysteresis prevents output
oscillation near the switching point, and allows clean switching of the output even in the presence of external mechanical vibration and electrical noise.
The TSOT-23 device is reversed from the UA package. The TSOT-23 output transistor will be latched on in the
presence of a sufficiently strong North pole magnetic field applied to the marked face.
Glossary of Terms
Output level
Output level
OUT = High
OUT = High
BHYS
BHYS
OUT = Low
OUT = Low
BRP
-30Gs typ
0mT
BOP
30Gs typ
BRP
-30Gs typ
Flux density
STT
UA package - Latch characteristic
package
0mT
BOP
30Gs typ
Flux density
- Latch characteristic
Internal Timing Circuit
Current
Period
Iaw
Sample &
Output
Iav
Isp
Awake Taw:20μs
Sleep Tsl:600μs
0
Time
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V3.10 Nov 1, 2013
SS542
Hall Latch - High Sensitivity
Absolute Maximum Ratings
Parameter
Symbol
VDD
Supply Voltage
Value
28
Units
V
Supply Current
IDD
50
mA
Output Voltage
VOUT
28
V
Output Current
IOUT
50
mA
Operating Temperature Range
TA
-40 to 85
°C
Storage Temperature Rang
TS
-50 to 150
°C
-
4000
V
ESD Sensitivity
Operating Temperature Range
Symbol
Value
Units
Temperature Suffix “ E”
TA
-40 to 85
°C
Temperature Suffix “ K”
TA
-40 to 125
°C
Temperature Suffix “ L”
TA
-40 to 150
°C
Exceeding the absolute maximum ratings may cause permanent damage. Exposure to absolute-maximum- rated conditions for extended periods may affect device reliability.
General Electrical Specifications
DC Operating Parameters TA = 25°C, VDD= 2.5V to 5.5V (unless otherwise specified)
Parameter
Symbol
Test Conditions
Operating voltage
VDD
Operating
Supply current
IDD
Average
Output Current
IOUT
Saturation Voltage
VSAT
IOUT=1mA
Awake mode time
TAW
Operating
Sleep mode time
TSL
Operating
Min
Typ
Max
Units
2.5
3
5.5
V
45
μA
1.0
mA
0.4
V
μS
20
μS
600
Magnetic Specifications
DC Operating Parameters VDD = 2.5 to 5.5V (unless otherwise specified)
Package
Parameter
Symbol
Operating Point
BOP
Test Conditions
Min
Typ
Max
Units
5
25
40
G
-40
-25
-5
G
Ta=25°C
UA
Release Point
BRP
Hysteresis
BHYST
Operating Point
BOP
Vdd=2.75V DC
40
G
-40
-25
-5
G
5
25
40
G
Ta=25°C
SO
Release Point
Hysteresis
BRP
Vdd=2.75V DC
BHYST
40
3
G
V3.10 Nov 1, 2013
SS542
Hall Latch - High Sensitivity
Output Behavior versus Magnetic Pole
DC Operating Parameters TA = -40°C to 150°C, VDD = 2.5 to 5.5V (unless otherwise specified)
Test Conditions (UA)
Test Conditions (SO)
OUT
B < BRP
B > BRP
High
B > BOP
B < BOP
Low
The SOT-23 device is reversed from the UA package. The SOT-23 output transistor will be turned on(drops low) in the presence of a
sufficiently strong North pole magnetic field applied to the marked face and turned off(hoists high) in the presence of a sufficiently
strong South pole magnetic field.
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V3.10 Nov 1, 2013
SS542
Hall Latch - High Sensitivity
Package Information
2.13
0.76 ± 0.05
1.58 ± 0.1
Package UA, 3-Pin SIP:
3° ± 1°
1.00
45° ± 1°
4.1 ± 0.1
1
2
3
3.18 ± 0.1
Sensor Location
Active Area Depth:
0.84(Nom)
3° ± 1°
6° ± 1°
3° ± 1°
6° ± 1°
1
2
0.05 ± 0.05
3
2.3.± 0.1
3 - 0.44
14 ± 0.5
3 - 0.39
Notes:
1). Controlling dimension : mm ;
2). Lesds must be free of flash and plating voids ;
3). Do not bend leads within 1 mm of lead to package interface ;
4). PINOUT: Pin 1
VDD
Pin 2 GND
Pin 3 Output
1.27
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V3.10 Nov 1, 2013
SS542
Hall Latch - High Sensitivity
Package STT, 3-Pin TSOT-23:
Notes:
1). PINOUT:
Top View
Pin 1 VDD
Pin 2 Output
Pin 3 GND
2). All dimensions are in millimeters ;
3
1.60 2.65
1
2
1.70
Side View
End View
2.82
0.08
0.70
0.70
0.20
0.00
0.35
Hall Plate Location
Bottom View of TSOT-23 Package
3
Chip
0.36
0.46
0.95
2
1
1.50
Ordering Information
Part No.
SS542ESTT
SS542EAU
SS542KSTT
SS542KAU
SS542LSTT
SS542LAU
Pb-free
YES
YES
YES
YES
YES
YES
Temperature Code
-40°C to 85°C
-40°C to 85°C
-40°C to 125°C
-40°C to 125°C
-40°C to 150°C
-40°C to 150°C
Package Code
TSOT-23
TO-92
TSOT-23
TO-92
TSOT-23
TO-92
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Packing
7-in. reel, 3000 pieces/ reel
Bulk, 1000 pieces/ bag
7-in. reel, 3000 pieces/ reel
Bulk, 1000 pieces/ bag
7-in. reel, 3000 pieces/ reel
Bulk, 1000 pieces/ bag
V3.10 Nov 1, 2013