ADS-931 16-Bit, 1 MHz Sampling A/D Converters PRODUCT OVERVIEW FEATURES 16-bit resolution 1MHz sampling rate Functionally complete No missing codes over full HI-REL temperature range Edge-triggered ±5V supplies, 1.85 Watts Small, 40-pin, ceramic TDIP 87dB SNR, –89dB THD Ideal for both time and frequency-domain applications The low-cost ADS-931 is a 16-bit, 1MHz sampling A/D converter. This device accurately samples full-scale input signals up to Nyquist frequencies with no missing codes. The dynamic performance of the ADS-931 has been optimized to achieve a signal-to-noise ratio (SNR) of 87dB and a total harmonic distortion (THD) of –89dB. Packaged in a 40-pin TDIP, the functionally complete ADS-931 contains a fast-settling sample-hold amplifier, a subranging (two-pass) A/D converter, an internal reference, timing/control logic, and error-correction circuitry. Digital input and output levels are TTL. The ADS-931 only requires the rising edge of the start convert pulse to operate. Requiring only ±5V supplies, the ADS-931 dissipates 1.85 Watts. The device is offered with a bipolar (±2.75V) analog input range or a unipolar (0 to –5.5V) input range. Models are available in commercial (0 to +70°C), industrial (–40 to +100°C), or HI-REL (–55 to +125°C) operating temperature ranges. A proprietary, auto-calibrating, error-correcting circuit enables the device to achieve specified performance over the full military temperature range. Typical applications include medical imaging, radar, sonar, communications and instrumentation. PIN INPUT/OUTPUT CONNECTIONS FUNCTION PIN FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 +3.2V REF. OUT UNIPOLAR ANALOG INPUT ANALOG GROUND OFFSET ADJUST GAIN ADJUST DIGITAL GROUND FIFO/DIR FIFO READ FSTAT1 FSTAT2 START CONVERT BIT 16 (LSB) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NO CONNECTION NO CONNECTION +5V ANALOG SUPPLY –5V SUPPLY ANALOG GROUND COMP. BITS OUTPUT ENABLE OVERFLOW EOC +5V DIGITAL SUPPLY DIGITAL GROUND BIT 1 (MSB) BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BLOCK DIAGRAM 10 FSTAT1 11 FSTAT2 GAIN ADJUST 6 GAIN ADJUST CKT. 8 FIFO/DIR 9 FIFO/READ 29 BIT 1 (MSB) ANALOG GROUND 4, 36 DIGITAL GROUND 7, 30 +5V DIGITAL SUPPLY 31 –5V SUPPLY 37 +5V ANALOG SUPPLY 38 NO CONNECTION OFFSET ADJUST 5 OFFSET ADJUST CKT. UNIPOLAR 2 39, 40 ANALOG INPUT 3 S/H 26 BIT 3 25 BIT 4 24 BIT 5 3-STATE OUTPUT REGISTER POWER and GROUNDING 27 BIT 2 CUSTOM GATE ARRAY PRECISION +3.2V REFERENCE 2-PASS ANALOG-TO-DIGITAL CONVERTER 28 BIT 1 (MSB) +3.2V REF. OUT 1 23 BIT 6 22 BIT 7 21 BIT 8 20 BIT 9 19 BIT 10 18 BIT 11 17 BIT 12 16 BIT 13 15 BIT 14 14 BIT 15 13 BIT 16 (LSB) OFFSET ADJUST 5 START CONVERT 12 EOC 32 34 OUTPUT ENABLE TIMING AND CONTROL LOGIC 33 OVERFLOW COMP. BITS 35 Figure 1. ADS-931 Functional Block Diagram DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 12 Aug 2015 MDA_ADS-931.D01 Page 1 of 9 ADS-931 16-Bit, 1 MHz Sampling A/D Converters ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS +5V Supply (Pins 31, 38) 0 to +6 –5V Supply (Pin 37) 0 to –6 Digital Inputs (Pins 8, 9, 12, 34, 35) –0.3 to +VDD +0.3 Analog Input (Pin 3) Bipolar ±5 Unipolar -10 to +5 Lead Temperature (10 seconds) +300 PHYSICAL/ENVIRONMENTAL PARAMETERS MIN. TYP. MAX. UNITS Operating Temp. Range, Case ADS-931MC, MC-C 0 — +70 °C ADS-931ME, ME-C –40 — +100 °C ADS-931MM, MM-C, 883-C –55 — +125 °C Thermal Impedance Volts θjc — 4 — Volts °C/Watt °C θca — 18 — °C/Watt Storage Temperature Range –65 — +150 °C Package Type 40-pin, metal-sealed, ceramic TDIP Weight 0.56 ounces (16 grams) FUNCTIONAL SPECIFICATIONS (TA = +25°C, -VCC = -5V +VDD = +5V, 1MHz sampling rate, and a minimum 3 minute warmup ➀ unless otherwise specified.) UNITS Volts Volts Volts +25°C ANALOG INPUT Input Voltage Range Unipolar Bipolar Input Resistance (pin 3) Input Resistance (pin 2) Input Capacitance 0 TO +70°C –55 TO +125°C MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS — — 655 — — 0 to –5.5 ±2.75 685 400 10 — — — — 15 — — 655 — — 0 to –5.5 ±2.75 685 426 10 — — — — 15 — — 655 — — 0 to –5.5 ±2.75 685 426 10 — — — — 15 Volts Volts Ω Ω pF DIGITAL INPUT Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" ➁ Start Convert Positive Pulse Width ➂ +2.0 — — — 40 — — — — 100 — +0.8 +20 –20 — +2.0 — — — 40 — — — — 100 — +0.8 +20 –20 — +2.0 — — — 40 — — — — 100 — +0.8 +20 –20 — Volts Volts μA μA ns STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Bipolar Zero Error (Tech Note 2) Bipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) — — –0.95 — — — — 16 16 ±1.0 ±0.5 ±0.1 ±0.1 ±0.1 ±0.1 — — — +1.0 ±0.3 ±0.2 ±0.3 ±0.3 — — — –0.95 — — — — 16 16 ±1.5 ±0.5 ±0.15 ±0.2 ±0.2 ±0.15 — — — +1.0 ±0.5 ±0.4 ±0.5 ±0.5 — — — –0.95 — — — — 16 16 ±2.0 ±0.5 ±0.5 ±0.5 ±0.4 ±0.5 — — — +1.5 ±0.8 ±0.9 ±0.9 ±0.9 — Bits LSB LSB %FSR %FSR %FSR %FSR Bits — — –91 –88 –80 –80 — — –91 –88 –80 –80 — — –90 –86 –78 –78 dB dB — — –89 –87 –79 –79 — — –89 –87 –79 –79 — — –87 –85 –77 –77 dB dB 84 83 87 86 — — 84 83 87 86 — — 82 80 86 84 — — dB dB 80 79 85 84 — — 80 79 85 84 — — 77 76 83 82 — — dB dB — — –89 82 — — — — –89 82 — — — — –89 82 — — dB μVrms — — — — — — 4.8 4.1 90 ±51 8 5 — — — — — — — — — — — — 4.8 4.1 90 ±51 8 5 — — — — — — — — — — — — 4.8 4.1 90 ±51 8 5 — — — — — — MHz MHz dB V/μs ns ps rms 700 — 1 725 — — — 500 — 700 — 1 725 — — — 500 — 700 — 1 725 — — — 500 — ns ns MHz DYNAMIC PERFORMANCE Peak Harmonics (–0.5dB) dc to 250kHz 250kHz to 500kHz Total Harmonic Distortion (–0.5dB) dc to 250kHz 250kHz to 500kHz Signal-to-Noise Ratio (w/o distortion, –0.5dB) dc to 250kHz 250kHz to 500kHz Signal-to-Noise Ratio (& distortion, –0.5dB) ➃ dc to 250kHz 250kHz to 500kHz Two-tone Intermodulation Distortion Distortion (fin = 98kHz, 240kHz, fs = 1MHz, –0.5dB) Noise Input Bandwidth (–3dB) Small Signal (–20dB input) Large Signal (–0.5dB input) Feedthrough Rejection (fin = 480kHz) Slew Rate Aperture Delay Time Aperture Uncertainty S/H Acquisition Time (to ±0.001%FSR, 5.5V step) Overvoltage Recovery Time ➄ A/D Conversion Rate DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 12 Aug 2015 MDA_ADS-931.D01 Page 2 of 9 ADS-931 16-Bit, 1 MHz Sampling A/D Converters +25°C ANALOG OUTPUT Internal Reference Voltage Drift External Current 0 TO +70°C –55 TO +125°C MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS 3.15 — — +3.2 ±30 5 3.25 — — 3.15 — — +3.2 ±30 5 3.25 — — 3.15 — — +3.2 ±30 5 3.25 — — Volts ppm/°C mA — +0.4 –4 +4 20 Volts Volts mA mA ns DIGITAL OUTPUTS Logic Levels Logic "1" +2.4 — — +2.4 — — +2.4 — Logic "0" — — +0.4 — — +0.4 — — Logic Loading "1" — — –4 — — –4 — — Logic Loading "0" — — +4 — — +4 — — Delay, Falling Edge of ENABLE to Output Data Valid — — 20 — — 20 — — Output Coding: Straight Binary, Complementary Binary, Complementary Offset Binary, Complementary Two's Complement, Offset Binary, Two's Complement POWER REQUIREMENTS , ±15V Power Supply Ranges +5V Supply –5V Supply Power Supply Currents +5V Supply –5V Supply Power Dissipation Power Supply Rejection +4.75 –4.75 +5.0 –5.0 +5.25 –5.25 +4.75 –4.75 +5.0 –5.0 +5.25 –5.25 +4.9 –4.9 +5.0 –5.0 +5.25 –5.25 Volts Volts — –140 — — +225 –135 1.85 — 260 — 2.0 ±0.07 — –140 — — +225 –135 1.85 — 260 — 2.0 ±0.07 — –140 — — +225 –135 1.85 — 260 — 2.0 ±0.07 mA mA Watts %FSR/%V Footnotes: ➀ All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warmup periods. The device must be continuously converting during this time. There is a slight degradation in performance when operating the device in the unipolar mode. ➁ When COMP. BITS (pin 35) is low, logic loading "0" will be –350μA. ➂ A 1MHz clock with a positive pulse width is used for all production testing. See Timing Diagram for more details. 40ns < Start Pulse < 175ns or 280ns < Start Pulse < 460ns ➃ Effective bits is equal to: (SNR + Distortion) – 1.76 + Full Scale Amplitude Actual Input Amplitude 6.02 ➄ This is the time required before the A/D output data is valid once the analog input is back within the specified range. This time is only guaranteed if the input does not exceed ±4.75V (bipolar) or +2 to –7.5V (unipolar). ➅ The minimum supply voltages of +4.9V and –4.9V for ±VDD are required for –55°C operation only. The minimum limits are +4.75V and –4.75V when operating at +125°C. TECHNICAL NOTES 1. Obtaining fully specified performance from the ADS-931 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (4, 7, 30 and 36) directly to a large analog ground plane beneath the package. 4. To enable the three-state outputs, connect ENABLE (pin 34) to a logic "0" (low). To disable, connect pin 34 to a logic "1" (high). 5. Applying a start convert pulse while a conversion is in progress (EOC = logic "1") will initiate a new and probably inaccurate conversion cycle. Data from both the interrupted and subsequent conversions will be invalid. Bypass all power supplies and the +3.2V reference output to ground with 4.7μF tantalum capacitors in parallel with 0.1μF ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. 2. The ADS-931 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warmup. To avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not using offset and gain adjust circuits. 3. Pin 35 (COMP. BITS) is used to select the digital output coding format of the ADS-931 (see Tables 2a and 2b). When this pin has a TTL logic "0" applied, it complements all of the ADS-931's B1-B16 & B1outputs. Pin 35 is TTL compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal pull-up resistor on pin 35 allowing it to be either connected to +5V or left open when a logic "1" is required. DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA 20 log 6. Do not enable/disable or complement the output bits or read from the FIFO during the conversion process (from the rising edge of EOC to the falling edge of EOC). 7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the input voltage exceeds that which produces an output of all 1’s or when the input equals or exceeds the voltage that produces all 0’s. When COMP BITS is activated, the above conditions are reversed. 8. When configuring the ADS-931 for the unipolar mode, Pin 1 (+3.2V REF.) should be connected to Pin 2 (Unipolar) through a non-inverting op-amp. For precision DC applications an OP- 07 type amplifier is recommended, while AC applications requiring the lowest level of harmonic distortion should consider the AD9631. When configuring the ADS-931 for the bipolar mode, Pin 2 (Unipolar) should be physically disconnected from the surrounding circuitry. This will help prevent noise from coupling into the A/D. • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 12 Aug 2015 MDA_ADS-931.D01 Page 3 of 9 ADS-931 16-Bit, 1 MHz Sampling A/D Converters INTERNAL FIFO OPERATION The ADS-931 contains an internal, user-initiated, 18-bit, 16- word FIFO memory. Each word in the FIFO contains the 16 data bits as well as the MSB and OVERFLOW bits. Pins 23 (FIFO/DIR) and 10 (FIFO READ) control the FIFO's operation. The FIFO's status can be monitored by reading pins 10 (FSTAT1) and 11 (FSTAT2). When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the digital data path. When pin 8 has a logic "0" applied, the FIFO is transparent, and the output data goes directly to the output three-state register (whose operation is controlled by pin 34 (ENABLE)). Read and write commands to the FIFO are ignored when the ADS-931 is operated in the "direct" mode. It takes a maximum of 20ns to switch the FIFO in or out of the ADS-931's digital data path. Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both equal to "1"), it can be read by dropping the FIFO READ line (pin 9) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is already present at the FIFO output, the first read command (the first rising edge applied to FIFO READ) will bring data from the second conversion to the output. Each subsequent read command/rising edge brings the next word to the output lines. After the 15th rising edge brings the 16th data word to the FIFO output, the subsequent falling edge on READ will update the status outputs (after a 20ns maximum delay) to FSTAT1 = 0, FSTAT2 = 1 indicating that the FIFO is empty. If a read command is issued after the FIFO empties, the last word (the 16th conversion) will remain present at the outputs. FIFO Reset Feature FIFO WRITE and READ Modes Once the FIFO has been enabled (pin 8 high), digital data is automatically written to it, regardless of the status of FIFO READ (pin 9). Assuming the FIFO is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 9 (which controls the FIFO's READ function) should not be low when data is first written to an empty FIFO. When the FIFO is initially empty, digital data from the first conversion (the "oldest" data) appears at the output of the FIFO immediately after the first conversion has been completed and remains there until the FIFO is read. At any time, the FIFO can be reset to an empty state by putting the ADS-931 into its "direct" mode (logic "0" applied to pin 8, FIFO/DIR) and also applying a logic "0" to the FIFO READ line (pin 9). The empty status of the FIFO will be indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status outputs change 40ns after applying the control signals. FIFO Status, FSTAT1 and FSTAT2 Monitor the status of the data in the FIFO by reading the two status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11). If the output three-state register has been enabled (logic "0" applied to pin 34), data from the first conversion will appear at the output of the ADS-931. Attempting to write a 17th word to a full FIFO will result in that data, and any subsequent conversion data, being lost. DELAY PIN CONTENTS Empty (0 words) <half full (≤7 words) half-full or more (≥8 words) Full (16 words) TRANSITION Direct mode to FIFO enabled 8 FIFO enabled to direct mode 8 0 1 FIFO READ to output data valid 9 0 FIFO READ to status update when changing from <half full (1 word) to empty 9 1 FIFO READ to status update when changing from rhalf full (8 words) to <half full (7 words) 9 0 FIFO READ to status update when changing from full (16 words) to rhalf full (15 words) 9 0 Falling edge of EOC to status update when writing first word into empty FIFO 32 1 Falling edge of EOC to status update when changing FIFO from <half full (7 words) to rhalf full (8 words) 32 1 Falling edge of EOC to status update when filling FIFO with 16th word 32 1 MIN. 1 FSTAT1 0 0 1 1 TYP. FSTAT2 1 0 0 1 MAX. UNITS – 10 20 ns 0 1 – 10 20 ns – – 40 ns 0 – – 20 ns 1 – – 110 ns – – 190 ns 0 – – 190 ns 0 – – 110 ns 0 – – 28 ns 1 Table 1. FIFO Delays DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 12 Aug 2015 MDA_ADS-931.D01 Page 4 of 9 ADS-931 16-Bit, 1 MHz Sampling A/D Converters Zero/Offset Adjust Procedure CALIBRATION PROCEDURE 1. Apply a train of pulses to the START CONVERT input (pin 12) so that the converter is continuously converting. Connect the converter per Figure 2. Any offset/gain calibration procedures should not be implemented until the device is fully warmed up. To avoid interaction, adjust offset before gain. The ranges of adjustment for the circuits in Figure 2 are guaranteed to compensate for the ADS-931’s initial accuracy errors and may not be able to compensate for additional system errors. 2. For unipolar or bipolar zero/offset adjust, apply –42μV to the ANALOG INPUT (pin 3). 3. For bipolar inputs, adjust the offset potentiometer until the code flickers between 1000 0000 0000 0000 and 0111 1111 1111 1111 with pin 35 tied high (complementary offset binary) or between 0111 1111 1111 1111 and 1000 0000 0000 0000 with pin 35 tied low (offset binary). For unipolar inputs, adjust the offset potentiometers until all output bits are 0's and the LSB flickers between 0 and 1 with Pin 35 tied high (straight binary) or until all bits are 1's and the LSB flickers between 0 and 1 with pin 35 tied low (complementary binary). A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This is accomplished by connecting LED's to the digital outputs and performing adjustments until certain LED's "flicker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. For the ADS-931, offset adjusting is normally accomplished when the analog input is 0 minus ½ LSB (–42μV). See Table 2b for the proper bipolar output coding. 4. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the trimpot until the output code flickers between all 0’s and all 1’s. Gain adjusting is accomplished when the analog input is at nominal full scale minus 1½ LSB's (+2.749874V). Gain Adjust Procedure Note: Connect pin 5 to ANALOG GROUND (pin 4) for operation without zero/offset adjustment. Connect pin 6 to pin 4 for operation without gain adjustment. 1. Apply +2.749874V to the ANALOG INPUT (pin 3). OUTPUT FORMAT 2. For bipolar inputs, adjust the gain potentiometer until all output bits are 0’s and the LSB flickers between a 1 and 0 with pin 35 tied high (complementary offset binary) or until all output bits are 1’s and the LSB flickers between a 1 and 0 with pin 35 tied low (offset binary). PIN 35 LOGIC LEVEL Complementary Offset Binary 1 Offset Binary 0 Complementary Two’s Complement (Using MSB, pin 29) 1 Two’s Complement (Using MSB, pin 29) 0 Straight Binary 1 Complementary Binary 0 3. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the gain trimpot until the output code flickers equally between 0111 1111 1111 1111 and 0111 1111 1111 1110. Table 2a. Setting Output Coding Selection (Pin 35) 20kΩ +5V 20kΩ –5V +5V 6 GAIN ADJUST +5V 31 4.7μF 4.7μF + 0.1μF –5V 0.1μF 4.7μF 5 OFFSET ADJUST 33 OVERFLOW 32 EOC 29 BIT 1 (MSB) 28 BIT 1 (MSB) +5V DIGITAL DIGITAL 7, 30 GROUND 38 + +5V 0.1μF –5V +5V ANALOG ANALOG 4, 36 GROUND 37 –5V 34 ENABLE FIFO/DIR CONNECT for UNIPOLAR MODE 10 FSTAT1 2 UNIPOLAR 11 FSTAT2 1 +3.2V REF. OUT BIT2 BIT 3 BIT 4 BIT 5 23 22 21 20 BIT 6 BIT 7 BIT 8 BIT 9 19 BIT 10 18 BIT 11 17 BIT 12 16 BIT 13 15 BIT 14 14 BIT 15 13 BIT 16 (LSB) ADS-931 8 27 26 25 24 ANALOG INPUT 3 FIFO READ 9 6.8μF +5V START CONVERT 12 COMP. BITS 35 0.1μF 4.7μF Figure 2. Bipolar Connection Diagram DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 12 Aug 2015 MDA_ADS-931.D01 Page 5 of 9 ADS-931 16-Bit, 1 MHz Sampling A/D Converters THERMAL REQUIREMENTS not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electricallyinsulating, thermallyconductive "pads" may be installed underneath the package. Devices should be soldered to boards rather than "socketed", and of course, minimal air flow over the surface can greatly help reduce the package temperature. All DATEL sampling A/D converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70°C and –55 to +125°C. All room-temperature (TA = +25°C) production testing is performed without the use of heat sinks or forced-air cooling. Thermal impedance figures for each device are listed in their respective specification tables. These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do N N+1 N+3 N+2 START CONVERT 100ns typ. Acquisition Time 730ns typ. 20ns typ. Hold INTERNAL S/H 270ns typ. 60ns typ. EOC 55ns typ. 280ns typ. Conversion Time 20ns typ. OUTPUT DATA 940ns typ. Data N-4 Valid Data N-2 Valid Data N-3 Valid Invalid Data 60ns typ. Data N-1 Valid Invalid Data Notes: 1. Scale is approximately 50ns per division. fs = 1MHz. 2. This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data from the first conversion to appear at the output of the A/D. 3. The start convert positive pulse width must be between either 40 and 175nsec or 280 and 460nsec (when sampling at 1MHz) to ensure proper operation. For sampling rates lower than 1MHz, the start pulse can be wider than 460nsec, however a minimum pulse width low of 40nsec should be maintained. A 1MHz clock with a 100nsec positive pulse width is used for all production testing. Figure 3. ADS-931 Timing Diagram 0 –10 Amplitude Relative to Full Scale (dB) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 0 50 100 150 200 250 300 350 400 450 500 Frequency (kHz) (fs = 1MHz, fin = 480kHz, Vin = –0.5dB, 16,384-point FFT) Figure 4. FFT Analysis of ADS-931 DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 12 Aug 2015 MDA_ADS-931.D01 Page 6 of 9 ADS-931 Figure 5. ADS-931 Evaluation Board Schematic 16-Bit, 1 MHz Sampling A/D Converters DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 12 Aug 2015 MDA_ADS-931.D01 Page 7 of 9 ADS-931 16-Bit, 1 MHz Sampling A/D Converters COMP. BINARY UNIPOLAR SCALE –FS +1 LSB –FS +1 1/2 LSB –7/8 FS –3/4 FS –1/2FS –1/2FS –1/2LSB –1/4FS –1/8FS –1 LSB –1/2LSB 0 INPUT RANGE 0 to 0 to –5.5V –5.499916 –5.499874 –4.812500 –4.125000 –2.750000 –2.749958 –1.375000 –0.687500 –0.000084 –0.000042 0.000000 MSB LSB 1111 1111 1111 1111 LSB "1" to "0" 1110 0000 0000 0000 1100 0000 0000 0000 1000 0000 0000 0000 0111 1111 1111 1111 0100 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0001 LSB "0" to "1" 0000 0000 0000 0000 MSB LSB 0000 0000 0000 0000 LSB "0" to "1" 0001 1111 1111 1111 0011 1111 1111 1111 0111 1111 1111 1111 1000 0000 0000 0000 1011 1111 1111 1111 1101 1111 1111 1111 1111 1111 1111 1110 LSB "1" to "0" 1111 1111 1111 1111 OFFSET BINARY MSB LSB 0111 1111 1111 1111 LSB "1" to "0" 0110 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1100 0000 0000 0000 1010 0000 0000 0000 1000 0000 0000 0001 LSB "0" to "1" 1000 0000 0000 0000 COMP. TWO'S COMP. MSB LSB 1000 0000 0000 0000 LSB "0" to "1" 1001 1111 1111 1111 1011 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0011 1111 1111 1111 0101 1111 1111 1111 0111 1111 1111 1110 LSB "1" to "0" 0111 1111 1111 1111 TWO'S COMP. INPUT RANGE ±2.75V +2.749916 +2.749874 +2.062500 +1.375000 0.000000 –0.000084 –1.375000 –2.062500 –2.749916 –2.749958 –2.750000 BIPOLAR SCALE +FS –1 LSB +FS –1 1/2 LSB +3/4 FS +1/2 FS 0 –1/2 LSB –1/2 FS –3/4 FS –FS +1 LSB –FS + 1/2 LSB –FS Table 2b. Output Coding INPUT RANGE INPUT PIN TIE TOGETHER 0 to –5.5V Pin 3 Pin 1 To Pin 2 ±2.75V Pin 3 Pin 2 is No Connect Table 3. Input Connections 0.71 4530 4000 DNL (LSB's) Number of Occurrences 2147 0.00 3000 2000 –0.56 0 65,536 Codes 1000 0 Digital Output Code Figure 7. ADS-931 Grounded Input Histogram This histogram represents the typical peak-to-peak noise (including quantization noise) associated with the ADS-931. 0 Digital Output Code 65,536 Figure 6. ADS-931 Histogram and Differential Nonlinearity DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 12 Aug 2015 MDA_ADS-931.D01 Page 8 of 9 ADS-931 16-Bit, 1 MHz Sampling A/D Converters MECHANICAL DIMENSIONS - INCHES (mm) 2.12/2.07 (53.85/52.58) 40 Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) ±0.010 (±0.254) 3 place decimal (.XXX) ±0.005 (±0.127) 21 Lead Material: Kovar alloy 1.11/1.08 (28.20/27.43) 1 Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 20 0.100 TYP. (2.540) 1.900 ±0.008 (48.260) 0.245 MAX. (6.223) PIN 1 INDEX ( ON TOP) 0.200/0.175 (5.080/4.445) 0.015/0.009 (0.381/0.229) 0.210 MAX. (5.334) 0.018 ±0.002 (0.457) 0.110/0.090 (2.794/2.286 0.900 ±0.010 (22.86) 0.110/0.090 (2.794/2.286) SEATING PLANE 0.035/0.015 (0.889/0.381) 0.045/0.035 (1.143/0.889) ORDERING INFORMATION MODEL NUMBER OPERATING TEMP. RANGE PACKAGE ADS-931MC 0 to +70°C TDIP No ADS-B931 Evaluation Board (without ADS-931) ADS-931MC-C 0 to +70°C TDIP Yes HS-40 Heat Sink for all ADS-931 models ADS-931ME –40 to +100°C TDIP No ADS-931ME-C –40 to +100°C TDIP Yes ADS-931MM –55 to +125°C TDIP No ADS-931MM-C –55 to +125°C TDIP Yes ADS-931/883 –55 to +125°C TDIP No ADS-931-C/883 –55 to +125°C TDIP Yes ROHS ACCESSORIES Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL. DATEL is a registered trademark of DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. ITAR and ISO 9001/14001 REGISTERED © 2015 DATEL, Inc. www.datel.com • e-mail: [email protected] 12 Aug 2015 MDA_ADS-931.D01 Page 9 of 9