ADCDS-1403

ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
PRODUCT OVERVIEW
The ADCDS-1403 is an application-specific
video signal processor designed for electronicimaging applications that employ CCD's (charge
coupled devices) as their photodetector. The
ADCDS-1403 incorporates a "user configurable"
input amplifier, a CDS (correlated double sampler)
and a sampling A/D converter in a single package,
providing the user with a complete, high performance, low-cost, low-power, integrated solution.
The key to the ADCDS-1403's performance is
a unique, high-speed, high-accuracy CDS circuit,
which eliminates the effects of residual charge,
FEATURES
„ 14-bit resolution
„ 3MPPS throughput rate (14-bits)
charge injection and "kT/C" noise on the CCD's
output floating capacitor, producing a "valid video"
output signal. The ADCDS-1403 digitizes this
resultant "valid video" signal using a high-speed,
low-noise sampling A/D converter.
The ADCDS-1403 requires only the rising edge
of start convert pulse to initiate its conversion
process. Additional features of the ADCDS-1403
include gain adjust, offset adjust, precision +2.4V
reference, and a programmable analog bandwidth
function.
INPUT/OUTPUT CONNECTIONS
Function
Pin
„ Functionally complete
Pin
„ Very low noise
1
FINE GAIN ADJUST
40
NO CONNECT
Function
+12V
2
OFFSET ADJUST
39
„ Excellent Signal-to-Noise ratio
3
DIRECT INPUT
38
–5VA
„ Edge triggered
4
INVERTING INPUT
37
ANALOG GROUND
5
NON-INVERTING INPUT
36
+5VA
6
+2.4V REF. OUTPUT
35
ANALOG GROUND
„ Low power, 500mW typical
7
ANALOG GROUND
34
+5VD
„ Low cost
8
NO CONNECT
33
DIGITAL GROUND
9
NO CONNECT
32
DIGITAL GROUND
10
BIT 14 (LSB)
31
A1
11
BIT 13
30
AØ
12
BIT 12
29
NO CONNECT
13
BIT 11
28
NO CONNECT
14
BIT 10
27
DATA VALID
15
BIT 9
26
REFERENCE HOLD
16
BIT 8
25
START CONVERT
17
BIT 7
24
OUT-OF-RANGE
18
BIT 6
23
BIT 1 (MSB)
19
BIT 5
22
BIT 2
20
BIT 4
21
BIT 3
„ Small, 40-pin, TDIP package
„ Programmable Analog Bandwidth
+12VA
39
759
+5VA
–5VA
38
+5VD
36
34
5239
INVERTING INPUT 4
25 START CONVERT
1 FINE GAIN ADJUST
INPUT AMPLIFIER
0.01µF
DIRECT INPUT 3
NON-INVERTING INPUT 5
5K 9
CORRELATED
DOUBLE
SAMPLER
23 BIT 1 (MSB)
SAMPLING
A/D
10 BIT 14 (LSB)
OFFSET ADJUST 2
REFERENCE HOLD 26
TIMING
AND
CONTROL
24 OUT-OF-RANGE
6
32, 33
DIGITAL GROUND
27
DATA VALID
+2.4V REFERENCE OUTPUT
7, 35, 37
30 31
AØ A1
ANALOG GROUND
Figure 1. ADCDS-1403 Functional Block Diagram
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
08 Jul 2015 ADCDS-1403.C01 Page 1 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
ABSOLUTE MAXIMUM RATINGS
DYNAMIC PERFORMANCE
PARAMETERS
MIN.
TYP.
MAX.
UNITS
+12V Supply (Pin 32)
–5V Supply (Pin 38)
+5V Supply (Pin 34, 36)
Digital Input (Pin 25, 26, 30, 31)
Analog Input (Pin 3,4,5)
Lead Temperature (10 seconds)
0
–6.5
–0.3
–0.3
–6
—
—
—
—
—
—
—
+14
+0.3
+6.5
Vdd+0.3V
+6
300
Volts
Volts
Volts
Volts
Volts
°C
Functional Specifications
The following specifications apply over the operating temperature range, under the following conditions: Vcc=+12V, +Vdd=+5V, Vee=–5V, fin=98KHz, sample rate=3MHz.
ANALOG INPUT
MIN.
TYP.
MAX.
UNITS
Input Voltage Range
(externally configurable)
Input Resistance
Input Capacitance
0.350
—
—
2.8
5000
10
—
—
—
Volts p-p
Ohm
pF
DIGITAL INPUTS
Logic Level
Logic 1
Logic 0
Logic Loading
Logic 1
Logic 0
+3.5
—
—
—
—
+.80
Volts
Volts
—
—
—
—
+10
–10
uA
uA
DIGITAL OUTPUTS
Logic Levels
Logic 1 (IOH = .5ma)
Logic 1 (IOH = 50μa)
Logic 0 (IOL = 1.6ma)
Logic 0 (IOL = 50ua)
+2.4
+4.5
—
—
Internal Reference
Voltage
(Fine gain adjust pin (1) grounded)
+25°C
0 to 70°C
–55 to +125°C
External Current
—
—
—
—
—
—
+0.4
+0.1
Volts
Volts
Volts
Volts
2.35
2.35
2.35
2.4
2.4
2.4
2.45
2.45
2.45
Volts
Volts
Volts
—
1.0
—
mA
STATIC PERFORMANCE
Differential Nonlinearity
(Histogram, 98kHz) +25°C
0 to 70°C
–55 to +125°C
–0.90
–0.90
–1.0
±0.5
±0.5
±0.6
+.90
+.90
+1.0
LSB
LSB
LSB
Integral Nonlinearity
+25°C
0 to 70°C
–55 to +125°C
—
—
—
±2.5
±2.5
±2.5
—
—
—
LSB
LSB
LSB
Guaranteed No Missing Codes
0 to 70°C
–55 to +125°C
14
14
—
—
—
—
LSB
LSB
DC Noise
+25°C
0 to 70°C
–55 to +125°C
—
—
—
1.0
1.0
1.25
1.6
2.0
2.5
LSB
LSB
LSB
Offset Error
+25°C
0 to 70°C
–55 to +125°C
—
—
—
±0.6
±0.6
±0.6
±1.25
±1.25
±1.45
%FSR
%FSR
%FSR
Gain Error
+25°C
0 to 70°C
–55 to +125°C
—
—
—
±1.00
±1.35
±1.35
±2.8
±2.8
±2.8
%FSR
%FSR
%FSR
MIN.
TYP.
MAX.
UNITS
100
—
—
ns
—
—
25
100
—
—
mV/us
mV/us
Peak Harmonic (SFDR)
(CDD-IN, input on pin (3)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
—
—
—
–76
–76
–74
—
—
—
dB
dB
dB
Peak Harmonic (SFDR)
(Input on pin (5)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
—
—
—
–76
–76
–74
—
—
—
dB
dB
dB
—
—
—
–75
–75
–74
—
—
—
dB
dB
dB
—
—
—
–76
–76
–74
—
—
—
dB
dB
dB
73
73
70
75
75
73
—
—
—
dB
dB
dB
73
73
70
75
75
73
—
—
—
dB
dB
dB
—
—
—
71
71
70
—
—
—
dB
dB
dB
—
—
—
71
71
70
—
—
—
dB
dB
dB
3
—
20
—
200
150
—
—
—
MHz
nsec
nsec
+12.6
+5.25
–5.25
Volts
Volts
Volts
Reference Hold
Aquisition Time
Droop
@ +25°C
@ –55 to +125°C
Total Harmonic Distortion
(CDD-IN, input on pin (3)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
(Input on pin (5)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
Signal-to-Noise Ratio
Without Distortion
(CDD-IN, input on pin (3)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
(Input on pin (5)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
Signal-to-Noise Ratio
With Distortion
(CDD-IN, input on pin (3)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
(Input on pin (5)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
SIGNAL TIMING
Conversion Rate
–55 to +125°C
Conversion Time
Start Convert Pulse Width
POWER REQUIREMENTS
Power Supply Range
+12V Supply
+5V Supply
–5V Supply
+11.4
+4.75
–4.75
+12.0
+5.0
–5.0
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
08 Jul 2015 ADCDS-1403.C01 Page 2 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
POWER REQUIREMENTS
MIN.
TYP.
MAX.
UNITS
Power Supply Current
+12V Supply
—
+13
+16
mA
Power Supply Current
+5V Supply
–5V Supply
—
—
+40
–27
+46
–35
mA
mA
Power Dissipation
—
0.50
0.60
Watts
Power Supply Rejection
(5%) @ +25°C
—
±0.02
±0.03
%FSR/%V
Operating Temperature Range
ADCDS-1403
ADCDS-1403EX
0
–55
—
—
+70
+125
°C
°C
Storage Temperature
–65
—
+150
°C
ENVIRONMENTAL
Package Type
Weight
40-pin, TDIP
16.10 grams
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADCDS-1403 requires
careful attention to pc-card layout and power supply decoupling.
The device's analog and digital grounds are connected to each other
internally. Depending on the level of digital switching noise in the overall
CCD system, the performance of the ADCDS-1403 may be improved by
connecting all ground pins (7,32,33,35, 37) to a large analog ground
plane beneath the package. The use of a single +5V analog supply for
both the +5VA (pin 36) and +5VD (pin 34) may also be beneficial.
2. Bypass all power supplies to ground with a 4.7μf tantalum capacitor in
parallel with a 0.1μf ceramic capacitor. Locate the capacitors as close to
the package as possible.
Direct Mode (AC Coupled)
This is the most common input configuration as it allows the ADCDS1403 to interface directly to the output of the CCD with a minimum amount
of analog "front-end" circuitry. This mode of operation is used with fullscale video input signals from 0.350Vp-p to 2.8Vp-p.
Figure 2a. describes the typical configuration for applications using a
video input signal with a maximum amplitude of 0.350Vp-p. The coarse
gain of the input amplifier is determined from the following equation:
VOUT = 2.8Vp-p = VIN*(1+(523/75)), with all internal resistors having a 1%
tolerance. Additional fine gain adjustment can be accomplished using the
Fine Gain Adjust (pin 1 see Figure 5).
Figure 2b. describes the typical configuration for applications using a
video input signal with an amplitude greater than 0.350Vp-p and less than
2.8Vp-p. Using a single external series resistor (see Figure 4.), the coarse
gain of the ADCDS-1403 can be set, with additional fine gain adjustments
being made using the Fine Gain Adjust function (pin 1 see Figure 5). The
coarse gain of the input amplifier can be determined from the following
equation:
VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors having
a 1% tolerance.
VIN
NO CONNECT
4
759
3
0.01µF
5239
VOUT = 2.8Vp-p
5
5k9
3. If using the suggested offset and gain adjust circuits
(Figure 3 & 5), place them as close to the ADCDS-1403's package as
possible.
4. A0 and A1 (pins 30, 31) should be bypassed with 0.1μf capacitors to
ground to reduce susceptibility to noise.
Figure 2a.
Rext
ADCDS-1403 Modes of Operation
The input amplifier stage of the ADCDS-1403 provides the designer
with a tremendous amount of flexibility. The architecture of the ADCDS1403 allows its input-amplifier to be configured in any of the following
configurations:
• Direct Mode (AC coupled)
• Non-Inverting Mode
• Inverting Mode
When applying inputs which are less than 2.8Vp-p, a coarse gain
adjustment (applying an external resistor to pin 4) must be performed to
ensure that the full scale video input signal (saturated signal) produces a
2.8Vp-p signal at the input-amplifier's output (Vout).
In all three modes of operation, the video portion of the signal at the
CDS input (i.e. input-amplifier's Vout) must be more negative than its associated reference level and Vout should
not exceed ±2.8V DC.
The ADCDS-1403 achieves it specified accuracies without the need
for external calibration. If required, the device's small initial offset and
gain errors can be reduced to zero using the FINE GAIN ADJUST (pin1) and
OFFSET ADJUST (pin 2) features.
VIN
NO CONNECT
4
759
3
0.01µF
5239
VOUT = 2.8Vp-p
5
5k9
Figure 2b.
Rext
NO CONNECT
VIN
4
759
3
0.01µF
5239
VOUT = 2.8Vp-p
5
5k9
Figure 2c.
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
08 Jul 2015 ADCDS-1403.C01 Page 3 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
Non-Inverting Mode
Inverting Mode
The non-inverting mode of the ADCDS-1403 allows the designer to
either attenuate or add non-inverting gain to the video input signal. This
configuration also allows bypassing the ADCDS-1403's internal coupling
capacitor, allowing the user to provide an external capacitor of appropriate
value.
Figure 2c. describes the typical configuration for applications using
video input signals with amplitudes greater than
0.350Vp-p and less than 2.8Vp-p (with common mode limit of ±2.5V DC).
Using a single external series resistor (see Figure 4.), the coarse gain of the
ADCDS-1403 can be set with additional fine gain adjustments being made
using the Fine Gain Adjust function (pin 1 see Figure 5). The coarse gain of
the circuit can be determined from the following equation:
VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors having
a 1% tolerance.
Figure 2d. describes the typical configuration for applications using a
video input signal whose amplitude is greater than 2.8Vp-p. Using a single
external series resistor (Rext 1) in conjunction with the internal 5K (1%)
resistor to ground, an attenuation of the input signal can be achieved.
Additional fine gain adjustments being made using the Fine Gain Adjust
function (pin 1). The coarse gain of this circuit can be determined from the
following equation:
VOUT = 2.8Vp-p = [VIN*(5000/(Rext1+5000))]*
[1+(523/(75+Rext2))], with all internal resistors having
a 1% tolerance.
The inverting mode of operation can be used in applications where the
analog input to the ADCDS-1403 has a video input signal whose amplitude
is more positive than its associated reference level. The ADCDS-1403's
correlated double sampler (i.e. input amplifier's VOUT) requires that the
video signal's amplitude be more negative than its reference level at
all times (see timing diagram for details). Using the ADCDS-1403 in the
inverting mode allows the designer to perform an additional signal inversion to correct for any analog "front end" pre-processing that may have
occurred prior to the ADCDS-1403.
Figure 2e. describes the typical configuration for applications using
a video input signal with a maximum amplitude of 0.350Vp-p. Additional
fine gain adjustments can be made using the Fine Gain Adjust function (pin
1). The coarse gain of this circuit can be determined from the following
equation:
VOUT = 2.8Vp-p = –VIN*(523/75), with all internal resistors having a 1%
tolerance.
Figure 2f. describes the typical configuration used in applications
needing to invert video input signals whose amplitude is greater than
0.350Vp-p. Using a single external series resistor (see Figure 4.), the initial
gain of the ADCDS-1403 can be set, with additional fine gain adjustments
being made using the Fine Gain Adjust function (pin 1). The coarse gain of
this circuit can be determined from the following equation:
VOUT = 2.8Vp-p = –VIN*(523/75+Rext), with all internal resistors having a
1% tolerance.
Rext2
4
759
5239
ADCDS-1403
3
0.01µF
VOUT = 2.8Vp-p
NO CONNECT
Rext1
+5V
5
VIN
5k9
20K9
Figure 2d.
–VIN
4
759
3
0.01µf
–5V
Figure 3. Offset Adjustment Circuit
VOUT = 2.8Vp-p
5
Coarse Gain Adjustment Plot
External Gain Resistor vs. Full Scale Video Input
Figure 2e.
4
759
3
0.01µf
5239
VOUT = 2.8Vp-p
NO CONNECT
5
5k9
External Gain Resistor (Ohms)
5k9
Rext
Offset
Adjust
2
5239
NO CONNECT
–VIN
External
Series
Resistor
10000
Direct Mode
& Non-Inverting
Mode
1000
Inverting Mode
100
10
0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
Full Scale
Video
Signal
(Volts) Plot
Figure
4. Coarse
Gain
Adjustment
Figure 2f.
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
08 Jul 2015 ADCDS-1403.C01 Page 4 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
Offset Adjustment
Manual offset adjustment for the ADCDS-1403 can be accomplished
using the adjustment circuit shown in Figure 3. A software controlled
D/A converter can be substituted for the 20KΩ potentiometer. The offset
adjustment feature allows the user to adjust the Offset/Dark Current level
of the ADCDS-1403 until the output bits are 00 0000 0000 0000 and the
LSB flickers between 0 and 1. Offset adjust should be performed before
gain adjust to avoid interaction. The ADCDS-1403's offset adjustment is
dependent on the value of the external series resistor used in the offset
adjust circuit (Figure 3). The Offset Adjustment graph (Figure 6) illustrates
the typical relationship between the external series resistor value and its
offset adjustment capability utilizing ±5V supplies.
For Example:
External 50KΩ resistor:
1.
10mV of noise or voltage variation at the potentiometer
will produce 0.25LSB's of output variation.
2.
100mV of noise or voltage variation at the potentiometer
will produce 2.5LSB's of output variation.
The Offset Adjustment Sensitivity graph (Figure 7) illustrates the offset
adjustment sensitivity over a wide range of external resistor and noise
values. If a large offset voltage is required, it is recommended that a very
low noise external reference be used in the offset adjust circuit in place
of power supplies. The ADCDS-1403's +2.4V reference output could be
configured to provide the reference voltage for this type of application.
Offset Adjustment Sensitivity
Fine Gain Adjustment
It should be noted that with increasing amounts of offset adjustment
(smaller values of external series resistors), the ADCDS-1403 becomes
more susceptible to power supply noise or voltage variations seen at the
wiper of the offset potentiometer.
Fine gain adjustment (pin 1) is provided to compensate for the tolerance of the external coarse gain resistor (Rext) and/or the unavailability of
exact coarse gain resistor (Rext) values. Note, the fine gain adjustment will
not change the expected input amplifier's full scale VOUT (2.8Vp-p.) Instead,
the gain of the ADCDS-1403's internal A/D is adjusted allowing the actual
input amplifier's full scale VOUT to produce an output code of all ones (11
1111 1111 1111).
Fine gain adjustment for the ADCDS-1403 is accomplished using
the adjustment circuit shown below (Figure 5). A software controlled D/A
converter can be substituted for the 20KΩ potentiometer. The fine gain
adjust circuit ensures that the video input signal (saturated signal) will be
properly scaled to obtain the desired Full Scale digital output of 11 1111
1111 1111, with the LSB flickering between 0 and 1. Fine gain adjust
should be performed following the offset adjust to avoid interaction. The
fine gain adjust provides ±256 codes of adjust when ±5V supplies are
used for the Fine Gain Adjust Circuit.
ADCDS-1403
Fine
Gain
Adjust
1
+5V
20K9
–5V
Figure 5. Fine Gain Adjustment Circuit
Offset Adjustment Sensitivity
External Series Resistor vs. Output Variation (LSB's)
Offset Adjustment vs. External Series Resistor
100
Output Variation (LSB's)
±LSB's of Adjustment
10000
1000
100
10
Peak-Peak
variation at
potentiometer
10
100mV
1
10mV
0.1
1mV
0.01
0
5k
10k 15k
20k 25k
30k 35k
40k 45k
50k
External Series Resistor (Ohm's)
Figure 6. Offset Adjustment vs. External Series Resistor
55k 60k
0
5K
10K 15K 20K 25K 30K 35K 40K 45K 50K 55K 60K
External Series Resistor Value (Ohms)
Figure 7. Offset Adjustment Sensitivity
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
08 Jul 2015 ADCDS-1403.C01 Page 5 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
Out-of-Range Indicator
Output Coding
The ADCDS-1403 provides a digital Out-of-Range output
signal (pin 24) for situations when the video input signal (saturated signal)
is beyond the input range of the internal A/D converter. The digital output
bits and the Out-of-Range signal correspond to a particular sampled video
input voltage, with both of these signals having a common pipeline delay.
Using the circuit described in Figure 8., both overrange and underrange conditions can be detected (see Table 1). When combined with a D/A
converter, digital detection and orrection can be performed for both the gain
and offset errors.
The ADCDS-1403's output coding is Straight Binary as indicated in
Table 2. The table shows the relationship between the output data coding
and the difference between the reference signal voltage and its corresponding video signal voltage. (These voltages are referred to the output of the
ADCDS-1403's input amplifier's VOUT).
MSB
"OVERRANGE"
OUT-OF-RANGE
"UNDERRANGE"
Figure 8. Overrange/ Underrange Circuit
Table 1. Out-of-Range Conditions
OUT OF
RANGE
MSB
OVER
RANGE
UNDER RANGE
INPUT SIGNAL
0
0
0
0
In Range
0
1
0
0
In Range
1
0
0
1
Underrrange
1
1
1
0
Overrange
Programmable Analog Bandwidth Function
When interfacing to CCD arrays with very high-speed "read-out" rates,
the ADCDS-1403's input stage must have sufficient analog bandwidth to
accurately reproduce the output signals of the CCD array. The amount of
analog bandwidth determines how quickly and accurately the "Reference
Hold" and the "CDS output" signals will settle. If only a single analog bandwidth was offered, the ADCDS-1403's bandwidth would be set to acquire
and digitize CCD output signals to 14-bit accuracy, at maximum conversion
rate of 3MHz (333ns see Figure 11. for details). Applications not requiring
the maximum conversion rate would be forced to use the full analog bandwidth at the possible expense of noise performance.
The ADCDS-1403 avoids this situation by offering a fully programmable
analog bandwidth function. The ADCDS-1403 allows the user to "bandwidth
limit" the input stage in order to realize the highest level of noise performance for the application being considered. Table 3. describes how to select
the appropriate reference hold "aquisition time" and CDS output "settling
time" needed for a particular application. Each of the selections listed in
Table 3. have been optimized to provide only enough analog bandwidth to
acquire a full scale input step, to 14-bit accuracy, in a single conversion.
Increasing the analog bandwidth (using a faster settling and acquisition
time) would only serve to potentially increase the amount of noise at the
ADCDS-1403's output. The ADCDS-1403 uses a two bit digital word to
select four different analog bandwidths for the ADCDS-1403's input stage
(See Table 3. for details).
Table 2. Output Coding
INPUT AMPLIFIER VOUT, ➀ (VOLTS P-P)
Video Signal-Reference Signal
Video Signal-Reference Signal
SCALE
DIGITAL OUTPUT
OUT-OF-RANGE
> –2.80000
>Full Scale –1LSB
11 1111 1111 1111
1
–2.80000
Full Scale –1LSB
11 1111 1111 1111
0
–2.10000
3/4FS
11 0000 0000 0000
0
–1.40000
1/2FS
10 0000 0000 0000
0
–0.70000
1/4FS
01 0000 0000 0000
0
–0.35000
1/8FS
00 1000 0000 0000
0
–0.000171
1 LSB
00 0000 0000 0001
0
0
0
00 0000 0000 0000
0
<0➁
<0
00 0000 0000 0000
1
Notes:
➀ Input Amplifier VOUT = (Video Signal - Reference Level)
➁ The video portion of the differential signal (input-amplifier's VOUT) must be more negative than its associated reference
level and VOUT should not exceed ±2.8V DC.
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
08 Jul 2015 ADCDS-1403.C01 Page 6 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
Table 3. Programmable Analog Bandwidth
REFERENCE HOLD
"ACQUISITION TIME"
CDS OUTPUT
"SETTLING TIME"
A0
(PIN 30)
A1
(PIN 31)
ADCDS-1403 MAXIMUM
CONVERSION RATE
–3DB BW
100ns
120ns
0
0
3MHz
10.5MHz
200ns
250ns
1
0
2MHz
6.6MHz
450ns
500ns
0
1
1MHz
3.7MHz
600ns
1000ns
1
1
0.5MHz
2.5MHz
Note: See Figure 11. for timing details
+12V
4.7μF
+
+5VD
4.7μF
+
–5VA
4.7μF
+
+5VA
4.7μF
+
0.1μF
0.1μF
0.1μF
0.1μF
39
+5V
1
20K
–5V
External Series
Resistor
+5V
36
38
23 BIT 1 (MSB)
FINE GAIN ADJUST
22 BIT 2
ADCDS-1403
2
36
21 BIT 3
20 BIT 4
19 BIT 5
OFFSET ADJUST
18 BIT 6
20K
3
–5V
4
17 BIT 7
DIRECT INPUT
16 BIT 8
INVERTING INPUT
15 BIT 9
14 BIT 10
5
13 BIT 11
NON-INVERTING INPUT
12 BIT 12
30
A
0.1μF
11 BIT 13
10 BIT 14 (LSB)
31
A1
0.1μF
25
START CONVERT
6
26
REF. HOLD
7, 35, 37
+2.4V REFERENCE OUT
24 OUT-OF-RANGE
27 DATA VALID
ANALOG GROUND
32, 33 DIGITAL GROUND
Figure 9. ADCDS-1403 Connection Diagram
Timing
The ADCDS-1403 requires two independently operated signals to accurately digitize the analog output signal from the CCD array.
•
Reference Hold (pin 26)
•
Start Convert (pin 25)
The "Reference Hold" signal controls the operation of an internal
sample-hold circuit. A logic "1" places the sample-hold into the hold mode,
capturing the value of the CCD's reference signal. The Reference Hold
Signal allows the user to control the exact moment when the sample-hold
is placed into the "hold" mode. For optimal performance the sample-hold
should be placed into the "hold" mode once the reference signal has fully
settled from all switching transients to the desired accuracy (user defined).
Once the reference signal has been "held" and the video portion of
the CCD's analog output signal appears at the ADCDS-1403's input, the
ADCDS-1403's correlated double sampler produces a "CDS Output" signal
(see Figure 11.) which is the difference between the "held" reference level
and its associated video level. When the "CDS Output" signal has settled
to the desired accuracy (user defined), the A/D conversion process can be
initiated with the rising edge of a single start convert (Pin 25) signal.
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
08 Jul 2015 ADCDS-1403.C01 Page 7 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
Once the A/D conversion has been initiated, Reference Hold (Pin 26)
can be placed back into the "Acquisition" mode in order to begin aquiring
the next reference level. For optimal performance the ADCDS-1403's
internal sample-hold should be placed back into the "Aquisition" mode
(Reference Hold to logic "0") during the CCD's "Reference Quiet Time"
("Reference Quiet Time" is defined as the period when the CCD's reference
signal has settled from all switching transients to the desired accuracy
(see Figure 10.)). Placing the sample-hold back into the "aquisition" mode
during the "Reference Quiet Time" prevents the ADCDS-1403's internal
amplifiers from unecessarily tracking (reproducing) the large switching
transients that occur during the CCD's reset to reference transition.
Reset
Reference
"Quiet Time"
CCD
OUTPUT
Reference
Video
100NS MIN.
HOLD
REFERENCE
HOLD
Acquisition Time
Acquisition mode during
Reference "Quiet Time"
Note: For optimal performance (Fastest Acquisition Time), the ADCDS-1403 should be placed into the Acquisition mode (Reference Hold to logic "0")
during the CCD output's Reference "Quiet Time". Reference "Quiet Time" is defined as the period when the reference signal's switching transients
have settled to an acceptable (user defined) accuracy.
Figure 10. Reference Hold Timing
Reset N
CCD
OUTPUT
Reset N+1
Ref NN
Ref.
Reset N+2
Reset N+3
Ref. N+1
Ref. N+2
Ref. N+3
Video
VideoN+2
N+1
Video N+1
Ref. N+4
Video
VideoN+3
N+1
Video N
Acquisition
Time
100ns min.
133ns min.
333ns
min
REFERENCE
HOLD IN
Reset N+4
Hold
120ns min.
min settling
settlingline
time
Full Scale
Step
N+2
N+1
N
CDS
OUTPUT
N+3
150ns typ.
min
N
START
CONVERT
N+1
N+2
N+3
DATA VALID
30ns min., 50ns max.
Invalid data
DATA
OUTPUT
DATA N-4 VALID
min
20ns max
DATA N-3 VALID
DATA N-2 VALID
DATA N-1 VALID
DATA N VALID
Note: As described in Figure 10, the 60ns min. is dependant on the quality of the CCD's Reference when the ADCDS-1403 is switched back into the track mode
Figure 11. ADCDS-1403 Timing Diagram
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
08 Jul 2015 ADCDS-1403.C01 Page 8 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
®
®
ADCDS-1403
1.27 TYP.
(32.25)
14-BIT, 3MHz
IMAGING SIGNAL PROCESSOR
Made in USA
2.24 TYP.
(56.90)
0.23 TYP.
(5.84)
0.100 TYP.
(2.540)
0.900 ±0.010
(22.86)
1.900 ±0.008
(48.260)
ORDERING INFORMATION
OPERATING
TEMP. RANGE
PACKAGE
ROHS
0 to +70°C
TDIP
No
ADCDS-1403EX
-55 to +125°C
TDIP
No
ADCDS-1403-C
0 to +70°C
TDIP
No
-55 to +125°C
TDIP
Yes
MODEL NUMBER
ADCDS-1403
ADCDS-1403EX-C
DATEL is a registered trademark of DATEL, Inc.
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information
contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of
licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice.
ITAR and ISO 9001/14001 REGISTERED
© 2015 DATEL, Inc.
www.datel.com • e-mail: help@datel.com
08 Jul 2015 ADCDS-1403.C01 Page 9 of 9