ADCDS-1410

ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
SMT
New ption
eO
g
ils
a
Pack 3 for deta
age 1
see p
FEATURES
PRODUCT OVERVIEW
„ 10 MPPS throughput rate
The ADCDS-1410 is an application-specific CCD
image converter designed for electronic-imaging
applications that employ CCD's (charge coupled
devices) as their photodetector. The ADCDS-1410
incorporates a "user configurable" input amplifier,
a CDS (correlated double sampler) and a 14-bit
resolution sampling A/D converter in a single
package, providing the user with a complete, high
performance, low-cost, low-power, integrated
solution.
„ Internal 14-bit resolution A/D
„ Internal correlated doubler sampler (CDS)
„ Resistor programmable gain adjustment
from 0dB to 18dB
„ 1 LSB RMS Noise @ 2.3MPPS
„ Low-Profile 44 Pin SMT Quad Pak or 40 Pin TDIP
„ Analog front end programmable bandwidth
„ Extended temperature range –55ºC to +100ºC
„ Low power, 800mW
„ Low cost, functionally complete
The key to the ADCDS-1410's performance is a
unique, high-speed, high-accuracy CDS circuit,
which eliminates the effects of residual charge,
charge injection and "kT/C" noise on the CCD's
output floating capacitor, producing a pixel data
output signal. The ADCDS-1410 digitizes this
resultant pixel data signal using a high-speed,
low-noise sampling A/D converter.
The ADCDS-1410 requires only the rising edge
of start convert pulse to initiate its conversion
process and a Reference Hold command to
acquire and hold the CCD reference level output.
Additional features of the ADCDS-1410 include
gain adjust, offset adjust, precision +2.4V
reference, and a programmable analog bandwidth
function.
FUNCTIONAL BLOCK DIAGRAM
+5VA
–5VA
+5V D
+12V
523
INVERTING INPUT
75
Fine Gain Adjust
INPUT AMPLIFIER
0.01μF
DIRECT INPUT
NON-INVERTING INPUT
5K 7
22pf
CORRELATED
DOUBLE
SAMPLER
BIT 1 (MSB)
SAMPLING
A/D
BIT 14 (LSB)
OFFSET ADJUST
REFERENCE HOLD
START CONVERT
TIMING
AND
CONTROL
Out-of-Range
+2.4V REFERENCE OUTPUT
DIGITAL GROUND
DATA VALID
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
ANALOG GROUND
AØ A1
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 1 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings
PARAMETERS
MIN.
TYP.
MAX.
UNITS
+12V Supply
0
—
+14
Volts
–5V Supply
–6.5
—
+0.3
Volts
+5V Supply
–0.3
—
+6.5
Volts
Digital Input
–0.3
—
Vdd+0.3V
Volts
Analog Input
–5
—
+5
Volts
Lead Temperature (10 seconds)
—
—
300
°C
FUNCTIONAL SPECIFICATIONS
The following specifications apply over the operating temperature range, under the
following conditions: Vcc= +12V, +Vdd= +5V, Vee= -5V, sample Rate = 10MHz.
Analog Input
Min.
Input Voltage Range (Reference
Signal - Pixel data Signal)
Gain of 7 (INV-IN to GND)
Gain of 1 (INV-IN Open)
Typ.
Max.
Noise
A1
A0
DC Noise Gain = 1 (INV-IN = NC) ➀
Start Convert Rate
10 MHz
LO
5 MHz
Typ.
Max.
Units
LO
0.8
136.5
1.0
171
LSB RMS
uV RMS
LO
HI
0.75
127.5
LSB RMS
uV RMS
3 MHz
HI
LO
0.73
125.5
LSB RMS
uV RMS
1.2 MHz
HI
HI
0.72
122.7
LSB RMS
uV RMS
DC Noise Gain = 7 (INV-IN = GND) ➀
Start Convert Rate
10 MHz
LO
LO
3.00
64
LSB RMS
uV RMS
5 MHz
LO
HI
2.81
60
LSB RMS
uV RMS
3 MHz
HI
LO
2.46
52.5
LSB RMS
uV RMS
1.2 kHz
HI
HI
2.38
50.8
LSB RMS
uV RMS
Units
0.35
–
2.80
–
–
Input Resistance
–
5000
–
Ohms
Input Capacitance
–
10
–
pF
V p-p
V p-p
Digital Inputs
Offset/Gain
Logic Levels
Logic 1 A0, A1
Logic 0 A0, A1
Logic 1 (REF HLD, START CON)
Logic 0 (REF HLD, START CON)
Logic Loading
Logic 1
Logic 0
Min.
3.5
–
+2.4
–
–
–
–
–
+Vdd
0.4
–
+0.8
Volts
Volts
Volts
Volts
–
–
–
–
+10
-10
uA
uA
4.5
–
5.0
–
+0.1
Volts
Volts
2.350
2.350
2.350
2.400
2.400
2.400
2.450
2.450
2.450
Volts
Volts
Volts
–
1.0
–
mA
–0.99
–0.99
–0.99
±0.5
±0.5
±0.6
+1.5
+1.5
+1.5
LSB
LSB
LSB
Integral Nonlinearity
+25°C
0 to 70°C
–55 to +100°C
–
–
–
±2.5
±2.5
±2.5
–
–
–
LSB
LSB
LSB
Guaranteed No Missing Codes
0 to 70°C
–55 to +100°C
14
14
–
–
–
–
LSB
LSB
Digital Outputs
Min.
Typ.
Max.
Units
Offset Error Gain = 1
+25°C
0 to 70°C
–55 to +100°C
–
–
–
±0.6
±0.6
±0.6
±3.0
±3.0
±6.0
%FSR
%FSR
%FSR
Gain Error Gain = 1
+25°C
0 to 70°C
–55 to +100°C
–
–
–
±1.0
±1.35
±1.35
±3.0
±3.0
±6.0
%FSR
%FSR
%FSR
14
10
5
3
±2.75
±3.5
–
–
–
–
–
–
–
–
MHz
MHz
MHz
MHz
0.001
–
–
–
100
50
10➂
–
–
MHz
nSec
nSec
+11.4
+4.75
–4.75
+12.0
+5.0
–5.0
+12.6
+5.25
–5.25
Volts
Volts
Volts
Power Supply Currents
+12V Supply
+5V Supply
-5V Supply
–
–
+30
+100
–65
+35
+110
–75
mA
mA
mA
Power Dissipation
Power Dissipation LP
–
–
1.21
800
1.355
–
Watts
Watts
Power Supply Rejection
(5%) @25°C
–
±0.04
±0.06
%FSR/%V
Bandwidth
Logic Levels
Logic 1 (50μA)
Logic 0 (50μA)
Internal Reference Voltage
(Fine gain adjust grounded)
+25°C
0 to 70°C
–55 to +100°C
Reference Current
Linearity
Differential Nonlinearity
(Histogram, 98kHz)
+25°C
0 to 70°C
–55 to +100°C
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
Input Amplifier –3db BW
10 MHz: A1= 0, A0 = 0
5 MHz: A1= 0, A0 = 1
3 MHz: A1= 1, A0 = 0
1.2 MHz: A1= 1, A0 = 1
Input Common Mode Voltage
Output Voltage Swing
Signal Timing ➀
Conversion Rate (–55 to 100°C)
Conversion Time
Start Convert Pulse Width
Power Requirements
Power Supply Range
+12V Supply
+5V Supply
-5V Supply
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 2 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
Environmental
Min.
Typ.
Max.
Units
Operating Temperature Range
ADCDS-1410
ADCDS-1410EX
0
–55
–
–
+70
+100
°C
°C
Storage Temperature
–65
–
+150
°C
Package Type
40-Pin, TDIP, 2.24"×1.27" FR4 PCB
44-Pin Quad Pak 0.99"x .099"×0.29
LCP Package, FR4 PCB
Weight
16.1 Grams
Pin Type
QuadPak: .025 Dia. Au/Ni plate over Cu
TDIP:
.020 Dia. Au plate over Phosphor Bronze.
Cover (TDIP Package)
Tin Plate Steel
➀ See Table 3.
➁ See Timing Specs, Table 2.
➂ See Technical Note: Optimal Performance.
DIRECT MODE (AC COUPLED)
This is the most common input configuration as it allows the ADCDS-1410
to interface directly to the output of the CCD with a minimum amount of
analog "front-end" circuitry. This mode of operation is used with full-scale
video input signals from 0.350Vp-p to 2.8Vp-p.
Figure 2a describes the typical configuration for applications using a video
input signal with a maximum amplitude of 0.350Vp-p. The coarse gain of
the input amplifier is determined from the following equation:
VOUT = 2.8Vp-p = VIN*(1+(523/75)), with all internal resistors having a 1%
tolerance. Additional fine gain adjustment can be accomplished using the
Fine Gain Adjust (see Figure 5).
Figure 2b describes the typical configuration for applications using a video
input signal with an amplitude greater than 0.350Vp-p and less than 2.8Vpp. Using a single external series resistor (see Figure 4.), the coarse gain of
the ADCDS-1410 can be set, with additional fine gain adjustments being
made using the Fine Gain Adjust function (see Figure 5). The coarse gain of
the input amplifier can be determined from the following equation:
VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors
having a 1% tolerance.
TECHNICAL NOTES
1. Obtaining fully specified performance from the
ADCDS-1410 requires careful attention to pc-card layout and power supply
decoupling. The device's analog and digital grounds are connected to each
other internally. Depending on the level of digital switching noise in the
overall CCD system, the performance of the ADCDS-1410 may be improved
by connecting all ground pins to a large analog ground plane beneath the
package. The use of a single +5V analog supply for both the +5VA and
+5VD may also be beneficial.
VIN
NO CONNECT
Direct 0.01μF
VOUT = 2.8Vp-p
NON-IN
5k
2. Bypass all power supplies to ground with a 4.7μf tantalum capacitor in
parallel with a 0.1μf ceramic capacitor. Locate the capacitors as close to
the package as possible.
Figure 2a.
3. If using the suggested offset and gain adjust circuits
(Figure 3 & 5), place them as close to the ADCDS-1410's package as possible.
Rext
4. A0 and A1 should be bypassed with 0.1μf capacitors to ground to reduce
susceptibility to noise.
INV-IN 75
VIN
ADCDS-1410 MODES OF OPERATION
The input amplifier stage of the ADCDS-1410 provides the designer with a
tremendous amount of flexibility. The architecture of the ADCDS-1410 allows
its input-amplifier to be configured in any of the following configurations:
• Direct Mode (AC coupled)
• Non-Inverting Mode
• Inverting Mode
When applying inputs which are less than 2.8Vp-p, a coarse gain adjustment
(applying an external resistor to INV-IN) must be performed to ensure that the
full scale video input signal (saturated signal) produces a 2.8Vp-p signal at the
input-amplifier's output (Vout).
In all three modes of operation, the video portion of the signal at the CDS
input (i.e. input-amplifier's Vout) must be more negative than its associated
reference level and Vout should
not exceed ±2.8V DC.
The ADCDS-1410 achieves it specified accuracies without the need for
external calibration. If required, the device's small initial offset and gain errors
can be reduced to zero using the FINE GAIN ADJUST and OFFSET ADJUST
features.
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
523
INV-IN 75
• Tel: (508) 339-3000
NO CONNECT
Direct
523
0.01μF
VOUT = 2.8Vp-p
NON-IN
5k
Figure 2b.
Rext
INV-IN 75
NO CONNECT
VIN
Direct
523
0.01μF
VOUT = 2.8Vp-p
NON-IN
5k
Figure 2c.
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 3 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
NON-INVERTING MODE
The non-inverting mode of the ADCDS-1410 allows the designer to either
attenuate or add non-inverting gain to the video input signal. This
configuration also allows bypassing the ADCDS-1410's internal coupling
capacitor, allowing the user to provide an external capacitor of appropriate
value.
Figure 2c describes the typical configuration for applications using video
input signals with amplitudes greater than
0.350Vp-p and less than 2.8Vp-p (with common mode limit of ±2.75V DC).
Using a single external series resistor (see Figure 4.), the coarse gain of the
ADCDS-1410 can be set with additional fine gain adjustments being made
using the Fine Gain Adjust function (see Figure 5). The coarse gain of the
circuit can be determined from the following equation:
VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors
having a 1% tolerance.
Figure 2d describes the typical configuration for applications using a
video input signal whose amplitude is greater than 2.8Vp-p. Using a single
external series resistor (Rext 1) in conjunction with the internal 5K (1%)
resistor to ground, an attenuation of the input signal can be achieved.
Additional fine gain adjustments being made using the Fine Gain Adjust
function. The coarse gain of this circuit can be determined from the
following equation:
VOUT = 2.8Vp-p = [VIN*(5000/(Rext1+5000))]*
[1+(523/(75+Rext2))], with all internal resistors having
a 1% tolerance.
INVERTING MODE
The inverting mode of operation can be used in applications where the
analog input to the ADCDS-1410 has a video input signal whose amplitude
is more positive than its associated reference level. The ADCDS-1410s
correlated double sampler (i.e. input amplifier's VOUT) requires that
the video signal's amplitude be more negative than its reference level
at all times (see timing diagram for details). Using the ADCDS-1410
in the inverting mode allows the designer to perform an additional signal
inversion to correct for any analog "front end" pre-processing that may
have occurred prior to the ADCDS-1410.
Figure 2e describes the typical configuration for applications using a video
input signal with a maximum amplitude of 0.350Vp-p. Additional fine gain
adjustments can be made using the Fine Gain Adjust function. The coarse
gain of this circuit can be determined from the following equation:
VOUT = 2.8Vp-p = –VIN*(523/75), with all internal resistors having a 1%
tolerance.
Figure 2f describes the typical configuration used in applications needing
to invert video input signals whose amplitude is greater than 0.350Vp-p.
Using a single external series resistor (see Figure 4.), the initial gain of the
ADCDS-1410 can be set, with additional fine gain adjustments being made
using the Fine Gain Adjust function. The coarse gain of this circuit can be
determined from the following equation:
VOUT = 2.8Vp-p = –VIN*(523/75+Rext), with all internal resistors having a
1% tolerance.
ADCDS-1410
Rext2
NO CONNECT
Rext1
INV-IN 75
Direct
DAC
523
+5V
0.01μF
VOUT = 2.8Vp-p
NON-IN
VIN
20KΩ
5k
NO CONNECT
INV-IN 75
Direct
523
0.01μf
VOUT = 2.8Vp-p
Coarse Gain Adjustment Plot
External Gain Resistor vs. Full Scale Video Input
Figure 2e.
INV-IN 75
NO CONNECT
Direct
523
0.01μf
VOUT = 2.8Vp-p
NON-IN
5k
External Gain Resistor (Ohms)
5k
Rext
Offset
Adjust
2
Figure 3. Offset Adjustment Circuit
NON-IN
–VIN
External
Series
Resistor
–5V
Figure 2d.
–VIN
10
or
10000
Direct Mode
& Non-Inverting
Mode
1000
Inverting Mode
100
10
0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
Full Scale Video Signal (Volts)
Figure 4. Coarse Gain Adjustment Plot
Figure 2f.
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 4 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
Offset Adjustment
Manual offset adjustment for the ADCDS-1410 can be accomplished
using the adjustment circuit shown in Figure 3. A software controlled
D/A converter can be substituted for the 20KΩ potentiometer. The offset
adjustment feature allows the user to adjust the Offset/Dark Current level
of the ADCDS-1410 until the output bits are 00 0000 0000 0000 and the
LSB flickers between 0 and 1. Offset adjust should be performed before
gain adjust to avoid interaction. The ADCDS-1410's offset adjustment is
dependent on the value of the external series resistor used in the offset
adjust circuit (Figure 3). The Offset Adjustment graph (Figure 6) illustrates
the typical relationship between the external series resistor value and its
offset adjustment capability utilizing ±5V supplies.
OFFSET ADJUSTMENT SENSITIVITY
It should be noted that with increasing amounts of offset adjustment
(smaller values of external series resistors), the ADCDS-1410 becomes
more susceptible to power supply noise or voltage variations seen at the
wiper of the offset potentiometer.
ADCDS-1410
DAC
or
Fine
Gain
Adjust
1
+5V
20KΩ
10
For Example:
External 50KΩ resistor:
1. 10mV of noise or voltage variation at the potentiometer
will produce 0.25LSB's of output variation.
2. 100mV of noise or voltage variation at the potentiometer
will produce 2.5LSB's of output variation.
The Offset Adjustment Sensitivity graph (Figure 7) illustrates the offset
adjustment sensitivity over a wide range of external resistor and noise
values. If a large offset voltage is required, it is recommended that a very
low noise external reference be used in the offset adjust circuit in place
of power supplies. The ADCDS-1410's +2.4V reference output could be
configured to provide the reference voltage for this type of application.
Fine Gain Adjustment
Fine gain adjustment is provided to compensate for the tolerance of the
external coarse gain resistor (Rext) and/or the unavailability of exact
coarse gain resistor (Rext) values. Note, the fine gain adjustment will not
change the expected input amplifier's full scale VOUT (2.8Vp-p.) Instead,
the gain of the ADCDS-1410's internal A/D is adjusted allowing the actual
input amplifier's full scale VOUT to produce an output code of all ones (11
1111 1111 1111).
Fine gain adjustment for the ADCDS-1410 is accomplished using the
adjustment circuit shown below (Figure 5). A software controlled D/A
converter can be substituted for the 20KΩ potentiometer. The fine gain
adjust circuit ensures that the video input signal (saturated signal) will be
properly scaled to obtain the desired Full Scale digital output of 11 1111
1111 1111, with the LSB flickering between 0 and 1. Fine gain adjust
should be performed following the offset adjust to avoid interaction. The
fine gain adjust provides ±256 codes of adjust when ±5V supplies are
used for the Fine Gain Adjust Circuit.
–5V
Figure 5. Fine Gain Adjustment Circuit
Offset Adjustment Sensitivity
External Series Resistor vs. Output Variation (LSB's)
Offset Adjustment vs. External Series Resistor
100
Output Variation (LSB's)
±LSB's of Adjustment
10000
1000
100
10
Peak-Peak
variation at
potentiometer
10
100mV
1
10mV
0.1
1mV
0.01
0
5k
10k 15k
20k 25k
30k 35k
40k 45k
50k
55k 60k
0
5K
External Series Resistor Value (Ohms)
External Series Resistor (Ohm's)
Figure 6. Offset Adjustment vs. External Series Resistor
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
10K 15K 20K 25K 30K 35K 40K 45K 50K 55K 60K
Figure 7. Offset Adjustment Sensitivity
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 5 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
OUT-OF-RANGE INDICATOR
The ADCDS-1410 provides a digital Out-of-Range output signal for
situations when the video input signal (saturated signal) is beyond the input
range of the internal A/D converter. The digital output bits and the Out-ofRange signal correspond to a particular sampled video input range, with
both of these signals having a common pipeline delay.
Using the circuit described in Figure 8, both over-range and under-range
conditions can be detected (see Table 1). When combined with a D/A
converter, digital detection and correction can be performed for both the
gain and offset errors.
MSB
"OVERRANGE"
OUT-OF-RANGE
"UNDERRANGE"
Figure 8. Overrange/ Underrange Circuit
Table 1. Out-of-Range Conditions
OUT OF
RANGE
MSB
OVER
RANGE
UNDER
RANGE
INPUT
SIGNAL
0
0
0
0
In Range
0
1
0
0
In Range
1
0
0
1
Underrange
1
1
1
0
Overrange
OUTPUT CODING
The ADCDS-1410's output coding is Straight Binary as indicated in Table 2.
The table shows the relationship between the output data coding and the
difference between the reference signal voltage and its corresponding video
signal voltage. (These voltages are referred to the output of the ADCDS1410's input amplifier's VOUT).
PROGRAMMABLE ANALOG BANDWIDTH FUNCTION
When interfacing to CCD arrays with very high-speed "read-out" rates,
the ADCDS-1410's input stage must have sufficient analog bandwidth to
accurately reproduce the output signals of the CCD array. The amount of
analog bandwidth determines how quickly and accurately the "Reference
Hold" and the "CDS output" signals will settle. If only a single analog
bandwidth was offered, the ADCDS-1410's bandwidth would be set to
acquire and digitize CCD output signals to 14-bit accuracy, at maximum
conversion rate of 10MHz (100ns see Figure 11. for details). Applications
not requiring the maximum conversion rate would be forced to use the full
analog bandwidth at the possible expense of noise performance.
The ADCDS-1410 avoids this situation by offering a fully programmable
analog bandwidth function. The ADCDS-1410 allows the user to "bandwidth
limit" the input stage in order to realize the highest level of noise
performance for the application being considered. Table 3. describes how
to select the appropriate reference hold "aquisition time" and CDS output
"settling time" needed for a particular application. Each of the selections
listed in Table 3. have been optimized to provide only enough analog
bandwidth to acquire a full scale input step, to 14-bit accuracy, in a single
conversion. Increasing the analog bandwidth (using a faster settling and
acquisition time) would only serve to potentially increase the amount of
noise at the ADCDS-1410's output. The ADCDS-1410 uses a two bit digital
word to select four different analog bandwidths for the ADCDS-1410's input
stage (See Table 3. for details).
Table 2. Output Coding
INPUT AMPLIFIER VOUT, ➀ (VOLTS P-P)
Video Signal-Reference Signal
> –2.80000
SCALE
DIGITAL OUTPUT
OUT-OF-RANGE
>Full Scale –1LSB
11 1111 1111 1111
1
–2.80000
Full Scale –1LSB
11 1111 1111 1111
0
–2.10000
3/4FS
11 0000 0000 0000
0
–1.40000
1/2FS
10 0000 0000 0000
0
–0.70000
1/4FS
01 0000 0000 0000
0
–0.35000
1/8FS
00 1000 0000 0000
0
–0.000171
1 LSB
00 0000 0000 0001
0
0
00 0000 0000 0000
0
<0
00 0000 0000 0000
1
0
Video Signal-Reference Signal
<0➁
Notes: ➀ Input Amplifier VOUT = (Video Signal - Reference Level)
➁ The video portion of the differential signal (input-amplifier's VOUT) must be more negative than its associated reference level and VOUT should not
exceed ±2.8V DC.
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 6 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
DAC
or
+12V
4.7μF
+
+5VD
4.7μF
+
–5VA
4.7μF
+
+5VA
4.7μF
+
0.1μF
0.1μF
0.1μF
0.1μF
39
+5V
1
20K7
DAC
36
+5V
2
External Series
Resistor
20K7
–5V
36
23 BIT 1 (MSB)
FINE GAIN ADJUST
–5V
or
38
OFFSET ADJUST
22 BIT 2
21 BIT 3
ADCDS-1410
TDIP
20 BIT 4
19 BIT 5
18 BIT 6
3
4
17 BIT 7
DIRECT INPUT
16 BIT 8
INVERTING INPUT
15 BIT 9
14 BIT 10
5
13 BIT 11
NON-INVERTING INPUT
12 BIT 12
30
A
0.1μF
11 BIT 13
10 BIT 14 (LSB)
31
A1
0.1μF
25
START CONVERT
6
26
REF. HOLD
7, 35, 37
+2.4V REFERENCE OUT
24 OUT-OF-RANGE
27 DATA VALID
ANALOG GROUND
32, 33 DIGITAL GROUND
Figure 9a. ADCDS-1410 TDIP Connection Diagram
DAC
or
+12V
4.7μF
+
+5VD
4.7μF
+
–5VA
4.7μF
+
+5VA
4.7μF
+
0.1μF
0.1μF
0.1μF
0.1μF
12, 13
+5V
1
20KΩ
DAC
+5V
2
External Series
Resistor
20KΩ
–5V
42, 43
9, 11
30 BIT 1 (MSB)
FINE GAIN ADJUST
–5V
or
38, 39
OFFSET ADJUST
29 BIT 2
28 BIT 3
ADCDS-1410
QUAD PAK
27 BIT 4
26 BIT 5
25 BIT 6
3
4
24 BIT 7
DIRECT INPUT
23 BIT 8
INVERTING INPUT
22 BIT 9
21 BIT 10
5
20 BIT 11
NON-INVERTING INPUT
19 BIT 12
35
A
0.1μF
18 BIT 13
17 BIT 14 (LSB)
36
A1
0.1μF
32
START CONVERT
7
33
6, 8, 10, 14, 41, 44
+2.4V REFERENCE OUT
16 OUT-OF-RANGE
REF. HOLD
34 DATA VALID
ANALOG GROUND
15, 31, 37, 40 DIGITAL GROUND
Figure 9a. ADCDS-1410 Quad Pak Connection Diagram
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 7 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
Programmable Analog Bandwidth Function
When interfacing to CCD arrays with very high-speed "read-out" rates,
the ADCDS-1410's input stage must have sufficient analog bandwidth to
accurately reproduce the output signals of the CCD array. The amount of
analog bandwidth determines how quickly and accurately the "Reference
Hold" and the "CDS output" signals will settle ➂. If only a single analog
bandwidth was offered, the ADCDS-1410's bandwidth would be set
to acquire and digitize CCD output signals to 14-bit accuracy, at the
maximum conversion rate of 10MHz (100ns see Figure 11 for details).
Applications not requiring the maximum conversion rate would be
forced to use the full analog bandwidth at the possible expense of noise
performance.
The ADCDS-1410 avoids this situation by offering a fully programmable
analog bandwidth function. The ADCDS-1410 allows the user to "bandwidth
limit" the input stage in order to realize the highest level of noise performance
for the application being considered. Table 3 describes recommendations
in selecting the appropriate reference hold (Reference Aquisition Time) and
CDS output (Pixel Data Settling Time) needed for a particular application.
Each of the selections listed in Functional Specifications: NOISE have been
optimized to provide only enough analog bandwidth to acquire a full scale
input step (Vsat), to 14-bit accuracy, in a single conversion. Increasing the
analog bandwidth (using a faster settling and acquisition time) would only
serve to potentially increase the amount of noise at the ADCDS-1410's output.
The ADCDS-1410 uses a two bit digital word to select four different analog
bandwidths for the ADCDS-1410's input stage (See Table 3 for details).
Functional Specifications: NOISE shows typical RMS noise for given bandwidth
and gain settings.
Table 3. Timing Specification ➂
Parameters
10 MHz Conversion
Conversion Time
A0
A1
Reference Acquisition Time
Pixel Data Settling Time
Start Convert
5 MHz Conversion
Conversion Time
A0
A1
Reference Acquisition Time
Pixel Data Settling Time
Start Convert
3 MHz Conversion
Conversion Time
A0
A1
Reference Acquisition Time
Pixel Data Settling Time
Start Convert
1.2 MHz Conversion
Conversion Time
A0
A1
Reference Acquisition Time
Pixel Data Settling Time
Start Convert
➂
Symbol➂
Min.
Typ.
Max.
Units
T1
–
–
–
–
–
20
100
LO
LO
40
40
50
–
–
–
–
–
–
ns
–
–
–
–
–
20
200
HI
LO
80
80
50
–
–
–
–
–
–
ns
–
–
–
–
–
20
333
LO
HI
150
150
50
–
–
–
–
–
–
ns
–
–
–
–
–
20
833
HI
HI
300
300
50
–
–
–
–
–
–
ns
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
ns
ns
ns
ns
ns
ns
ns
ns
See timing figures 10 and 11.
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 8 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
Timing
The ADCDS-1410 requires two independently operated signals to
accurately digitize the analog output signal from the CCD array.
•
Reference Hold
•
Start Convert
The "Reference Hold" signal controls the operation of the internal
correlated double sampler (CDS) circuit. A logic "1" capture the value of
the CCD's reference signal. The Reference Hold Signal allows the user to
control the exact moment when the internal CDS is placed into the "hold"
mode. For optimal performance the internal CDS should be placed into the
"hold" mode once the reference signal has fully settled from all switching
transients to the desired accuracy (t2).
Once the reference signal has been "held" and the pixel data portion
of the CCD's analog output signal appears at the ADCDS-1410's input,
the ADCDS-1410's correlated double sampler produces a "CDS Output"
signal (see Figure 11.) which is the difference between the "held"
reference level and its associated pixel data level (Reference-Pixel Data).
When the "CDS Output" signal has settled to the desired accuracy (t3), the
A/D conversion process can be initiated with the rising edge of the Start
Convert signal.
Once the A/D conversion has been initiated, the Reference Hold can be
placed back into the "Acquisition" mode in order to begin aquiring the
next reference level. For optimal performance the ADCDS-1410's should
be placed back into the "Aquisition" mode (Reference Hold to logic "0")
during the CCD's "Reference Quiet Time" ("Reference Quiet Time" is
defined as the period when the CCD's reference signal has settled from
all switching transients to the desired accuracy (see Figure 10.) Placing
the sample-hold back into the "aquisition" mode during the "Reference
Quiet Time" prevents the ADCDS-1410's internal amplifiers from
unnecessarily tracking (reproducing) the reset feedthrough glitch that
occurs during the CCD's reset to reference transition.
Disturbances to the system while the A/D is undergoing a conversion can
result in degradation of performance. It is therefore recommended that
both digital and analog signals (including the Reference/Pixel data inputs
to the ADCDS) not be allowed to switch prior to the rising edge of the
Start Convert Command.
Reset
Reference
"Quiet Time"
CCD
OUTPUT
Reference
Video
50ns
REFERENCE
HOLD
HOLD
Acquisition Time
Acquisition mode during
Reference "Quiet Time"
Note: For optimal performance (Fastest Acquisition Time), the ADCDS-1410 should be placed into the Acquisition mode (Reference Hold to logic "0")
during the CCD output's Reference "Quiet Time". Reference "Quiet Time" is defined as the period when the reference signal's switching transients
have settled to an acceptable (user defined) accuracy.
Figure 10. Reference Hold Timing
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 9 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
Reset N
Reset N+1
Ref.
Ref NN
Reset N+2
Ref. N+2
Ref. N+1
CCD OUTPUT
Reset N+3
Reset N+4
Ref. N+3
Video
VideoN+2
N+1
Video N+1
Ref. N+4
Video
VideoN+3
N+1
Video N
Acquisition
Time
100ns
133ns min.
min
50ns min.
Hold
REFERENCE HOLD IN
40ns min. settling time
Full Scale
Step
N+2
N+1
N
CDS OUTPUT
N+3
50ns typ.
20ns
N
N+2
N+1
N+3
START CONVERT
DATA VALID
30ns min., 50ns max.
Invalid data
DATA OUTPUT
DATA N-4 VALID
20ns min
max
DATA N-3 VALID
DATA N-2 VALID
DATA N-1 VALID
DATA N VALID
Figure 11. ADCDS-1410 Timing Diagram
ADCDS-1410 10 MHz
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
Figure 9. ADCDS-1410 Differential Nonlinearity, LSBs
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 10 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
ADCDS-1410 Grounded Input Histogram – 10 MHz Rate
10 MHz Rate Gain = 7 A1 = LO A0 = LO
3.00 LSB RMS 64 uV RMS
10 MHz Rate Gain =1 A1 = LO A0 =LO
0.80 LSB RMS 136.5 uV RMS
3000
8000
7000
2500
6000
2000
5000
4000
1500
3000
1000
2000
500
40
38
36
34
32
30
28
26
24
22
20
18
0
16
More
31
30
29
28
27
26
0
12
1000
Output Code
Output Code
ADCDS-1410 Grounded Input Histogram – 5 MHz Rate
5 MHz Rate Gain = 7 A1 = LO A0 = HI
2.81 LSB RMS 60 uV RMS
5 MHz Rate Gain = 1 A1 = LO A0 =HI
0.75 LSB RMS 127.4 uV RMS
3000
9000
8000
2500
7000
6000
2000
5000
4000
1500
3000
2000
1000
1000
0
0
34
More
33
32
31
30
29
28
27
26
25
24
23
22
Output Code
Output Code
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
21
20
19
18
17
16
15
14
13
12
More
14
13
12
11
10
500
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 11 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
ADCDS-1410 Grounded Input Histogram – 3 MHz Rate
3 MHz Rate Gain = 7 A1 = HI A0 = LO
2.46 LSB RMS 52.5 uV RMS
3 MHz Rate Gain = 1 A1 = HI A0 =LO
0.73 LSB RMS 125.5 uV RMS
3500
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
3000
2500
2000
1500
1000
32
More
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
More
14
15
0
13
12
11
10
500
Output Code
Output Code
ADCDS-1410 Grounded Input Histogram – 3 MHz Rate
1.2 MHz Rate Gain = 7 A1 = HI A0 = HI
2.38 LSB RMS 50.8 uV RMS
1.2 MHz Rate Gain =1 A1 = HI A0 = HI
0.72 LSB RMS 122.7 uV RMS
3500
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
3000
2500
2000
1500
1000
More
35
34
33
32
31
30
29
28
27
26
Output Code
Output Code
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
25
24
23
22
21
20
19
18
0
17
More
12
11
10
9
8
500
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 12 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
MECHANICAL DIMENSIONS inches (mm)
TOP VIEW
14-BIT, 10MHz
CCD IMAGE PROCESSOR
Contact Factory
for Quad Pak
Availability
1.27 TYP.
(32.25)
ADCDS-1410
CENTER PICKUP POINT
FOR 8mm PICKUP
NOZZLE
14-BIT, 10MHz
CCD IMAGE PROCESSOR
ADCDS-1410
8.00
.315
PIN #1 LOCATED
AT 'BEVELED'
CORNER
2.24 TYP. (56.90)
SIDE VIEW
0.254 TYP.
(6.45)
7.39
.29
0.32 TYP
(8.128)
32.77
1.29
PIN #1
1.900 ±0.008
(48.260)
PIN #68
0.254 TYP.
(6.45)
TDIP
Package
32.77
1.29
0.900 ±0.010
(22.86)
24.13
.950
16.38
.645
12.07
.475
16 EQ SPACES
AT .050 EA =.800
(4 PLACES)
CL
24.13
.950
TDIP Package
1.70
4x .067
MOUNING
STANDOFFS
0.64
.025 TYP
PINS WITH
SPHERICAL TIPS
12.07
.475
16.38
.645
CL
BOTTOM VIEW
Quad Pak
ORDERING INFORMATION
MODEL NUMBER
ADCDS-1410
ADCDS-1410EX
OPERATING
TEMP. RANGE
PACKAGE
ROHS
0 to +70°C
TDIP
No
-55 to +100°C
TDIP
No
ADCDS-1410LP
0 to +70°C
TDIP
No
ADCDS-1410-C
0 to +70°C
TDIP
Yes
ADCDS-1410EX-C
-55 to +100°C
TDIP
Yes
ADCDS-1410LP-C
0 to +70°C
TDIP
Yes
Contact Factory
quad-pak
ADCDS-1410
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 13 of 14
ADCDS-1410
14-Bit, 10 Megapixels/Second CCD Image Converter
INPUT/OUTPUT CONNECTIONS— ADCDS-1410 TDIP Package
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
FUNCTION
FINE GAIN ADJUST
Offset Adjust
Direct Input
Inverting Input
Non-Inverting Input
+2.4v Ref. Output
Analog Ground
No Connect
No Connect
Bit 14 (Lsb)
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
PIN
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
FUNCTION
No Connect
+12v
–5va
Analog Ground
+5va
Analog Ground
+5vd
Digital Ground
Digital Ground
A1
A
No Connect
No Connect
Data Valid
Reference Hold
Start Convert
Out-Of-Range
Bit 1 (Msb)
Bit 2
Bit 3
ANALOG GND
+ 5VA
+ 5VA
ANALOG GND
DIGITAL GND
+5VD
+5VD
DIGITAL GND
A1
A0
DATA VALID
44
43
42
41
40
39
38
37
36
35
34
INPUT/OUTPUT CONNECTIONS— ADCDS-1410 44-Pin Quad Pak
FINE GAIN ADJUST
1
33
REFERENCE HOLD
OFFSET ADJUST
2
32
START CONVERT
DIRECT INPUT
3
31
DIGITAL GND
INVERTING INPUT
4
30
BIT 1 (MSB)
NON-INVERTING INPUT
5
29
BIT 2
ANALOG GND
6
28
BIT 3
+2.4V REF OUTPUT
7
27
BIT 4
ANALOG GND
8
26
BIT 5
-5VA
9
25
BIT 6
ANALOG GND
10
24
BIT 7
-5VA
11
23
BIT 8
22
BIT 9
17
BIT 14 (LSB)
20
16
Out-of-Range
21
15
DIGITAL GND
BIT 10
14
ANALOG GND
19
13
DATEL is a registered trademark of DATEL, Inc.
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
18
12
+12v
+12v
44-Pin Package
DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information
contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of
licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice.
ITAR and ISO 9001/14001 REGISTERED
© 2015 DATEL, Inc.
www.datel.com • e-mail: [email protected]
25 Jun 2015
MDA_ADCDS-1410.B05 Page 14 of 14