ADS-930

ADS-930
16-Bit, 500kHz Sampling A/D Converters
PRODUCT OVERVIEW
The low-cost ADS-930 is a high-performance,
16-bit, 500kHz sampling A/D converter. This device
accurately samples fullscale input signals up to
Nyquist frequencies with no missing codes. The
dynamic performance of the ADS-930 is optimized to
achieve a THD of –89dB and an SNR of 83dB.
Packaged in a small, 40-pin, ceramic TDIP, the
functionally complete ADS-930 contains a fast-settling sample-hold amplifier, a subranging (three-pass)
A/D converter, an internal reference, an on-board FIFO,
timing and control logic, three-state outputs and errorcorrection circuitry. Digital inputs/ outputs are TTL.
Requiring ±15V and +5V supplies, the ADS-930
typically dissipates 3.5 Watts. The unit is offered with
a bipolar input range of ±5V or a unipolar input range
of 0 to –10V. Models are available for use in either
commercial (0 to +70°C), industrial (–40 to +100°C),
or HI-REL (–55 to +125°C) operating temperature
ranges. Typical applications include radar, sonar,
medical/graphic imaging, and FFT spectrum analysis.
FEATURES
„ 16-bit resolution
„ 500kHz sampling rate
„ Functionally complete
„ Excellent dynamic performance
„ 83dB SNR, –89dB THD
„ No missing codes
„ Small, 40-pin, TDIP package
„ 3.5 Watts power dissipation
„ On-board FIFO
PIN
INPUT/OUTPUT CONNECTIONS
FUNCTION
PIN FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
+10V REF. OUT
BIPOLAR
ANALOG INPUT
ANALOG GROUND
OFFSET ADJUST
GAIN ADJUST
+15V SUPPLY
COMP. BITS
ENABLE
FIFO READ
ANALOG GROUND
–15V SUPPLY
ANALOG GROUND
OVERFLOW
EOC
+5V SUPPLY
START CONVERT
DIGITAL GROUND
FSTAT1
FSTAT2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
BIT 1 (MSB)
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
ANALOG GROUND
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
DIGITAL GROUND
FIFO/DIR
BIT 15
BIT 16 (LSB)
BLOCK DIAGRAM
19 FSTAT1
20 FSTAT2
GAIN ADJUST 6
GAIN
ADJUST
CKT.
23 FIFO/DIR
10 FIFO READ
40 BIT 1 (MSB)
+5V SUPPLY
16
+15V SUPPLY
7
–15V SUPPLY
OFFSET ADJUST 5
12
ANALOG GROUND
4, 11, 13, 30
DIGITAL GROUND
18, 24
BIPOLAR 2
OFFSET
ADJUST
CKT.
ANALOG INPUT 3
S/H
36 BIT 4
3-STATE
OUTPUT REGISTER
POWER AND GROUNDING
38 BIT 2
37 BIT 3
CUSTOM GATE ARRAY
PRECISION
+10V REFERENCE
+10V REF. OUT 1
3-PASS ANALOG-TO-DIGITAL CONVERTER
39 BIT 1 (MSB)
35 BIT 5
34 BIT 6
33 BIT 7
32 BIT 8
31 BIT 9
29 BIT 10
28 BIT 11
27 BIT 12
26 BIT 13
25 BIT 14
22 BIT 15
21 BIT 16 (LSB)
START CONVERT 17
EOC 15
9 ENABLE
TIMING AND
CONTROL LOGIC
14 OVERFLOW
COMP. BITS 8
Figure 1. ADS-930 Functional Block Diagram
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
12 Aug 2015
MDA_ADS-930.C01 Page 1 of 8
ADS-930
16-Bit, 500kHz Sampling A/D Converters
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
LIMITS
+15V Supply (Pin 7)
0 to +16
–15V Supply (Pin 12)
0 to –16
+5V Supply (Pin 16)
0 to +6
Digital Inputs (Pin 8, 9, 10, 17, 23)
–0.3 to +VDD +0.3
Analog Input (Pin 3)
Unipolar
–12.5 to +12.5
Bipolar
–7.5 to +12.5
Lead Temperature (10 seconds)
+300
PHYSICAL/ENVIRONMENTAL
PARAMETERS
MIN.
TYP.
MAX.
UNITS
Operating Temp. Range, Case
ADS-930MC, MC-C
0
—
+70
°C
ADS-930ME, ME-C
–40
—
+100
°C
ADS-930MM, MM-C, 883-C
–55
—
+125
°C
Thermal Impedance
θjc
—
4
—
°C/Watt
θca
—
18
—
°C/Watt
Storage Temperature Range
–65
—
+150
°C
Package Type
40-pin, metal-sealed, ceramic TDIP
Weight
0.56 ounces (16 grams)
UNITS
Volts
Volts
Volts
Volts
Volts
Volts
°C
FUNCTIONAL SPECIFICATIONS
(TA = +25°C, ±VCC= ±15V +VDD = +5V, 500kHz sampling rate, and a minimum 5 minute warmup ➀ unless otherwise specified.)
+25°C
ANALOG INPUT
Input Voltage Range
Bipolar
Unipolar
Input Resistance
Input Capacitance
DIGITAL INPUT
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0" ➁
Start Convert Positive Pulse Width ➂
STATIC PERFORMANCE
Resolution
Integral Nonlinearity (fin = 10kHz)
Differential Nonlinearity (fin = 10kHz)
Full Scale Absolute Accuracy
Unipolar Zero Error (Tech Note 2)
Bipolar Zero Error (Tech Note 2)
Bipolar Offset Error (Tech Note 2)
Gain Error (Tech Note 2)
No Missing Codes (fin = 10kHz)
DYNAMIC PERFORMANCE
Peak Harmonics (–0.5dB)
dc to 100kHz
100kHz to 250kHz
Total Harmonic Distortion (–0.5dB)
dc to 100kHz
100kHz to 250kHz
Signal-to-Noise Ratio (w/o distortion, –0.5dB)
dc to 100kHz
100kHz to 250kHz
Signal-to-Noise Ratio (& distortion, –0.5dB) ➃
dc to 100kHz
100kHz to 250kHz
Two-tone Intermodulation Distortion (fin = 100kHz,
240kHz, fs = 500kHz, –0.5dB)
Noise
Input Bandwidth (–3dB)
Small Signal (–20dB input)
Large Signal (–0.5dB input)
Feedthrough Rejection (fin = 250kHz)
Slew Rate
Aperture Delay Time
Aperture Uncertainty
S/H Acquisition Time
(to ±0.003%FSR, 10V step)
Overvoltage Recovery Time ➄
A/D Conversion Rate
0 TO +70°C
–55 TO +125°C
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
UNITS
—
—
1.4
—
±5
0 to –10
1.5
7
—
—
1.7
15
—
—
1.4
—
±5
0 to –10
1.5
7
—
—
1.7
15
—
—
1.4
—
±5
0 to –10
1.5
7
—
—
1.7
15
Volts
Volts
kΩ
pF
+2.0
—
—
—
175
—
—
—
—
200
—
+0.8
+20
–20
215
+2.0
—
—
—
175
—
—
—
—
200
—
+0.8
+20
–20
215
+2.0
—
—
—
175
—
—
—
—
200
—
+0.8
+20
–20
215
Volts
Volts
μA
μA
ns
—
—
—
—
—
—
—
—
16
16
±1.0
±0.75
±0.05
±0.05
±0.05
±0.05
±0.1
—
—
—
—
±0.18
±0.085
±0.085
±0.15
±0.15
—
—
—
—
—
—
—
—
—
16
16
±1.5
±1.0
±0.2
±0.1
±0.15
±0.1
±0.15
—
—
—
—
±0.5
±0.2
±0.25
±0.25
±0.35
—
—
—
—
—
—
—
—
—
16
16
±2.0
±1.5
±0.5
±0.2
±0.25
±0.25
±0.25
—
—
—
—
±0.8
±0.3
±0.5
±0.5
±0.65
—
Bits
LSB
LSB
%FSR
%FSR
%FSR
%FSR
%FSR
Bits
—
—
–91
–86
—
—
—
—
–91
–86
—
—
—
—
–87
–84
—
—
dB
dB
—
—
–89
–84
–81
—
—
—
–89
–84
–81
—
—
—
–85
–82
–76
—
dB
dB
81
—
83
80
—
—
81
—
83
80
—
—
75
—
80
79
—
—
dB
dB
78
—
81
78
—
—
77
—
81
78
—
—
72
—
78
76
—
—
dB
dB
—
—
–82
150
—
—
—
—
–82
150
—
—
—
—
–81
150
—
—
dB
μVrms
—
—
—
—
—
—
2
1.1
–96
±80
±10
50
—
—
—
—
—
—
—
—
—
—
—
—
2
1.1
–96
±80
±10
50
—
—
—
—
—
—
—
—
—
—
—
—
2
1.1
–96
±80
±10
50
—
—
—
—
—
—
MHz
MHz
dB
V/μs
ns
ps rms
—
—
500
680
600
—
720
1000
—
—
—
500
680
600
—
720
1000
—
—
—
500
680
600
—
720
1000
—
ns
ns
kHz
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
12 Aug 2015
MDA_ADS-930.C01 Page 2 of 8
ADS-930
16-Bit, 500kHz Sampling A/D Converters
+25°C
0 TO +70°C
–55 TO +125°C
ANALOG OUTPUT
Internal Reference
Voltage
Drift
External Current
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
UNITS
+9.95
—
—
+10.0
±10
—
+10.05
—
1
+9.95
—
—
+10.0
±10
—
+10.05
—
1
+9.95
—
—
+10.0
±10
—
+10.05
—
1
Volts
ppm/°C
mA
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Delay, Falling Edge of ENABLE to Output Data Valid
Output Coding
+2.4
—
—
+2.4
—
—
+2.4
—
—
—
—
+0.4
—
—
+0.4
—
—
+0.4
—
—
–4
—
—
–4
—
—
–4
—
—
+4
—
—
+4
—
—
+4
—
—
10
—
—
10
—
—
10
Complementary Offset Binary; Complementary Two's Complement, Offset Binary, Two's Complement
Volts
Volts
mA
mA
ns
+14.5
–14.5
+4.75
+15.0
–15.0
+5.0
+15.5
–15.5
+5.25
+14.5
–14.5
+4.75
+15.0
–15.0
+5.0
+15.5
–15.5
+5.25
+14.5
–14.5
+4.75
+15.0
–15.0
+5.0
+15.5
–15.5
+5.25
Volts
Volts
Volts
—
—
—
—
—
–100
+80
3.5
—
—
–125
+90
4.25
±0.02
±0.02
—
—
—
—
—
–100
+80
3.5
—
—
–125
+90
4.25
±0.02
±0.02
—
—
—
—
—
–100
+80
3.5
—
—
–125
+90
4.25
±0.02
±0.02
mA
mA
Watts
%FSR/%V
%FSR/%V
POWER REQUIREMENTS , ±15V
Power Supply Ranges
+15V Supply
–15V Supply
+5V Supply
Power Supply Currents
–15V Supply
+5V Supply
Power Dissipation
Power Supply Rejection
Power Supply Rejection
Footnotes:
➀ All power supplies must be on before applying a start convert pulse. All supplies and
the clock (START CONVERT) must be present during warmup periods. The device
must be continuously converting during this time.
➁ When COMP. BITS (pin 8) is low, logic loading "0" will be –350μA.
➂ A 200ns wide start convert pulse is used for all production testing. For applications
requiring less than a 500kHz sampling rate, wider start convert pulses can be used.
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-930 requires careful
attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For
optimal performance, tie all ground pins (4, 11, 13, 18, 24 and 30) directly
to a large analog ground plane beneath the package.
Bypass all power supplies and the +10V reference output to ground with
4.7μF tantalum capacitors in parallel with 0.1μF ceramic capacitors. Locate
the bypass capacitors as close to the unit as possible.
2. The ADS-930 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors
can be reduced to zero using the adjustment circuitry shown in Figure 2.
When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warmup. To avoid interaction, always
adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not
using offset and gain adjust circuits.
3. Pin 8 (COMP. BITS) is used to select the digital output coding format of the
ADS-930. See Tables 3a and 3b. When this pin has a TTL logic "0" applied,
it complements all of the ADS-930's digital outputs.
When pin 8 has a logic "1" applied and the ADS-930 is operated within its
unipolar (0 to –10V) input range, the output coding is straight binary. Apply-
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
➃ Effective bits is equal to:
(SNR + Distortion) – 1.76 +
20 log
Full Scale Amplitude
Actual Input Amplitude
6.02
ing a logic "0" to pin 8 under these conditions changes the output coding to
complementary binary.
When pin 8 has a logic "1" applied and the ADS-930 is operated within its
bipolar (±5V) input range, the output coding is offset binary. Applying a logic
"0" to pin 8 under these conditions changes the coding to complementary
offset binary. Using the MSB output (pin 40) instead of the MSB output (pin
39) under these conditions changes the respective output codings to two's
complement and complementary two's complement.
Pin 8 is TTL-compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal
pull-up resistor on pin 8 allowing it to be either connected to +5V or left
open when a logic "1" is required.
4. To enable the three-state outputs, connect ENABLE (pin 9) to a logic "0"
(low). To disable, connect pin 9 to a logic "1" (high).
5. Applying a start convert pulse while a conversion is in progress (EOC =
logic "1") will initiate a new and probably inaccurate conversion cycle.
6. Do not enable/disable or complement the output bits or read from the FIFO
during the conversion process (from the falling edge of START CONVERT to
the falling edge of EOC).
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
12 Aug 2015
MDA_ADS-930.C01 Page 3 of 8
ADS-930
16-Bit, 500kHz Sampling A/D Converters
INTERNAL FIFO OPERATION
Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both = "1"), it can be
read by dropping the FIFO READ line (pin 10) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is
already present at the FIFO output, the first read command (the first rising
edge applied to FIFO READ) will bring data from the second conversion to the
output. Each subsequent read command/rising edge brings the next word to
the output lines.
The ADS-930 contains an internal, user-initiated, 18-bit, 16- word FIFO
memory. Each word in the FIFO contains the 16 data bits as well as the MSB
and OVERFLOW bits. Pins 23 (FIFO/DIR) and 10 (FIFO READ) control the FIFO's
operation. The FIFO's status can be monitored by reading pins 19 (FSTAT1)
and 20 (FSTAT2).
When pin 23 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the
digital data path. When pin 23 has a logic "0" applied, the FIFO is transparent,
and the output data goes directly to the output three-state register (whose
operation is controlled by pin 9 (ENABLE)). Read and write commands to the
FIFO are ignored when the ADS-930 is operated in the "direct" mode. It takes
a maximum of 20ns to switch the FIFO in or out of the ADS-930's operation.
FIFO WRITE and READ Modes
Once the FIFO has been enabled (pin 23 high), digital data is automatically
written to it, regardless of the status of FIFO READ (pin 10). Assuming the FIFO
is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 10 (which controls the FIFO's READ
function) should not be low when data is first written to an empty FIFO.
When the FIFO is initially empty, digital data from the first conversion (the
"oldest" data) appears at the output of the FIFO immediately after the first
conversion has been completed and remains there until the FIFO is read.
If a read command is issued after the FIFO has been emptied, the last word
(the 16th conversion) will remain present at the outputs.
FIFO Reset Feature
At any time, the FIFO can be reset to an empty state by putting the ADS-930
into its "direct" mode (logic "0" applied to pin 23, FIFO/DIR) and also applying
a logic "0" to the FIFO READ line (pin 10). The empty status of the FIFO will
be indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status
outputs will change 40ns after the control signals have been applied.
FIFO Status, FSTAT1 and FSTAT2
The status of the data in the FIFO can be monitored by reading the two status
pins, FSTAT1 (pin 19) and FSTAT2 (pin 20).
CONTENTS
If the output three-state register has been enabled (logic "0" applied to pin
9), data from the first conversion will appear at the output of the ADS-930.
Attempting to write a 17th word to a full FIFO will result in that data, and any
subsequent conversion data, being lost.
DELAY
PIN
23
FIFO enabled to direct mode
23
FIFO READ to output data valid
10
FIFO READ to status update when changing
from <half full (1 word) to empty
10
FIFO READ to status update when changing
from rhalf full (8 words) to <half full (7 words)
10
FIFO READ to status update when changing
from full (16 words) to rhalf full (15 words)
10
0
Falling edge of EOC to status update when writing
first word into empty FIFO
15
1
Falling edge of EOC to status update when
changing FIFO from <half full (7 words) to
rhalf full (8 words)
15
1
Falling edge of EOC to status update when filling
FIFO with 16th word
15
1
0
1
0
1
0
FSTAT2
0
1
<half full (≤7 words)
0
0
half-full or more (≥8 words)
1
0
Full (16 words)
1
1
TRANSITION
Direct mode to FIFO enabled
FSTAT1
Empty (0 words)
MIN.
1
TYP.
MAX.
UNITS
–
10
20
ns
–
10
20
ns
–
–
40
ns
0
–
–
28
ns
1
–
–
110
ns
–
–
190
ns
–
–
190
ns
–
–
110
ns
–
–
28
ns
0
1
1
0
0
0
Table 1. FIFO Delays
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
12 Aug 2015
MDA_ADS-930.C01 Page 4 of 8
ADS-930
16-Bit, 500kHz Sampling A/D Converters
Zero/Offset Adjust Procedure
CALIBRATION PROCEDURE (Refer to Figure 2 and Tables 3a and 3b)
1. Apply a train of pulses to the START CONVERT input (pin 17) so that the
converter is continuously converting.
Connect the converter per Table 2 for the appropriate input voltage range.
Any offset/gain calibration procedures should not be implemented until
the device is fully warmed up. To avoid interaction, adjust offset before
gain. The ranges of adjustment for the circuits in Figure 2 are guaranteed
to compensate for the ADS-930's initial accuracy errors and may not be
able to compensate for additional system errors.
2. For unipolar or bipolar zero/offset adjust, apply –76.3μV to the ANALOG
INPUT (pin 3).
A/D converters are calibrated by positioning their digital outputs exactly
on the transition point between two adjacent digital output codes. This is
accomplished by connecting LED's to the digital outputs and performing
adjustments until certain LED's "flicker" equally between on and off. Other
approaches employ digital comparators or microcontrollers to detect when
the outputs change from one code to the next.
For the ADS-930, offset adjusting is normally accomplished when the analog input is 0 minus ½ LSB (–76μV). See Table 3b for the proper bipolar
and unipolar output coding.
Gain adjusting is accomplished when the analog input is at nominal full
scale minus 1½ LSB's (–9.999771V for unipolar and +4.999771V for
bipolar).
3. For a bipolar input - adjust the offset potentiometer until the code flickers
between 1000 0000 0000 0000 and 0111 1111 1111 1111 with pin 8
tied high (offset binary) or between 0111 1111 1111 1111 and 1000 0000
0000 0000 with pin 8 tied low (complementary offset binary).
For a unipolar input - adjust the offset potentiometer until all output bits
are 0's and the LSB flickers between 0 and 1 with pin 8 tied high (straight
binary) or until all output bits are 1's and the LSB flickers between 0 and 1
with pin 8 tied low (complementary binary).
4. Two's complement coding requires using BIT 1 (MSB) (pin 40). With pin 8
tied high, adjust the trimpot until the output code flickers between all 0's
and all 1's.
20k7
Note: Connect pin 5 to ANALOG GROUND (pin 4) for operation without
zero/offset adjustment. Connect pin 6 to pin 4 for operation without gain
adjustment.
DIGITAL
18, 24 GROUND
Pins 1 and 2
+15V
7 +15V
+
Pins 2 and 4
Pin 3
4.7μF
0.1μF
4, 11 ANALOG
13, 30 GROUND
+
Pin 3
±5V
Table 2. Input Connections
4.7μF
0.1μF
12 –15V
–15V
OUTPUT FORMAT
15
14
40
39
38
37
36
35
34
33
32
31
29
28
27
26
25
22
21
0.1μF
TIE TOGETHER
0 to –10V
5
OFFSET
ADJUST
+5V
16 DIGITAL
4.7μF
INPUT PIN
–15V
+15V
6
GAIN
ADJUST
+5V
INPUT RANGE
20k7
–15V
+15V
ADS-930
PIN 8 LOGIC LEVEL
Straight Binary
9 ENABLE
1
23 FIFO/DIR
Complementary Binary
0
Complementary Offset Binary
0
19 FSTAT1
Offset Binary
1
20 FSTAT2
Complementary Two’s Complement (Using MSB, pin 40)
0
Two’s Complement (Using MSB, pin 40)
1
ANALOG INPUT
EOC
OVERFLOW
BIT 1 (MSB)
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
BIT 16 (LSB)
3
FIFO READ 10
+5V
2 BIPOLAR
START CONVERT 17
1 +10V REF. OUT
Table 3a. Setting Output Coding Selection (Pin 8)
0.1μF
COMP. BITS
4.7μF
8
Figure 2. Bipolar Connection Diagram
STRAIGHT BIN.
UNIPOLAR
SCALE
–FS +1 LSB
–FS +1 1/2 LSB
–7/8 FS
–3/4 FS
–1/2FS
–1/2FS –1/2LSB
–1/4FS
–1/8FS
–1 LSB
–1/2LSB
0
INPUT RANGE 0 to
–10V
–9.999847
–9.999771
–8.750000
–7.500000
–5.000000
–4.999924
–2.500000
–1.250000
–0.000153
–0.000076
0.000000
MSB
LSB
1111 1111 1111 1111
LSB "1" to "0"
1110 0000 0000 0000
1100 0000 0000 0000
1000 0000 0000 0000
0111 1111 1111 1111
0100 0000 0000 0000
0010 0000 0000 0000
0000 0000 0000 0001
LSB "0" to "1"
0000 0000 0000 0000
COMP. OFF. BIN.
COMP. BINARY
OUTPUT CODING
MSB
LSB MSB
LSB
0000 0000 0000 0000 0111 1111 1111 1111
LSB "0" to "1"
LSB "1" to "0"
0001 1111 1111 1111 0110 0000 0000 0000
0011 1111 1111 1111 0100 0000 0000 0000
0111 1111 1111 1111 0000 0000 0000 0000
1000 0000 0000 0000 1111 1111 1111 1111
1011 1111 1111 1111 1100 0000 0000 0000
1101 1111 1111 1111 1010 0000 0000 0000
1111 1111 1111 1110 1000 0000 0000 0001
LSB "1" to "0"
LSB "0" to "1"
1111 1111 1111 1111 1000 0000 0000 0000
OFFSET BINARY
COMP. TWO'S COMP.
MSB
LSB
1000 0000 0000 0000
LSB "0" to "1"
1001 1111 1111 1111
1011 1111 1111 1111
1111 1111 1111 1111
0000 0000 0000 0000
0011 1111 1111 1111
0101 1111 1111 1111
0111 1111 1111 1110
LSB "1" to "0"
01111111 1111 1111
TWO'S COMP.
INPUT RANGE
±5V
+4.999847
+4.999771
+3.750000
+2.500000
0.000000
–0.000076
–2.500000
–3.750000
–4.999847
–4.999924
–5.000000
BIPOLAR
SCALE
+FS –1 LSB
+FS –1 1/2 LSB
+3/4 FS
+1/2 FS
0
–1/2 LSB
–1/2 FS
–3/4 FS
–FS +1 LSB
–FS + 1/2 LSB
–FS
Table 3b. Output Coding
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
12 Aug 2015
MDA_ADS-930.C01 Page 5 of 8
ADS-930
16-Bit, 500kHz Sampling A/D Converters
Gain Adjust Procedure
THERMAL REQUIREMENTS
1. Apply +4.999771V to the ANALOG INPUT (pin 3) for bipolar gain adjust or
apply –9.999771V to pin 3 for unipolar gain adjust.
All DATEL sampling A/D converters are fully characterized and specified over
operating temperature (case) ranges of 0 to +70°C and –55 to +125°C. All
room-temperature (TA = +25°C) production testing is performed without the
use of heat sinks or forced-air cooling. Thermal impedance figures for each
device are listed in their respective specification tables.
2. For a unipolar input - adjust the gain potentiometer until all output bits are
1's and the LSB flickers between a 1 and 0 with pin 8 tied high (straight
binary) or until all output bits are 0's and the LSB flickers between a 1 and
0 with pin 8 tied low (complementary binary).
For a bipolar input - adjust the gain potentiometer until all output bits are
1's and the LSB flickers between a 1 and 0 with pin 8 tied low (complementary offset binary) or until all output bits are 0's and the LSB flickers
between a 1 and 0 ith pin 8 tied high (offset binary).
3. Two's complement coding requires using pin 40. With pin 8 tied high,
adjust the gain trimpot until the output code flickers equally between 1000
0000 0000 0000 and 1000 0000 0000 0001.
These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do
not overheat. The ground and power planes beneath the package, as well as
all pcb signal runs to and from the device, should be as heavy as possible to
help conduct heat away from the package. Electrically insulating, thermally
conductive "pads" may be installed underneath the package. Devices should
be soldered to boards rather than "socketed", and of course, minimal air flow
over the surface can greatly help reduce the package temperature.
N
START
CONVERT
175ns min., 200ns typ., 215ns max .
N+1
10ns min., 25ns max.
INTERNAL S/H
10ns min.
25ns max.
Acquisition Time
Hold 1.54μs typ.
460ns typ. 545ns max.
140ns max.
EOC
780ns ±30ns
Conversion Time
700ns ±30ns
1.39μs min.
OUTPUT
DATA
Data N-1 Valid
Data N Valid
30ns min .
Invalid
Data
Note: Scale is approximately 50ns per division.
Figure 3. ADS-930 Timing Diagram
Figure 4. FFT Analysis of ADS-930
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
12 Aug 2015
MDA_ADS-930.C01 Page 6 of 8
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
SG1
TRIGGER
2
• Tel: (508) 339-3000
•
www.datel.com
•
12 Aug 2015
21
23
25
22
26
19
20
24
17
18
13
14
15
11
12
16
9
10
5
3
1
7
4
P2
P2
8
1
P4
11
6
2
74HCT86
U5
ANALOG
INPUT
2
8
7
6
5
4
3
2
12
13
1
P3
2
33PF
C2
2.2MF
.1MF
C3
1
SG3
2.2MF
C4
2 +
1
3
+15V
C7
.22MF
PULSE
WIDTH
R3
20K
2
R4
15K
-15V
+5V
1
2
3
+5V
-15V
C13
+
0.1MF 1
2.2MF
C1
9
10
11
12
13
14
15
C6
2 +
0.1MF 1
C5
U6
74HCT
123
16
+5V
OFFSET
20K
R1
+15V
+5V
+5V
1
1
C9
9
U5
C8
2
+5V
J11
J5
J7
J8
J10
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
U1
ADS-930
1
2
B9
B8
B7
B6
B5
B4
B3
B2
B1
B1
B16
B15
DIR
DGND
B14
B13
B12
B11
B10
AGND
ENBL
2
5
6
9
12
15
16
19
1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
2. SG1-SG3 ARE INITIALLY OPEN.
1. C14 & C15 SHOULD BE 16V OR GREATER.
NOTES:
FS2
FS1
DGND
TRIG
+5V
EOC
O.F.
AGND
-15V
AGND
READ
ENB
COMPB
+15V
GAIN
OFFSET
AGND
ANAIN
B.P.
REF
10
74HCT373
20
3
1D
1Q
4
2D
2Q
7
3D
3Q
8
4D
4Q
13
5D
5Q
U4
14
6D
6Q
17
7D
7Q
18
8D
8Q
11
LTCH
C12
0.1MF
Figure 5. ADS-930 Evaluation Board Schematic
74HCT86
8
1
74HCT86
U5
2
14
U5
7
4
5
2MH
J12
J9
J6
J4
+15V
0.22MF
74HCT86
2
0.1MF
6
10
3
L1
+5V
-15V
P1-7
P1-9
P1-11
-15V
R2
20K
GAIN
3
+15V
J2 J1
J3
C14
0.1MF
C15
2.2MF
(SEE NOTE 1)
+
+5V
J14
J13
SG2
J15
LTCH
8D
7D
6D
5D
4D
3D
2D
1D
11
18
17
14
13
8
7
4
3
LTCH
8D
7D
6D
5D
4D
3D
2D
1D
74HCT373
11
18
17
14
13
8
7
4
3
74HCT373
8Q
7Q
6Q
5Q
4Q
ENBL
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
1
ENBL
10
U3
20
C11
0.1MF
10
+5V
U2
3Q
2Q
1Q
1
C10
0.1MF
20
+5V
1
19
16
15
12
9
6
5
2
1
19
16
15
12
9
6
5
2
2
2
TRIG
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
2
J16
J17
P1
P1
P1
P1
4 (LSB)
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34 (MSB)
J18
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
FS2
FS1
DIR
READ
ENB
COMPB
ENABLE
EOC
O.F.
B1
U1-10
U1-9
U1-8
ADS-930
16-Bit, 500kHz Sampling A/D Converters
e-mail: help@datel.com
MDA_ADS-930.C01 Page 7 of 8
ADS-930
16-Bit, 500kHz Sampling A/D Converters
MECHANICAL DIMENSIONS - INCHES (mm)
2.12/2.07
(53.85/52.58)
40
Dimension Tolerances (unless otherwise indicated):
2 place decimal (.XX) ±0.010 (±0.254)
3 place decimal (.XXX) ±0.005 (±0.127)
21
Lead Material: Kovar alloy
1.11/1.08
(28.20/27.43)
1
Lead Finish: 50 microinches (minimum) gold plating
over 100 microinches (nominal) nickel plating
20
0.100 TYP.
(2.540)
1.900 ±0.008
(48.260)
0.245 MAX.
(6.223)
PIN 1 INDEX
( ON TOP)
0.200/0.175
(5.080/4.445)
0.015/0.009
(0.381/0.229)
0.210 MAX.
(5.334)
0.018 ±0.002
(0.457)
0.110/0.090
(2.794/2.286)
SEATING
PLANE
0.035/0.015
(0.889/0.381)
0.045/0.035
(1.143/0.889)
0.110/0.090
(2.794/2.286
0.900 ±0.010
(22.86)
ORDERING INFORMATION
MODEL
NUMBER
ADS-930MC
ADS-930MC-C
OPERATING
TEMP. RANGE
PACKAGE
ROHS
0 to +70°C
TDIP
No
ADS-EVAL3
Evaluation Board (without ADS-930)
HS-40
Heat Sink for all ADS-930 models
0 to +70°C
TDIP
Yes
ADS-930ME
–40 to +100°C
TDIP
No
ADS-930ME-C
–40 to +100°C
TDIP
Yes
ADS-930MM
–55 to +125°C
TDIP
No
ADS-930MM-C
–55 to +125°C
TDIP
Yes
ADS-930/883
–55 to +125°C
TDIP
No
ADS-930-C/883
–55 to +125°C
TDIP
Yes
ACCESSORIES
Receptacles for pc board mounting can be ordered through AMP, Inc., part # 3-331272-8 (Component Lead Socket), 40 required. For MIL-STD-883 product,
or surface mount packaging, contact DATEL.
DATEL is a registered trademark of DATEL, Inc.
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information
contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of
licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice.
ITAR and ISO 9001/14001 REGISTERED
© 2015 DATEL, Inc.
www.datel.com • e-mail: help@datel.com
12 Aug 2015
MDA_ADS-930.C01 Page 8 of 8