ADS-935 16-Bit, 5MHz Sampling A/D Converters PRODUCT OVERVIEW The ADS-935 is a 16-bit, 5MHz sampling A/D converter. This device accurately samples full-scale input signals up to Nyquist frequencies with no missing codes. The dynamic performance of the ADS-935 has been optimized to achieve a signal-to-noise ratio (SNR) of 83dB and a total harmonic distortion (THD) of –86dB. Packaged in a 40-pin TDIP, the functionally complete ADS-935 contains a fast-settling sample-hold amplifier, a subranging (two-pass) A/D converter, an internal reference, timing/control logic, and error-correction circuitry. Digital input and output levels are TTL. The ADS-935 only requires the rising edge of the start convert pulse to operate. FEATURES 16-bit resolution 5MHz sampling rate Functionally complete No missing codes over full HI-REL temperature range Edge-triggered ±5V, ±12V or ±15V supplies, 3.0 Watts Small, 40-pin, ceramic TDIP 83dB SNR, –86dB THD Ideal for both time and frequency-domain applications Requiring ±5V supplies and either ±12v or ±15V supplies, the ADS-935 dissipates 3.3 Watts. The device is offered with a bipolar (±2.75V) or a unipolar (0 to –5.5V) analog input range. Models are available in commercial (0 to +70°C), industrial (–40 to +100°C), or HI-REL (–55 to +125°C) operating temperature ranges. A proprietary, auto-calibrating, error-correcting circuit enables the device to achieve specified performance over the full military temperature range. Typical applications include medical imaging, radar, sonar, communications and instrumentation. PIN INPUT/OUTPUT CONNECTIONS FUNCTION PIN FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 +3.2V REF. OUT UNIPOLAR ANALOG INPUT ANALOG GROUND OFFSET ADJUST GAIN ADJUST DIGITAL GROUND FIFO/DIR FIFO READ FSTAT1 FSTAT2 START CONVERT BIT 16 (LSB) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 +12V/+15V –12V/–15V +5V ANALOG SUPPLY –5V SUPPLY ANALOG GROUND COMP. BITS OUTPUT ENABLE OVERFLOW EOC +5V DIGITAL SUPPLY DIGITAL GROUND BIT 1 (MSB) BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BLOCK DIAGRAM POWER AND GROUNDING +5V ANALOG SUPPLY 38 +5V DIGITAL SUPPLY 31 –5V SUPPLY 37 ANALOG GROUND 4, 36 DIGITAL GROUND 7, 30 –12/–15V ANALOG SUPPLY 39 +12/+15V ANALOG SUPPLY 40 UNIPOLAR 2 Figure 1. ADS-935 Functional Block Diagram DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 13 Aug 2015 MDA_ADS-935.C02 Page 1 of 8 ADS-935 16-Bit, 5MHz Sampling A/D Converters ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS +5V Supply (Pins 31, 38) 0 to +6 –5V Supply (Pin 37) 0 to –6 +12V/+15V Supply (pin 40) 0 to +16V –12V/–15V Supply (pin 39) 0 to -16V Digital Inputs (Pin 8, 9, 12, 34, 35) –0.3 to +Vdd +0.3 Analog Input (Pin 3) ±6 Lead Temperature (10 seconds) +300 UNITS Volts Volts Volts Volts Volts Volts °C FUNCTIONAL SPECIFICATIONS (TA = +25°C, ±VCC = ±12/15V ±VDD = ±5V, 5MHz sampling rate, and a minimum 3 minute warmup ➀ unless otherwise specified.) PHYSICAL/ENVIRONMENTAL PARAMETERS MIN. TYP. MAX. UNITS Operating Temp. Range, Case ADS-935MC, MC-C 0 — +70 °C ADS-935ME, ME-C –40 — +100 °C ADS-935MM, MM-C, 883 –55 — +125 °C Thermal Impedance θjc — 4 — °C/Watt θca — 18 — °C/Watt Storage Temperature Range –65 — +150 °C Package Type 40-pin, metal-sealed, ceramic TDIP Weight 0.56 ounces (16 grams) +25°C ANALOG INPUT Input Voltage Range Unipolar Bipolar Input Resistance (pin 3) Input Resistance (pin 2) Input Capacitance DIGITAL INPUT Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" ➁ Start Convert Positive Pulse Width ➂ STATIC PERFORMANCE Resolution Integral Nonlinearity (fin = 10kHz) Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Bipolar Zero Error (Tech Note 2) Bipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) DYNAMIC PERFORMANCE Peak Harmonics (–0.5dB) dc to 500kHz 500kHz to 2.45MHz Total Harmonic Distortion (–0.5dB) dc to 500kHz 500kHz to 1MHz Signal-to-Noise Ratio (w/o distortion, –0.5dB) dc to 500kHz 500kHz to 2.45MHz Signal-to-Noise Ratio (& distortion, –0.5dB) ➃ dc to 500kHz 500kHz to 2.45MHz Two-tone Intermodulation Distortion (fin = 200kHz, fs = 5MHz, –0.5dB) Noise Input Bandwidth (–3dB) Small Signal (–20dB input) Large Signal (–0.5dB input) Feedthrough Rejection (fin = 1MHz) Slew Rate Aperture Delay Time Aperture Uncertainty S/H Acquisition Time (to ±0.001%FSR, 5.5V step) Overvoltage Recovery Time ➄ A/D Conversion Rate 0 TO +70°C –55 TO +125°C MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS — — — — — 0 to –5.5 ±2.75 400 480 10 — — — — 15 — — — — — 0 to –5.5 ±2.75 400 480 10 — — — — 15 — — — — — 0 to –5.5 ±2.75 400 480 10 — — — — 15 Volts Volts Ω Ω pF +2.0 — — — 30 — — — — 100 — +0.8 +20 –20 105 +2.0 — — — 30 — — — — 100 — +0.8 +20 –20 105 +2.0 — — — 30 — — — — 100 — +0.8 +20 –20 105 Volts Volts μA μA ns — — –0.95 — — — — 16 16 ±1.0 ±0.5 ±0.15 ±0.1 ±0.1 ±0.15 — — — +1.0 ±0.3 ±0.2 ±0.2 ±0.3 — — — –0.95 — — — — 16 16 ±1.5 ±0.5 ±0.3 ±0.2 ±0.2 ±0.3 — — — +1.0 ±0.5 ±0.4 ±0.4 ±0.5 — — — –0.95 — — — — 16 16 ±2.0 ±0.5 ±0.5 ±0.4 ±0.4 ±0.5 — — — +1.5 ±0.8 ±0.6 ±0.6 ±0.8 — Bits LSB LSB %FSR %FSR %FSR %FSR Bits — — –87 –82 –82 –80 — — –87 –82 –82 –80 — — –82 –78 –78 –78 dB dB — — –86 –81 –81 –80 — — –86 –81 –81 –80 — — –81 –77 –76 –76 dB dB 84 82 86 85 — — 84 82 86 85 — — 77 77 80 80 — — dB dB 80 79 82 81 — — 80 79 82 81 — — 76 76 78 75 — — dB dB — — –86 80 –85 — — — –86 80 –85 — — — –86 80 –82 — dB μVrms — — — — — — 25 15 90 ±400 4 2 — — — — — — — — — — — — 25 15 90 ±400 4 2 — — — — — — — — — — — — 25 15 90 ±400 4 2 — — — — — — MHz MHz dB V/μs ns ps rms — — 5 80 200 — — — — — — 5 80 200 — — — — — — 5 90 200 — — — — ns ns MHz DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 13 Aug 2015 MDA_ADS-935.C02 Page 2 of 8 ADS-935 16-Bit, 5MHz Sampling A/D Converters +25°C ANALOG OUTPUT Internal Reference Voltage Drift External Current DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Output Coding ➅ –55 TO +125°C TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS — — — +3.2 ±30 5 — — — — — — +3.2 ±30 5 — — — — — — +3.2 ±30 5 — — — Volts ppm/°C mA +2.4 — — — POWER REQUIREMENTS Power Supply Ranges ➆ +5V Supply –5V Supply +12V Supply ➇ –12V Supply ➇ +15V Supply ➇ –15V Supply ➇ Power Supply Currents +5V Supply –5V Supply –12/15V Supply ➇ +12/15V Supply ➇ Power Dissipation Power Supply Rejection 0 TO +70°C MIN. — — +2.4 — — +2.4 — — — +0.4 — — +0.4 — — +0.4 — –4 — — –4 — — –4 — +4 — — +4 — — +4 (Offset) Binary / Complementary (Offset) Binary / Two's Complement / Complementary Two's Complement Volts Volts mA mA +4.75 –4.75 +11.5 –11.5 +14.5 –14.5 +5.0 –5.0 +12.0 –12.0 +15.0 –15.0 +5.25 –5.25 +12.5 –12.5 +15.5 –15.5 +4.75 –4.75 +11.5 –11.5 +14.5 –14.5 +5.0 –5.0 +12.0 –12.0 +15.0 –15.0 +5.25 –5.25 +12.5 –12.5 +15.5 –15.5 +4.9 –4.9 +11.5 –11.5 +14.5 –14.5 +5.0 –5.0 +12.0 –12.0 +15.0 –15.0 +5.25 –5.25 +12.5 –12.5 +15.5 –15.5 Volts Volts Volts Volts Volts Volts — –170 –65 — — — +240 –150 –50 +65 3.3 — +260 — — +105 4.0 ±0.07 — –170 –65 — 3.3 — +240 –150 –50 +65 4.0 — +260 — — +105 — ±0.07 — –170 –65 — 3.3 — +240 –150 –50 +65 4.0 — +260 — — +105 Watts ±0.07 mA mA mA mA Footnotes: ➀ All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warmup periods. The device must be continuously converting during this time. ➁ When COMP. BITS (pin 35) is low, logic loading "0" will be –350μA. ➂ A 5MHz clock with a 50nsec positive pulse width is used for all production testing. See Timing Diagram for more details. ➃ Effective bits is equal to: Full Scale Amplitude (SNR + Distortion) – 1.76 + 20 log Actual Input Amplitude %FSR/%V ➄ This is the time required before the A/D output data is valid once the analog input is back within the specified range. ➅ The minimum supply voltages of +4.9V and –4.9V for ±VDD are required for –55°C operation only. The minimum limits are +4.75V and –4.75V when operating at +125°C. ➆ The minimum supply voltages of +4.9V and –4.9V for ±VDD are required for –55°C operation only. The minimum limits are +4.75V and –4.75V when operating at +125°C. ➇ ±12V only or ±15V only required. 6.02 TECHNICAL NOTES 1. Obtaining fully specified performance from the ADS-935 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (4, 7, 30 and 36) directly to a large analog ground plane beneath the package. For the best performance it is recommended to use a single power source for both the +5V analog and +5V digital supplies. Bypass all power supplies and the +3.2V reference output to ground with 4.7μF tantalum capacitors in parallel with 0.1μF ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. Pin 35 is TTL compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal pull-up resistor on pin 35 allowing it to be either connected to +5V or left open when a logic "1" is required. 4. To enable the three-state outputs, connect OUTPUT ENABLE (pin 34) to a logic "0" (low). To disable, connect pin 34 to a logic "1" (high). 2. The ADS-935 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warmup. To avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not using offset and gain adjust circuits. 3. Pin 35 (COMP. BITS) is used to select the digital output coding format of the ADS-935 (see Tables 2a and 2b). When this pin has a TTL logic "0" applied, it complements all of the ADS-935's digital outputs. DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA When pin 35 has a logic "1" applied, the output coding is complementary offset binary. Applying a logic "0" to pin 35 changes the coding to offset binary. Using the MSB output (pin 29) instead of the MSB output (pin 28) changes the respective output codings to complementary two's complement and two's complement. 5. Applying a start convert pulse while a conversion is in progress (EOC = logic "1") will initiate a new and probably inaccurate conversion cycle. Data from both the interrupted and subsequent conversions will be invalid. 6. Do not enable/disable or complement the output bits or read from the FIFO during the conversion process (from the rising edge of EOC to the falling edge of EOC). 7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the input voltage exceeds that which produces an output of all 1’s or when the input equals or exceeds the voltage that produces all 0’s. When COMP BITS is activated, the above conditions are reversed. • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 13 Aug 2015 MDA_ADS-935.C02 Page 3 of 8 ADS-935 16-Bit, 5MHz Sampling A/D Converters INTERNAL FIFO OPERATION The ADS-935 contains an internal, user-initiated, 18-bit, 16-word FIFO memory. Each word in the FIFO contains the 16 data bits as well as the MSB and OVERFLOW bits. Pins 8 (FIFO/DIR) and 9 (FIFO READ) control the FIFO's operation. The FIFO's status can be monitored by reading pins 10 (FSTAT1) and 11 (FSTAT2). When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the digital data path. When pin 8 has a logic "0" applied, the FIFO is transparent and the output data goes directly to the output three-state register (whose operation is controlled by pin 34 (ENABLE)). Read and write commands to the FIFO are ignored when the ADS-935 is operated in the "direct" mode. It takes a maximum of 20ns to switch the FIFO in or out of the ADS-935's digital data path. Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both equal to "1"), it can be read by dropping the FIFO READ line (pin 9) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is already present at the FIFO output, the first read command (the first rising edge applied to FIFO READ) will bring data from the second conversion to the output. Each subsequent read command/rising edge brings the next word to the output lines. After the 15th rising edge brings the 16th data word to the FIFO output, the subsequent falling edge on READ will update the status outputs (after a 20ns maximum delay) to FSTAT1 = 0, FSTAT2 = 1 indicating that the FIFO is empty. If a read command is issued after the FIFO empties, the last word (the 16th conversion) will remain present at the outputs. FIFO Reset Feature FIFO WRITE and READ Modes Once the FIFO has been enabled (pin 8 high), digital data is automatically written to it, regardless of the status of FIFO READ (pin 9). Assuming the FIFO is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 9 (which controls the FIFO's READ function) should not be low when data is first written to an empty FIFO. When the FIFO is initially empty, digital data from the first conversion (the "oldest" data) appears at the output of the FIFO immediately after the first conversion has been completed and remains there until the FIFO is read. At any time, the FIFO can be reset to an empty state by putting the ADS-935 into its "direct" mode (logic "0" applied to pin 8, FIFO/DIR) and also applying a logic "0" to the FIFO READ line (pin 9). The empty status of the FIFO will be indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status outputs change 40ns after applying the control signals. FIFO Status, FSTAT1 and FSTAT2 Monitor the status of the data in the FIFO by reading the two status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11). If the output three-state register has been enabled (logic "0" applied to pin 34), data from the first conversion will appear at the output of the ADS-935. Attempting to write a 17th word to a full FIFO will result in that data, and any subsequent conversion data, being lost. DELAY PIN CONTENTS Empty (0 words) <half full (≤8 words) half-full or more (≥8 words) Full (16 words) TRANSITION Direct mode to FIFO enabled 8 FIFO enabled to direct mode 8 0 1 FIFO READ to output data valid 9 0 FIFO READ to status update when changing from <half full (1 word) to empty 9 1 FIFO READ to status update when changing from rhalf full (8 words) to <half full (7 words) 9 0 FIFO READ to status update when changing from full (16 words) to rhalf full (15 words) 9 0 Falling edge of EOC to status update when writing first word into empty FIFO 32 1 Falling edge of EOC to status update when changing FIFO from <half full (7 words) to rhalf full (8 words) 32 1 Falling edge of EOC to status update when filling FIFO with 16th word 32 1 FSTAT1 0 0 1 1 FSTAT2 1 0 0 1 MIN. TYP. MAX. UNITS – 10 20 ns 0 1 – 10 20 ns – – 40 ns 0 – – 20 ns 1 – – 110 ns – – 190 ns 0 – – 190 ns 0 – – 110 ns 0 – – 28 ns 1 1 Table 1. FIFO Delays DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 13 Aug 2015 MDA_ADS-935.C02 Page 4 of 8 ADS-935 16-Bit, 5MHz Sampling A/D Converters Zero/Offset Adjust Procedure CALIBRATION PROCEDURE 1. Apply a train of pulses to the START CONVERT input (pin 12) so that the converter is continuously converting. Connect the converter per Figure 2. Any offset/gain calibration procedures should not be implemented until the device is fully warmed up. To avoid interaction, adjust offset before gain. The ranges of adjustment for the circuits in Figure 2 are guaranteed to compensate for the ADS-935’s initial accuracy errors and may not be able to compensate for additional system errors. 2. For zero/offset adjust, apply –42μV to the ANALOG INPUT (pin 3). 3. Adjust the offset potentiometer until the code flickers between 1000 0000 0000 0000 and 0111 1111 1111 1111 with pin 35 tied high (complementary offset binary) or between 0111 1111 1111 1111 and 1000 0000 0000 0000 with pin 35 tied low (offset binary). A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This is accomplished by connecting LED's to the digital outputs and performing adjustments until certain LED's "flicker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. 4. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the trimpot until the output code flickers between all 0’s and all 1’s. Gain Adjust Procedure For the ADS-935, offset adjusting is normally accomplished when the analog input is 0 minus ½ LSB (–42μV). See Table 2b for the proper bipolar output coding. 1. For gain adjust, apply +2.749874V to the ANALOG INPUT (pin 3). Gain adjusting is accomplished when the analog input is at nominal full scale minus 1½ LSB's (+2.749874V). Note: Connect pin 5 to ANALOG GROUND (pin 4) for operation without zero/offset adjustment. Connect pin 6 to pin 4 for operation without gain adjustment. OUTPUT FORMAT PIN 35 LOGIC LEVEL Complementary (Offset) Binary 1 (Offset) Binary 0 Complementary Two’s Complement (Using MSB, pin 29) 1 Two’s Complement (Using MSB, pin 29) 0 2. Adjust the gain potentiometer until all output bits are 0’s and the LSB flickers between a 1 and 0 with pin 35 tied high (complementary offset binary) or until all output bits are 1’s and the LSB flickers between a 1 and 0 with pin 35 tied low (offset binary). 3. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the gain trimpot until the output code flickers equally between 0111 1111 1111 1111 and 0111 1111 1111 1110. 4. To confirm proper operation of the device, vary the applied input voltage to obtain the output coding listed in Table 2b. Table 2a. Setting Output Coding Selection (Pin 35) Figure 2. Bipolar Connection Diagram DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 13 Aug 2015 MDA_ADS-935.C02 Page 5 of 8 ADS-935 16-Bit, 5MHz Sampling A/D Converters UNIPOLAR SCALE 0 –1 LSB 0 –1 1/2 LSB 0 – 1/8 FS 0 – 1/4 FS –1/2 FS – 1/2LSB –1/2 LSB –3/4 FS –7/8 FS –FS +1 LSB –FS + 1/2 LSB –FS INPUT RANGE 0 to –5.5V –0.000084 –0.000126 –0.687500 –1.375000 –2.749958 –2.750000 –4.125000 –4.812500 –5.499916 –5.499958 –5.500000 COMP. BINARY BINARY COMP. TWO'S COMP. TWO'S COMP. MSB LSB 1111 1111 1111 1111 LSB "1" to "0" 1110 0000 0000 0000 1100 0000 0000 0000 1000 0000 0000 0000 0111 1111 1111 1111 0100 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0001 LSB "0" to "1" 0000 0000 0000 0000 OFFSET BINARY MSB LSB 0000 0000 0000 0000 LSB "0" to "1" 0001 1111 1111 1111 0011 1111 1111 1111 0111 1111 1111 1111 1000 0000 0000 0000 1011 1111 1111 1111 1101 1111 1111 1111 1111 1111 1111 1110 LSB "1" to "0" 1111 1111 1111 1111 COMP. OFF. BIN. MSB LSB 0111 1111 1111 1111 LSB "1" to "0" 0110 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1100 0000 0000 0000 1010 0000 0000 0000 1000 0000 0000 0001 LSB "0" to "1" 1000 0000 0000 0000 TWO'S COMP. MSB LSB 1000 0000 0000 0000 LSB "0" to "1" 1001 1111 1111 1111 1011 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0011 1111 1111 1111 0101 1111 1111 1111 0111 1111 1111 1110 LSB "1" to "0" 0111 1111 1111 1111 COMP. TWO'S COMP. INPUT RANGE ±2.75V +2.749916 +2.749874 +2.062500 +1.375000 0.000000 –0.000084 –1.375000 –2.062500 –2.749916 –2.749958 –2.750000 BIPOLAR SCALE +FS –1 LSB +FS –1 1/2 LSB +3/4 FS +1/2 FS 0 –1/2 LSB –1/2 FS –3/4 FS –FS +1 LSB –FS + 1/2 LSB –FS Table 2b. Output Coding THERMAL REQUIREMENTS not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electrically insulating, thermallyconductive "pads" may be installed underneath the package. Devices should be soldered to boards rather than "socketed", and of course, minimal air flow over the surface can greatly help reduce the package temperature. All DATEL sampling A/D converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70°C and –55 to +125°C. All room-temperature (TA = +25°C) production testing is performed without the use of heat sinks or forced-air cooling. Thermal impedance figures for each device are listed in their respective specification tables. These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do N N+1 N+2 N+3 START CONVERT Acquisition A q s Time e 75ns 5 s typ. y 20ns 0 s typ. y INTERNAL S/H Hold od 125ns typ. p 20ns 2 n typ. t p 50ns 0 s typ. y EOC 110ns typ. p Conversion o v r o Time Tm 150ns 1 0 s typ. y 20ns 0 s typ. y . OUTPUT DATA Data N-4 Valid Data N-3 Valid Data N-2 Valid Invalid Data 50ns typ. Data N-1 Valid Invalid Data NOTES: 1. Scale is approximately 20ns per didsion.fs = 5MHz 2. This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data from the first conversion to appear at the output of the A/D. Figure 3. ADS-935 Timing Diagram DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 13 Aug 2015 MDA_ADS-935.C02 Page 6 of 8 DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com 7 X1 5MHZ 8 14 B1 • 13 Aug 2015 SG4 SG3 SG2 SG1 26 24 22 20 18 16 14 12 10 8 6 4 2 50 R6 P2 3 2 0.1μF 3 2 J1 4 7 2 6 5 AGND C13 2.2μF AGND C11 2.2μF L1 1 SG5 20mH L4 20mH L3 20mH L2 +5VA –5VA +5VD +5VF AGND 2 AGND OFFSET ADJUST AGND C2 2.2μF C1 2.2μF 20mH 3.3k R3 C9 2.2μF DGND 2.2μF C7 DGND C10 1 33pF 2 1 74HCT74 U1 4 +5VF 6 R2 +15V DGND +5VA –15V –5VA +5VD 3 2 1 DGND DGND C6 2.2μF +5VF 25 23 21 19 17 15 13 11 9 7 5 3 1 AR1 C5 DGND START CONVERT 7 1 13 8 9 14 74HCT74 U1 10 DGND 11 12 AGND DGND 2 AGND +5VF B2 ANALOG INPUT AMPLIFIER OPTION AGND R1 3 1 –5VA R4 20k +5VA DGND SG9 RD FIF 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B9 B10 B11 B12 B13 B14 B15 LSB START FSTAT2 FSTAT1 READ FIFO/DIR DGND GAIN OFFSET AGND ANA IN AGND UUT U6 3 1 –5VA R5 20k DGND 38 39 12 13 3 EOC AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 +5VD COMP –5VA +5VA 3 FST1 7 74HC86 U5 14 74HC86 8 U5 FST2 U5 DGND +5VF 9 10 2 1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 74HC86 B8 B7 B6 B5 B4 B3 B2 MSB MSB DGND +5VD EOC OF ENABLE COMP AGND -5VA 37 +5VA –12/–15V 40 DGND C15 0.1μF AB2 AB1 C16 0.1μF AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 DGND C8 0.1μF +5VF DGND C17 0.1μF +5VF AB7 AB6 AB5 AB4 AB3 DGND A +5VF Figure 4. ADS-935 Evaluation Board Schematic 2 +5VA GAIN ADJUST +5VF +12/+15V C4 2.2μF ADS-935 +3.2VREF AGND C3 0.1μF 74HC86 4 U5 6 START CONVERT 5 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 –15V –5VA +15V +5VA SG6 SG8 SG7 U2 10 2 3 4 5 6 7 8 9 2 3 4 DGND 15 14 13 12 20 11 U3 10 1 U4 10 1 11 1 74HCT573 20 11 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 B9 B10 B11 B12 B13 B14 B15 +5VD FIF RD DGND COMP START B16 (LSB) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1(MSB) AGND DGND 1 3 5 7 9 1 2 3 1 2 3 1 2 3 J5 J4 J3 FIFO/DIR READ COMPLIM ENABLE FST2 FST1 FIF/DIR N.C. READ COMPLIM ENABLE DGND DGND DGND DGND DGND DGND DGND EOC OVRFLW 1 2 3 J2 2 4 6 8 10 12 11 14 13 16 15 18 17 P1 20 19 22 21 24 23 26 25 28 27 30 29 32 31 B1B MSB DGND AGND C21 2.2μF +5VA C12 2.2μF –5VA AGND C14 2.2μF +5VD 34 33 C20 0.1μF +5VA C19 0.1μF –5VA DGND AGND 0.1μF 0.1μF C18 0.1μF +5VD B16 (LSB) DGND B8 B7 B6 B5 B4 B3 B2 B1 (MSB) DGND 19 B1B MSB 18 OVRFLW 17 74HCT573 16 20 5 74HCT573 6 7 8 9 2 3 4 5 6 7 8 9 ADS-935 16-Bit, 5MHz Sampling A/D Converters Preliminary Evaluation Board - Modified ADS-B933 to include ±12V or ±15V Supplies to U6 e-mail: [email protected] MDA_ADS-935.C02 Page 7 of 8 ADS-935 16-Bit, 5MHz Sampling A/D Converters MECHANICAL DIMENSIONS - INCHES (mm) ORDERING INFORMATION MODEL NUMBER OPERATING TEMP. RANGE PACKAGE ADS-935MC 0 to +70°C TDIP No ADS-935MC-C 0 to +70°C TDIP Yes ROHS ADS-935ME –40 to +100°C TDIP No ADS-935ME-C –40 to +100°C TDIP Yes ADS-935MM –55 to +125°C TDIP No ADS-935MM-C –55 to +125°C TDIP Yes ADS-935/883 –55 to +125°C TDIP No ACCESSORIES ADS-B935 HS-40 Evaluation Board (without ADS-935) Heat Sink for all ADS-935 models Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL. DATEL is a registered trademark of DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. ITAR and ISO 9001/14001 REGISTERED © 2015 DATEL, Inc. www.datel.com • e-mail: [email protected] 13 Aug 2015 MDA_ADS-935.C02 Page 8 of 8