Data Sheet μPD720201/μPD720202 ASSP (USB3.0 HOST CONTROLLER) R19DS0047EJ0500 Rev.5.00 Jan. 17, 2013 1. OVERVIEW The μPD720201 and μPD720202 are Renesas’ third generation Universal Serial Bus 3.0 host controllers, which comply with Universal Serial Bus 3.0 Specification, and Intel’s eXtensible Host Controller Interface (xHCI). These devices reduce power consumption and offer a smaller package foot-print making them ideal for designers who wish to add the USB3.0 interface to mobile computing devices such as laptops and notebook computers. The μPD720201 supports up to four USB3.0 SuperSpeed ports and the μPD720202 supports up to two USB3.0 SuperSpeed ports. The μPD720201 and μPD720202 use a PCI Express® Gen 2 system interface bus allowing system designers to easily add up to four (μPD720201) or two (μPD720202) USB3.0 SuperSpeed ports to systems containing the PCI Express bus interface. When connected to USB 3.0compliant peripherals, the μPD720201 and μPD720202 can transfer information at clock speeds of up to 5 Gbps. The μPD720201 and μPD720202 and USB3.0 standard are fully compliant and backward compatible with the previous USB2.0 standard. The new USB3.0 standard supports data transfer speeds of up to ten times faster than those of the previous-generation USB2.0 standard, enabling quick and efficient transfers of large amounts of information. 1.1 Features z z <R> <R> z z z z z z z z z z z Compliant with Universal Serial Bus 3.0 Specification Revision 1.0, which is released by USB Implementers Forum, Inc Supports the following speed data rate as follows: Low-Speed (1.5 Mbps) / Full-Speed (12 Mbps) / Hi-Speed (480 Mbps) / SuperSpeed (5 Gbps) μPD720201 supports up to 4 downstream ports for all speeds μPD720202 supports up to 2 downstream ports for all speeds Supports all USB compliant data transfer types as follows; Control / Bulk / Interrupt / Isochronous transfer Compliant with Intel’s eXtensible Host Controller Interface (xHCI) Specification Revision 1.0 Supports USB debugging capability on all SuperSpeed ports. Supports USB legacy function Compliant with PCI Express Base Specification Revision 2.0 Supports Latency Tolerance Reporting ECN of PCI Express Specification Supports ExpressCardTM Standard Release1.0 Supports PCI Express Card Electromechanical Specification Revision 2.0 Supports PCI Bus Power Management Interface Specification Revision 1.2 Supports USB Battery Charging Specification Revision 1.2 and other portable devices DCP mode of BC 1.2 CDP mode of BC 1.2 China Mobile Phone Chargers EU Mobile Phone Chargers Apple iOS products Operational registers are direct-mapped to PCI memory space Supports Serial Peripheral Interface (SPI) type ROM for Firmware Supports Firmware Download Interface from system BIOS or system software System clock: 24 MHz crystal R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 1 of 40 μPD720201/μPD720202 z z 1. OVERVIEW Small and low count pin package with improved signal pin assignment for efficient PCB layout μPD720201 adopts 68pin QFN (8 x 8) μPD720202 adopts 48pin QFN (7 x 7) 3.3 V and 1.05 V power supply R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 2 of 40 μPD720201/μPD720202 1.2 1. OVERVIEW Applications Desktop and Laptop computers, Tablet, Server, PCI Express Card / Express Card, Digital TV, Set-Top-Box, BD Player/Recorder, Media Player, Digital Audio systems, Projector, Multi Function Printer, Storage, Router, NAS, etc 1.3 Ordering Information Part Number Package Operating temperature Remark μPD720201K8-701-BAC-A μPD720202K8-701-BAA-A 68-pin QFN (8 × 8) 48-pin QFN (7 x 7) 0 ~ 85 °C Lead-free product Lead-free product μPD720201K8-711-BAC-A μPD720202K8-711-BAA-A 68-pin QFN (8 × 8) 48-pin QFN (7 x 7) -40 ~ 85 °C Lead-free product Lead-free product <R> Note μPD720201K8-711-BAC-A & μPD720202K8-711-BAA-A should use the FW Download function. μPD720201K8-711-BAC-A & μPD720202K8-711-BAA-A do not support the External ROM (Serial Peripheral Interface (SPI) type ROM). μPD720201 & μPD720202 should download the firmware from the External ROM (-701 versions only) or by FW download function after Power on Reset. Regarding the External ROM & FW Download function, refer to “6.How to Access External ROM” & “7. FW Download Interface” in the μPD720201 & μPD720202 User’s manual : R19UH0078E. R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 3 of 40 μPD720201/μPD720202 1.4 1. OVERVIEW Block Diagram Figure 1-1. μPD720201 Block Diagram Figure 1-2. μPD720202 Block Diagram PCI Express Gen2 Interface Complies with PCI Express Gen2 interface, with 1 lane. This block includes both the link and PHY layers. xHCI Controller Handles all support required for USB 3.0, SuperSpeed and Hi-/Full-/Low-speed. This block includes the register interface from the system. Root hub Hub function in host controller. SS PHY For SuperSpeed Tx/Rx HS/FS/LS PHY For Hi-/Full-/Low-Speed Tx/Rx Power SW I/F Connected to external power switch for port power control and over current detection. SPI Interface Connected to external serial ROM. When system BIOS or system software does not support FW download function, the external serial ROM is required. OSC Internal oscillator block. R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 4 of 40 μPD720201/μPD720202 1.5 1. OVERVIEW Pin Configuration (TOP VIEW) • 68-pin QFN (8 × 8) μPD720201K8-701-BAC-A μPD720201K8-711-BAC-A U2DP4 VDD33 U3RXDN4 U3RXDP4 VDD10 U3TXDN4 U3TXDP4 VDD10 U2DM3 U2DP3 VDD33 U3RXDN3 U3RXDP3 VDD10 U3TXDN3 U3TXDP3 Pin Configuration of μPD720201 U2DM4 Figure 1-3. 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 SMIB 1 51 U2DM2 PERSTB 2 50 U2DP2 PEWAKEB 3 49 VDD33 PECLKP 4 48 U3RXDN2 PECLKN 5 47 U3RXDP2 AVDD33 6 46 VDD10 PETXP 7 45 U3TXDN2 PETXN 8 44 U3TXDP2 VDD10 9 43 VDD10 PERXP 10 42 U2DM1 PERXN 11 41 U2DP1 VDD10 12 40 VDD33 PECREQB 13 39 U3RXDN1 PONRSTB 14 38 U3RXDP1 VDD33 15 37 VDD10 SPISO 16 36 U3TXDN1 SPICSB 17 35 U3TXDP1 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 SPISCK SPISI OCI4B PPON4 OCI3B PPON3 OCI2B PPON2 OCI1B PPON1 VDD10 VDD33 XT2 XT1 AVDD33 RREF IC(L) GND R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 5 of 40 μPD720201/μPD720202 1. OVERVIEW • 48-pin QFN (7 x 7) μPD720202K8-701-BAA-A μPD720202K8-711-BAA-A PERSTB SMIB U2DM2 U2DP2 VDD33 VDD10 U3RXDN2 U3RXDP2 VDD10 U3TXDN2 U3TXDP2 Pin Configuration of μPD720202 PEWAKEB Figure 1-4. 48 47 46 45 44 43 42 41 40 39 38 37 PECLKP 1 36 U2DM1 PECLKN 2 35 U2DP1 AVDD33 3 34 VDD33 PETXP 4 33 VDD10 PETXN 5 32 U3RXDN1 VDD10 6 31 U3RXDP1 GND PECREQB 10 27 IC(L) PONRSTB 11 26 RREF VDD33 12 25 AVDD33 R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 13 14 15 16 17 18 19 20 21 22 23 24 XT1 U3TXDP1 XT2 28 VDD33 9 VDD10 VDD10 PPON1 U3TXDN1 OCI1B 29 PPON2 8 OCI2B PERXN SPISI VDD10 SPISCK 30 SPICSB 7 SPISO PERXP Page 6 of 40 μPD720201/μPD720202 2. PIN FUNCTION 2. PIN FUNCTION This section describes each pin functions. 2.1 Power supply Table 2-1. Power Supply Pin Name μPD720201 μPD720202 Pin No. Pin No. VDD33 15, 29, 40, 49, 57, 66 12, 22, 34, 43 Power +3.3 V power supply VDD10 9, 12, 28, 37, 43, 46, 54, 60, 63 6, 9, 21, 30, 33, 39, 42 Power +1.05 V power supply. AVDD33 6, 32 3, 25 Power +3.3 V power supply for analog circuit. GND GND PAD GND PAD Power Connect to ground. IC(L) 34 27 2.2 I/O Type I Function Test pin. Connect to ground. Analog Signal Table 2-2. Pin Name RREF 2.3 720201 Pin No. 33 720202 Pin No. 26 Analog Signal I/O Type Active Level USB2 − Function Reference resistor connection. System clock Table 2-3. System Clock Pin Name XT1 XT2 720201 Pin No. 31 30 720202 Pin No. 24 23 R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Type Active Level I (OSC) − O (OSC) − Function Oscillator in Connect to 24 MHz crystal. Oscillator out Connect to 24 MHz crystal. Page 7 of 40 μPD720201/μPD720202 2.3.1 2. PIN FUNCTION System Interface signal Table 2-4. System Interface Signal Pin Name 720201 Pin No. 720202 Pin No. I/O Type Active Level Function PONRSTB 14 11 I (3.3 V Schmitt Input) Low Power on reset signal. When supporting wakeup from D3cold, this signal should be pulled high with system auxiliary power supply. SMIB 1 46 O (Open Drain) Low System management Interrupt signal. This is controlled with the USB Legacy Support Control/Status register. Refer to the User’s Manual. 2.3.2 PCI Express Interface Table 2-5. PCI Express Interface Pin Name 720201 Pin No. 720202 Pin No. I/O Type Active Level Function PECLKP 4 1 I (PCIE) − PCI Express 100 MHz Reference Clock. PECLKN 5 2 I (PCIE) − PCI Express 100 MHz Reference Clock. PETXP 7 4 O (PCIE) − PCI Express Transmit Data+. PETXN 8 5 O (PCIE) − PCI Express Transmit Data-. PERXP 10 7 I (PCIE) − PCI Express Receive Data+. PERXN 11 8 I (PCIE) − PCI Express Receive Data-. PERSTB 2 47 I (3.3 V Input) Low PCI Express “PERST#” signal. PEWAKEB 3 48 O (Open Drain) Low PCI Express “WAKE#” signal. This signal is used for remote wakeup mechanism, and requests the recovery of power and reference clock input. PECREQB 13 10 O (Open Drain) Low PCI Express “CLKREQ#” signal. This signal is used to request run/stop of reference clock. R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 8 of 40 μPD720201/μPD720202 2.3.3 2. PIN FUNCTION USB Interface Table 2-6. USB Interface Pin Name 720201 Pin No. 720202 Pin No. I/O Type Active Level Function U3TXDP1 35 28 O (USB3) − USB3.0 Transmit data D+ signal for SuperSpeed U3TXDN1 36 29 O (USB3) − USB3.0 Transmit data D- signal for SuperSpeed U3RXDP1 38 31 I (USB3) − USB3.0 Receive data D+ signal for SuperSpeed U3RXDN1 39 32 I (USB3) − USB3.0 Receive data D- signal for SuperSpeed U2DP1 41 35 I/O (USB2) − USB2.0 D+ signal for Hi-/Full-/Low-Speed U2DM1 42 36 I/O (USB2) − USB2.0 D− signal for Hi-/Full-/Low-Speed OCI1B 26 19 I (3.3 V Input) Low O (3.3 V Output) High PPON1 27 20 Over-current status input signal. 0: Over-current condition is detected 1: No over-current condition is detected USB port power supply control signal. 0: Power supply OFF 1: Power supply ON U3TXDP2 44 37 O (USB3) − USB3.0 Transmit data D+ signal for SuperSpeed U3TXDN2 45 38 O (USB3) − USB3.0 Transmit data D- signal for SuperSpeed U3RXDP2 47 40 I (USB3) − USB3.0 Receive data D+ signal for SuperSpeed U3RXDN2 48 41 I (USB3) − USB3.0 Receive data D- signal for SuperSpeed U2DP2 50 44 I/O (USB2) − USB2.0 D+ signal for Hi-/Full-/Low-Speed U2DM2 51 45 I/O (USB2) − USB2.0 D− signal for Hi-/Full-/Low-Speed OCI2B 24 17 I (3.3 V Input) Low O (3.3 V Output) High PPON2 25 R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 18 Over-current status input signal. 0: Over-current condition is detected 1: No over-current condition is detected USB port power supply control signal. 0: Power supply OFF 1: Power supply ON Page 9 of 40 μPD720201/μPD720202 Pin Name 2. PIN FUNCTION 720201 Pin No. 720202 Pin No. I/O Type Active Level Function U3TXDP3 52 − O (USB3) − USB3.0 Transmit data D+ signal for SuperSpeed U3TXDN3 53 − O (USB3) − USB3.0 Transmit data D- signal for SuperSpeed U3RXDP3 55 − I (USB3) − USB3.0 Receive data D+ signal for SuperSpeed U3RXDN3 56 − I (USB3) − USB3.0 Receive data D- signal for SuperSpeed U2DP3 58 − I/O (USB2) − USB2.0 D+ signal for Hi-/Full-/Low-Speed U2DM3 59 − I/O (USB2) − USB2.0 D− signal for Hi-/Full-/Low-Speed OCI3B 22 − I (3.3 V Input) Low O (3.3 V Output) High PPON3 23 − Over-current status input signal. 0: Over-current condition is detected 1: No over-current condition is detected USB port power supply control signal. 0: Power supply OFF 1: Power supply ON U3TXDP4 61 − O (USB3) − USB3.0 Transmit data D+ signal for SuperSpeed U3TXDN4 62 − O (USB3) − USB3.0 Transmit data D- signal for SuperSpeed U3RXDP4 64 − I (USB3) − USB3.0 Receive data D+ signal for SuperSpeed U3RXDN4 65 − I (USB3) − USB3.0 Receive data D- signal for SuperSpeed U2DP4 67 − I/O (USB2) − USB2.0 D+ signal for Hi-/Full-/Low-Speed U2DM4 68 − I/O (USB2) − USB2.0 D− signal for Hi-/Full-/Low-Speed OCI4B 20 − I (3.3 V Input) Low O (3.3 V Output) High PPON4 21 − Over-current status input signal. 0: Over-current condition is detected 1: No over-current condition is detected USB port power supply control signal. 0: Power supply OFF 1: Power supply ON Note 1: The SuperSpeed signals (U3TXDPx, U3TXDNx, U3RXDPx, U3RXDNx) and high-/full-/low-signals (U2DPx, U2DMx) of μPD720201 and μPD720202 shall be connected to the same USB connecter, Refer to μPD720201/μPD720202 User’s Manual. Note 2: The Timing of PPONx assertion is changed from μPD720200. The PPONx of μPD720200A, μPD720201 and μPD720202 are asserted after the software sets Max Device Slots Enable(MaxSlotsEn) field in Configure(CONFIG) register or Host Controller Reset(HCRST) flag in USBCMD register. On μPD720200, the PPON(2:1) are asserted immediately after the PCIe Reset. Regarding the CONFIG and USBCMD register, refer to the μPD720201/μPD720202 User's Manual. R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 10 of 40 μPD720201/μPD720202 2.3.4 2. PIN FUNCTION SPI Interface Table 2-7. SPI Interface Pin Name SPISCK SPICSB SPISI SPISO 720201 Pin No. 720202 Pin No. Type Active Level 18 15 O (3.3 V Output) − O (3.3 V Output) − O (3.3 V Output) − I (3.3 V Input) - 17 19 16 R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 14 16 13 Function SPI serial flash ROM clock signal. When the external serial ROM is not mounted, this signal should be pulled down through a pulldown resistor. SPI serial flash ROM chip select signal. When the external serial ROM is not mounted, this signal should be pulled down through a pulldown resistor. SPI serial flash ROM slave input signal. When the external serial ROM is not mounted, this signal should be pulled down through a pulldown resistor. SPI serial flash ROM slave output signal. This signal should be pulled up through a pull-up resistor in all cases. Page 11 of 40 μPD720201/μPD720202 3. ELECTRICAL SPECIFICATIONS 3. ELECTRICAL SPECIFICATIONS 3.1 Buffer List • 3.3 V input buffer OCI(4:1)B, PERSTB, IC(L) • 3.3 V input schmitt buffer PONRSTB • 3.3 V IOLH = 4mA output buffer PPON(4:1) • 3.3 V IOL = 4mA bi-directional buffer SPISO, SPISI, SPISCK, SPICSB • Open drain buffer PEWAKEB, PECREQB, SMIB • 3.3 V oscillator interface XT1, XT2 • USB Classic interface U2DP(4:1), U2DN(4:1), RREF • PCI Express Serdes PECLKP, PECLKN, PETXP, PETXN, PERXP, PERXN • USB SuperSpeed Serdes (Serializer-Deserializer) U3TXDP(4:1), U3TXDN(4:1), U3RXDP(4:1), U3RXDN(4:1) R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 12 of 40 μPD720201/μPD720202 3.2 3. ELECTRICAL SPECIFICATIONS Terminology Table 3-1. Terms Used in Absolute Maximum Ratings Parameter Symbol Meaning Power supply voltage VDD33, VDD10, AVDD33 Indicates the voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Input voltage VI Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Output voltage VO Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Output current IO Indicates absolute tolerance values for DC current to prevent damage or reduced reliability when current flows out of or into output pin. Storage temperature Tstg Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current is applied to the device. Table 3-2. Terms Used in Recommended Operating Range Parameter Symbol Meaning Power supply voltage VDD33, VDD10, AVDD33 Indicates the voltage range for normal logic operations occur when GND = 0 V. High-level input voltage VIH Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the “Min.” value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the “Max.” value is applied, the input voltage is guaranteed as low level voltage. Input rise time Tri Indicates the limit value for the time period when an input voltage applied to the input pins of the device rises from 10% to 90%. Input fall time Tfi Indicates the limit value for the time period when an input voltage applied to the input pins of the device falls from 90% to 10%. Operating temperature TA Indicates the ambient temperature range for normal logic operations. Table 3-3. Term Used in DC Characteristics Parameter Symbol Meaning Off-state output leakage current IOZ Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Input leakage current II Indicates the current that flows when the input voltage is supplied to the input pin. R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 13 of 40 μPD720201/μPD720202 3.3 3. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Table 3-4. Parameter Power supply voltage Absolute Maximum Ratings Symbol Condition Rating Units VDD33, AVDD33 −0.5 to +4.6 V VDD10 −0.5 to +1.4 V Input voltage, 3.3 V buffer VI VI < VDD33 + 0.5 V −0.5 to +4.6 V Output voltage, 3.3 V buffer VO VO <VDD33 + 0.5 V −0.5 to +4.6 V Output current IO 4 mA Type 8 mA Storage temperature Tstg −65 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. 3.4 Recommended Operating Ranges Table 3-5. Recommended Operating Ranges Parameter Operating voltage Symbol Condition VDD33, AVDD33 VDD10 Min. Typ. Max. Units 3.0 3.3 3.6 V 0.9975 1.05 1.1025 V High-level input voltage VIH 2.0 VDD33+0.3 V Low-level input voltage VIL −0.3 0.8 V Input rise time Tri Normal Buffer 0 200 ns Schmitt Buffer 0 10 ms Normal Buffer 0 200 ns Schmitt Buffer 0 10 ms TA 0 +85 °C TA -40 +85 °C Input fall time Operating ambient temperature Tfi (μPD720201K8-701-BAC-A, μPD720202K8-701-BAA-A) Operating ambient temperature (μPD720201K8-711-BAC-A, μPD720202K8-711-BAA-A) R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 14 of 40 μPD720201/μPD720202 3.5 3. ELECTRICAL SPECIFICATIONS DC Characteristics Table 3-6. DC Characteristics Parameter Symbol Condition Min. Max. Units Off-state output current IOZ VI = VDD33 or GND ±10 μA Input leakage current II VI = VDD33 or GND ±10 μA Low-level output voltage VOL IOL = 0mA 0.1 V High-level output voltage VOH IOH = 0mA VDD33-0.1 V Table 3-7. USB interface block Parameter Min. Max. Unit ZHSDRV 40.5 49.5 Ω High-level input voltage (drive) VIH 2.0 High-level input voltage (floating) VIHZ 2.7 Low-level input voltage VIL Differential input sensitivity VDI ⏐(D+) − (D−)⏐ 0.2 Differential common mode range VCM Includes VDI range 0.8 2.5 V High-level output voltage VOH RL of 14.25 kΩ to GND 2.8 3.6 V Low-level output voltage VOL RL of 1.425 kΩ to 3.6 V 0.0 0.3 V SE1 VOSE1 0.8 Output signal crossover point voltage VCRS 1.3 2.0 V Hi-speed squelch detection threshold (differential signal) VHSSQ 100 150 mV Hi-Speed disconnect detection threshold (differential signal) VHSDSC 525 625 mV Hi-Speed data signaling common mode voltage range VHSCM −50 +500 mV Hi-Speed differential input signaling level See Figure 3-13 Output pin impedance Symbol Conditions Input Levels for Low-/Full-Speed: V 3.6 V 0.8 V V Output Levels for Low-/Full-Speed: V Input Levels for Hi-Speed: Output Levels for Hi-Speed: Hi-Speed idle state VHSOI −10 +10 mV Hi-Speed data signaling high VHSOH 360 440 mV Hi-Speed data signaling low VHSOL −10 +10 mV Chirp J level (differential signal) VCHIRPJ 700 1100 mV Chirp K level (differential signal) VCHIRPK −900 −500 mV R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 15 of 40 μPD720201/μPD720202 3.6 3. ELECTRICAL SPECIFICATIONS Pin Capacitance Table 3-8. Pin capacitance Parameter Symbol SPI Interface Pin capacitance 3.7 Condition Min. CSPI Max. Units 5 pF Sequence for turning on or off power It is recommended that the time difference between the start of power-supply rise (3.3V or 1.05V) and the point where both power supplies are stabilized should be within 100ms, regardless of the order of power source. A voltage of 0.1VDD has to be raised to 0.9VDD while the time difference is measured. Figure 3-1. Order of Power Source 3.3V 1.05V 0.9VDD 0.1VDD 0.1VDD GND Within 100ms R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Within 100ms Page 16 of 40 μPD720201/μPD720202 3.8 AC Characteristics 3.8.1 System Clock 3. ELECTRICAL SPECIFICATIONS Table 3-9. System clock (XT1/XT2) ratings Parameter Symbol Clock frequency FCLK Clock duty cycle TDUTY Condition Crystal Min. Typ. Max. Units −100 ppm 24 +100 ppm MHz 40 50 60 % Remark Required accuracy of crystal or oscillator block includes initial frequency accuracy, the spread of Crystal capacitor loading, supply voltage, temperature and aging, etc. 3.8.2 PCI Express Reference Clock Table 3-10. PCI Express Interface - Reference Clock (PECLKP and PECLKN) Timings Parameter Symbol Condition Min. Max. Units Rising Edge Rate TRISE See Figure 3-5 0.6 4.0 V/ns Falling Edge Rate TFALL See Figure 3-5 0.6 4.0 V/ns Differential Input High Voltage VIH See Figure 3-8 +150 Differential Input Low Voltage VIL See Figure 3-8 Absolute crossing point voltage VCROSS See Figure 3-3 Variation of VCROSS over all rising clock edge VCROSS DELTA See Figure 3-4 Ring-back Voltage Margin VRB See Figure 3-8 −100 Time before VRB is allowed TSTABLE See Figure 3-8 500 Average Clock Period Accuracy TPERIOD AVG −300 +2800 ppm Absolute Period (including Jitter and Spread Spectrum) TPERIOD ABS 9.847 10.203 ns Cycle to Cycle Jitter VCCJITTER 150 ps Absolute Max input voltage VMAX See Figure 3-3 +1.15 V Absolute Min input voltage VMIN See Figure 3-3 −0.3 V 60 % 20 % 60 Ω Duty Cycle See Figure 3-6 Rising edge rate (PECLKP) to falling edge rate (PECLKN) matching See Figure 3-7 Clock source DC impedance R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 ZC-DC See Figure 3-2 +250 40 40 mV −150 mV +550 mV +140 mV +100 mV ps Page 17 of 40 μPD720201/μPD720202 3. ELECTRICAL SPECIFICATIONS Figure 3-2. PCI Express Reference Clock System Measurement Point and Loading Figure 3-3. PCI Express Single-Ended Measurement Points for Absolute Cross Point and Swing Figure 3-4. PCI Express Single-Ended Measurement Points for Delta Cross Point Figure 3-5. PCI Express Single-Ended Measurement Points for Rise and Fall Time Matching R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 18 of 40 μPD720201/μPD720202 3. ELECTRICAL SPECIFICATIONS Figure 3-6. PCI Express Differential Measurement Points for Duty Cycle and Period Figure 3-7. PCI Express Differential Measurement Points for Rise and Fall Time Figure 3-8. PCI Express Differential Measurement Points for Ring-back R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 19 of 40 μPD720201/μPD720202 3.8.3 3. ELECTRICAL SPECIFICATIONS Reset Table 3-11. Power on Reset (PONRSTB) Timings Parameter Symbol Power on reset time Condition TPONRST See Figure 3-9 Min. Max. 1 Units ms Remarks 1. There is no order to power-on of VDD33, AVDD33, AVDD33 and VDD10. 2. All power sources should be stable within 100 ms from the fastest rising edge of power sources. 3. PONRSTB shall be de-asserted after all power sources and the system clock become stable. 4. PONRSTB shall be de-asserted before de-asserting PERSTB. Table 3-12. PCI Express Interface - PERSTB Signal Timings Parameter Symbol Condition Min. Max. Units Power stable to PERSTB inactive TPVPERL See Figure 3-9 100 ms PECLKP/PECLKN stable before PERSTB inactive TPERST-CLK See Figure 3-9 100 μs Figure 3-9. Power Up and Reset Remark As a power saving feature, the μPD720201 / μPD720202 stops XT1/XT2 oscillation whenever PERSTB is asserted (low) while PONRSTB is inactive (high). XT1/XT2 oscillation does not stop while PONRSTB is asserted (low). R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 20 of 40 μPD720201/μPD720202 3.8.4 3. ELECTRICAL SPECIFICATIONS PCI Express CLKREQ# Table 3-13. PCI Express Interface – Power-Up and PECREQB Signal Timings Parameter Symbol PONRSTB inactive to PECREQB Output active TPVCRL Condition Min. See Figure 3-10 Max. Units 1 μs Max. Units Table 3-14. PCI Express Interface – PECREQB Clock Control Timings Parameter Symbol Condition PECREQB de-asserted high to clock parked TCRHOFF See Figure 3-11 PECREQB asserted low to clock active TCRLON See Figure 3-11 Min. 0 ns 400 ns Figure 3-10. PCI Express Power-Up PECREQB Timing Power Stable VDD33 & VDD10 PONRSTB inactive PONRSTB TPVCRL PECREQB PECLKP PECLKN Figure 3-11. PCI Express PECREQB Clock Control Timing R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 21 of 40 μPD720201/μPD720202 3.8.5 3. ELECTRICAL SPECIFICATIONS PCI Express Interface – Differential Transmitter (TX) Specifications (Refer to PCI Express Base Specification Revision 2.0 for more information) Table 3-15. PCI Express Interface – Differential Transmitter (TX) Specifications (1/2) Parameter Unit Interval Symbol UI Differential Peak to Peak(p-p) Tx voltage swing VTX-DIFFp-p Tx de-emphasis level ratio VTX-DE-RATIO-3.5dB Tx de-emphasis level ratio VTX-DE-RATIO-6dB 2.5GT/s 5.0GT/S. Units 399.88(min) 199.94(min) ps 400.12(max) 200.06(max) 0.8(min) 0.8(min) 1.2(max) 1.2(max) 3.0(min) 3.0(min) 4.0(max) 4.0(max) Not specified 5.5(min) V dB dB 6.5(max) Instantaneous lone pulse width TMIN-PULSE Transmitter Eye including all jitter sources TTX-EYE Maximum time between the jitter median and max deviation from the median TTX-EYE-MEDIAN-to- Not specified 0.9(min) UI 0.75(min) 0.75(min) UI 0.125(max) Not specified UI MAX-JITTER Tx deterministic jitter >1.5MHz TTX-HF-DJ-DD Not specified 0.15(max) UI Tx RMS jitter > 1.5MHz TTX-LF-RMS Not specified 3.0 ps RMS Transmitter rise and fall time TTX-RISE-FALL 0.125(min) 0.15(max) UI Tx rise/fall mismatch TRF-MISMATCH Not specified 0.1(max) UI Maximum Tx PLL bandwidth BWTX-PLL 22(max) 16(max) MHz Minimum Tx PLL BW for 3dB peaking BWTX-PLL-LO-3DB 1.5(min) 8(min) MHz Minimum Tx PLL BW for 1dB peaking BWTX-PLL-LO-1DB Not specified 5(min) MHz Tx PLL peaking with 8MHz min BW PKGTX-PLL1 Not specified 3.0(max) dB Tx PLL peaking with 5MHz min BW PKGTX-PLL2 Not specified 1.0(max) dB Tx package plus Si differential return loss RLTX-DIFF 10(min) 10(min) for 0.05 – 1.25GHz dB 8(min) for 1.25 – 2.5GHz Tx package plus Si common mode return loss RLTX-CM 6(min) 6(min) dB DC differential Tx impedance ZTX-DIFF-DC 80(min) 120(max) Ω 120(max) R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 22 of 40 μPD720201/μPD720202 3. ELECTRICAL SPECIFICATIONS (2/2) Parameter Symbol 2.5GT/s 5.0GT/S. Units Tx AC common mode voltage (5GT/s) VTX-CM-AC-PP Not specified 100(max) mVPP Tx AC common mode voltage (2.5GT/s) VTX-CM-AC-P 20 Not specifed mV Transmitter short-circuit current limit ITX-SHORT 90(max) 90(max) mA Transmitter DC common-mode voltage VTX-DC-CM 0(min) 0(min) V 3.6(max) 3.6(max) 0(min) 0(min) 100(max) 100(max) 0(min) 0(min) 25(max) 25(max) 0(min) 0(min) 20(max) 20(max) Not specified 0(min) Absolute Delta of DC Common Mode Voltage during L0 and Electrical Idle VTX-CM-DC-ACTIVEIDLE-DELTA Absolute Delta of DC Common Mode Voltage between PETXP and PETXN VTX-CM-DC-LINE-DELTA Electrical Idle Differential Peak Output Voltage VTX-IDLE-DIFF-AC-p DC Electrical Idle Differential Output Voltage VTX-IDLE-DIFF-DC The amount of voltage change allowed during Receiver Detection VTX-RCV-DETECT Minimum time spent in Electrical Idle mV mV mV mV 5(max) 600(max) 600(max) mV TTX-IDLE-MIN 20(min) 20(min) ns Maximum time to transition to a valid Electrical Idle after sending an EIOS TTX-IDLE-SET-TO-IDLE 8(max) 8(max) ns Maximum time to transition to valid diff signaling after leaving Electrical Idle TTX-IDLE-TO-DIFF-DATA 8(max) 8(max) ns Crosslink random timeout TCROSSLINK 1.0(max) 1.0(max) ns Lane-to-Lane Output Skew LTX-SKEW 500ps + 2UI(max) 500ps + 4UI(max) ps AC Coupling Capacitor CTX 75(min) 75(min) nF 200(max) 200(max) R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 23 of 40 μPD720201/μPD720202 3.8.6 3. ELECTRICAL SPECIFICATIONS PCI Express Interface – Differential Receiver (RX) Specifications (Refer to PCI Express Base Specification Revision 2.0 for more information) Table 3-16. PCI Express Interface – Differential Receiver (RX) Specifications (1/2) Parameter Unit Interval Symbol UI 2.5GT/s 5.0GT/S. Units 399.88(min) 199.94(min) ps 400.12(max) 200.06(max) 0.175(min) 0.120(min) 1.2(max) 1.2(max) 0.175(min) 0.100(min) 1.2(max) 1.2(max) Differential Rx peak-peak voltage for common Reference clock Rx architecture VRX-DIFF-PP-CC Differential Rx peak-peak voltage for data clocked Rx architecture VRX-DIFF-PP-DC Receiver eye time opening tRX-EYE 0.40(min) Not specified UI Max Rx inherent timing error tRX-TJ-CC Not specified 0.40(max) UI Max Rx inherent timing error tRX-TJ-DC Not specified 0.34(max) UI Max Rx inherent deterministic timing error tRX-DJ-DD-CC Not specified 0.30(max) UI Max Rx inherent deterministic timing error tRX-DJ-DD-DC Not specified 0.24(max) UI Max time delta between median and deviation from median tRX-EYE-MEDIAN-to-MAX- 0.3(max) Not specified UI JITTER Minimum width pulse at Rx tRX-MIN-PULSE Not specified 0.6(min) UI Min/max pulse voltage on consecutive UI tRX-MAX-MIN-RATIO Not specified 5(max) - Maximum Rx PLL bandwidth BWRX-PLL-HI 22(max) 16(max) MHz Minimum Rx PLL BW for 3dB peaking BWRX-PLL-LO-3DB 1.5(min) 8(min) MHz Minimum Rx PLL BW for 1dB peaking BWRX-PLL-LO-1DB Not specified 5(min) MHz Rx PLL peaking with 8 MHz min BW PKGRX-PLL1 Not specified 3.0 dB Rx PLL peaking with 5MHz min BW PKGRX-PLL2 Not specified 1.0 dB Rx package plus Si differential return loss RLRX-DIFF 10(min) 10(min) for 0.05 – 1.25GHz dB V V 8(min) for 1.25 – 2.5GHz Common mode Rx return loss RLRX-CM 6(min) 6(min) dB Receiver DC single ended impedance ZRX-DC 40(min) 40(min) Ω 60(max) 60(max) DC differential impedance ZRX-DIFF-DC 80(min) Not specified Ω 120(max) R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 24 of 40 μPD720201/μPD720202 3. ELECTRICAL SPECIFICATIONS (2/2) Parameter Symbol 2.5GT/s 5.0GT/S. Units Rx AC common mode voltage VRX-CM-AC-P 150(max) 150(max) mVP DC input CM input Impedance for V>0 during Reset or power down ZRX-HIGH-IMP-DC-POS 50k(min) 50k(min) Ω DC input CM input Impedance for V<0 during Reset or power down ZRX-HIGH-IMP-DC-NEG 1.0k(min) 1.0k(min) Ω Electrical Idle Detect Threshold VRX-IDLE-DET-DIFFp-p 65(min) 65(min) mV 175(max) 175(max) 10(max) 10(max) ms 20(max) 8(max) ns Unexpected Electrical Idle Enter Detect Threshold Integration Time ENTERTIME Lane to Lane skew LRX-SKEW R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 tRX-IDLE-DET-DIFF- Page 25 of 40 μPD720201/μPD720202 3.8.7 3. ELECTRICAL SPECIFICATIONS USB3.0 SuperSpeed Interface – Differential Transmitter (TX) Specifications (Refer to Universal Serial Bus 3.0 Specification Revision 1.0 for more information) Table 3-17. Transmitter Normative Electrical Parameters Parameter Symbol Min Max Units 199.94 200.06 ps Unit Interval UI Differential p-p Tx voltage swing VTX-DIFF-PP 0.8 1.2 V Tx de-emphasis VTX-DE-RATIO 3.0 4.0 dB DC differential impedance RTX-DIFF-DC 72 120 Ω The amount of voltage change allowed during Receiver Detection VTX-RCV-DETECT 0.6 V AC Coupling Capacitor CAC-COUPLING 200 nF Maximum slew rate tCDR-SLEW-MAX 75 10 ms/s Max Units Table 3-18. Transmitter Informative Electrical Parameters Parameter Symbol Min Deterministic min pulse tMIN-PULSE-Dj 0.96 UI Tx min pulse tMIN-PULSE-Tj 0.90 UI Transmitter Eye tTX-EYE 0.625 UI Tx deterministic jitter tTX-DJ-DD 0.205 UI Tx input capacitance for return loss CTX-PARASITIC 1.25 pF Transmitter DC common mode impedance RTX-DC 30 Ω Transmitter short-circuit current limit ITX-SHORT 60 mA Transmitter DC common-mode voltage VTX-DC-CM 2.2 V Tx AC common mode voltage VTX-CM-AC-PP-ACTIVE 100 mVp-p Absolute DC Common Mode Voltage between U1 and U0 VTX-CM-DC-ACTIVE- 200 mV Electrical Idle Differential Peak- Peak Output voltage VTX-IDLE-DIFF-AC-pp 0 10 mV DC Electrical Idle Differential Output Voltage VTX-IDLE-DIFF-DC 0 10 mV R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 18 0 IDLE-DELTA Page 26 of 40 μPD720201/μPD720202 3.8.8 3. ELECTRICAL SPECIFICATIONS USB3.0 SuperSpeed Interface – Differential Receiver (RX) Specifications (Refer to Universal Serial Bus 3.0 Specification Revision 1.0 for more information) Table 3-19. Receiver Normative Electrical Parameters Parameter Symbol Min Max Units 199.94 200.06 ps Unit Interval UI Receiver DC common mode impedance RRX-DC 18 30 Ω DC differential impedance RRX-DIFF-DC 72 120 Ω DC Input CM Input Impedance for V>0 during Reset of Power down ZRX-HIGH-IMP-DC-POS 25k LFPS Detect Threshold VRX-LFPS-DET-DIFF-p-p 100 Ω 300 mV Max Units Table 3-20. Receiver Informative Electrical Parameters Parameter Symbol Min Differential Rx peak-to-peak voltage VRX-DIFF-PP-POST-EQ Max Rx inherent timing error TRX-Tj 0.45 UI Max Rx inherent deterministic timing error TRX-DJ-DD 0.285 UI Rx input capacitance for return loss CRX-PARASITIC 1.1 pF Rx AC common mode voltage VRX-CM-AC-P 150 mVPeak Rx AC common mode voltage during the U1 to U0 transition VRX-CM-DC-ACTIVE-IDLE- 200 mVPeak R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 30 mV DELTA-P Page 27 of 40 μPD720201/μPD720202 3.8.9 3. ELECTRICAL SPECIFICATIONS USB2.0 interface (Refer to Universal Serial Bus Specification Revision 2.0 for more information) Table 3-21. Low-Speed Source Electrical Characteristics Parameter Symbol Min Max Units Driver Characteristics: Transition Time: Rise Time TLR 75 300 ns Fall Time TLF 75 300 ns Rise and Fall Time Matching TLRFM 80 125 % 1.49925 1.50075 Mb/s TLDEOP −40 100 ns To Next Transition TDDJ1 −25 25 ns For Paired Transitions TDDJ2 −14 14 ns To Next Transition TUJR1 −152 152 ns For Paired Transitions TUJR2 −200 200 ns Source SE0 interval of EOP TLEOPT 1.25 1.50 μs Receiver SE0 interval of EOP TLEOPR 670 Width of SE0 interval during differential transition TLST Clock Timings: Low-Speed Data Rate TLDRATHS Low-Speed Data Timing: Source Jitter for Differential Transition to SE0 Transition Source Jitter total (including frequency tolerance): Differential Receiver Jitter: R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 ns 210 ns Page 28 of 40 μPD720201/μPD720202 3. ELECTRICAL SPECIFICATIONS Table 3-22. Full-Speed Source Electrical Characteristics Parameter Symbol Min Max Units Driver Characteristics: Rise Time TFR 4 20 ns Fall Time TFF 4 20 ns Differential Rise and Fall Time Matching TFRFM 90 111.11 % Clock Timings: Full-Speed Data Rate TFDRATHS 11.9940 12.0060 Mb/s Frame Interval TFRAME 0.9995 1.0005 ms Consecutive Frame Interval Jitter TRFI 42 ns −2 5 ns Full-Speed Data Timing: Source Jitter for Differential Transition to SE0 Transition TFDEOP Source Jitter total (including frequency tolerance): To Next Transition TDJ1 −3.5 3.5 ns For Paired Transitions TDJ2 −4 4 ns To Next Transition TJR1 −18.5 18.5 ns For Paired Transitions TJR2 −9 9 ns Source SE0 interval of EOP TFEOPT 160 175 ns Receiver SE0 interval of EOP TFEOPR 82 Width of SE0 interval during differential transition TFST Receiver Jitter: R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 ns 14 ns Page 29 of 40 μPD720201/μPD720202 3. ELECTRICAL SPECIFICATIONS Table 3-23. Hi-Speed Source Electrical Characteristics Parameter Symbol Min Max Units Driver Characteristics: Rise Time (10% - 90%) THSR 500 ps Fall Time (10% - 90%) THSF 500 ps Driver waveform requirements See Figure 3-15 Clock Timings: Hi-Speed Data Rate THSDRAT 497.760 480.240 Mb/s Microframe Interval THSFRAME 124.9375 125.0625 μs Consecutive Microframe Interval Difference THSRFI 4 Hi-Speed bit times Hi-Speed Data Timing: Data source jitter See Figure 3-15 Receiver jitter tolerance See Figure 3-13 Table 3-24. Parameter Symbol Hub Event Timings Min Max Units Time to detect a downstream facing port connect event TDCNN 2.5 2000 μs Time to detect a disconnect event at a hub’s downstream facing port TDDIS 2 2.5 μs Duration of driving resume to a downstream port TDRSMDN 20 Time from detecting downstream resume to rebroadcast TURSM Inter-packet delay for packets traveling in same direction THSIPDSD 88 Bit times Inter-packet delay for packets traveling in opposite direction THSIPDOD 8 Bit times Inter-packet delay for root hub response for Hi-Speed THSRSPIPD1 Time for which a Chirp J or Chirp K must be continuously detected by hub during Reset handshake TFILT Time after end of device Chirp K by which hub must start driving first Chirp K in the hub’s chirp sequence TDCHBIT Time for which each individual Chirp J or Chirp K in the chirp sequence is driven downstream by hub during reset TDCHBIT Time before end of reset by which a hub must end its downstream chirp sequence TDCHSE0 R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 ms 1.0 192 ms Bit times μs 2.5 100 μs 40 60 μs 100 500 μs Page 30 of 40 μPD720201/μPD720202 3. ELECTRICAL SPECIFICATIONS Figure 3-12. Differential Input Sensitivity Range for Low-/Full-Speed Differential Input Voltage Range Differential Output Crossover Voltage Range −1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4.6 Input Voltage Range (V) Figure 3-13. Receiver Sensitivity for Transceiver at U2DP/U2DM Level 1 +400 mV Differential Point 3 Point 1 Point 4 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 0% 100% Unit Interval Figure 3-14. Receiver Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ D− Gnd 15.8 Ω 143 Ω R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 50 Ω Coax 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 143 Ω Page 31 of 40 μPD720201/μPD720202 3. ELECTRICAL SPECIFICATIONS Figure 3-15. Transmit Waveform for Transceiver at U2DP/U2DM +400 mV Differential Level 1 Point 3 Point 4 Point 1 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 3-16. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ D− Gnd 15.8 Ω 143 Ω 50 Ω Coax 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 143 Ω Figure 3-17. Differential Data Jitter for Low-/Full-Speed R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 32 of 40 μPD720201/μPD720202 Figure 3-18. 3. ELECTRICAL SPECIFICATIONS Differential-to-EOP Transition Skew and EOP Width for Low-/Full-Speed Figure 3-19. Receiver Jitter Tolerance for Low-/Full-Speed R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 33 of 40 μPD720201/μPD720202 3.8.10 3. ELECTRICAL SPECIFICATIONS SPI Type Serial ROM Interface <R> Table 3-25. SPI Type Serial ROM Interface Signals Timing (SPI Mode 0) Parameter Symbol SPISCK Clock Frequency Min. Max. Units 1 20 MHz Clock pulses width Low tSCLLOW 25 ns Clock pulses width high tSCLHIGH 25 ns SPICSB disable time tSCSDIS 100 ns SPICSB setup time tSCSSU 25 ns SPICSB hold time tSCSH 20 ns SPISI setup time to SPISCK rising edge tSDWSU 6 ns SPISI hold time from SPISCK rising edge tSDWH 6 ns SPISO validate time from SPISCK falling edge tSDRVALID SPISO hold time from SPISCK falling edge tSDRH SPISO pull-up time from SPICSB disabled (Note) tSRDET 25 ns 0 ns 170 ns <R> Note “SPISO disable time from SPICSB disabled [tSDRDIS]” is expanded including “SPISO pull-up time [tSRDET]” as of Rev5.00. This specification must be met only if μPD720201 and μPD720202 aborts firmware loading by PCIe reset. R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 34 of 40 μPD720201/μPD720202 3. ELECTRICAL SPECIFICATIONS Figure 3-20. <R> SPI Type Serial ROM Signal Timing Figure 3-21. SPISO Pull-up Timing from SPICSB disabled R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 35 of 40 μPD720201/μPD720202 3.9 3. ELECTRICAL SPECIFICATIONS Power Consumption Table 3-26. Parameter Device connection Power No device Consumption 1 device Power Consumption of μPD720201 Condition 3 devices 4 devices 10 0.4 1.0 mA There is no device on the ports under the L0 condition. 150 3 22 mA 30 3 10 mA Only one device is connected on the port. Full-Speed data transfer on the port. 140 3 22 mA Hi-Speed data transfer on the port. 150 35 22 mA SuperSpeed transfer on the port. 430 3 32 mA Low-Speed data transfer on the both ports. 40 3 10 mA Full-Speed data transfer on the both ports. 160 4 22 mA Hi-Speed data transfer on the both ports. 150 43 22 mA SuperSpeed transfer on the both ports. 520 3 32 mA Low-Speed data transfer on the three ports. 40 3 10 mA Full-Speed data transfer on the three ports. 170 5 22 mA Hi-Speed data transfer on the three ports. 150 48 22 mA SuperSpeed transfer on the three ports. 610 3 32 mA Low-Speed data transfer on the four ports. 40 3 11 mA Full-Speed data transfer on the four ports. 180 6 22 mA Hi-Speed data transfer on the four ports. 150 55 22 mA SuperSpeed transfer on the four ports. 700 3 32 mA 710 57 32 mA Power consumption during system sleep condition. (Wake On Connect, Wake On Disconnect and Wake On Over-current are disabled.) 0.9 0.3 0.1 mA Power consumption during system sleep condition. (Wake On Connect, Wake On Disconnect and/or Wake On Over-current are enabled.) 3.4 0.3 1.0 mA Power consumption during system sleep condition with one LS device enabling the remote wakeup function. 2.9 0.3 0.1 mA Two devices are connected on the ports. Three devices are connected on the ports. Four devices are connected on the ports. Four SuperSpeed hub are connected on the 4 SS hubs with SS and all ports under SS and HS data transfer. HS devices No device (D3-cold) LS device (D3-cold) VDD33 AVDD33 Units line line There is no device on the ports under the L1 condition. Low-Speed data transfer on the port. 2 devices VDD10 line Typical condition (TA = 25°C, VDD33 = 3.3 V, VDD10 = 1.05 V), operating PCI Express Gen2 system. R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 36 of 40 μPD720201/μPD720202 3. ELECTRICAL SPECIFICATIONS Table 3-27. Parameter Device connection Power No device Consumption 1 device 2 devices Power Consumption of μPD720202 Condition VDD10 line VDD33 AVDD3 Units line 3 line There is no device on the ports under the L1 condition. 8 0.2 1.0 mA There is no device on the ports under the L0 condition. 150 3 22 mA Low-Speed data transfer on the port. 30 2 10 mA Full-Speed data transfer on the port. 130 3 22 mA Hi-Speed data transfer on the port. 140 35 22 mA SuperSpeed transfer on the port. 360 2 32 mA Low-Speed data transfer on the both ports. 30 2 11 mA Full-Speed data transfer on the both ports. 150 3 22 mA Hi-Speed data transfer on the both ports. 140 43 22 mA SuperSpeed transfer on the both ports. 450 2 32 mA 460 42 32 mA Only one device is connected on the port. Two devices are connected on the ports. 2 SS hubs with SS and HS devices Two SuperSpeed hub are connected on the both ports under SS and HS data transfer. No device (D3-cold) Power consumption during system sleep condition. (Wake On Connect, Wake On Disconnect and Wake On Over-current are disabled.) 0.7 0.1 0.1 mA Power consumption during system sleep condition. (Wake On Connect, Wake On Disconnect and/or Wake On Over-current are enabled.) 2.2 0.1 0.9 mA Power consumption during system sleep condition with one LS device enabling the remote wakeup function. 1.8 0.1 0.1 mA LS device (D3-cold) Typical condition (TA = 25°C, VDD33 = 3.3 V, VDD10 = 1.05 V), operating PCI Express Gen2 system. R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 37 of 40 μPD720201/μPD720202 4. PACKAGE DRAWINGS 4. PACKAGE DRAWINGS • μPD720201K8-701-BAC-A • μPD720201K8-711-BAC-A 68-PIN QFN (8x8) R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 38 of 40 μPD720201/μPD720202 4. PACKAGE DRAWINGS • μPD720202K8-701-BAA-A • μPD720202K8-711-BAA-A 48-PIN QFN (7x7) R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 39 of 40 μPD720201/μPD720202 5. RECOMMENDED SOLDERING CONDITIONS 5. RECOMMENDED SOLDERING CONDITIONS The μPD720201 and μPD720202 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact a Renesas Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.renesas.com/prod/package/manual/ ) • μPD720201K8-701-BAC-A : 68-PIN QFN (8x8) • μPD720202K8-701-BAA-A : 48-PIN QFN (7x7) • μPD720201K8-711-BAC-A : 68-PIN QFN (8x8) • μPD720202K8-711-BAA-A : 48-PIN QFN (7x7) Soldering Method Infrared reflow Soldering Conditions Peak package’s surface temperature: 260°C, Reflow time: 60 seconds or less Symbol IR60-107-3 (220°C or higher), Maximum allowable number of reflow processes: 3, Exposure limit Note : 7 days (10 hours pre-backing is required at 125°C afterwards), Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. <Caution> Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Note The Maximum number of days during which the product can be stored at a temperature of 25°C and a relative humidity of 65% or less after dry-pack package is opened. R19DS0047EJ0500 Rev. 5.00 Jan. 17, 2013 Page 40 of 40 μPD720201/μPD720202 Data Sheet REVISION HISTORY Rev. Date Description Page 0.01 Dec. 7, 2010 - 0.02 Apr. 21, 2011 - Summary First Edition issued z Chapter1 ¾ z ¾ z June 6, 2011 - z September 16, 2011 - z 1.00 September 26, 2011 - Updated the section 1.2 Applications Chapter 2 ¾ z Updated the Recommended Soldering Condition Information Chapter 1 ¾ z Changed the revision of USB Battery Charging Specification Chapter 5 ¾ 0.04 Updated Package information. Chapter 1 ¾ z Updated Table 5-1. SPI Interface Chapter4 ¾ 0.03 Updated ordering information. Chapter2 Modified the misdescription of SMIB (I/O Type) of Table 2-4. System Interface Signal. Chapter 3 ¾ Updated the SPI Type Serial ROM Interface ¾ Updated the Power Consumption z Document promoted from Preliminary Data to full Data. z Chapter 3 (Document No. R19DS0047E) ¾ 2.00 March 2, 2012 - z Chapter 1 ¾ z Modified the misdescription OCIxB of the section 3.1 Buffer List Modified the typo of part number of section 1.5 Pin Configuration Chapter 2 ¾ Changed the Function of SPISO of Table 2-7. SPI Interface All trademarks and registered trademarks are the property of their respective owners. C-1 Rev. Date Description Page 3.00 May 25, 2012 - Summary z z Chapter 1 ¾ Updated 1.3 Ordering Information ¾ Updated 1.5 Pin Configuration (TOP VIEW) Chapter 3 ¾ ¾ Deleted the condition of Table 3-6. DC Characteristics ¾ Deleted the condition of Table 3-9. System clock (XT1/XT2) ratings ¾ Deleted the condition of Table 3-11. Power on Reset (PONRSTB) Timings ¾ Change the parameter name & value of Table 3-13. PCI Express Interface -Power-Up and PECREQB Signal Timings ¾ Added the remark to Figure 3-9. Power Up and Reset z Chapter 4 z Chapter 5 ¾ ¾ 4.00 September 20, 2012 - z January 17, 2013 z z z Added the part number Added the part number Chapter 3 ¾ 5.00 Updated the Operating Temperature Table 3-5. Recommended Operating Ranges Deleted the description of section 3.9 Chapter 1 ¾ Updated 1.1 Features ¾ Added “Note” to 1.3 Ordering Information Chapter 3 ¾ Updated Table3-25 SPI Type Serial ROM Interface Signals Timing (SPI Mode 0) ¾ Added Figure 3-21 SPISO Pull-up Timing from SPICSB disabled All Chapters ¾ Modified the typo All trademarks and registered trademarks are the property of their respective owners. C-2 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. 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Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics. 6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products. 11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-651-700, Fax: +44-1628-651-804 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Düsseldorf, Germany Tel: +49-211-65030, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. 7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898 Renesas Electronics Hong Kong Limited Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2886-9318, Fax: +852 2886-9022/9044 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949 Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 © 2012 Renesas Electronics Corporation. All rights reserved. Colophon 2.2