RL78 Microcontroller (RL78 Protocol A)

APPLICATION NOTE
RL78 Microcontrollers
RL78 Microcontrollers (RL78 Protocol A)
Programmer Edition
R01AN0815EJ0100
Rev. 1.00
Nov 7, 2011
Introduction
This application note is intended for users who understand the functions of the RL78 microcontrollers and
who will use this product to design application systems.
The purpose of this application note is to help users understand how to develop dedicated flash memory
programmers for rewriting the internal flash memory of the RL78 microcontrollers.
NOTICE:
There are corrections and additions on page 21, 75 and 79
in this document.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
Overview ........................................................................................................................................... 5
Communication Modes.................................................................................................................... 6
1.2.1 Single-wire UART communication ........................................................................................ 6
1.2.2 Two-wire UART communication ........................................................................................... 7
Command List and Status List ....................................................................................................... 8
1.3.1 Command list ........................................................................................................................ 8
1.3.2 Status list............................................................................................................................... 9
Power Application and Setting Flash Memory Programming Mode......................................... 10
1.4.1 Mode setting flowchart ........................................................................................................ 12
Shutting Down Target Power Supply ........................................................................................... 13
Command Execution Flow at Flash Memory Rewriting ............................................................. 13
CHAPTER 2
2.1
2.2
2.3
3.2
3.3
3.4
3.5
3.6
3.7
COMMAND/DATA FRAME FORMAT......................................................................... 16
Command Frame Transmission Processing............................................................................... 18
Data Frame Transmission Processing......................................................................................... 18
Data Frame Reception Processing............................................................................................... 18
CHAPTER 3
3.1
FLASH MEMORY PROGRAMMING............................................................................. 5
DESCRIPTION OF COMMAND PROCESSING ....................................................... 19
Reset Command ............................................................................................................................. 19
3.1.1 Description .......................................................................................................................... 19
3.1.2 Command frame and status frame ..................................................................................... 19
Baud Rate Set Command .............................................................................................................. 20
3.2.1 Description .......................................................................................................................... 20
3.2.2 Command frame and status frame ..................................................................................... 20
Block Erase Command .................................................................................................................. 22
3.3.1 Description .......................................................................................................................... 22
3.3.2 Command frame and status frame ..................................................................................... 22
Programming Command ............................................................................................................... 23
3.4.1 Description .......................................................................................................................... 23
3.4.2 Command frame and status frame ..................................................................................... 23
3.4.3 Data frame and status frame .............................................................................................. 23
3.4.4 Completion of transferring all data and status frame .......................................................... 24
Verify Command ............................................................................................................................. 25
3.5.1 Description .......................................................................................................................... 25
3.5.2 Command frame and status frame ..................................................................................... 25
3.5.3 Data frame and status frame .............................................................................................. 25
Block Blank Check Command ...................................................................................................... 27
3.6.1 Description .......................................................................................................................... 27
3.6.2 Command frame and status frame ..................................................................................... 27
Silicon Signature Command ......................................................................................................... 28
3.7.1 Description .......................................................................................................................... 28
3.7.2 Command frame and status frame ..................................................................................... 28
3.7.3 Silicon signature data frame ............................................................................................... 28
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3.8
Checksum Command..................................................................................................................... 30
3.8.1 Description .......................................................................................................................... 30
3.8.2 Command frame and status frame ..................................................................................... 30
3.8.3 Checksum data frame ......................................................................................................... 30
3.9 Security Set Command.................................................................................................................. 31
3.9.1 Description .......................................................................................................................... 31
3.9.2 Command frame and status frame ..................................................................................... 31
3.9.3 Data frame and status frame .............................................................................................. 32
3.10 Security Get Command ................................................................................................................. 34
3.10.1 Description .......................................................................................................................... 34
3.10.2 Command frame and status frame ..................................................................................... 34
3.10.3 Data frame and security flag............................................................................................... 35
3.11 Security Release Command.......................................................................................................... 36
3.11.1 Description .......................................................................................................................... 36
3.11.2 Command frame and status frame ..................................................................................... 36
CHAPTER 4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
UART COMMUNICATION MODE ............................................................................... 37
Command Frame Transmission Processing Flowchart............................................................. 37
Data Frame Transmission Processing Flowchart....................................................................... 38
Data Frame Reception Processing Flowchart............................................................................. 39
Reset Command ............................................................................................................................. 40
4.4.1 Processing sequence chart................................................................................................. 40
4.4.2 Description of processing sequence................................................................................... 41
4.4.3 Status at processing completion......................................................................................... 41
4.4.4 Flowchart............................................................................................................................. 42
Baud Rate Set Command .............................................................................................................. 43
4.5.1 Processing sequence chart................................................................................................. 43
4.5.2 Description of processing sequence................................................................................... 44
4.5.3 Status at processing completion......................................................................................... 44
4.5.4 Flowchart............................................................................................................................. 45
Block Erase Command .................................................................................................................. 46
4.6.1 Processing sequence chart................................................................................................. 46
4.6.2 Description of processing sequence................................................................................... 47
4.6.3 Status at processing completion......................................................................................... 47
4.6.4 Flowchart............................................................................................................................. 48
Programming Command ............................................................................................................... 49
4.7.1 Processing sequence chart................................................................................................. 49
4.7.2 Description of processing sequence................................................................................... 50
4.7.3 Status at processing completion......................................................................................... 51
4.7.4 Flowchart............................................................................................................................. 52
Verify Command............................................................................................................................. 53
4.8.1 Processing sequence char.................................................................................................. 53
4.8.2 Description of processing sequence................................................................................... 54
4.8.3 Status at processing completion......................................................................................... 54
4.8.4 Flowchart............................................................................................................................. 55
Block Blank Check Command ...................................................................................................... 56
4.9.1 Processing sequence chart................................................................................................. 56
4.9.2 Description of processing sequence................................................................................... 57
4.9.3 Status at processing completion......................................................................................... 57
4.9.4 Flowchart............................................................................................................................. 58
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4.10 Silicon Signature Command ......................................................................................................... 59
4.10.1 Processing sequence chart................................................................................................. 59
4.10.2 Description of processing sequence................................................................................... 60
4.10.3 Status at processing completion......................................................................................... 60
4.10.4 Flowchart............................................................................................................................. 61
4.11 Checksum Command..................................................................................................................... 62
4.11.1 Processing sequence chart................................................................................................. 62
4.11.2 Description of processing sequence................................................................................... 63
4.11.3 Status at processing completion......................................................................................... 63
4.11.4 Flowchart............................................................................................................................. 64
4.12 Security Set Command.................................................................................................................. 65
4.12.1 Processing sequence chart................................................................................................. 65
4.12.2 Description of processing sequence................................................................................... 66
4.12.3 Status at processing completion......................................................................................... 66
4.12.4 Flowchart............................................................................................................................. 67
4.13 Security Get Command ................................................................................................................. 68
4.13.1 Processing sequence chart................................................................................................. 68
4.13.2 Description of processing sequence................................................................................... 69
4.13.3 Status at processing completion......................................................................................... 69
4.13.4 Flowchart............................................................................................................................. 70
4.14 Security Release Command.......................................................................................................... 71
4.14.1 Processing sequence chart................................................................................................. 71
4.14.2 Description of processing sequence................................................................................... 72
4.14.3 Status at processing completion......................................................................................... 72
4.14.4 Flowchart............................................................................................................................. 73
CHAPTER 5
5.1
5.2
FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS ........... 75
Flash Memory Parameter Characteristics of RL78 ..................................................................... 75
5.1.1 Flash memory parameter characteristics in full-speed mode ............................................. 75
5.1.2 Flash memory parameter characteristics in wide-voltage mode ........................................ 79
UART Communication Mode......................................................................................................... 83
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CHAPTER
1
FLASH MEMORY
PROGRAMMING
To rewrite the contents of the internal flash memory of the RL78, a dedicated flash memory programmer (hereafter
referred to as the “programmer”) is usually used.
This Application Note explains how to develop a dedicated programmer.
1.1
Overview
The RL78 incorporates firmware that controls flash memory programming.
The programming to the internal flash
memory is performed by transmitting/receiving commands between the programmer and the RL78 via serial
communication.
Figure 1-1.
System Outline of Flash Memory Programming in RL78
RL78
Firmware
Serial
communication
Programmer
CPU
Flash memory
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1.2
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Communication Modes
As serial communications for writing the flash memory, single-wire UART communication or two-wire UART
communication can be used.
1.2.1
By exchanging the master and slave, an optimum communication can be realized.
Single-wire UART communication
Figure 1-2.
Single-wire UART Communication
The TOOL0 pin is used for single-wire UART communication. The communication conditions are shown below.
Table 1-1.
Single-wire UART Communication Conditions
Item
Baud rate
Description
Communication is performed at 115,200 bps until the Baud Rate Set
command for baud rate setting command processing is transmitted.
The transmission rate is changed to the baud rate set by the Baud Rate
Set command from the transmission of the Reset command for baud
rate command processing.
to 3.2
For details of the settable baud rate, refer
Baud Rate Set Command.
Parity bit
None
Data length
8 bits (LSB first)
Start bit
1 bit
Stop bit
2 bits (programmer → RL78)/1 bit (RL78 → programmer)
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1.2.2
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Two-wire UART communication
Figure 1-3.
Two-wire UART Communication
TxD and RxD pins are used for two-wire UART communication. The communication conditions are shown below.
Table 1-2.
Two-wire UART Communication Conditions
Item
Baud rate
Description
Communication is performed at 115,200 bps until the Baud Rate Set
command for baud rate setting command processing is transmitted.
The transmission rate is changed to the baud rate set by the Baud Rate
Set command from the transmission of the Reset command for baud
rate command processing.
to 3.2
For details of the settable baud rate, refer
Baud Rate Set Command.
Parity bit
None
Data length
8 bits (LSB first)
Start bit
1 bit
Stop bit
2 bits (programmer → RL78)/1 bit (RL78 → programmer)
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1.3
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Command List and Status List
The flash memory incorporated in the RL78 can be rewritten by using the commands listed in Table 1-2. The
programmer transmits commands to control these functions to the RL78, and checks the response status sent from the
RL78, to manipulate the flash memory.
1.3.1
Command list
The commands used by the programmer and their functions are listed below.
Table 1-3.
Command
Number
List of Commands Transmitted from Programmer to RL78
Command Name
Function
00H
Reset
Detects synchronization in communication.
22H
Block Erase
Erases a specified area in the flash memory.
40H
Programming
Writes data to a specified area in the flash memory.
13H
Verify
Compares the contents in a specified area in the flash memory
with the data transmitted from the programmer.
32H
Block Blank Check
Checks the erase status of a specified block in the flash memory.
9AH
Baud Rate Set
Sets a baud rate and a voltage.
C0H
Silicon Signature
Reads RL78 information (such as product name and flash
memory configuration).
A0H
Security Set
Sets a security flag, boot block cluster block number, and FSW.
A1H
Security Get
Reads a security flag, boot block cluster block number, boot area
exchange flag, and FSW (flash option).
A2H
Security Release
Initializes all flash options.
B0H
Checksum
Reads the checksum value of data in a specified area.
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1.3.2
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Status list
The following table lists the status codes the programmer receives from the RL78.
Table 1-4.
Status Code
Status Code List
Status
Description
04H
Command number error
Error returned if a command not supported is received
05H
Parameter error
Error returned if the value of a parameter to be appended to a command is not
appropriate.
06H
Normal acknowledgment
Normal acknowledgment
(ACK)
07H
Checksum error
Error returned if transmitted data frame has an abnormality
0FH
Verify error
Error returned if a verify error has occurred upon verifying data transmitted
10H
Protect error
Error returned if an attempt is made to execute processing that is prohibited
from the programmer
by the Security Set command
15H
Negative
Negative acknowledgment
acknowledgment (NACK)
1AH
Erase error
Erase error
1BH
IVerify error/Blank error
Internal verify error or blank check error
1CH
Write error
Write error
Reception of a checksum error or NACK is treated as an immediate abnormal end in this manual. When a dedicated
programmer is developed, however, the processing may be retried without problem from the wait immediately before
transmission of the command that results a checksum error or NACK.
In this event, limiting the retry count is
recommended for preventing infinite repetition of the retry operation.
Although not listed in the above table, if a time-out error (BUSY time-out or time-out in data frame reception during
UART communication) occurs, it is recommended to shutdown the power supply to the RL78 (refer to 1.5
Shutting
Down Target Power Supply) and then connect the power supply again.
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1.4
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Power Application and Setting Flash Memory Programming Mode
To rewrite the contents of the flash memory with the programmer, the RL78 must first be set to the flash memory
programming mode (serial programming mode).
If the TOOL0 pin is at the low level on reset release, the RL78 is first set to the pre-mode. After data for setting a
communication mode and the Baud Rate Set command have been transmitted, the RL78 is set to an operation mode of
the serial programming mode.
The following figure illustrates a timing chart for setting the flash memory programming mode and selecting the
communication mode.
Figure 1-4.
Setting Flash Memory Programming Mode and Selecting Communication Mode
Single-wire UART
Within 100 ms
VDD
RESET
TOOL0
Baud Rate Set
command frame
"3Ah" @ 115,200 bps
1-byte data for setting mode
<1>
<2> <3>
<4> <5>
<6>
<7>
<1>: Power (VDD) application
<2>: TOOL0 = Low level
<3>: Reset release
<4>: TOOL0 = High level
<5>: Start of 1-byte data transmission
<6>: End of 1-byte data transmission
<7>: Completion of Baud Rate Set command
Two-wire UART
Within 100 ms
VDD
RESET
TOOL0
"00h" @ 115,200 bps
1-byte data for setting mode
Baud Rate Set
command frame
FP_TxD
FP_RxD
<1>
<2> <3>
<4> <5>
<6>
<7>
<1>: Power (VDD) application
<2>: TOOL0 = Low level
<3>: Reset release
<4>: TOOL0 = High level
<5>: Start of 1-byte data transmission
<6>: End of 1-byte data transmission
<7>: Completion of Baud Rate Set command
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After reset release, 1-byte data is transmitted at 115,200 bps to set the RL78 to the serial programming mode and
determine a communication mode. (Note, however, that this data can be set to 00H in the two-wire UART mode even by
low-level control at 78.125 μs).
The relationship between the 1-byte data and communication interface is shown below.
Table 1-5.
1-byte Data and Communication Interface of RL78
1-byte Data
Communication Interface
3AH
Single-wire UART
00H
Two-wire UART
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1.4.1
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Mode setting flowchart
Transition processing to
programming mode
RESET pin low output
TOOL0 low output
VDD pin high output
(Target power supply on)
Wait
tTR
RESET pin high output
Wait
tRT
TOOL0 pin high output
Wait
tTM
1-byte data
(single-wire/two-wire
identified value) transmission
Wait
tMB
Baud Rate Set
command processing
Normal completion
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1.5
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Shutting Down Target Power Supply
After each command execution is completed, shut down the power supply to the target after setting the RESET pin to
low level, as shown below.
Set other pins to Hi-Z when shutting down the power supply to the target.
Caution
Shutting down the power supply and inputting a reset during command processing are prohibited.
Figure 1-5.
Timing for Terminating Flash Memory Programming Mode
VDD
RESET
Reset input
1.6
Power shutdown
Command Execution Flow at Flash Memory Rewriting
Figure 1-6 illustrates the basic flowchart when flash memory rewriting is performed with the programmer.
Other than commands shown in Figure 1-6, the Verify command and Checksum command are also supported.
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Figure 1-6.
Basic Flowchart for Flash Memory Rewrite Processing
Basic flow
Power application to target
(see Figure 1-4)
Mode setting (reset release)
(see 1.4)
Baud rate setting
(see 3.2)
Silicon signature acquisition
(Silicon Signature command)
(see 3.7)
Command execution
Processing
completed?
No
Yes
Target power shutdown
processing
(see 1.5)
Reset input and power shutdown during rewriting is
prohibited because security information may be
lost.
End
Remark
The example of each command execution is shown in Figure 1-7.
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Figure 1-7. General Command Execution Flow at Flash Memory Rewriting
General command flow
Block Blank Check
command (See 3.6)
Yes
No
Block Erase command
execution (See 3.3)
Programming command
execution (See 3.7)
Verify command
execution (See 3.4)
This command is used to check whether
data communication between programmer
and target device was normally completed.
Security Set command
execution (See 3.9)
End
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CHAPTER
2
COMMAND/DATA FRAME FORMAT
The programmer uses the command frame to transmit commands to the RL78. The RL78 uses the data frame to
transmit write data or verify data to the programmer.
A header, footer, data length information, and checksum are
appended to each frame to enhance the reliability of the transferred data.
The following shows the format of a command frame and data frame.
Figure 2-1.
Command Frame Format
SOH
LEN
COM
Command information (variable length)
SUM
ETX
(1 byte)
(1 byte)
(1 byte)
(Max. 255 bytes)
(1 byte)
(1 byte)
Figure 2-2.
Data Frame Format
STX
LEN
Data (variable length)
SUM
ETX or ETB
(1 byte)
(1 byte)
(Max. 256 bytes)
(1 byte)
(1 byte)
Table 2-1.
Description of Symbols in Each Frame
Symbol
Value
Description
SOH
01H
Command frame header
STX
02H
Data frame header
LEN
−
Data length information (00H indicates 256).
Command frame: COM + command information length
Data frame:
Data field length
COM
−
Command number
SUM
−
Checksum data for a frame
Obtained by sequentially subtracting all of calculation target data from the initial
value (00H) in 1-byte units (borrow is ignored).
The calculation targets are as
follows.
Command frame: LEN + COM + all of command information
Data frame:
LEN + all of data
ETB
17H
Footer of data frame other than the last frame
ETX
03H
Command frame footer, or footer of last data frame
The following shows examples of calculating the checksum (SUM) for a frame.
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[Command frame]
No command information is included in the following example of a Security Get command frame, so LEN and COM are
targets of checksum calculation.
SOH
LEN
COM
SUM
ETX
01H
01H
A1H
Checksum
03H
Checksum calculation targets
For this command frame, checksum data is obtained as follows.
00H (initial value) − 01H (LEN) − A1H (COM) = 5EH (Borrow ignored. Lower 8 bits only.)
The Security Get command frame finally transmitted is as follows.
SOH
LEN
COM
SUM
ETX
01H
01H
A1H
5EH
03H
[Data frame]
To transmit a data frame as shown below, LEN and D1 to D4 are targets of checksum calculation.
STX
LEN
D1
D2
D3
D4
SUM
ETX
02H
04H
FFH
80H
40H
22H
Checksum
03H
Checksum calculation targets
For this data frame, checksum data is obtained as follows.
00H (initial value) − 04H (LEN) − FFH (D1) − 80H (D2) − 40H (D3) − 22H (D4)
= 1BH (Borrow ignored. Lower 8 bits only.)
The data frame finally transmitted is as follows.
STX
LEN
D1
D2
D3
D4
SUM
ETX
02H
04H
FFH
80H
40H
22H
1BH
03H
When a data frame is received, the checksum data is calculated in the same manner, and the obtained value is used to
detect a checksum error by judging whether the value is the same as that stored in the SUM field of the receive data.
When a data frame as shown below is received, for example, a checksum error is detected.
STX
LEN
D1
D2
D3
D4
SUM
ETX
02H
04H
FFH
80H
40H
22H
1AH
03H
↑ Normally 1BH
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2.1
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Command Frame Transmission Processing
For details of the flowchart of processing to transmit command frames, read 4.1
Command Frame Transmission
Processing Flowchart.
2.2
Data Frame Transmission Processing
The write data frame (user program), verify data frame (user program), and security data frame (security flag) are
transmitted as a data frame.
For details of the flowchart of processing to transmit data frames, read 4.2
Data Frame Transmission Processing
Flowchart.
2.3
Data Frame Reception Processing
The status frame, silicon signature data frame, security data frame, and checksum data frame are received as a data
frame.
For details of the flowchart of processing to receive data frames, read 4.3
Data Frame Reception Processing
Flowchart.
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CHAPTER
3.1
3.1.1
3
DESCRIPTION OF COMMAND PROCESSING
Reset Command
Description
This command follows the Baud Rate Set command and is used to check if synchronization is performed at the baud
rate that has been newly set by the Baud Rate Set command.
3.1.2
Command frame and status frame
Figure 3-1 shows the format of a command frame for the Reset command, and Figure 3-2 shows the status frame for
the command.
Figure 3-1. Reset Command Frame (from Programmer to RL78)
SOH
LEN
COM
SUM
ETX
01H
01H
00H (Reset)
Checksum
03H
Figure 3-2. Status Frame for Reset Command (from RL78 to Programmer)
STX
LEN
Data
SUM
ETX
02H
01H
ST1
Checksum
03H
Remark
ST1: Synchronization detection result
See 4.4
Reset Command for details on the flowchart of the processing sequence between the programmer and the
RL78, and the flowchart of command processing.
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3.2
3.2.1
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Baud Rate Set Command
Description
This command is used to set a baud rate (115,200 bps by default) for UART communication and input information on
the data that sets a voltage.
The RL78 determines the operating frequency and programming mode by using voltage setting data and option byte.
3.2.2
Command frame and status frame
Figure 3-3 shows the format of a command frame for the Baud Rate Set command, and Figure 3-4 shows the status
frame for the command.
Figure 3-3. Baud Rate Set Command Frame (from Programmer to RL78)
SOH
LEN
COM
Command
Information
01H
03H
9AH
D01
SUM
ETX
Checksum
03H
Note
D02
Note For details of the command information setting, refer to Table 3-1. If data other than in Table 3-1 is set, a
time-out error will occur.
If a time-out error has occurred, execute a hardware reset and re-set the flash memory programming mode.
Remark
D01:
D02:
Baud rate setting data
Voltage setting data. Data on the voltage supplied to the target when the flash memory is written is
rounded off at the first place below decimal point and transmitted as hexadecimal data.
Example:
Voltage
D02
3.69 V → 36 → 24H
2.11 V → 21 → 15H
Table 3-1. Baud Rate Setting Data Format
Data
Set Baud Rate (bps)
00H
115,200
01H
250,000
02H
500,000
03H
1,000,000
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Figure 3-4. Status Frame for Baud Rate Set Command (from RL78 to Programmer)
Remark
STX
LEN
02H
03H
Data
ST1
D01
D02
SUM
ETX
checksum
03H
ST1:
Synchronization detection result
D01:
Transmitted as hexadecimal data. Wait time and time-out are set based on this frequency.
Example:
32 MHz: 20H
20 MHz: 18H 14H
D02:
Sets a programming mode.
To write in the full-speed mode: 00H
To write in the wide-voltage mode: 01H
See 4.5
Baud Rate Set Command for details on the flowchart of the processing sequence between the programmer
and the RL78, and the flowchart of command processing.
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RL78 Microcontroller
3.3
3.3.1
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Block Erase Command
Description
This command is used to erase the content of flash memory of the block with the specified number.
A block can be specified by specifying the first address of arbitrary block in block units.
Erasing cannot be performed, however, if execution of this command is prohibited due to the security setting (see 3.9
Security Set Command).
3.3.2
Command frame and status frame
Figure 3-7 shows the format of a command frame for the Block Erase command, and Figure 3-8 shows the status
frame for the command.
Figure 3-7. Block Erase Command Frame (from Programmer to RL78)
Command
SOH
LEN
COM
SUM
ETX
Information
01H
Remark
04H
22H
(Block Erase)
SAL SAM SAH Checksum
03H
SAH to SAL: Block erase start address (start address of any block)
SAH: Start address, high (bits 23 to 16)
SAM: Start address, middle (bits 15 to 8)
SAL:
Start address, low (bits 7 to 0)
Figure 3-8. Status Frame for Block Erase Command (from RL78 to Programmer)
STX
LEN
Data
SUM
ETX
02H
01H
ST1
Checksum
03H
Remark
ST1: Block erase result
See 4.6
Block Erase Command for details on the flowchart of the processing sequence between the programmer
and the RL78, and the flowchart of command processing.
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RL78 Microcontroller
3.4
3.4.1
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Programming Command
Description
This command is used to write the user program to the flash memory by transmitting write data after having transmitted
the write start address and the write end address. Internal verification is then executed after the last data has been
transmitted and writing has been completed.
The write start/end address can be set only in the block start/end address units.
Addresses must not be specified extending from the code flash memory to data flash memory.
If both of the status frames (ST1 and ST2) after the last data transmission indicate ACK, the RL78 firmware
automatically executes internal verify. Therefore, the Status command for this internal verify must be transmitted.
3.4.2
Command frame and status frame
Figure 3-9 shows the format of a command frame for the Programming command, and Figure 3-10 shows the status
frame for the command.
Figure 3-9. Programming Command Frame (from Programmer to RL78)
SOH
LEN
01H
07H
Remark
COM
Command Information
40H
(Programming)
SAL
SAM
SAH
EAL
EAM
EAH
SUM
ETX
Checksum
03H
SAH to SAL: Write start addresses
EAH to EAL: Write end addresses
Figure 3-10. Status Frame for Programming Command (from RL78 to Programmer)
Remark
3.4.3
STX
LEN
Data
SUM
ETX
02H
01H
ST1 (a)
Checksum
03H
ST1 (a): Command reception result
Data frame and status frame
Figure 3-11 shows the format of a frame that includes data to be written, and Figure 3-12 shows the status frame for
the data.
Figure 3-11. Data Frame to Be Written (from Programmer to RL78)
STX
02H
Remark
LEN
00H
(= 256)
Data
SUM
ETX/ETB
Write Data
Checksum
03H/17H
Write Data: User program to be written
Figure 3-12. Status Frame for Data Frame (from RL78 to Programmer)
Remark
STX
LEN
02H
02H
Data
ST1 (b)
ST2 (b)
SUM
ETX
Checksum
03H
ST1 (b): Data reception check result
ST2 (b): Write result
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RL78 Microcontroller
3.4.4
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Completion of transferring all data and status frame
Figure 3-13 shows the status frame after transfer of all data is completed.
Figure 3-13. Status Frame After Completion of Transferring All Data (from RL78 to Programmer)
STX
LEN
Data
SUM
ETX
02H
01H
ST1 (c)
Checksum
03H
Remark
ST1 (c): Internal verify result
See 4.7
Programming Command for details on the flowchart of the processing sequence between the programmer
and the RL78, and the flowchart of command processing.
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RL78 Microcontroller
3.5
3.5.1
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Verify Command
Description
This command is used to compare the data transmitted from the programmer with the data read from the RL78 (read
level) in the specified address range, and check whether they match.
The verify start/end address can be set only in the block start/end address units.
Addresses must not be specified extending from the code flash memory to data flash memory.
3.5.2
Command frame and status frame
Figure 3-14 shows the format of a command frame for the Verify command, and Figure 3-15 shows the status frame for
the command.
Figure 3-14. Verify Command Frame (from Programmer to RL78)
SOH
LEN
01H
07H
Remark
COM
Command Information
13H
SAL
(Verify)
SAM
SAH
EAL
EAM
EAH
SUM
ETX
Checksum
03H
SAH to SAL: Verify start addresses
EAH to EAL: Verify end addresses
Figure 3-15. Status Frame for Verify Command (from RL78 to Programmer)
Remark
3.5.3
STX
LEN
Data
SUM
ETX
02H
01H
ST1 (a)
Checksum
03H
ST1 (a): Command reception result
Data frame and status frame
Figure 3-16 shows the format of a frame that includes data to be verified, and Figure 3-17 shows the status frame for
the data.
Figure 3-16. Data Frame of Data to Be Verified (from Programmer to RL78)
STX
02H
Remark
LEN
00H
(= 256)
Data
SUM
ETX/ETB
Verify Data
Checksum
03H/17H
Verify Data: User program to be verified
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Figure 3-17. Status Frame for Data Frame (from RL78 to Programmer)
Remark
STX
LEN
02H
02H
Data
ST1 (b)
ST2 (b)
SUM
ETX
Checksum
03H
ST1 (b): Data reception check result
ST2 (b): Verify resultNote
Note Even if a verify error occurs in the specified address range, ACK is always returned as the verify result. The
status of all verify errors are reflected in the verify result for the last data. Therefore, the occurrence of verify
errors can be checked only when all the verify processing for the specified address range is completed.
See 4.8
Verify Command for details on the flowchart of the processing sequence between the programmer and the
RL78, and the flowchart of command processing.
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RL78 Microcontroller
3.6
3.6.1
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Block Blank Check Command
Description
This command is used to check if a block in the flash memory, with a specified block number, is blank (erased state).
A block can be specified with the start address of the blank check start block and the last address of the blank check
end block. Successive multiple blocks can be specified. However, blocks must not be specified extending from the code
flash memory to data flash memory.
To execute the Block Blank Check command alone, set the blank check area specification field (D01) to “00H”
regardless of the specified range. Set D01 to “01H” to execute the Block Blank Check command with all the blocks
specified and before the flash memory is erased.
3.6.2
Command frame and status frame
Figure 3-18 shows the format of a command frame for the Block Blank Check command, and Figure 3-19 shows the
status frame for the command.
Figure 3-18. Block Blank Check Command Frame (from Programmer to RL78)
SOH
LEN
01H
08H
Remark
COM
Command Information
32H
(Block Blank Check)
SAL
SAM SAH
EAL
EAM
SUM
EAH
D01 Checksum
ETX
03H
SAH to SAL: Block blank check start address (start address of any block)
SAM: Start address, middle (bits 15 to 8)
SAL:
Start address, low (bits 7 to 0)
SAH:
Start address, high (bits 23 to 16)
EAH to EAL: Block blank check end address (last address of any block)
EAM: End address, middle (bits 15 to 8)
D01:
EAL:
End address, low (bits 7 to 0)
EAH:
End address, high (bits 23 to 16)
Blank check specification area
00H:
Specified block (When performing a block blank check for a single block)
01H:
Specified block and flash option (When performing a blank check for the
complete area before erasing the chip)
Figure 3-19. Status Frame for Block Blank Check Command (from RL78 to Programmer)
STX
LEN
Data
SUM
ETX
02H
01H
ST1
Checksum
03H
Remark
ST1: Block blank check result
See 4.9
Block Blank Check Command for details on the flowchart of the processing sequence between the
programmer and the RL78, and the flowchart of command processing.
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RL78 Microcontroller
3.7
3.7.1
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Silicon Signature Command
Description
This command is used to read information (silicon signature) of the RL78.
3.7.2
Command frame and status frame
Figure 3-20 shows the format of a command frame for the Silicon Signature command, and Figure 3-21 shows the
status frame for the command.
Figure 3-20. Silicon Signature Command Frame (from Programmer to RL78)
SOH
LEN
01H
01H
COM
C0H
(Silicon Signature)
SUM
ETX
Checksum
03H
Figure 3-21. Status Frame for Silicon Signature Command (from RL78 to Programmer)
Remark
3.7.3
STX
LEN
Data
SUM
ETX
02H
01H
ST1
Checksum
03H
ST1: Command reception result
Silicon signature data frame
Figure 3-22 shows the format of a frame that includes silicon signature data.
Figure 3-22. Silicon Signature Data Frame (from RL78 to Programmer)
STX
LEN
02H
16H
Remark
Data
DEC
DEV
CEN
DEN
VER
(3 bytes)
(10 bytes)
(3 bytes)
(3 bytes)
(3 bytes)
SUM
ETX
checksum
03H
DEC: Device code
DEV:
Device name
CEN: Last address of code flash ROM
Example) In the case of 00FFFFH: FFH, FFH, 00H
DEN: Last address of data flash ROM
Example) In the case of 0F1FFFH: FFH, 1FH, 0FH
000000H is transmitted with a model not supporting the data flash memory.
VER:
Firmware version
Example) If version is V1.23: 01H, 02H, 03H
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Table 3-2. Example of Silicon Signature Data (R5F100LE (RL78/G13))
Field Name
Content
Length (Byte)
DEC
Device code
3
Example of Silicon Signature Data
10H
00H
06H
DEV
Device name
52H
= ‘R’
35H
= ‘5’
46H
= ‘F’
31H
= ‘1’
30H
= ‘0’
20H
= ‘0’
4CH
= ‘L’
45H
= ‘E’
20H
=‘’
20H
=‘’
10
FFH
CEN
Code flash ROM last address
(00FFFFh)
3
FFH
00H
FFH
DEN
Data flash ROM last address
(001FFFh)
3
1FH
00H
01H
VER
Firmware version
(V1.23)
3
02H
03H
See 4.10
Silicon Signature Command for details on the flowchart of the processing sequence between the
programmer and the RL78, and the flowchart of command processing.
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RL78 Microcontroller
3.8
3.8.1
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Checksum Command
Description
This command is used to acquire the checksum data in the specified area.
For the checksum calculation start/end address, specify a fixed address in block units (1 KB) starting from the top of the
flash memory.
Addresses must not be specified extending from the code flash memory to data flash memory.
Checksum data is obtained by sequentially subtracting data in the specified address range from the initial value
(0000H) in 1-byte units.
3.8.2
Command frame and status frame
Figure 3-26 shows the format of a command frame for the Checksum command, and Figure 3-27 shows the status
frame for the command.
Figure 3-26. Checksum Command Frame (from Programmer to RL78)
SOH
LEN
01H
07H
Remark
COM
Command Information
B0H
SAL
(Checksum)
SAM
SAH
EAL
EAM
EAH
SUM
ETX
Checksum
03H
SAH to SAL: Checksum calculation start addresses
EAH to EAL: Checksum calculation end addresses
Figure 3-27. Status Frame for Checksum Command (from RL78 to Programmer)
Remark
3.8.3
STX
LEN
Data
SUM
ETX
02H
01H
ST1
Checksum
03H
ST1: Command reception result
Checksum data frame
Figure 3-28 shows the format of a frame that includes checksum data.
Figure 3-28. Checksum Data Frame (from RL78 to Programmer)
Remark
STX
LEN
02H
02H
Data
CK1
CK2
SUM
ETX
Checksum
03H
CK1: Lower 8 bits of checksum data
CK2: Higher 8 bits of checksum data
See 4.11
Checksum Command for details on the flowchart of the processing sequence between the programmer
and the RL78, and the flowchart of command processing.
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RL78 Microcontroller
3.9
3.9.1
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Security Set Command
Description
This command is used to perform security settings (enabling/disabling of write, block erase, and boot block cluster
rewriting, and setting of flash shield window and others). By performing these settings with this command, rewriting of
the flash memory by an unauthorized party can be restricted. The security settings performed by this command are also
valid for the data flash memory.
Caution
Even after the security setting, additional setting of changing from enable to disable can be
performed; however, changing from disable to enable is not possible. If an attempt is made to
perform such a setting, a protect error (10H) will occur. If such setting is required, the Security
Release command must first be executed.
If block erase or boot block cluster rewriting has been disabled, however, the Security Release
command cannot be executed. Re-confirmation of security setting execution is therefore
recommended before disabling block erase or boot block cluster rewriting, due to this programmer
specification.
3.9.2
Command frame and status frame
Figure 3-29 shows the format of a command frame for the Security Set command, and Figure 3-30 shows the status
frame for the command.
Figure 3-29. Security Set Command Frame (from Programmer to RL78)
SOH
LEN
01H
01H
COM
A0H
(Security Set)
SUM
ETX
Checksum
03H
Figure 3-30. Status Frame for Security Set Command (from RL78 to Programmer)
Remark
STX
LEN
Data
SUM
ETX
02H
01H
ST1 (a)
Checksum
03H
ST1 (a): Command reception result
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RL78 Microcontroller
3.9.3
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Data frame and status frame
Figure 3-31 shows the format of a security data frame, and Figure 3-32 shows the status frame for the data.
Figure 3-31. Security Data Frame (from Programmer to RL78)
STX
LEN
02H
08H
Remarks 1. FLG:
Data
FLG
BOT
SSL
SSH
SEL
SEH
RES
(2 bytes)
SUM
ETX
Checksum
03H
Security flag
BOT:
Boot block cluster block number
SSL:
Flash shield window start block number (Lower)
SSH:
Flash shield window start block number (Higher)
SEL:
Flash shield window end block number (Lower)
SEH:
Flash shield window end block number (Higher)
RES:
Invalid data
2. If the flash shield window is not to be set, set SSL/SSH to 0000H and SEL/SEH to the target device end
block number.
Figure 3-32. Status Frame for Security Data Writing (from RL78 to Programmer)
Remark
STX
LEN
Data
SUM
ETX
02H
01H
ST1 (b)
Checksum
03H
ST1 (b): Security data write result
The following table shows the contents in the security flag field.
Table 3-3. Contents of Security Flag Field
Item
Contents
Bit 7
Fixed to “1”
Bit 6
Fixed to “1”
Bit 5
Fixed to “1”
Bit 4
Programming disable flag (1: Enables programming, 0: Disable
programming)
Bit 3
Fixed to “1”
Bit 2
Block erase disable flag (1: Enables block erase, 0: Disable block erase)
Bit 1
Bit 0
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Boot block cluster rewrite disable flag (1: Enables boot block cluster
rewrite, 0: Disable boot block cluster rewrite)
Fixed to “1”
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
The following table shows the relationship between the security flag field settings and the enable/disable status of each
operation.
Table 3-4. Security Flag Field and Enable/Disable Status of Each Operation
Command
Command Operation After Security Setting
√: Execution possible, ×: Execution impossible
U: Writing and erase in boot block cluster are impossible
Writing and block erase in boot block cluster are impossible
Block Erase
Security
Programming
Release
Target Area
Code flash memory
Data flash memory
Code flash memory
Data flash memory
−
√
√
×
×
√
×
×
√
√
×
U
√
U
√
×
Security
Setting Item
Disable
programming
Disable block erase
Boot block cluster
rewrite disable flag
For the relationship between the security function and command, and for security in the self-programming mode, refer
to the User’s Manual of each product.
See 4.12
Security Set Command for details on the flowchart of the processing sequence between the programmer
and the RL78, and the flowchart of command processing.
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
3.10 Security Get Command
3.10.1 Description
This command is used to acquire security information set to the RL78 (such as writing, block erasure,
enabling/disabling rewriting of boot block cluster, and setting of flash shield window).
3.10.2 Command frame and status frame
Figure 3-33 shows the format of a command frame for the Security Get command, and Figure 3-34 shows the status
frame for the command.
Figure 3-33. Security Get Command Frame (from Programmer to RL78)
SOH
LEN
01H
01H
COM
A1H
(Security Set)
SUM
ETX
Checksum
03H
Figure 3-34. Status Frame for Security Get Command (from RL78 to Programmer)
Remark
STX
LEN
Data
SUM
ETX
02H
01H
ST1
Checksum
03H
ST1: Command reception result
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
3.10.3 Data frame and security flag
Figure 3-35 shows the format of a security data frame.
Figure 3-35. Security Data Frame (from RL78 to Programmer)
STX
LEN
02H
08H
Remark
Data
FLG
BOT
SSL
SSH
SEL
SEH
RES
(2 bytes)
SUM
ETX
Checksum
03H
FLG: Security flag
BOT: Boot block cluster block number
SSL: Flash shield window start block number (Lower)
SSH: Flash shield window start block number (Higher)
SEL: Flash shield window end block number (Lower)
SEH: Flash shield window end block number (Higher)
RES: Invalid data
The following table shows the contents in the security flag field.
Table 3-5. Contents of Security Flag Field
Item
Bit 7
Fixed to “1”
Bit 6
Fixed to “1”
Bit 5
Fixed to “1”
Bit 4
Programming disable flag (1: Enables programming, 0: Disable
programming)
Bit 3
Fixed to “1”
Bit 2
Block erase disable flag (1: Enables block erase, 0: Disable block erase)
Bit 1
Bit 0
See 4.13
Contents
Boot block cluster rewrite disable flag (1: Enables boot block cluster
rewrite, 0: Disable boot block cluster rewrite)
Boot area exchange flag (“1”: Provided, “0”: None)
Security Get Command for details on the flowchart of the processing sequence between the programmer
and the RL78, and the flowchart of command processing.
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
3.11 Security Release Command
3.11.1 Description
This command is used to initialize the security information set to the RL78 (such as writing, block erasure,
enabling/disabling rewriting of boot block cluster, and setting of flash shield window).
The Security Release command can be executed only when all the following conditions are satisfied.
• “Block erase” and “Boot block cluster rewrite” are not prohibited.
If these are prohibited, a Protect error occurs.
• The code flash memory and data flash memoryNote are blank.
If they are not blank, a Blank error occurs.
Note Only with a model with data flash memory
3.11.2 Command frame and status frame
Figure 3-36 shows the format of a command frame for the Security Release command, and Figure 3-37 shows the
status frame for the command.
Figure 3-36. Security Release Command Frame (from Programmer to RL78)
SOH
LEN
01H
01H
COM
A2H
(Security Release)
SUM
ETX
Checksum
03H
Figure 3-37. Status Frame for Security Release Command (from RL78 to Programmer)
Remark
See 4.14
STX
LEN
Data
SUM
ETX
02H
01H
ST1
Checksum
03H
ST1: Command reception result
Security Release Command for details on the flowchart of the processing sequence between the
programmer and the RL78, and the flowchart of command processing.
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
CHAPTER
4.1
4
UART
COMMUNICATION MODE
Command Frame Transmission Processing Flowchart
Command frame
transmission processing
Command frame header
(SOH = 01H) transmission
Wait between data
transmissions
tDR
Data length (LEN)
transmission
Wait between data
transmissions
tDR
Command number (COM)
transmission
(LEN 1) bytes
transmitted?
Yes
No
Wait between data
transmissions
tDR
Transmits 1-byte
command information
Wait between data
transmissions
tDR
Checksum data (SUM)
transmission
Wait between data
transmissions
tDR
Command frame footer
(ETX = 03H) transmission
End of command frame
transmission
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RL78 Microcontroller
4.2
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Data Frame Transmission Processing Flowchart
Data frame transmission
processing
Data frame header
(SOH = 03H) transmission
Wait between data
transmissions
tDR
Data length (LEN)
transmission
Wait between data
transmissions
tDR
Command number (COM)
transmission
LEN bytes
transmitted?
Yes
No
Wait between data
transmissions
tDR
Transmits 1-byte data
Wait between data
transmissions
tDR
Checksum data (SUM)
transmission
Wait between data
transmissions
tDR
No
Last data frame?
Yes
Transmission of last data
frame footer (ETX = 03H)
Transmission of footer other
than those of last data frame
(ETB = 17H)
End of data frame
transmission
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RL78 Microcontroller
4.3
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Data Frame Reception Processing Flowchart
Data frame reception
processing
Yes
Data frame header
(STX = 02H)
received?
No
No
Timed out?
tCSx/tDSx/tSSx
Yes
Reception time-out error
Yes
Data length (LEN)
received?
No
No
Timed out?
tDT
Yes
Reception time-out error
Yes
1-byte data received?
No
No
Timed out?
tDT
Yes
Reception time-out error
No
LEN bytes received?
Yes
Yes
Checksum data
(SUM) received?
No
No
Timed out?
tDT
Yes
Reception time-out error
Yes
Data frame footer
received?
No
Timed out?
No
tDT
Yes
Reception time-out error
Checksum error?
Yes
No
End of data frame
reception
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Checksum error
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RL78 Microcontroller
4.4
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Reset Command
4.4.1 Processing sequence chart
Reset command processing sequence
RL78
Programmer
tSNx/tDNx
<1>
<2>
Time-out
occurs
<3>
Reset command frame transmission
Time-out check for
status frame reception
tCS1
Status frame received within specified time
Time-out error [C]
<4>
Status frame reception
Reception status
[ACK/other than ACK]
Other than ACK
ACK
Abnormal
termination [B]
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Normal completion
[A]
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.4.2 Description of processing sequence
<1> Waits from the previous frame reception until the next command processing starts (wait time tSN6).
<2> The Reset command is transmitted by command frame transmission processing.
<3> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS1).
<4> The status code is checked.
When ST1 = ACK: Normal completion [A]
When ST1 ≠ ACK: Abnormal termination [B]
4.4.3 Status at processing completion
Status at Processing Completion
Status Code
Normal
Normal
completion
[A]
acknowledgment
(ACK)
Abnormal
Checksum error
07H
The checksum of the transmitted command frame
does not match.
Negative
15H
Command frame data is abnormal (such as invalid
data length (LEN) or no ETX).
−
The status frame was not received within the
specified time.
termination
[B]
06H
Description
R01AN0815EJ0100 Rev. 1.00
Nov 7, 2011
command
was
executed
normally
and
synchronization between the programmer and the
RL78 has been established.
acknowledgment
(NACK)
Time-out error [C]
The
Page 41 of 90
RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.4.4 Flowchart
Reset command
processing
tSN6
Command frame
transmission
processing (Reset)
Status frame
received?
No
Yes
No
Timed out?
Yes
tCS1
Time-out error [C]
Status = ACK?
No
Yes
Normal completion [A]
R01AN0815EJ0100 Rev. 1.00
Nov 7, 2011
No
Abnormal termination [B]
Page 42 of 90
RL78 Microcontroller
4.5
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Baud Rate Set Command
4.5.1 Processing sequence chart
Baud Rate Set command processing sequence
Programmer
<1>
Waits from the mode setting until
the next command transmission
<2>
Time-out
occurs
RL78
tMB
Baud Rate Set command frame transmission
Time-out check for
status frame reception
<3>
tCS6
Status frame receive within specified time
Time-out error [C]
<4>
Status frame reception
Reception status
[ACK/other than ACK]
Other than ACK
ACK
Abnormal termination
[B]
<5>
<6>
Re-calculates timing parameters
based on the operating
frequency and programming
mode of the target which
have been received in <4>.
The baud rate of UART is
switched to the value set by
the Baud Rate Set command.
<7>
<8>
Time-out occurs
<9>
Wait from status frame
transmission until Reset
command transmission
tSN6
Reset command frame transmission
Time-out check for
status frame reception
tCS1
Status frame received within specified time
Time-out error [C]
<10>
Status frame reception
Reception status
[ACK/other than ACK]
Other than ACK
ACK
Abnormal termination
[B]
Normal completion [A]
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.5.2 Description of processing sequence
<1> Waits from the mode setting until the next command transmission (wait time tMB).
<2> The Baud Rate Set command is transmitted by command frame transmission processing.
<3> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS6).
<4> The status code is checked.
When ST1 = ACK: Proceeds to <5>.
When ST1 ≠ ACK: Abnormal termination [B]
<5> Re-calculates timing parameters based on the operating frequency and programming mode of the target which
have been received.
<6> Switches the baud rate for UART communication to the value set by the Baud Rate Set command.
<7> Waits from the command transmission until the Reset command transmission (wait time tSN6).
<8> The Reset command is transmitted by command frame transmission processing.
<9> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS1).
<10> The status code is checked.
When ST1 = ACK: Normal completion [A]
When ST1 ≠ ACK: Abnormal termination [B]
4.5.3 Status at processing completion
Status at Processing Completion
Normal
Normal
completion
[A]
acknowledgment
(ACK)
Abnormal
Checksum error
termination
[B]
Status Code
Description
06H
The command was executed normally and the
synchronization of the UART communication speed
has been established between the programmer and
the RL78.
07H
The checksum of the transmitted command frame
does not match.
Command number
04H
error
Parameter error
Command other than Baud Rate Set command has
been received.
05H
Command information (D01) is illegal.
Or, command
information (D02) indicates less than 1.8 V.
Negative
15H
Time-out error [C]
Note
Command frame data is abnormal (such as invalid
data length (LEN) or no ETX).
acknowledgment
(NACK)
−
Data frame reception was timed out.
Note If the Baud Rate Set command has not been completed normally, execute a hardware reset and re-set to the
flash memory programming mode.
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.5.4 Flowchart
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Page 45 of 90
RL78 Microcontroller
4.6
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Block Erase Command
4.6.1 Processing sequence chart
Block Erase command processing sequence
RL78
Programmer
tSNx/tDNx
<1>
<2>
Time-out
occurs
Block Erase command frame transmission
<3>
Time-out check for
status frame reception
tCS3
Status frame received within specified time
<4>
Status frame reception
Time-out error [C]
Other than
ACK
Reception status
[ACK/other than ACK]
ACK
To <1>
Abnormal termination [B]
Specified block
completely erased?
No
Yes
Normal completion [A]
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Page 46 of 90
RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.6.2 Description of processing sequence
<1> Waits from the previous frame reception until the next command transmission (wait time tSNx/tDNx).
<2> The Block Erase command is transmitted by command frame transmission processing.
<3> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS3).
<4> The status code is checked.
When ST1 = ACK: Normal completion [A] if the specified block has been erased.
Returns to <1> if the specified block has not been erased.
When ST1 ≠ ACK: Abnormal termination [B]
4.6.3 Status at processing completion
Status at Processing Completion
Normal
Normal
completion
[A]
acknowledgment
(ACK)
Abnormal
Parameter error
termination
[B]
Status Code
Description
06H
The command was executed normally and block
erase was performed normally.
05H
The specified start address is not the first address of
the block.
Checksum error
07H
The checksum of the transmitted command frame
does not match.
Protect error
10H
Block erase is prohibited in the security setting.
A
boot block is included in the specified range and
boot block rewrite is prohibited.
Negative
15H
Erase error
Time-out error [C]
Command frame data is abnormal (such as invalid
data length (LEN) or no ETX).
acknowledgment
(NACK)
1AH
−
An erase error has occurred.
The status frame was not received within the
specified time.
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Page 47 of 90
RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.6.4 Flowchart
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Page 48 of 90
RL78 Microcontroller
4.7
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Programming Command
4.7.1 Processing sequence chart
Programming command processing sequence
Programmer
RL78
tSNx/tDNx
<1>
<2>
Time-out
occurs
Programming command frame transmission
<3>
Time-out check for
status frame reception
tCS5
Status frame received within specified time
Time-out error [C]
Status frame reception
<4>
Reception status
[ACK/other than ACK]
Other than ACK
ACK
Abnormal termination [B]
tSD5
<5>
Time-out
occurs
<6>
Data frame (user data) transmission
<7>
Time-out check for
status frame reception
tDS5
Status frame received within specified time
Time-out error [C]
Status frame reception
<8>
Other than ACK
Reception status (ST1)
[ACK/other than ACK]
ACK
Abnormal termination [B]
Other than ACK
Reception status (ST2)
[ACK/other than ACK]
ACK
Abnormal termination [D]
No
To <5>
All data frames
transmitted?
[Yes/No]
Yes
Time-out
occurs
<9>
Time-out check for
status frame reception
tSS5
Status frame received within specified time
Time-out error [C]
<10>
Status frame reception
Reception status
[ACK/other than ACK]
Other than ACK
ACK
Abnormal termination [E]
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Normal completion [A]
Page 49 of 90
RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.7.2 Description of processing sequence
<1> Waits from the previous frame reception until the next command transmission (wait time tSNx/tDNx).
<2> The Programming command is transmitted by command frame transmission processing.
<3> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS5).
<4> The status code is checked.
When ST1 = ACK: Proceeds to <5>.
When ST1 ≠ ACK: Abnormal termination [B]
<5> Waits from the previous frame reception until the next data frame transmission (wait time tSD5).
<6> User data is transmitted by data frame transmission processing.
<7> A time-out check is performed from user data transmission until data frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tDS5).
<8> The status code (ST1/ST2) is checked (also refer to the processing sequence chart and flowchart).
When ST1 ≠ ACK: Abnormal termination [B]
When ST1 = ACK: The following processing is performed according to the ST2 value.
• When ST2 = ACK: Proceeds to <9> when transmission of all data frames is completed.
If there still remain data frames to be transmitted, the processing re-executes the
sequence from <5>.
• When ST2 ≠ ACK: Abnormal termination [D]
<9> A time-out check is performed until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tSS5).
<10> The status code is checked.
When ST1 = ACK: Normal completion [A]
When ST1 ≠ ACK: Abnormal termination [E]
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.7.3 Status at processing completion
Status at Processing Completion
Normal
Normal
completion
[A]
acknowledgment
(ACK)
Abnormal
Parameter error
Status Code
Description
06H
The command was executed normally and the user
data was written normally.
05H
termination
[B]
The start/end address is out of the flash memory
range, the specified start/end address is not the
first/end address of the block, or the write start
address is larger than the end address.
Or, the address range specified by the start/end
address extends from the code flash memory to the
data flash memory.
Checksum error
07H
The checksum of the transmitted command frame
or data frame does not match.
Protect error
10H
Write is prohibited in the security setting.
A boot
block is included in the specified range and boot
block rewrite is prohibited.
Negative
15H
acknowledgment
(NACK)
Time-out error [C]
Command frame data or data frame data is
abnormal (such as invalid data length (LEN) or no
ETX).
−
The status frame was not received within the
specified time.
Abnormal
IVerify error
1BH
termination
[D], [E]
Write error
1CH
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A write error has occurred.
Page 51 of 90
RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.7.4 Flowchart
Programming command
processing
tSNx/tDNx
Command frame
transmission
processing
(Programming)
Status frame
received?
No
Yes
No
Timed out?
tCS5
Yes
Time-out error [C]
Status = ACK?
No
Yes
Abnormal termination [B]
tSD5
Data frame
transmission
processing
(User program)
Status frame
received?
No
Yes
No
Timed out?
tDS5
Yes
Time-out error [C]
ST1 = ACK?
No
Yes
ST2 = ACK?
Abnormal termination [B]
No
Yes
Abnormal termination [D]
No
All data frames
transmitted?
Yes
Status frame
received?
No
Yes
No
Timed out?
No
Status = ACK?
Yes
Abnormal termination [E]
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Yes
tSS5
Time-out error [C]
Normal completion [A]
Page 52 of 90
RL78 Microcontroller
4.8
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Verify Command
4.8.1 Processing sequence char
Verify command processing sequence
RL78
Programmer
<1>
tSNx/tDNx
<2>
Verify command frame transmission
Time-out
occurs
Time-out check for
status frame reception
<3>
tCS2
Status frame received within specified time
Time-out error [C]
Status frame reception
<4>
Reception status
[ACK/other than ACK]
Other than ACK
ACK
Abnormal termination [B]
tSD2
<5>
<6>
Time-out
occurs
Data frame (user data for verify) transmission
<7>
Time-out check for
status frame reception
tDS2
Status frame received within specified time
Time-out error [C]
<8>
Other than ACK
Status frame reception （ST1/ST2）
Reception status (ST1)
[ACK/other than ACK]
ACK
Abnormal termination [B]
Reception status (ST2)
[ACK/other than ACK]
Other than ACK
ACK
Abnormal termination [D]
No
To <5>
All data frames
transmitted?
[Yes/No]
Yes
Normal completion [A]
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Page 53 of 90
RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.8.2 Description of processing sequence
<1> Waits from the previous frame reception until the next command transmission (wait time tSNx/tDNx).
<2> The Verify command is transmitted by command frame transmission processing.
<3> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS2).
<4> The status code is checked.
When ST1 = ACK: Proceeds to <5>.
When ST1 ≠ ACK: Abnormal termination [B]
<5> Waits from the previous frame reception until the next data frame transmission (wait time tSD2).
<6> User data for verifying is transmitted by data frame transmission processing.
<7> A time-out check is performed from user data transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tDS2).
<8> The status code (ST1/ST2) is checked (also refer to the processing sequence chart and flowchart).
When ST1 ≠ ACK: Abnormal termination [B]
When ST1 = ACK: The following processing is performed according to the ST2 value.
• When ST2 = ACK: If transmission of all data frames is completed, the processing ends normally [A].
If there still remain data frames to be transmitted, the processing re-executes the
sequence from <5>.
• When ST2 ≠ ACK: Abnormal termination [D]
4.8.3 Status at processing completion
Status at Processing Completion
Normal
Normal
completion
[A]
acknowledgment
(ACK)
Abnormal
Parameter error
Status Code
Description
06H
The command was executed normally and the
verify was completed normally.
05H
termination
[B]
The start/end address is out of the flash memory
range, the start/end address is not the start/end
address of the block, or the verify start address is
larger than the end address.
Or, the address range specified by the start/end
address extends from the code flash memory to
the data flash memory.
Checksum error
07H
The checksum of the transmitted command frame
or data frame does not match.
Negative
15H
acknowledgment
(NACK)
Time-out error [C]
Command frame data or data frame data is
abnormal (such as invalid data length (LEN) or no
ETX).
−
The status frame was not received within the
specified time.
Abnormal
Verify error
0FH (ST2)
A verify error has occurred.
termination
[D]
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Page 54 of 90
RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.8.4 Flowchart
Verify command
processing
tSNx/tDNx
Command frame
transmission
processing
(Verify)
Status frame
received?
No
Yes
No
Timed out?
tCS2
Yes
Time-out error [C]
ST1 = ACK?
No
Yes
Abnormal termination [B]
tSD2
Data frame
transmission
processing
(User program)
Status frame
received?
No
Yes
No
Timed out?
tDS2
Yes
Time-out error [C]
ST1 = ACK?
No
Yes
ST2 = ACK?
Abnormal termination [B]
No
Yes
Abnormal termination [D]
No
All data frames
transmitted?
Yes
Normal completion [A]
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Page 55 of 90
RL78 Microcontroller
4.9
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Block Blank Check Command
4.9.1 Processing sequence chart
Block Blank Check command processing sequence
Programmer
RL78
tSNx/tDNx
<1>
<2>
Block Blank Check command frame transmission
<3>
Time-out
occurs
Status frame received
within specified time
<4>
Time-out check for
status frame reception
tCS4
Status frame reception
Time-out error [C]
Reception status
[ACK/other than ACK]
Other than ACK
ACK
Abnormal termination [B]
Normal completion [A]
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.9.2 Description of processing sequence
<1> Waits from the previous frame reception until the next command transmission (wait time tSNx/tDNx).
<2> The Block Blank Check command is transmitted by command frame transmission processing.
<3> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS4).
<4> The status code is checked.
When ST1 = ACK: Normal completion [A]
When ST1 ≠ ACK: Abnormal termination [B]
4.9.3 Status at processing completion
Status at Processing Completion
Normal
Normal
completion
[A]
acknowledgment
(ACK)
Abnormal
Parameter error
Status Code
06H
Description
The command was executed normally and block
blank check was executed normally.
05H
termination
[B]
The end address is out of the flash memory range,
or the start/end address is not the start/end
address of the block.
The start address is larger than the end address or
the value of parameter D01 is other than 00H or
01H.
Or, the address range specified by the start/end
address extends from the code flash memory to
the data flash memory.
Checksum error
07H
The checksum of the transmitted command frame
does not match.
Negative
15H
Command frame data is abnormal (such as invalid
data length (LEN) or no ETX).
1BH
The flash memory of the specified block is not
blank.
−
The status frame was not received within the
specified time.
acknowledgment
(NACK)
Blank error
Time-out error [C]
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Page 57 of 90
RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.9.4 Flowchart
Block Blank Check
command processing
tSNx/tDNx
Command frame
transmission
processing
(Block Blank Check)
Status frame
received?
No
Yes
No
Timed out?
Yes
tCS4
Time-out error [C]
Status = ACK?
No
Yes
Abnormal termination [B]
Normal completion [A]
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Page 58 of 90
RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.10 Silicon Signature Command
4.10.1 Processing sequence chart
Silicon Signature command processing sequence
Programmer
RL78
tSNx/tDNx
<1>
<2>
Time-out
occurs
Silicon Signature command frame transmission
Time-out check for
status frame reception
<3>
tCS11
Status frame received
within specified time
Status frame reception
<4>
Time-out error [C]
Reception status
[ACK/other than ACK]
Other than ACK
ACK
<5>
Abnormal termination [B]
Time-out
occurs
Time-out check for
data frame reception
tSD11
Data frame received
within specified time
<6>
Data frame (Silicon Signature) reception
Time-out error [C]
Normal data frame?
[Yes/No]
No
Data frame error [D]
Yes
Normal completion [A]
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.10.2 Description of processing sequence
<1> Waits from the previous frame reception until the next command transmission (wait time tSNx/tDNx).
<2> The Silicon Signature command is transmitted by command frame transmission processing.
<3> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS11).
<4> The status code is checked.
When ST1 = ACK: Proceeds to <5>.
When ST1 ≠ ACK: Abnormal termination [B]
<5> A time-out check is performed until data frame (silicon signature data) reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tSD11).
<6> The received data frame (silicon signature data) is checked.
If data frame is normal:
Normal completion [A]
If data frame is abnormal: Data frame error [D]
4.10.3 Status at processing completion
Status at Processing Completion
Normal completion [A]
Abnormal
termination
[B]
Checksum error
Status Code
Description
−
The command was executed normally and silicon
signature was acquired normally.
07H
The checksum of the transmitted command frame
does not match.
Negative
15H
Time-out error [C]
Command frame data is abnormal (such as invalid
data length (LEN) or no ETX).
acknowledgment
(NACK)
−
The status frame or data frame was not received
within the specified time.
Data frame error [D]
−
The checksum of the data frame received as
silicon signature data does not match.
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.10.4 Flowchart
Silicon Signature
command processing
tSNx/tDNx
Command frame
transmission
processing
(Silicon Signature)
Status frame
received?
No
Yes
No
Timed out?
tCS11
Yes
Time-out error [C]
No
Abnormal termination [B]
Status = ACK?
Yes
No
Yes
No
Timed out?
No
Normal data frame?
Yes
Data frame error [D]
R01AN0815EJ0100 Rev. 1.00
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Yes
tSD11
Time-out error [C]
Normal completion [A]
Page 61 of 90
RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.11 Checksum Command
4.11.1 Processing sequence chart
Checksum command processing sequence
Programmer
RL78
tSNx/tDNx
<1>
Checksum command frame transmission
<2>
Time-out
occurs
Time-out check for
status frame reception
<3>
tCS10
Status frame received
within specified time
Status frame reception
<4>
Time-out error [C]
Reception status
[ACK/other than ACK]
Other than ACK
ACK
Abnormal termination [B]
<5>
Time-out check for
data frame reception
tSD10
Time-out
occurs Data frame received
within specified time
<6>
Data frame (checksum data) reception
Time-out error [C]
Normal data frame?
[Yes/No]
No
Yes
Data frame error [D]
Normal completion [A]
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.11.2 Description of processing sequence
<1> Waits from the previous frame reception until the next command transmission (wait time tSNx/tDNx).
<2> The Checksum command is transmitted by command frame transmission processing.
<3> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS10).
<4> The status code is checked.
When ST1 = ACK: Proceeds to <5>.
When ST1 ≠ ACK: Abnormal termination [B]
<5> A time-out check is performed until data frame (checksum data) reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tSD10).
<6> The received data frame (checksum data) is checked.
If data frame is normal:
Normal completion [A]
If data frame is abnormal: Data frame error [D]
4.11.3 Status at processing completion
Status at Processing Completion
Normal completion [A]
Abnormal
Parameter error
Status Code
Description
−
The command was executed normally and
checksum data was acquired normally.
05H
termination
[B]
The start/end address is out of the flash memory
range.
The specified start/end address is not the
start/end address of the block.
The start address is larger than the end address.
Or, the address range specified by the start/end
address extends from the code flash memory to
the data flash memory.
Checksum error
07H
The checksum of the transmitted command
frame does not match.
Negative
15H
Time-out error [C]
Command frame data is abnormal (such as
invalid data length (LEN) or no ETX).
acknowledgment
(NACK)
−
The status frame or data frame was not received
within the specified time.
Data frame error [D]
−
The checksum of the data frame received as
checksum data does not match.
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.11.4 Flowchart
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Page 64 of 90
RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.12 Security Set Command
4.12.1 Processing sequence chart
Security Set command processing sequence
Programmer
RL78
tSNx/tDNx
<1>
<2>
Time-out
occurs
Security Set command frame transmission
<3>
Time-out check for
tCS7
status frame reception
Status frame received within specified time
Time-out error [C]
<4>
Status frame reception
Reception status
[ACK/other than ACK]
Other than ACK
ACK
Abnormal termination [B]
tSD7
<5>
<6>
Time-out
occurs
<7>
Data frame (security data) transmission
Time-out check for
tDS7
status frame reception
Status frame received within specified time
Time-out error [C]
<8>
Status frame reception
Reception status
[ACK/other than ACK]
Other than ACK
ACK
Abnormal termination [D]
Normal completion [A]
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.12.2 Description of processing sequence
<1> Waits from the previous frame reception until the next command transmission (wait time tSNx/tDNx).
<2> The Security Set command is transmitted by command frame transmission processing.
<3> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS7).
<4> The status code is checked.
When ST1 = ACK: Proceeds to <5>.
When ST1 ≠ ACK: Abnormal termination [B]
<5> Waits from the previous frame reception until the next data frame transmission (wait time tSD7).
<6> The data frame (security setting data) is transmitted by data frame transmission processing.
<7> A time-out check is performed until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tDS7).
<8> The status code is checked.
When ST1 = ACK: Normal completion [A]
When ST1 ≠ ACK: Abnormal termination [D]
4.12.3 Status at processing completion
Status at Processing Completion
Normal
Normal
completion
[A]
acknowledgment
(ACK)
Abnormal
Parameter error
Status Code
Description
06H
The command was executed normally and security
setting data was set normally.
05H
termination
[B]
Parameter BOT does not match the specifications of
the RL78.
The FSW setting block number is not set so that the
start block number is larger than the end block
number.
Or, the FSW end block number is larger than the last
block number of the code flash memory.
Checksum error
07H
The checksum of the transmitted command frame or
data frame does not match.
Protect error
10H
An already prohibited flag is to be enabled.
Negative
15H
Command frame data is abnormal (such as invalid
data length (LEN) or no ETX).
−
The status frame or data frame was not received within
the specified time.
acknowledgment
(NACK)
Time-out error [C]
Abnormal
Erase error
1AH
termination
[D]
IVerify error
1BH
Write error
1CH
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Writing security data has failed.
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.12.4 Flowchart
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.13 Security Get Command
4.13.1 Processing sequence chart
Security Get command processing sequence
Programmer
RL78
tSNx/tDNx
<1>
Security Get command frame transmission
<2>
Time-out check for
status frame reception
<3>
tCS8
Time-out
occurs
Status frame received
within specified time
Status frame reception
<4>
Time-out error [C]
Reception status
[ACK/other than ACK]
Other than ACK
ACK
Abnormal termination [B]
Time-out
occurs
<5>
Time-out check for
data frame reception
tSD8
Data frame received
within specified time
<6>
Data frame (security data) reception
Time-out error [C]
Normal data frame?
[Yes/No]
No
Yes
Data frame error [D]
Normal completion [A]
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.13.2 Description of processing sequence
<1> Waits from the previous frame reception until the next command transmission (wait time tSNx/tDNx).
<2> The Security Get command is transmitted by command frame transmission processing.
<3> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS8).
<4> The status code is checked.
When ST1 = ACK: Proceeds to <5>.
When ST1 ≠ ACK: Abnormal termination [B]
<5> A time-out check is performed until data frame (security data) reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tSD8).
<6> The received data frame (version data) is checked.
If data frame is normal:
Normal completion [A]
If data frame is abnormal: Data frame error [D]
4.13.3 Status at processing completion
Status at Processing Completion
Normal completion [A]
Abnormal
termination
[B]
Checksum error
Status Code
Description
−
The command was executed normally and
security setting data was set normally.
07H
The checksum of the transmitted command
frame does not match.
Negative
15H
Normal acknowledgment (ACK)
Time-out error [C]
Command frame data is abnormal (such as
invalid data length (LEN) or no ETX).
acknowledgment
(NACK)
06H
−
The command was transmitted normally.
The status frame or data frame was not received
within the specified time.
Data frame error [D]
−
The checksum of the data frame received as
security data does not match.
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.13.4 Flowchart
Security Get
command processing
tSNx/tDNx
Command frame
transmission
processing
(Security Get)
Status frame
received?
No
Yes
No
Timed out?
tCS8
Yes
Time-out error [C]
No
Abnormal termination [B]
Status = ACK?
Yes
No
Yes
No
Timed out?
No
tSD8
Normal data frame?
Yes
Yes
Time-out error [C]
Data frame error [D]
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Normal completion [A]
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.14 Security Release Command
4.14.1 Processing sequence chart
The Security Release command can be executed only when all the code flash area and data flash area are blank.
Therefore, the block erase processing indicated by the dotted line above must be executed in advance.
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.14.2 Description of processing sequence
<1> Waits from the previous frame reception until the next command transmission (wait time tSNx/tDNx).
<2> The Block Erase command is transmitted by command frame transmission processing.
<3> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS3).
<4> The status code is checked.
When ST1 = ACK: Proceed to <5> if all the blocks have been erased.
Return to <1> if the specified block has not been erased.
When ST1 ≠ ACK: Abnormal termination [B]
<5> Waits from the previous frame reception until the next command transmission (wait time tSN3).
<6> The Security Release command is transmitted by command frame transmission processing.
<7> A time-out check is performed from command transmission until status frame reception.
If a time-out occurs, a time-out error [C] is returned (time-out time tCS9).
<8> The status code is checked.
When ST1 = ACK: Normal completion [A]
Execute the following processing.
To execute Security Release command alone:
Output the low level to the Reset pin and terminate.
To execute a command immediately after Security Release command:
Execute mode re-setting processing.
When ST1 ≠ ACK: Abnormal termination [B]
4.14.3 Status at processing completion
The following table shows the status codes that may be output after the Security Release command has been
executed.
Status at Processing Completion
Status Code
Description
06H
The command was executed normally and the
Normal
Normal
completion
[A]
acknowledgment
(ACK)
Abnormal
Checksum error
07H
The checksum of the transmitted command frame
or data frame does not match.
Protect error
10H
Block erase or boot block rewrite is prohibited in the
security setting.
Negative
15H
Command frame data is abnormal (such as invalid
data length (LEN) or no ETX).
Blank error
1BH
The code flash memory and/or data flash memory
is not blank.
Erase error/
1AH/1BH/1CH
The security setting could not be initialized
normally.
−
The status frame was not received within the
specified time.
termination
[B]
security setting was initialized normally.
acknowledgment
(NACK)
IVerify error/
Write error
Time-out error [C]
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4.14.4 Flowchart
Security Release
command processing
tSNx/tDNx
Command frame
transmission
processing
(Block Erase)
Status frame
received?
No
Yes
No
Timed out?
tCS3
Yes
Time-out error [C]
Status = ACK?
No
Yes
No
Abnormal termination [B]
All blocks
completely
erased?
Erasure of all blocks by Block
Erase command processing
Yes
tSN3
Command frame
transmission
processing
(Security Release)
Status frame
received?
No
Yes
No
Timed out?
tCS9
Yes
Time-out error [C]
Status = ACK?
No
Yes
Executing
command immediately after
Security Release?
Abnormal termination [B]
Yes
No Executing alone
RESET pin low output
Mode re-setting
processing
Normal completion [A]
The Security Release command can be executed only when all the code flash area and data flash area are blank.
Therefore, the block erase processing indicated by the dotted line above must be executed in advance.
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Mode re-setting processing
Low output to Reset
Low output to TOOL0
Reset release
TOOL0 pulled up
Waits for mode setting data.
Mode setting 1-byte data
@115,200 bps
Communication mode determined
Mode setting data
Single-wire UART: 3AH
Two-wire UART: 00H
Single-wire UART: Input/output Tool0
Two-wire UART: Input RxD, output TxD
Baud Rate Set command processing
Normal completion
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RL78 Microcontroller
CHAPTER
5
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
FLASH MEMORY
PROGRAMMING PARAMETER CHARACTERISTICS
This chapter describes the characteristics of parameter transmitted between the programmer and the devices (RL78) in
the flash memory programming mode. Refer to the user’s manual of the devices (RL78) for electrical specifications
when designing a programmer.
5.1
Flash Memory Parameter Characteristics of RL78
5.1.1 Flash memory parameter characteristics in full-speed mode
(1) Flash memory programming mode setting time
Parameter
Symbol
MIN.
¯¯¯¯¯¯¯¯¯¯↑
TOOL0↓ to RESET
tTR
tSU
¯¯¯¯¯¯¯¯¯¯
RESET↑ to TOOL0↑
tRT
723 μs+tHD
TOOL0↑ to Receive mode info
tTM
16 μs
Receive mode info to Receive Baud Rate Set Command
tMB
62 μs
¯¯¯¯¯¯¯¯¯¯
RESET↑ to Receive Baud Rate Set Command
tRB
100 ms
TYP.
MAX.
Note 2
Note 2
Note 2
100msNote1
Note 1
Notes 1. The location indicated differs depending on the setting of the option byte.
Option byte (0000C3H.bit6) = 0: ¯¯¯¯¯¯¯¯¯¯
RESET↑ to Baud Rate Set Command reception: within 100 ms
= 1: TOOL0↑ to Baud Rate Set command reception: within 100 ms
To permit both of the option byte settings, complete the reception of the Baud Rate Set command within 100
ms from ¯¯¯¯¯¯¯¯¯¯
RESET↑ (refer to the User's Manual of each device (tSUINIT)).
2. The flash memory programmer needs the specified wait time before transmission.
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
(2) Programming characteristic
Wait
Between data transmissions
Condition
16 MHz≤fCLK≤32 MHz
Data
reception
Check Sum command
0 μs
Note 3
tDT
tSD10
data frame transmission
Note 2
6/fCLK
10/fCLK
Notes 1
48/fCLK+
72/fCLK+
15564/fCLK
30720/fCLK
×BLK
Notes 2, 4
Programming command
tSD5
41/fCLK
Note 3
Verify command
tSD2
41/fCLK
Note 3
Security Set command
tSD7
32/fCLK
Note 3
Security Get command
tSD8
139/fCLK
Signature command
tSD11
340/fCLK
From status frame transmission until
Reset command
tSN1
51/fCLK
Note 3
next command frame reception
Verify command
tSN2
54/fCLK
Note 3
Block Erase command
tSN3
51/fCLK
Note 3
Block Blank Check command
tSN4
51/fCLK
Note 3
Programming command
tSN5
51/fCLK
Note 3
Baud Rate Set command
tSN6
67 μs
Security Set command
tSN7
51/fCLK
Note 3
Security Release command
tSN9
51/fCLK
Note 3
From data frame transmission until
Security Get command
tDN8
44/fCLK
Note 3
next command frame reception
Checksum command
tDN10
44/fCLK
Note 3
Signature command
tDN11
44/fCLK
Note 3
From status frame transmission until
MAX.
Note 3
136/fCLK − 8 μs
0.75 MHz≤fCLK<16 MHz
Note 5
MIN.
tDR
Note 5
Data transmission
From status frame transmission until
Symbol
×BLK
Notes 1, 4
data frame reception (1)
From status frame transmission until
data frame reception (2)
From status frame transmission until
data frame reception (3)
From status frame transmission until
Note 2
212/fCLK
Note 1
Note 2
512/fCLK
data frame reception (4)
From status frame transmission until
Note 1
data frame reception (5)
Note 3
Notes 1. This is as a guide of the time-out time.
2. The Flash memory programmer must be ready for receiving communication data within the specified time.
3. The Flash memory programmer needs the specified time before transmission.
4. The detail of the symbol is as follows.
BLK: Number of blocks (in 1024-byte units)
5. The device operates at either 0.75 MHz or 1 MHz since reset release until reception of the Baud Rate Set
command. Calculate the time on the assumption that fclk = 0.75 MHz so that communication can be executed
during this period.
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
(3) Command characteristics
Command
Reset
Verify
Symbol
Condition
tCS1
−
tCS2
tDS2
Block Erase
Block Blank Check
tCS3
tCS4
MIN.
MAX.
58/fCLK
Note 2
Code flash
58/fCLK
Note 2
Data flash
58/fCLK
Note 2
Code flash
64/fCLK
Note 2
11981/fCLK
Data flash
64/fCLK
Note 2
11980/fCLK
Code flash
58/fCLK
Note 2
67731/fCLK+255098 μs
Data flash
58/fCLK
Note 2
281423/fCLK+264790 μs
Code flash
58/fCLK
Note 2
Note 1
255/fCLK
Note 1
335/fCLK
Note 1
351/fCLK
Note 1
Note 1
Note 1
Note 1
3805/fCLK+91 μs+
(1457/fCLK+80 μs)×BLK+
(203/fCLK+18 μs)×N
Data flash
58/fCLK
Notes 1, 3
2503/fCLK+86 μs+
Note 2
(5827/fCLK+318 μs)×BLK
Programming
tCS5
58/fCLK
1432/fCLK
Data flash
58/fCLK
Note 2
346/fCLK
Code flash
64/fCLK
Note 2
113502/fCLK+71753 μs
Data flash
64/fCLK
Note 2
309870/fCLK+219761 μs
Code flash
1294/fCLK+37 μs
Code flash
tDS5
tSS5
Notes 1, 3
Note 2
Note 1
Note 1
Note 1
Note 1
1732/fCLK+36 μs+
Note 2
(7096/fCLK+892 μs)×BLK+
(182/fCLK+17 μs)×N
Data flash
Notes 1, 3
397/fCLK+30 μs+
282/fCLK+22 μs
Note 2
(28382/fCLK+3568 μs)×BLK
Baud Rate Set
tCS6
−
58 μs
Security Set
tCS7
−
58/fCLK
Note 2
168/fCLK
tDS7
−
60/fCLK
Note 2
277095/fCLK+1027564 μs
Security Get
tCS8
−
58/fCLK
Note 2
154/fCLK
Security Release
tCS9
Model with data flash
58/fCLK
Note 2
Notes 1, 3
4735 μs
Note 2
Note 1
Note 1
Note 1
Note 1
146110/fCLK+511868 μs+
(1457/fCLK+80 μs)×CBLK+
(5827/fCLK+318 μs)×DBLK+
(203/fCLK+18 μs)×N
Model without data
58/fCLK
Note 2
145783/fCLK+511837 μs+
(1457/fCLK+80 μs)×CBLK+
flash
(203/fCLK+18 μs)×N
Checksum
tCS10
Signature Get
tCS11
Notes 1, 4
Code flash
58/fCLK
Note 2
203/fCLK
Data flash
58/fCLK
Note 2
219/fCLK
−
58/fCLK
Note 2
111/fCLK
Notes 1, 4
Note 1
Note 1
Note 1
Notes 1. This is as a guide of the time-out time.
2. The Flash memory programmer must be ready for receiving communication data within the specified time.
3. The details of the symbols are as follows.
BLK: Number of blocks (in 1024-byte units)
N:
Number of times Flash memory is to be accessed
Expression (Result of division in parentheses is rounded off at decimal point):
(End address/40000H) – (Start address/40000H) + 1
[Example]
Start address = 00000H & End address = 3FFFFH → N = 1
Start address = 3FC00H & End address = 403FFH → N = 2
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4. The details of the symbols are as follows.
CBLK: Total number of blocks of CodeFlash
[Example] Code Flash size = 64 KB → CBLK = 64
DBLK: Total number of blocks of DataFlash
[Example] Data Flash size = 4 KB → DBLK = 4
N:
Number of times Flash memory is to be accessed
Expression (Rounded off at decimal point): CBLK/256
[Example] CBLK = 256 → N = 1
CBLKK = 384 → N = 2
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RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
5.1.2 Flash memory parameter characteristics in wide-voltage mode
(1) Flash memory programming mode setting time
Parameter
Symbol
MIN.
¯¯¯¯¯¯¯¯¯¯↑
TOOL0↓ to RESET
tTR
¯¯¯¯¯¯¯¯¯¯↑ to TOOL0↑
RESET
tRT
723 μs+tHD
TOOL0↑ to Receive mode info
tTM
16 μs
Receive mode info to Receive Baud Rate Set Command
tMB
62 μs
¯¯¯¯¯¯¯¯¯¯↑ to Receive Baud Rate Set Command
RESET
tRB
100 ms
TYP.
MAX.
tSU
Note 2
Note 2
Note 2
100msNote1
Note 1
Notes 1. The location indicated differs depending on the setting of the option byte.
Option byte (0000C3H.bit6) = 0: ¯¯¯¯¯¯¯¯¯¯
RESET↑ to Baud Rate Set Command reception: within 100 ms
= 1: TOOL0↑ to Baud Rate Set command reception: within 100 ms
To permit both of the option byte settings, complete the reception of the Baud Rate Set command within 100
ms from ¯¯¯¯¯¯¯¯¯¯
RESET↑ (refer to the User's Manual of each device (tSUINIT)).
2. The flash memory programmer needs the specified wait time before transmission.
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
(2) Programming characteristic
Wait
Between data transmissions
Condition
16 MHz≤fCLK≤32 MHz
Data
reception
Check Sum command
0 μs
Note 3
tDT
tSD10
data frame transmission
Note 1
6/fCLK
10/fCLK
Note 2
48/fCLK+
72/fCLK+
15564/fCLK×
30720/fCLK×
BLK
Notes 2, 4
Programming command
tSD5
41/fCLK
Note 3
Verify command
tSD2
41/fCLK
Note 3
Security Set command
tSD7
32/fCLK
Note 3
Security Get command
tSD8
139/fCLK
Signature command
tSD11
340/fCLK
From status frame transmission until
Reset command
tSN1
51/fCLK
Note 3
next command frame reception
Verify command
tSN2
54/fCLK
Note 3
Block Erase command
tSN3
51/fCLK
Note 3
Block Blank Check command
tSN4
51/fCLK
Note 3
Programming command
tSN5
51/fCLK
Note 3
Baud Rate Set command
tSN6
67 μs
Security Set command
tSN7
51/fCLK
Note 3
Security Release command
tSN9
51/fCLK
Note 3
From data frame transmission until
Security Get command
tDN8
44/fCLK
Note 3
next command frame reception
Checksum command
tDN10
44/fCLK
Note 3
Signature command
tDN11
44/fCLK
Note 3
From status frame transmission until
MAX.
Note 3
136/fCLK − 8 μs
0.75 MHz≤fCLK<16 MHz
Note 5
MIN.
tDR
Note 5
Data transmission
From status frame transmission until
Symbol
BLK
Notes 1, 4
data frame reception (1)
From status frame transmission until
data frame reception (2)
From status frame transmission until
data frame reception (3)
From status frame transmission until
Note 2
212/fCLK
Note 1
Note 2
512/fCLK
data frame reception (4)
From status frame transmission until
Note 1
data frame reception (5)
Note 3
Notes 1. This is as a guide of the time-out time.
2. The Flash memory programmer must be ready for receiving communication data within the specified time.
3. The Flash memory programmer needs the specified time before transmission.
4. The detail of the symbol is as follows.
BLK: Number of blocks (in 1024-byte units)
5. The device operates at either 0.75 MHz or 1 MHz since reset release until reception of the Baud Rate Set
command. Calculate the time on the assumption that fclk = 0.75 MHz so that communication can be executed
during this period.
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
(3) Command characteristics
Command
Reset
Verify
Symbol
Condition
tCS1
−
tCS2
tDS2
Block Erase
Block Blank Check
tCS3
tCS4
MIN.
MAX.
58/fCLK
Note 2
255/fCLK
Code flash
58/fCLK
Note 2
Note 1
335/fCLK
Data flash
58/fCLK
Note 2
351/fCLK
Code flash
64/fCLK
Note 2
11981/fCLK
Data flash
64/fCLK
Note 2
11980/fCLK
Code flash
58/fCLK
Note 2
59455/fCLK+265331 μs
Data flash
58/fCLK
Note 2
248862/fCLK+299307 μs
Code flash
58/fCLK
Note 2
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
3799/fCLK+134 μs+
(1259/fCLK+278 μs)×BLK+
(199/fCLK+57 μs)×N
Data flash
58/fCLK
Notes 1, 3
2494/fCLK+168 μs+
Note 2
(5035/fCLK+1110 μs)×BLK
Programming
tCS5
58/fCLK
Note 2
1432/fCLK
Data flash
58/fCLK
Note 2
346/fCLK
Code flash
64/fCLK
Note 2
107803/fCLK+138891 μs
Data flash
64/fCLK
Note 2
287076/fCLK+488315 μs
Code flash
1287/fCLK+72 μs
Code flash
tDS5
tSS5
Notes 1, 3
Note 1
Note 1
Note 1
Note 1
1732/fCLK+36 μs+
Note 2
(4351/fCLK+7324 μs)×BLK+
(184/fCLK+44 μs)×N
Data flash
Notes 1, 3
398/fCLK+58 μs+
276/fCLK+57 μs
Note 2
(17403/fCLK+29293 μs)×BLK
Baud Rate Set
tCS6
−
58 μs
Security Set
tCS7
−
58/fCLK
Note 2
168/fCLK
tDS7
−
60/fCLK
Note 2
242909/fCLK+1075967 μs
Security Get
tCS8
−
58/fCLK
Note 2
154/fCLK
Security Release
tCS9
Model with data flash
58/fCLK
Note 2
Notes 1, 3
4735 μs
Note 2
Note 1
Note 1
Note 1
Note 1
128408/fCLK+534723 μs+
(1259/fCLK+278 μs)×CBLK+
(5035/fCLK+1110 μs)×DBLK+
(199/fCLK+57 μs)×N
Model without data
58/fCLK
Note 2
128084/fCLK+534653 μs+
(1259/fCLK+278 μs)×CBLK+
flash
(199/fCLK+57 μs)×N
Checksum
tCS10
Signature Get
tCS11
Notes 1, 4
Code flash
58/fCLK
Note 2
203/fCLK
Data flash
58/fCLK
Note 2
219/fCLK
−
58/fCLK
Note 2
111/fCLK
Notes 1, 4
Note 1
Note 1
Note 1
Notes 1. This is as a guide of the time-out time.
2. The Flash memory programmer must be ready for receiving communication data within the specified time.
3. The details of the symbols are as follows.
BLK: Number of blocks (in 1024-byte units)
N:
Number of times Flash memory is to be accessed
Expression (Result of division in parentheses is rounded off at decimal point):
(End address/40000H) – (Start address/40000H) + 1
[Example]
Start address = 00000H & End address = 3FFFFH → N = 1
Start address = 3FC00H & End address = 403FFH → N = 2
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
4. The details of the symbols are as follows.
CBLK: Total number of blocks of CodeFlash
[Example] Code Flash size = 64 KB → CBLK = 64
DBLK: Total number of blocks of DataFlash
[Example] Data Flash size = 4 KB → DBLK = 4
N:
Number of times Flash memory is to be accessed
Expression (Rounded off at decimal point): CBLK/256
[Example] CBLK = 256 → N = 1
CBLKK = 384 → N = 2
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RL78 Microcontroller
5.2
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
UART Communication Mode
In the figure below, TOOL0 is illustrated as two separate lines for the sake of description, but it is actually a single line.
The VDD level of TOOL0 can be achieved by using a pull-up resistor (the pin is Hi-Z).
(a) Data frame
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
(b) Programming mode setting
Single-wire UART
VDD
RESET
TOOL0
Baud Rate Set
command frame
"3Ah" @ 115,200 bps
1-byte data for setting mode
tTR
tRT
tTM
tMB
tRB
Two-wire UART
VDD
RESET
TOOL0
"00h" @ 115,200 bps
1-byte data for setting mode
tTR
tRT
tTM
tMB
Baud Rate Set
command frame
FP_TxD
FP_RxD
tRB
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RL78 Microcontroller
(c) Reset
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
command/Block
Erase
command/Block
Blank
Check
command/Baud
Rate
Set
command/Security Release command
(d) Verify command/Security Set command
Single-wire UART
Command
frame
Data
frame
Data
frame (1)
Status
frame (1)
Data
frame (n 1)
Status
frame (n 1)
Data
frame (n)
Next
command
frame
Status
frame (n)
TOOL0 (output)
TOOL0 (input)
tCS2, 7
tSD2, 7
tDS2, 7
tDS2, 7
Two-wire UART
Command
frame
Data
frame
Data
frame (1)
Status
frame (1)
Data
frame (n 1)
tSD2, 7
Status
frame (n 1)
tDS2, 7
Data
frame (n)
tSN2, 7
Next
command
frame
Status
frame (n)
TOOLTxD
TOOLRxD
tCS2, 7
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tSD2, 7
tDS2, 7
tDS2, 7
tSD2, 7
tDS2, 7
tSN2, 7
Page 85 of 90
RL78 Microcontroller
RL78 Microcontroller (RL78 Protocol A) Programmer Edition
(e) Programming command
Single-wire UART
Status
frame
Command
frame
Data
frame (1)
Status
frame (1)
Data
frame (n 1)
Data
frame (n)
Status
frame (n 1)
Last
status
frame
Status
frame (n)
Next
command
frame
TOOL0 (output)
TOOL0 (input)
tCS5
tSD5
tDS5
tDS5
Two-wire UART
Status
frame
Command
frame
Data
frame (1)
Status
frame (1)
Data
frame (n 1)
tSD5
Status
frame (n 1)
tDS5
Data
frame (n)
tSS5
tSN5
Last
status
frame
Status
frame (n)
Next
command
frame
TOOLTxD
TOOLRxD
tCS5
tSD5
tDS5
tDS5
tSD5
tDS5
tSS5
tSN5
(f) Security Get command/Check Sum command/Signature command
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RL78 Microcontroller (RL78 Protocol A) Programmer Edition
Website and Support
Renesas Electronics Website
http://www.renesas.com/
Inquiries
http://www.renesas.com/inquiry
R01AN0815EJ0100 Rev. 1.00
Nov 7, 2011
Page 87 of 90
Revision Record
Rev.
Date
Description
Page
1.00
Nov. 7, 2011
−
Summary
First edition issued
All trademarks and registered trademarks are the property of their respective owners.
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
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technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
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You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5.
When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
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assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
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The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
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You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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Colophon 1.1