To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. HAF2021(L), HAF2021(S) Silicon N Channel MOS FET Series Power Switching REJ03G0179-0200Z (Previous ADE-208-1459A(Z)) Rev.2.00 Mar.05.2004 Description This FET has the over temperature shut–down capability sensing to the junction temperature. This FET has the built–in over temperature shut–down circuit in the gate area. And this circuit operation to shut–down the gate voltage in case of high junction temperature like applying over power consumption, over current etc. Features • • • • Logic level operation (6 V Gate drive) High endurance capability against to the short circuit Built–in the over temperature shut–down circuit Latch type shut–down operation (Need 0 voltage recovery) Outline D LDPAK 4 4 1. Gate 2. Drain 3. Source 4. Drain Gate resistor G Temperature Sensing Circuit Latch Circuit 1 Gate Shut-down Circuit 1 S Rev.2.00, Mar.05.2004, page 1 of 8 2 3 2 3 HAF2021(L), HAF2021(S) Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Drain to source voltage Gate to source voltage Gate to source voltage Drain current VDSS VGSS VGSS ID 60 16 –2.5 50 V V V A Drain peak current Body-drain diode reverse drain current Channel dissipation Channel temperature Storage temperature ID(pulse)Note1 IDR Pch Note2 Tch Tstg 100 50 100 150 –55 to +150 A A W °C °C Notes: 1. PW ≤ 10µs, duty cycle ≤ 1 % 2. Value at Ta = 25°C Typical Operation Characteristics Item Symbol Min Typ Max Unit Input voltage VIH VIL IIH1 IIH2 IIL IIH(sd)1 IIH(sd)2 Tsd VOP 3.5 — — — — — — — 3.5 — — — — — 0.6 0.35 175 — — 1.2 100 50 1 — — — 12 V V µA µA µA mA mA °C V Input current (Gate non shut down) Input current (Gate shut down) Shut down temperature Gate operation voltage Rev.2.00, Mar.05.2004, page 2 of 8 Test Conditions Vi = 6 V, VDS = 0 Vi = 3.5 V, VDS = 0 Vi = 1.2 V, VDS = 0 Vi = 6 V, VDS = 0 Vi = 3.5 V, VDS = 0 Channel temperature HAF2021(L), HAF2021(S) Electrical Characteristics (Ta = 25°C) Item Symbol Min Typ Max Unit Test Conditions Drain current Drain current Drain to source breakdown voltage Gate to source breakdown voltage Gate to source breakdown voltage Gate to source leak current ID1 ID2 V(BR)DSS V(BR)GSS V(BR)GSS IGSS1 IGSS2 IGSS3 IGSS4 IGS(op)1 IGS(op)2 IDSS VGS(off) |yfs| RDS(on) 90 — 60 16 –2.5 — — — — — — — 2.2 15 — — — — — — — — — — 0.6 0.35 — — 50 8 — 10 — — — 100 50 1 –100 — — 10 3.4 — 12 A mA V V V µA µA µA µA mA mA µA V S mΩ VGS = 6 V, VDS = 10 V VGS = 1.2 V, VDS = 10 V ID = 10 mA, VGS = 0 IG = 300 µA, VDS = 0 IG = –100 µA, VDS = 0 VGS = 6 V, VDS = 0 VGS = 3.5 V, VDS = 0 VGS = 1.2 V, VDS = 0 VGS = –2.4 V, VDS = 0 VGS = 6 V, VDS = 0 VGS = 3.5 V, VDS = 0 VDS = 60 V, VGS = 0 ID = 1 mA, VDS = 10 V ID = 25 A, VDS = 10 V Note3 ID = 25 A, VGS = 10 V Note3 Static drain to source on state resistance RDS(on) — 9.5 15 mΩ ID = 25 A, VGS = 6 V Note3 Output capacitance Turn-on delay time Rise time Turn-off delay time Fall time Body–drain diode forward voltage Body–drain diode reverse recovery time Coss td(on) tr td(off) tf VDF trr — — — — — — — 1450 20 75 3 2.6 0.9 110 — — — — — — — pF µs µs µs µs V ns VDS = 10 V , VGS = 0, f = 1 MHz ID = 25 A, VGS = 10 V RL = 1.2 Ω Over load shut down operation time Note4 tos — 0.8 — ms VGS = 6 V, VDD = 16 V Input current (shut down) Zero gate voltage drain current Gate to source cutoff voltage Forward transfer admittance Static drain to source on state resistance Notes: 3. Pulse test 4. Including the junction temperature rise of the over loaded condition. Rev.2.00, Mar.05.2004, page 3 of 8 IF = 50 A, VGS = 0 IF = 50 A, VGS = 0 diF/ dt =50 A/µs HAF2021(L), HAF2021(S) Main Characteristics Power vs. Temperature Derating (A) 100 50 50 100 150 100 8V DC 20 PW Op er 10 1 = at 5 ion Operation in this area 0.3 µs m s 10 m s (T c= 2 is limited by R DS(on) 1 0.5 Ta = 25°C 200 0 25 °C ) 0.5 1 2 5 10 20 50 100 Drain to Source Voltage VDS (V) Tc (°C) Typical Transfer Characteristics 50 Pulse Test VDS = 10 V Pulse Test 40 6V (A) 80 50 Typical Output Characteristics 10 V 10 100 Drain Current ID Pch (W) Channel Dissipation 150 Case Temperature 60 Drain Current ID (A) Thermal shut down Operation Area 200 0 Drain Current ID Maximum Safe Operation Area 500 200 40 20 30 Tc = -25°C 20 25°C 75°C 10 4V VGS = 3.5 V 2 4 6 Drain to Source Voltage Drain to Source Saturation Voltage VDS(on) (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage 0.8 Pulse Test 0.6 ID = 50 A 0.4 25 A 0.2 10 A 0 2 4 6 Gate to Source Voltage Rev.2.00, Mar.05.2004, page 4 of 8 0 8 10 VDS (V) 8 VGS 10 (V) Drain to Source On State Resistance RDS(on) (mΩ) 0 2 4 6 Gate to Source Voltage VGS (V) 8 Static Drain to Source State Resistance vs. Drain Current 50 20 VGS = 6 V 10 VGS = 10 V 5 2 Pulse Test 1 1 2 5 10 20 Drain Current ID 50 100 200 (A) Static Drain to Source State Resistance vs. Temperature 25 Pulse Test 20 25 A, 10 A 15 10 VGS = 6 V ID = 50 A 25 A, 10 A 5 0 -25 VGS = 10 V 0 25 50 75 100 125 150 Case Temperature Tc (°C) Body to Drain Diode Reverse Recovery Time 1000 di / dt = 50 A / µs VGS = 0, Ta = 25°C 500 200 100 50 VDS = 10 V 50 Pulse Test Tc = -25°C 20 10 5 25°C 2 1 75°C 0.5 0.2 0.1 0.1 0.5 1 5 10 Drain Current ID (A) 500 VGS = 10 V, VDD = 30 V PW = 300 µs, duty < 1 % 200 100 tr 50 td(on) 20 10 td(off) 5 tf 2 1 50 1 0.5 1 2 5 10 20 50 100 Reverse Drain Current IDR (A) Reverse Drain Current vs. Source to Drain Voltage 50 100 Switching Characteristics 20 10 5 10 Drain Current 50 100 ID (A) 500 Typical Capacitance vs. Drain to Source Voltage 10000 Pulse Test Capacitance C (pF) Reverse Drain Current IDR (A) 100 1000 Switching Time t (µs) Reverse Recovery Time trr (ns) ID = 50 A Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Drain to Source On State Resistance RDS(on) (mΩ) HAF2021(L), HAF2021(S) 40 30 0, -5 V 20 VGS = 5 V Coss 1000 100 10 0 VGS = 0 f = 1 MHz 10 0.4 0.8 1.2 Source to Drain Voltage Rev.2.00, Mar.05.2004, page 5 of 8 1.6 VSD 2.0 (V) 0 10 20 30 40 Drain to Source Voltage VDS 50 (V) HAF2021(L), HAF2021(S) Shutdown Case Temperature vs. Gate to Source Voltage 10 8 200 V DD= 16 V 6 4 2 0 0.0001 0.001 0.1 0.01 Shutdown Time of Load-Short Test Shutdown Case Temperature Tc (°C) VGS 12 Gate to Source Voltage (V) Gate to Source Voltage vs. Shutdown Time of Load-Short Test 180 160 140 120 I D= 5 A 100 0 2 Pw (S) 4 6 Gate to Source Voltage 8 10 VGS (V) Normalized Transient Thermal Impedance γs (t) Normalized Transient Thermal Impedance vs. Pulse Width 3 Tc = 25°C 1 D=1 0.3 0.5 0.2 0.1 0.03 θ ch- c(t) = γ s (t) • θ ch- c θ ch- c = 1.25°C/W, Tc = 25°C 0.1 0.02 1 0.0 t ho PDM D= lse PW pu T 1s 0.01 10 µ PW T 100 µ 1m 10 m 100 m 1 10 Pulse Width PW (S) Switching Time Test Circuit Waveform Vout Monitor Vin Monitor 90% D.U.T. RL Vin 50Ω 10 V V DD = 30 V Vin Vout 10% 10% 90% td(on) Rev.2.00, Mar.05.2004, page 6 of 8 tr 10% 90% td(off) tf HAF2021(L), HAF2021(S) Package Dimensions As of January, 2003 Unit: mm 8.6 ± 0.3 11.3 ± 0.5 0.3 10.0 +– 0.5 (1.4) 4.44 ± 0.2 10.2 ± 0.3 1.3 ± 0.15 1.3 ± 0.2 1.37 ± 0.2 0.76 ± 0.1 2.54 ± 0.5 2.54 ± 0.5 2.49 ± 0.2 11.0 ± 0.5 0.2 0.86 +– 0.1 0.4 ± 0.1 Package Code JEDEC JEITA Mass (reference value) LDPAK (L) — — 1.40 g As of January, 2003 Unit: mm (1.5) 10.0 2.49 ± 0.2 0.2 0.1 +– 0.1 7.8 7.0 + 0.3 – 0.5 8.6 ± 0.3 (1.5) 7.8 6.6 1.3 ± 0.15 1.7 (1.4) 4.44 ± 0.2 10.2 ± 0.3 2.2 1.37 ± 0.2 2.54 ± 0.5 0.2 0.86 +– 0.1 2.54 ± 0.5 0.4 ± 0.1 0.3 3.0 +– 0.5 1.3 ± 0.2 Package Code JEDEC JEITA Mass (reference value) Rev.2.00, Mar.05.2004, page 7 of 8 LDPAK (S)-(1) — — 1.30 g HAF2021(L), HAF2021(S) Ordering Information Part Name Quantity Shipping Container HAF2021-90L HAF2021-90S HAF2021-90STL HAF2021-90STR Max:50pcs/sack Max:50pcs/sack 1000pcs/Reel 1000pcs/Reel sack sack Embossed tape Embossed tape Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.2.00, Mar.05.2004, page 8 of 8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. 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