DM164 Version : A.003 Issue Date : 2011/05/18 File Name : SP-DM164-A.03.doc Total Pages : 31 8x3-CHANNEL CONSTANT CURRENT LED DRIVER 新竹市科學園區展業一路 9 號 7 樓之 1 SILICON TOUCH TECHNOLOGY INC. 9-7F-1, Prosperity Road I, Science Based Industrial Park, Hsin-Chu, Taiwan 300, R.O.C. Fax：886-3-5645626 Tel：886-3-5645656 DM164 DM164 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS General Description The DM164 is a LED current sink driver incorporating independent shift registers and data latches for grayscale PWM data (GD mode*1) and current adjustment data (D&G mode*1), 8x3-channels constant current circuitry with current value set by 3 external resistors, 65,536 grayscale PWM function unit, 128 levels current adjustment for each channel and 256 levels global brightness control (White balance). Each channel provides maximum current of 90mA. The DM164 also supports the LED open detection capability, thermal alarm and shutdown function. There are two methods to communicate error signals to the system. One is through serial output data to indicate which channel has failure. The other is by means of dedicated Alarm pin. Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Constant current outputs with current value set by 3 external resistors. Max PWM clock frequency Cascade: 36MHz@VDD=3.3V(Refresh rate≒550Hz), 40MHz@VDD=5V (610Hz) Max data clock frequency Cascade: 30MHz@VDD=3.3V, 35MHz@VDD=5V Maximum output current: 90mA Maximum output voltage: 17V 16-bit grayscale for each LED 8-bit current adjustment for global brightness control (White Balance) 7-bit current adjustment for each LED (Dot Correction) Supply Voltage: 3V to 5.5V LED Open Detection Thermal Alarm and Shutdown Alarm (junction temperature >130oC) Shutdown (junction temperature > 170oC) One-Shot Option Built-in Buffer for Data, PWM Clock, Latch signal and Data Clock Average Separate IOUT PWM Waveform Option Package z LQFP48 (7mmX7mm), QFN48 (7mmX7mm) *1: See Page 10 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 1 DM164 Block Diagram IOUT0 ALARM IOUT1 IOUT23 ‧‧‧ EN_B EN_B T130 Open Detection Thermal Alarm / Shutdown REXT_R Constant Current Driver Constant Current Reference REXT_G REXT_B Open Detection Constant Current Driver Delay00 Global G 8-bit DA Global R 8-bit DA Dot Correction 7-bit DA Global G Latch 8 15 Global R Latch 16 23 Dot Correction Latch 24 30 Global B 8-bit DA EN_B ONEST 16-bit counter GCK 16-bit PWM Generator Open Detection ‧‧‧ Constant Current Driver ‧‧‧ Delay01 ‧‧‧ Dot Correction 7-bit DA 16-bit PWM Generator Delay23 Dot Correction 7-bit DA ‧‧‧ 16 Global B Latch 0 7 0 Data Latch 15 Data Latch Dot Correction Latch 31 37 16 Data Latch Dot Correction Latch 185 191 ‧‧‧ 31 365 383 192 LTH 0 DCKPH Shift Register 191 384 GCK MSEL DIN 0 GCKO 0 1 DCK 16-bit PWM Generator 1 0 PWM Data Shift Register 383 DOUT 1 0 DCKO LTHO DOUTPH DISSIPATION RATINGS PACKAGE QFN48 LQFP48 POWER DISSIPATION (Tj_max=150 oC) 4.00 W 2.16 W THERMAL RESISTANCE (Rja, Ta=25oC) 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS 31.22 57.86 o o C/W C/W Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 2 DM164 Pin Description MSEL LTHO DCKO DOUT 39 38 37 VSS4 43 40 GCK 44 VSS3 VDD2 45 GCKO LTH 46 41 DCK 47 42 DIN 48 LQFP48 (Top View) IOUT20 27 IOUT21 IOUT1 11 26 IOUT22 IOUT0 12 25 IOUT23 ALARM REXT_B REXT_G REXT_R 24 28 10 23 9 IOUT2 DOUT IOUT3 37 IOUT19 22 29 DCKO 8 38 IOUT4 21 IOUT18 LTHO 30 MSEL 7 39 IOUT5 40 IOUT17 20 31 19 6 VSS2 IOUT6 ONEST IOUT16 GCKO 32 41 5 18 IOUT7 VSS1 IOUT15 VSS3 33 VSS4 4 42 IOUT8 43 IOUT14 17 34 IWAVE 3 GCK IOUT9 16 IOUT13 VDD1 35 15 2 DOUTPH IOUT10 14 IOUT12 DCKPH 36 13 1 EN_B IOUT11 DIN DCK LTH VDD2 48 47 46 45 44 QFN48 (Top View) 9 28 IOUT20 IOUT2 10 27 IOUT21 IOUT1 11 26 IOUT22 IOUT0 12 25 IOUT23 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS 24 IOUT3 ALARM IOUT19 23 29 REXT_B 8 22 IOUT4 21 IOUT18 REXT_R IOUT17 30 REXT_G 31 7 20 6 IOUT5 ONEST IOUT6 19 IOUT16 18 32 VSS2 5 VSS1 IOUT7 17 IOUT15 IWAVE IOUT14 33 16 34 4 VDD1 3 IOUT8 15 IOUT9 DOUTPH IOUT13 14 IOUT12 35 DCKPH 36 2 13 1 IOUT10 EN_B IOUT11 Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 3 DM164 PIN NAME FUNCTION VDD1,VDD2 Power supply terminal. VSS1~4 Ground terminal. External resistor connected between REXT and GND for driver current setting. REXT_R REXT_R controls outputs: IOUT0, 3, 6, 9, 12, 15, 18, 21. REXT_G REXT_G controls outputs: IOUT1, 4, 7, 10, 13, 16, 19, 22. REXT_B REXT_B controls outputs: IOUT2, 5, 8, 11, 14, 17, 20, 23. LED driver outputs. IOUT12~23 LED driver outputs. DIN Serial input for grayscale PWM data and current adjustment data. Serial output for grayscale PWM data and current adjustment data. Synchronous clock input for serial data transfer. The input data of DIN can be transferred at either the rising edges of DCK or the falling edges of DCK depending on the signal DCKPH. Synchronous clock output for serial data transfer. DCKO= DCK . When DCKPH = L, input data is shifted in by rising edge of DCK, When DCKPH = H, input data is shifted in by falling edge of DCK When DOUTPH = H, DOUT is shifted out with half DCK cycle delay When DOUTPH = L, DOUT is shifted out without delay Data latch input pin. When DCKPH=L & LTH=H or DCKPH=H & LTH=L, internal latches become transparent and PWM counter value will be set to FFFF(h). When DCKPH=L & LTH=L or DCKPH=H & LTH=H, internal latches hold data. DCK DCKO DCKPH DOUTPH LTH 21 22 23 12,11,10,9,8,7, 6,5,4,3,2,1 36,35,34,33,32,31 30,29,28,27,26,25 IOUT0~11 DOUT QFN48 / LQFP48 pin number 16,45 18,19,42,43 48 37 47 38 14 15 46 LTHO Data latch output pin. LTHO= LTH 39 GCK Clock input for PWM operation. When DCKPH=L (DCKPH=H), the internal PWM counter will count up with rising (falling) edge of GCK. 44 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 4 DM164 GCKO EN_B MSEL ALARM IWAVE ONEST GCKO= GCK Clock output. 41 Blank all outputs. When EN_B = H, all outputs are forced OFF. When EN_B = L, all outputs are controlled by grayscale PWM control. When MSEL = H, the device is operated in Dot Correction Data & Global Brightness Control Data Input Mode (D&G mode). When MSEL = L, the device is operated in Grayscale PWM Data Input Mode (GD mode). Output open drain terminal for an alarm function. when EN_B = L, It will go low as LED open when EN_B = H, It will go low as chip overheated. When IWAVE = H, traditional Iout waveform. When IWAVE = L, average separate Iout waveform. When ONEST = H, one-shot function is enabled. When ONEST = L, one-shot function is disabled. 13 40 24 17 20 Maximum Ratings (Ta=25°C, Tj(max) = 150°C) CHARACTERISTIC SYMBOL Supply Voltage Input Voltage Output Current Output Voltage DCK Frequency FDCK GCK Frequency FGCK GND Terminal Current Power Dissipation Thermal Resistance Operating Temperature Storage Temperature VDD VIN IOUT VOUT RATING UNIT -0.3 ~ 7.0 -0.3 ~ VDD+0.3 90 -0.3 ~ 17 Cascade Vdd=5V 35 Vdd=3.3V Cascade Vdd=5V 40 Vdd=3.3V IGND PD Rth(j-a) Top Tstg V V mA V MHz 30 36 MHz 2200 4.00 ( QFN48); 2.16 (LQFP48) (Ta=25°C) 31.22 ( QFN48 ); 57.86 (LQFP48) -40 ~ 85 -55 ~ 150 mA W ℃/W ℃ ℃ Recommended Operating Condition DC Characteristics (Ta = 25°C) CHARACTERISTIC Supply Voltage Output Voltage Output Current Input Voltage SYMBOL CONDITION VDD VOUT IO IOH IOL VIH ⎯ ⎯ OUTn SERIAL-OUT SERIAL-OUT ⎯ 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS MIN. TYP. MAX. UNIT 3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 5.5 17 90 V V ⎯ ⎯ mA VDD+0.2 V ⎯ ⎯ ⎯ ⎯ 0.7 VDD Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 5 DM164 VIL ⎯ -0.2 ⎯ 0.3 VDD AC Characteristics (VDD = 5.0 V, Ta = 25°C, REXT = 3.9kΩ) CHARACTERISTIC DCK Frequency DCK pulse duration DCK rise/fall time GCK Frequency GCK pulse duration GCK rise/fall time SYMBOL CONDITION MIN. TYP. MAX. UNIT FDCK ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 13 5 ⎯ 12 5 35 ⎯ ⎯ 40 ⎯ Trgk/ Tfgk Cascade operation High or low level Single, CLoad=13pF Cascade operation High or low level Single, CLoad=13pF ⎯ MHz ns ns MHz ns ns Set-up Time for DIN Tsu0 Before DCK rising edge ⎯ 10 ⎯ ns Hold Time for DIN Th0 After DCK rising edge ⎯ 10 ⎯ ns Twhdk / Twldk Trdk/ Tfdk FGCK Twhgk / Twlgk Tsu1 Before LTH falling edge ⎯ 30 ⎯ ns TwLTH ⎯ ⎯ 15 ⎯ ns Set-up Time for LTH Tsu2 Before GCK rising edge ⎯ 10 ⎯ ns Set-up Time for MSEL Tsu3 Before DCK rising edge ⎯ 10 ⎯ ns Hold Time for MSEL Th3 After DCK rising edge ⎯ 30 ⎯ ns Set-up Time for DCK LTH Pulse Width AC Characteristics (VDD = 3.3 V, Ta = 25°C, REXT = 3.9kΩ) CHARACTERISTIC DCK Frequency DCK pulse duration DCK rise/fall time GCK Frequency GCK pulse duration GCK rise/fall time SYMBOL CONDITION MIN. TYP. MAX. UNIT FDCK ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 15 4 ⎯ 13 4 30 ⎯ ⎯ 36 ⎯ ⎯ MHz ns ns MHz ns ns Trgk/ Tfgk Cascade operation High or low level Single, CLoad=13pF Cascade operation High or low level Single, CLoad=13pF Set-up Time for DIN Tsu0 Before DCK rising edge ⎯ 10 ⎯ ns Hold Time for DIN Th0 After DCK rising edge ⎯ 10 ⎯ ns Twhdk / Twldk Trdk/ Tfdk FGCK Twhgk / Twlgk Tsu1 Before LTH falling edge ⎯ 30 ⎯ ns TwLTH ⎯ ⎯ 15 ⎯ ns Set-up Time for LTH Tsu2 Before GCK rising edge ⎯ 10 ⎯ ns Set-up Time for MSEL Tsu3 Before DCK rising edge ⎯ 10 ⎯ ns Hold Time for MSEL Th3 After DCK rising edge ⎯ 30 ⎯ ns Set-up Time for DCK LTH Pulse Width See Page 9: Timing Diagram 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 6 DM164 Electrical Characteristics (VDD = 5.0 V, Ta = 25°C unless otherwise noted) CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. Input Voltage “H” Level Input Voltage “L” Level Output Leakage Current VIH VIL Ileak ⎯ ⎯ 0.7 VDD GND VDD 0.3 VDD ± 0.1 Output Voltage ( DOUT) VOL VOH ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ V Output Current (Channel-Channel) IOL1 ⎯ ±1 ±3 % Output Current (Chip-Chip) IOL3 ⎯ ⎯ ±6 % Output Voltage Regulation % / Vout ⎯ ± 0.1 ± 0.5 %/V 13 mA IDD, analog 1 Supply Current ⎯ ⎯ VOUT = 17 V IOL = 2 mA IOH = -2 mA VOUT = 1.0V REXT = 3.9kΩ VOUT = 1.0V REXT = 3.9kΩ REXT = 3.9kΩ Vout = 1.0~3.0V VDD=5.0V, REXT = 3.9kΩ , REXT = 1.4kΩ VDD=3.3V, REXT = 3.9kΩ , REXT = 1.4kΩ Cload=2pF, IDD, digital DCK=GCK=10MHz VDD=5.0V VDD=3.3V UNIT V uA ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2.4 1.8 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ MIN. TYP. MAX. UNIT ⎯ 5 10 ns ⎯ 5 10 ns ⎯ 8 30 ns ⎯ 8 30 ns 34 12 33 Switching Characteristics (VDD = 5.0V, Ta = 25°C) CHARACTERISTIC SYMBOL DOUT Rise time tr DOUT Fall time tf IOUT Rise time tr IOUT Fall time tf CONDITION VIH=VDD VIL=GND REXT=3.9kΩ CL=13pF VIH=VDD, VIL=GND REXT=3.9kΩ VLED=5.0V RL=100Ω, CL=33pF 10% to 80% DOUT Tplh0 After DCK rising edge ⎯ 28 ⎯ ns DOUT Tphl0 After DCK rising edge ⎯ 28 ⎯ ns DCKO Tplh1 After DCK falling edge ⎯ 14 ⎯ DCKO Tphl1 After DCK rising edge ⎯ 17 ⎯ ns ns LTHO Tplh2 After LTH falling edge ⎯ 14 ⎯ ns LTHO Tphl2 After LTH rising edge ⎯ 17 ⎯ ns GCKO Tplh3 After GCK falling edge ⎯ 16 ⎯ ns GCKO Tphl3 After GCK rising edge ⎯ 16 ⎯ ns IOUT0 (turn on) Tplh4 After GCK rising edge ⎯ 30 ⎯ ns IOUT0 (turn off) Tphl4 After GCK rising edge ⎯ 31 ⎯ ns IOUT0 (turn on) Tplh5 After EN_B falling edge ⎯ 27 ⎯ ns IOUT0 (turn off) Tphl5 After EN_B rising edge ⎯ 25 ⎯ ns 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 7 DM164 Switching Characteristics (VDD = 3.3V, Ta = 25°C) CHARACTERISTIC SYMBOL DOUT Rise time tr DOUT Fall time tf IOUT Rise time tr IOUT Fall time tf CONDITION VIH=VDD VIL=GND REXT=3.9kΩ CL=13pF VIH=VDD, VIL=GND REXT=3.9kΩ VLED=5.0V RL=100Ω, CL=33pF 10% to 80% MIN. TYP. MAX. UNIT ⎯ 4 10 ns ⎯ 4 10 ns ⎯ 12 30 ns ⎯ 12 30 ns After DCK rising edge ⎯ 35 ⎯ DOUT Tphl0 After DCK rising edge ⎯ 35 ⎯ ns ns DCKO Tplh1 After DCK falling edge ⎯ 21 ⎯ ns DCKO Tphl1 After DCK rising edge ⎯ 19 ⎯ ns LTHO Tplh2 After LTH falling edge ⎯ 20 ⎯ ns DOUT Tplh0 LTHO Tphl2 After LTH rising edge ⎯ 20 ⎯ ns GCKO Tplh3 After GCK falling edge ⎯ 23 ⎯ ns GCKO Tphl3 After GCK rising edge ⎯ 23 ⎯ ns IOUT0 (turn on) Tplh4 After GCK rising edge ⎯ 42 ⎯ ns IOUT0 (turn off) Tphl4 After GCK rising edge ⎯ 41 ⎯ ns IOUT0 (turn on) Tplh5 After EN_B falling edge ⎯ 39 ⎯ ns IOUT0 (turn off) Tphl5 After EN_B rising edge ⎯ 33 ⎯ ns 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 8 DM164 Timing Diagram MODE Twhdk Th3 Tsu3 DCK Tsu0 Th0 Tsu1 DIN TwLTH LTH Tphl1 Tplh1 DCKO Tplh0 Tphl0 DOUT Tphl2 Tplh2 LTHO Tsu2 GCK Tphl3 Tplh3 GCKO Tphl4 Tplh4 IOUT0 (current) Tphl5 Tplh5 EN_B 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 9 DM164 Serial Data Interface The DM164 includes a flexible data transfer interface. The data can be transferred from DIN pin to the shift registers at either the rising edge of DCK or the falling edge of DCK depending on the signal DCKPH. After all data are clocked in, a high level LTH signal can transfer the serial data to the data latches (Level Sensitive). The serial data format can be 192-bit or 384-bit wide, depending on the operating mode of the device. Operating Modes The DM164 has two operating modes depending on the signal MSEL. Table 1 shows the available operating modes. When MSEL = H, the device operates at the D&G mode. D&G mode is used to set dot correction data and global brightness control data after IC power up or any time. When MSEL = L, the device becomes GD mode. GD mode is used to set grayscale PWM data after D&G mode. MSEL H L Table 1. Two Operating Modes MODE Dot Correction Data & Global Brightness Control Data Input Mode (D&G mode) Grayscale PWM Data Input Mode (GD mode) SHIFT REGISTER 192-bit 384-bit D&G Mode Data Format At D&G mode, dot correction data of all channels and global brightness control data of different colors are transferred into the chip at the same time. The complete dot correction data format consists of 24 x 7-bit and the global brightness control data of three different colors consists of 3 x 8-bit. The total shift registers width at D&G mode is 192-bit. All data is clocked in with MSB first. Figure 1 shows the D&G mode data format. MSB 191 IOUT23 DC6 185 ‧‧‧ IOUT23 184 IOUT23 IOUT22 DC0 DC6 31 ‧‧‧ 30 IOUT01 IOUT00 DC0 DC6 IOUT22~IOUT01 ‧‧‧ 24 23 IOUT00 DC0 GB_R7 IOUT00 ‧‧‧ 16 15 GB_R0 GB_G7 GLOBAL_R ‧‧‧ GLOBAL_G LSB 0 8 7 GB_G0 GB_B7 ‧‧‧ GB_B0 GLOBAL_B Figure 1. D&G Mode Data Format (D&G[191:0]) To operate the DM164 in D&G mode, MSEL must be set to high. The shift register width is 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 10 DM164 then set to 192-bit wide. The input data can be transferred at either the rising edge of DCK or the falling edge of DCK by setting DCKPH to L or H. After all data are transferred into the D&G mode shift registers, the D&G mode data can be latched from shift registers to the data latches by a LTH signal at either D&G mode or GD mode. Figure 2 shows the D&G mode data input timing chart. D&G mode DCKPH GD mode GND MSEL DIN D&G[191] DCK D&G[190] 1 D&G[189] 2 D&G[0] 3 GD[383] GD[382] 192 DOUT D&G[191] (DOUTPH=L) DOUT D&G[191] (DOUTPH=H) LTH Figure 2. D&G Mode Data Input Timing Chart GD Mode Data Format At GD mode, the grayscale PWM data will be transferred to the shift registers. The complete grayscale PWM data format consists of 24 x 16-bit. The total shift registers width at GD mode is 384-bit. All grayscale PWM data is clocked in with MSB first. Figure 3 shows the GD mode data format. MSB 383 IOUT 23-15 ‧‧‧ IOUT23 368 IOUT 23-0 367 IOUT 22-15 366 IOUT 22-14 ‧‧‧ 17 IOUT 01-1 16 IOUT 01-0 15 IOUT 00-15 IOUT22 ~ IOUT01 ‧‧‧ LSB 0 IOUT 00-0 IOUT00 Figure 3. GD Mode Data Format (GD[383:0]) When MSEL is set to low, the DM164 enters GD mode. The internal shift registers changes to 384-bit wide. The input data can be transferred at either the rising edge of DCK or the falling edge of DCK by setting DCKPH to L or H. After all data are transferred into the GD mode shift registers, the GD mode data can be latched from shift registers to the data latches by a LTH signal at GD mode only. Figure 4 shows the GD mode data input timing chart. 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 11 DM164 D&G mode GD mode MSEL DIN DCK (DCKPH=L) DCK (DCKPH=H) D&G[0] GD[383]a GD[0]a GD[382]a GD[383]b GD[0]b GD[382]b 192 1 2 384 1 2 384 192 1 2 384 1 2 384 ER[382]a ER[381]a 10 GCK Latencies LTH DOUT GD[383]a (DOUTPH=L) DOUT GD[383]a (DOUTPH=H) ER[383]a ER[383]a ER[382]a ER[0]a ER[0]a Figure 4. GD Mode Data Input Timing Chart Thermal Alarm and Shutdown The DM164 provides a temperature error detection circuit, when EN_B=H and the junction temperature of the IC reaches about 130oC, a T130 signal will change the ALARM pin to low level. At this moment, the system should start up the fan or decrease the output currents to lower the junction temperature. If the system has not any protected circuit, the junction temperature might continue to rise. Once it reaches approximately above 170oC, a T170 signal and a Shutdown signal will cause the driver to shutdown all the outputs, the ALARM pin remains in low level. Basically, the IC will cool down and return to the safe operating temperature approximately below 130oC. When the operating temperature below 130oC, the ALARM pin will reset to high level, disable the warning, and restart all the outputs. Operation in the thermal situation for a long time may cause chip damage permanently. The thermal error signals (T130, T170, Shutdown) can be transferred out from DOUT pin. Normal Normal Alarm 130 C T130 =“L＂ T170 =“L＂ Normal Normal 170 C T130 =“H＂ T170 =“L＂ T130 =“H＂ T170 =“H＂ Alarm Alarm + Shutdowm Figure 5. Thermal Alarm and Shutdown 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 12 DM164 Open Detection If there is any one of the 24 LEDs open or disconnected, the DM164 can detect and report the error. The open detection circuit works when the following two conditions are met simultaneously: 1. IOUTn is on (IOUTn > 200ns and EN_B=”L”). 2. When the output voltage at IOUTn is less than 0.2 V The open error signal (OPE) has two methods to communicate the error signals to the system. One is through serial output data to indicate which channel has failure (OPEn=H => IOUTn is open). The other is by means of dedicated Alarm pin when EN_B=L. Status Information Output When the DM164 operates at GD mode, after the LTH signal latches the input data from shift registers to the data latches, the shift registers data will be replaced by the status information. The status information includes the thermal error signals (Shutdown, T130 and T170,), open error signals (OPE) and dot correction data (DC), which will be transferred out from DOUT pin. Figure 6 shows the status information format. (a. IOUT shut down => Shut down=L, b. Tj>130℃ => T130=H, c. Tj>170℃ => T170=H) MSB 383 DC[6] 23 ... ... 377 376 375 DC[0] OPE 23 23 Shut down 374 T130 373 ... T170 ... 368 367 X DC[6] 22 DC IOUT23 ... ... 361 360 DC[0] OPE 22 22 359 ... X ... DC IOUT22 8-bit 8-bit DC[6] 20 ... ... 327 ... 320 319 DC[0] OPE 20 20 X ... X DC[6] 19 DC IOUT20 Reserved DC[6] 02 ... ... Reserved 343 ... 336 DC[0] OPE 21 21 X ... X DC IOUT21 Reserved ... ... 16-bit 312 311 ... 304 303 DC[0] OPE 19 19 X ... X DC[6] 18 313 Reserved ... ... 296 295 ... 288 DC[0] OPE 18 18 X ... X 297 DC IOUT18 8-bit 41 ... 344 345 8-bit DC IOUT19 8-bit 47 X DC[6] 21 ... 16-bit 328 329 351 8-bit 16-bit 335 352 Reserved 8-bit 16-bit 16-bit 16-bit ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ 40 DC[0] OPE 02 02 DC IOUT02 39 ... X ... Reserved 8-bit 32 31 X DC[6] 01 ... ... 25 24 DC[0] OPE 01 01 DC IOUT01 ... X ... Reserved 8-bit 16-bit 23 16 15 X DC[6] 00 ... ... 9 8 DC[0] OPE 00 00 DC IOUT00 7 ... 0 X ... X Reserved 8-bit 16-bit 16-bit Figure 6. Status Information Data Format (ER[383:0]) 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 13 DM164 In order to catch correct open error signals. DCK must wait for at least 10 GCK latencies after the LTH signal latches the input data. Figure 7 shows the timing chart. GD mode MSEL DIN GND GD[383]a DCK (DCKPH=L) DCK (DCKPH=H) GD[382]a GD[0]a GD[383]b GD[0]b GD[382]b 1 2 384 1 2 384 1 2 384 1 2 384 ER[382]a ER[381]a 10 GCK Latencies LTH GCK DOUT ER[383]a GD[383]a (DOUTPH=L) DOUT GD[383]a (DOUTPH=H) ER[383]a ER[0]a ER[382]a ER[0]a Figure 7. Open Error Signals Timing Chart IOUT Delay & EN_B Delay The DM164 provides delay circuits between IOUTs. All IOUTs are divided into eight groups and every three outputs of different colors form a group. For example, IOUT0 IOUT1 and IOUT2 form the group1; IOUT3 IOUT4 and IOUT5 form the group2. The delay time between every group is half GCK cycle time. Each IOUT delay in the same group is 5ns (typical). Figure 8 shows the IOUT delay timing chart. Besides the iout delay, the EN_B is also associated with GKC signal. When EN_B goes high and GCK keeps going, then each group of IOUTs will turn off one by one depending on the GCK sequence. If EN_B goes high but GCK stops going, then the IOUTs will not turn off normally. LTH GCK IO U T 0 G ro u p 1 1 2 6 H a lf G C K C y c le 5ns IO U T 4 IO U T 2 1 G ro u p 8 5 5ns IO U T 3 IO U T 5 4 5ns IO U T 1 IO U T 2 G ro u p 2 3 1 G C K L a te n c y 5ns . . . . . . 5ns IO U T 2 2 5ns IO U T 2 3 Figure 8. IOUT Delay Timing Chart 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 14 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS IOUT21,22,23 IOUT18,19,20 IOUT15,16,17 IOUT12,13,14 IOUT 9,10,11 IOUT 6, 7, 8 IOUT 3, 4, 5 IOUT 0, 1, 2 EN_B Internal counter GCK LTH DCK DIN 1 GD[383]a 384 GD[0]a 65535 1 2 4.5 GCK Latency 4 GCK Latency 3.5 GCK Latency 3 GCK Latency 2.5 GCK Latency 2 GCK Latency 1.5 GCK Latency 1 GCK Latency 0 3 4 5 Iout Delay & EN_B Delay Waveform 6 7 8 9 1 GD[383]b 65534 384 GD[0]b 65535 0 1 3 3 4 5 DM164 Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 15 DM164 One-Shot Option The DM164 provides an option that users can make the output turn on for just a PWM cycle time, i.e. in the GD mode, after a LTH signal, the output only turn on for 65536 TGCK time. After 65536 TGCK, the output will automatically turn off. This is called One-Shot function. Figure 9 shows the difference between One-Shot or not. When ONEST = H, one-shot function is enabled. The output will just turn on at 1st PWM cycle. When ONEST = L, one-shot function is disabled. The output will repeat at every PWM cycle. GD mode MSEL GND DCKPH GND DIN GD[383] DCK 1 GD[0] 384 LTH GCK Internal counter 65535 0 1 65535 1st PWM cycle 0 1 65535 2nd PWM cycle 0 1 65535 3rd PWM cycle IOUT0 (ONEST=H) IOUT0 (ONEST=L) Figure 9. One-Shot Operation Grayscale PWM Operation When DCKPH=L, the grayscale PWM cycle starts with the falling edge of LTH (see Figure 10). A LTH = H signal will set the 16-bit PWM counter value to FFFFh. The first GCK pulse after LTH increases the PWM counter by one and switches on all IOUT with grayscales value not zero. Each following rising edge of GCK increases the PWM counter by one. The DM164 compare the grayscale PWM value of each output IOUT with grayscale counter value. If the grayscale PWM value is larger than grayscale counter value, the IOUT will switch on. 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 16 DM164 D&G Mode Data Input Cycle 1st GD Mode Data Input Cycle 2nd GD Mode Data Input Cycle MSEL DCK 1 384 1 LTH GCK 16-bit COUNTER ... FF FFh 0 ? FF FFh 0 ? FFFFh FF FFh 0 1 GCK cycle FF FFh 0 0 1 GCK cycle IOUT0 (ONEST=L) IOUT0 (ONEST=H) 65536 GCK cycle < 65536 GCK cycle 65536 GCK cycle Figure 10. Grayscale PWM Operation Maximum Output Current The maximum output current is set by an external resistor. The resistor is connected between Rext and GND. Varying the resistor value can adjust the current scale ranging from 5mA to 90mA. The reference voltage of REXT terminal (Vrext) is approximately 1.23V. The maximum output current (Imax) value can be calculated roughly by the following equation: Vrext (V) Imax ≅ × 64 Rrext (Ω) where: Vrext = 1.23V Rrext = external resistor. Global Brightness Control The global brightness control function can adjust the global current of each color independently. The output current (Iglobal) can be adjusted in 256 steps from ((1/256)*100)% to 100% of the maximum output current. The following equation can calculate the global brightness control current (Iglobal) Iglobal ≅ GB+1 × Imax 256 where: Imax = the maximum output current. GB = the global brightness control value for different colors. 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 17 DM164 Dot Correction Besides global brightness control, the DM164 also has the capability to adjust the output current of each channel IOUT00 to IOUT23 independently. The output current (Idot) can be adjusted in 128 steps from ((1/128)*100) % to 100% of the global brightness control current. The following equation can calculate the dot correction current (Idot) Idot ≅ DC+1 DC+1 GB+1 × Iglobal ≅ × × Imax 128 128 256 where: Iglobal = the global brightness control current DC = the dot correction value for each output. Average Separate IOUT Waveform The DM164 incorporates a different PWM counter, hence the IOUT waveform demonstrate a very different characteristics compare to conventional PWM counter. In the DM164, when IWAVE=”L,” the IOUT waveform is averagely divided into 32(maximum) sections. Figure 11 shows the difference between traditional IOUT waveform and particular IOUT waveform. Traditional IOUT = 2 GCK cycle (2 / 65536)*100% Luminance (IWAVE=＂H＂) Particular t (IWAVE=＂L＂) Traditional IOUT = 4 GCK cycle (4 / 65536)*100% Luminance (IWAVE=＂H＂) Particular IOUT = 8 GCK cycle Traditional (8 / 65536)*100% Luminance (IWAVE=＂H＂) Particular ‧ ‧ ‧ ‧ ‧ ‧ IOUT = 32 GCK cycle ‧ ‧ (32 / 65536)*100% Luminance ‧ Particular (IWAVE=＂H＂) t t (IWAVE=＂L＂) Traditional t t (IWAVE=＂L＂) (IWAVE=＂H＂) t t (IWAVE=＂L＂) Traditional t IOUT = 64 GCK cycle ‧ ‧ ‧ (64 / 65536)*100% Luminance Particular t t (IWAVE=＂L＂) Figure 11. Average Separate IOUT Waveform 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 18 DM164 Output Current vs. External Resistor Output Current Performance vs. Output Voltage 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 19 DM164 Application Diagram a) DCK LTH and GCK signals: Global Connected * Each DCKPH input pin of all chips should be connected to the same voltage level. Figure 12 shows that all DCKPH pins are connected to VSS. Vled ... VDD ... Chip 01 VSS Chip 02 IOUT0 REXT_R IOUT1 REXT_R IOUT1 REXT_G IOUT2 REXT_G IOUT2 REXT_B ‧ ‧ ‧ REXT_B ‧ ‧ ‧ VSS ‧ ‧ ‧ IOUT0 VSS IOUT23 EN_B ‧ ‧ ‧ IOUT0 REXT_R IOUT1 REXT_R IOUT1 REXT_G IOUT2 REXT_G IOUT2 REXT_B ‧ ‧ ‧ REXT_B ‧ ‧ ‧ ‧ ‧ ‧ VSS IOUT23 EN_B ONEST DOUTPH DOUTPH DCKPH ‧ ‧ ‧ IOUT23 EN_B ONEST DOUTPH DCKPH VDD VSS ONEST DOUTPH Chip 04 IOUT0 VDD IOUT23 EN_B ONEST DIN Chip 03 VDD VDD ... ... DCKPH DCKPH GCKI GCKO GCKI GCKO GCKI GCKO GCKI LTHI LTHO LTHI LTHO LTHI LTHO LTHI GCKO LTHO DCKI DCKO DCKI DCKO DCKI DCKO DCKI DCKO DIN DOUT DIN DOUT DIN DOUT DIN DOUT DOUT DCKI LTHI GCKI DOUTPH ONEST EN_B Figure 12. DCK LTH and GCK signals: Global Connected b) DCK LTH and GCK signals: Cascade Connected * DCKPH input pins of odd stages (Chip01, Chip03…) and even stages (Chip02, Chip04…) should be connected to different voltage level. Figure 13 shows that CLKPH pins of odd stages are connected to VSS, and CLKPH pins of even stages are connected to VDD. Vled ... VDD ... Chip 01 VSS Chip 02 Chip 03 Chip 04 VDD IOUT0 VDD IOUT0 VDD IOUT0 VDD IOUT0 REXT_R IOUT1 REXT_R IOUT1 REXT_R IOUT1 REXT_R IOUT1 REXT_G IOUT2 REXT_G IOUT2 REXT_G IOUT2 REXT_G IOUT2 REXT_B ‧ ‧ ‧ REXT_B ‧ ‧ ‧ REXT_B ‧ ‧ ‧ REXT_B ‧ ‧ ‧ VSS EN_B IOUT23 ONEST ‧ ‧ ‧ VSS EN_B ‧ ‧ ‧ IOUT23 ONEST DOUTPH VSS EN_B ‧ ‧ ‧ IOUT23 EN_B ‧ ‧ ‧ IOUT23 DOUTPH DOUTPH DCKPH VSS ONEST ONEST DOUTPH DCKPH GCKI LTHI DCKI DIN ... ... DCKPH DCKPH GCKI GCKO GCKI GCKO GCKI GCKO GCKI GCKO LTHI LTHO LTHI LTHO LTHI LTHO LTHI LTHO DOUT DCKI DCKO DCKI DCKO DCKI DCKO DCKI DCKO DCKO DIN DOUT DIN DOUT DIN DOUT DIN DOUT DOUT GCKO DOUTPH ONEST EN_B Figure 13. DCK LTH and GCK signals: Cascade Connected 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 20 DM164 c) Less Than 16-bit PWM Grayscale Application c.1 IWAVE=”H” and less than 16-bit PWM application When the DM164 operates at n-bit PWM grayscale application and IWAVE is set to ”H” (where n is less than 16). Users must add k-bit dummy data into the 16-bit GD mode data of each channel (where k = 16-n). The 16-bit GD mode data format of each channel is showed below: n-bit PWM Data k-bit Dummy Data 0 0 ‧‧‧ PWM MSB PWM MSB-1 Data [n-1] Data [n-2] k-bit ‧‧‧ PWM LSB+1 PWM LSB Data [1] Data [0] n-bit 16-bit The k-bit MSB of 16-bit GD mode data of each channel must be filled with all “0” ( k=16-n ). For example: When the DM164 operates at 14-bit PWM grayscale application and IWAVE=”H”, the 2-bit MSB of the 16-bit GD mode data must be filled with “0”. The 16-bit data format is showed below: 2-bit Dummy Data 0 0 14-bit PWM Data PWM MSB PWM MSB-1 Data [13] Data [12] 2-bit ‧‧‧ PWM LSB+1 PWM LSB Data [1] Data [0] 14-bit 16-bit Figure 14 shows the timing diagram when the DM164 operates at n-bit PWM grayscale application. The frame cycle of n-bit PWM grayscale application can be controlled by GCK and LTH signals. 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 21 DM164 D&G mode GD mode MSEL DIN DCK (DCKPH=L) DCK (DCKPH=H) D&G[0] GD[383]a GD[0]a GD[382]a GD[383]b GD[382]b GD[0]b 192 1 2 384 1 2 384 192 1 2 384 1 2 384 10 GCK Latencies LTH ... GCK ... 2 n GCK cycles Figure 14. Operating at n-bit PWM Grayscale Application Timing Diagram c.2 IWAVE=”L” and 11~15-bit PWM application When the DM164 operates at n-bit PWM grayscale application and IWAVE is set to ”L” (where n is between 11~15). Users must add k-bit dummy data into the 16-bit GD mode data of each channel (where k = 16-n). The 16-bit GD mode data format of each channel is showed below: n-bit PWM Data PWM MSB PWM MSB-1 Data [n-1] Data [n-2] ‧‧‧ PWM LSB+1 PWM LSB Data [1] Data [0] k-bit Dummy Data 0 0 ‧‧‧ n-bit k-bit 16-bit The k-bit LSB of 16-bit GD mode data of each channel must be filled with all “0” ( k=16-n & k < 6). For example: When the DM164 operates at 14-bit PWM grayscale application and IWAVE=”L”, the 2-bit LSB of the 16-bit GD mode data must be filled with “0”. The 16-bit data format is showed below: 14-bit PWM Data PWM MSB PWM MSB-1 Data [13] Data [12] PWM LSB+1 PWM LSB Data [1] Data [0] ‧‧‧ 14-bit 2-bit Dummy Data 0 0 2-bit 16-bit 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 22 DM164 c.3 IWAVE=”L” and Less than 11-bit PWM application When the DM164 operates at n-bit PWM grayscale application and IWAVE is set to ”L” (where n is less than 11). Users must add k-bit dummy data into the 16-bit GD mode data of each channel (where k = 16-n). The 16-bit GD mode data format of each channel is showed below: n-bit PWM Data (k-5) bits Dummy Data 0 ‧‧‧ 0 PWM MSB PWM MSB-1 Data [n-1] Data [n-2] (k-5)-bit ‧‧‧ PWM LSB+1 PWM LSB Data [1] Data [0] 5 bits Dummy Data 0 n-bit ‧‧‧ 0 5-bit 16-bit The 5 bits LSB and (k-5) bits MSB of 16-bit GD mode data of each channel must be filled with all “0” ( k=16-n & k > 5). For example: When the DM164 operates at 10-bit PWM grayscale application and IWAVE=”L”, the 5-bit LSB and 1-bit MSB of the 16-bit GD mode data must be filled with “0”. The 16-bit data format is showed below: 10-bit PWM Data 1 bit 0 1-bit PWM MSB PWM MSB-1 Data [9] Data [8] PWM LSB+1 PWM LSB Data [1] Data [0] ‧‧‧ 5 bits Dummy Data 0 10-bit ‧‧‧ 0 5-bit 16-bit 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 23 DM164 d) Power-on Reset Suggestion The DM164 doesn’t built-in automatic power-on reset function. In order to make sure the DM164 can work normally after the power-on situation. Users can add an LTH pulse before normal operation, like Figure 15 shows. a. D&G Mode First POWER-ON NORMAL OPERATION VDD D&G Mode GD Mode MSEL DIN D&G[191] DCK (DCKPH=L) DCK At Least 10 GCK Latencies (DCKPH=H) LTH D&G[190] GD[383] GD[382] GD[0] 1 2 192 1 2 384 1 2 192 1 2 384 10 GCK Latencies … GCK D&G[0] … … … … EN_B b. GD Mode First POWER-ON NORMAL OPERATION VDD GD Mode D&G Mode MSEL DIN DCK (DCKPH=L) DCK (DCKPH=H) LTH GCK At Least 10 GCK Latencies … GD[383] GD[382] 1 2 384 1 2 192 1 2 384 1 2 192 GD[0] D&G[191] D&G[0] D&G[190] 10 GCK Latencies … … … … VDD Figure 15. Power-on Reset Suggestion Timing Diagram 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 24 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS 1 192N D&G[191]N_A D&G[191]N_A 1 GD[383]N_A 192N D&G[0]1_A Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. (DOUTPH=H) DOUT (DOUTPH=L) DOUT LTH (DCKPH=H) DCK (DCKPH=L) DCK DIN MSEL 384N 384N 1 1 GD[383]N_A GD[383]N_A GD[383]N_A GD[0]1_A GD Mode of Frame A GD[383]N_A GD[383]N_A 10 GCK Latencies DIN 1 1 2 2 D&G[191]N_A D&G[190]N_A 1[23] D&G[191]N_A D&G[191]N_A 192N 192N 2[23] GD[383]N_A GD[383]N_A D&G[0]1_A D&G[191]N_B ER[383]N_A ER[382]N_A ER[381]N_A 2 2 GD[382]N_B ER[382]N_A 1 1 GD[383]N_B 384N 384N ... n-1[23] ... 2 2 D&G[190]N_A D&G[190]N_A D&G[189]N_A 1 1 D&G[191]N_B D&G[0]1_A D&G[191]N_B 192N 192N D&G[0]1_B GD[383]N_B GD[383]N_B D&G[0]1_A DOUTN GD[383]N_B GD[383]N_B 10 GCK Latencies GD[0]1_B D&G Mode of Frame B D&G[191]N_A D&G[191]N_A 384N 384N ER[0]1_A ER[0]1_A D&G[191]N_B D&G[190]N_B ER[382]N_A ER[381]N_A 2 2 GD[382]N_B n[23] N DM164 n[0] GD Mode of Frame B N-1 DM164 GD[383]N_B GD[383]N_B GD[0]1_B ER[383]N_A ER[0]1_A ER[0]1_A GD Mode of Frame B ER[383]N_A 10 GCK Latencies D&G[190]N_A 1 1 GD[383]N_B ... n-1[0] D&G[191]N_B ER[383]N_A ER[382]N_A 192N 2 D&G[0]1_A 192N D&G[0]1_B 2 D&G[190]N_A D&G[189]N_A 1 1 D&G[191]N_A D&G[191]N_A ... 2 DM164 2[0] D&G Mode of Frame B 1 DM164 ... D&G[191]N_B D&G[190]N_B D&G[0]1_A D&G Mode of Frame A 384N 384N GD[0]1_A GD Mode of Frame A 2. GD Mode First (DOUTPH=H) DOUT (DOUTPH=L) DOUT LTH (DCKPH=H) DCK (DCKPH=L) DCK DIN MSEL D&G Mode of Frame A 1. D&G Mode First 1[0] DM164 Mode Transfer Operation Timing Diagram (N Chip Cascade) Page 25 DM164 Power Dissipation The power dissipation of a semiconductor chip is limited to its package and ambient temperature, in which the device requires the maximum output current calculated for given operating conditions. The maximum allowable power consumption can be calculated by the following equation: Pd(max)(Watt) = Tj(junction temperature)(max)(°C)– Ta(ambient temperature)(°C) Rth(junction-to-air thermal resistance)(°C/Watt) Power Dissipation Pd ( W ) The relationship between power dissipation and operating temperature can be refer to the figure below: QFN48 4.0 Tj(max)=150 oC Rja(QFN48)=31.22 oC/W 3.0 Rja(LQFP48)=57.86 oC/W LQFP48 2.0 1.0 0.0 0 20 40 60 80 100 120 140 o Ambient Temperature Ta ( C ) Based on the Pd(max), the maximum allowable voltage of output terminal can be determined by the following equation: Vout0 x Iout0 x Duty0 + . . . + Vout23 x Iout23 x Duty23 < Pd(max) – VDD x IDD 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 26 DM164 Package Outline Dimension LQFP48 LQFP48 - DIMENSION (mm) SYMBOL MIN. NOM. MAX. SYMBOL A - - 1.600 E 9.000 BSC A1 0.050 - 0.150 E1 7.000 BSC A2 1.350 - 1.450 e 0.500 BSC c1 0.090 - 0.160 b 0.170 - 0.270 0.450 - 0.750 D 9.000 BSC L D1 7.000 BSC L1 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS MIN. NOM. MAX. 1.000 REF Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 27 DM164 QFN48-Saw Type QFN48 - DIMENSION (mm) SYMBOL MIN. NOM. MAX. SYMBOL A 0.700 0.750 0.800 E A1 0.000 0.020 0.050 E2 A3 b 0.203 REF 0.180 D D2 0.250 0.300 5.200 5.300 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS NOM. MAX. 7.000 BSC 5.100 e 7.000 BSC 5.100 MIN. 5.200 5.300 0.500 BSC. k 0.200 - - L 0.300 0.400 0.500 y 0.080 Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 28 DM164 QFN48- Punch Type QFN48 - DIMENSION (mm) SYMBOL MIN. NOM. MAX. SYMBOL MIN. NOM. MAX. A 0.800 0.850 0.900 D2 4.900 5.100 5.300 A1 0.000 0.020 0.050 E 6.900 7.000 7.100 A2 0.650 REF E1 6.650 6.750 6.850 A3 0.203 REF E2 4.900 5.100 5.300 b 0.180 0.250 0.300 e C 0.240 0.420 0.600 K 0.200 - - D 6.900 7.000 7.100 L 0.300 0.400 0.500 D1 6.650 6.750 6.850 θº 0.000 - 12.000 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS 0.500 BSC Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 29 DM164 The products listed herein are designed for ordinary electronic applications, such as electrical appliances, audio-visual equipment, communications devices and so on. Hence, it is advisable that the devices should not be used in medical instruments, surgical implants, aerospace machinery, nuclear power control systems, disaster/crime-prevention equipment and the like. Misusing those products may directly or indirectly endanger human life, or cause injury and property loss. Silicon Touch Technology, Inc. will not take any responsibilities regarding the misusage of the products mentioned above. Anyone who purchases any products described herein with the above-mentioned intention or with such misused applications should accept full responsibility and indemnify. Silicon Touch Technology, Inc. and its distributors and all their officers and employees shall defend jointly and severally against any and all claims and litigation and all damages, cost and expenses associated with such intention and manipulation. Silicon Touch Technology, Inc. reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS Version:A.003 未經授權而逕予重製、複製、使用或公開本文件，行為人得被追究侵權之相關民刑事責任 Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement. Page 30