RENESAS R5F36CAMDFB

To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
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You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
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incurred by you resulting from errors in or omissions from the information included herein.
Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and
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expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”:
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
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damages arising out of the use of Renesas Electronics products beyond such specified ranges.
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specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
M16C/6C Group
RENESAS MCU
1.
REJ03B0277-0100
Rev.1.00
Jul.15, 2009
Overview
1.1
Features
The M16C/6C Group microcomputer (MCU) incorporates the M16C/60 Series CPU core and flash
memory, employing sophisticated instructions for a high level of efficiency. This MCU has 1 MB of address
space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a
multiplier for high-speed operation processing.
This MCU consumes little power, and supports operating modes that allow additional power control. The
MCU also uses an anti-noise configuration to reduce emissions of electromagnetic noise and is designed
to withstand electromagnetic interference (EMI). By integrating many of the peripheral functions, including
the multifunction timer and serial interface, the number of system components has been reduced.
1.1.1
Applications
This MCU can be used in Peripherals (USB applicable), audio components, cameras, televisions,
household appliances, office equipment, communication devices, mobile devices, industrial equipment,
and other applications.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 1 of 90
M16C/6C Group
1.2
1. Overview
Specifications
Table 1.1 to Table 1.2 list specifications.
Table 1.1
Specifications (1/2)
Item
Function
Description
CPU
Central processing unit
Core
((multiplier: 16-bit × 16-bit 32-bit,
multiply and accumulate instruction: 16-bit × 16-bit + 32-bit 32-bit))
• Number of basic instructions: 91
• Minimum instruction execution time: 31.25 ns (f(BCLK) = 32 MHz, VCC1
= VCC2 = 2.7 to 5.5 V)
• Operating modes: Single-chip, memory expansion, and microprocessor
Memory
ROM, RAM, data flash
See “Refer to Table 1.3 “Product List” .”
Voltage
Detection
Voltage detector
• Power-on reset
• 3 voltage detection points (detection level of voltage detection 0
selectable)
• 5 circuits:
Clock
Clock generator
External Bus
Bus memory expansion
Expansion
Main clock, sub clock, low-speed on-chip oscillator (125 kHz), high-speed
on-chip oscillator (40 MHz ± 10%), PLL frequency synthesizer
• Oscillation stop detection: Main clock oscillation stop/reoscillation
detection function
• Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16
• Power saving features: Wait mode, stop mode
• Real-time clock
• Address space: 1 MB
• External bus interface: 0 to 3 wait states, 4 chip select outputs, 3 V and 5 V
interfaces
• Bus format: Separate bus or multiplexed bus selectable, data bus width (8
bits), number of address buses(12, 16, or 20)
I/O Ports
Programmable I/O ports
Interrupts
Watchdog Timer
DMA
DMAC
• CMOS I/O ports: 85 (selectable pull-up resistors)
• N-channel open drain ports: 3
• Interrupt vectors: 70
• External interrupt inputs: 13 (NMI, INT × 8, key input × 4)
• Interrupt priority levels: 7
15-bit timer × 1 (with prescaler)
Automatic reset start function selectable
• 4 channels, cycle steal mode
• Trigger sources:55
• Transfer modes: 2 (single transfer, repeat transfer)
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 2 of 90
M16C/6C Group
1. Overview
Table 1.2
Specifications (2/2)
Item
Function
Timer A
Timer B
Timers
Three-phase motor control
timer functions
Real-time clock
Timer S (Input capture/output
compare)
Serial
Interface
UART0 to UART5
Multi-master I2C-bus Interface
Description
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse width
modulation (PWM) mode
Event counter two-phase pulse signal processing (two-phase encoder
input) × 3
Programmable output mode × 3
16-bit timer × 6
Timer mode, event counter mode, pulse period measurement mode,
pulse width measurement mode
• Three-phase inverter control (timer A1, timer A2, timer A4, timer B2)
• On-chip dead time timer
• Count: second, minute, hour, day of the week
• Input base timer: 16 bits X 1
• I/O: 8 channels
• Time measurement register, Waveform generation register: 16 bits X
8
Clock synchronous/asynchronous × 6 channels
I2C-bus, IEBus(1),
Special mode 2, SIM (UART2)
1 channel
• Full speed (12 Mbps, USB 2.0 compliant)
• Transfer type: Control IN/OUT, Bulk IN X 2, Bulk OUT X 2,
USB Functions
A/D Converter
D/A Converter
CRC Calculator
Flash Memory
Interrupt IN X 2
• FIFO size: 584 bytes
• Setup 8 bytes
• Control IN 16 bytes
• Control OUT 16 bytes
• Interrupt IN 16 bytes: 2 channels
• Bulk IN 64 bytes X 2: 2 channels
• Bulk OUT 64 bytes X 2: 2 channels
10-bit resolution × 26 channels (2 circuits), including sample and hold
function
Conversion time: 1.72 μs
8-bit resolution × 2 circuits
CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1)
compliant
• Program/erase power supply voltage: 2.7 to 5.5 V
• Program/erase cycles: 1,000 times (program ROM 1, program ROM
2), or 10,000 times (data flash)
• Program security: ROM code protect, ID code check
Debug Functions
Operation Frequency/Supply Voltage
Current Consumption
Operating Temperature
Package
On-chip debug, on-board flash rewrite, address match interrupt × 4
32 MHz/VCC1 = 2.7 to 5.5 V, VCC2 = 2.7 V to VCC1
27 mA (32 MHz/VCC1 = VCC2 = 3 V)
2.0 μA(VCC1 = VCC2 = 3 V (in stop mode)
-20°C to 85°C, -40°C to 85°C (2),
100-pin QFP: PRQP0100JD-B (Previous package code: 100P6F-A)
100-pin LQFP: PLQP0100KB-A (Previous package code: 100P6Q-A)
Notes:
1. IEBus is a registered trademark of NEC Electronics Corporation.
2. Refer to Table 1.2 “Specifications (2/2)” and Table 1.3 “Product List”regarding operating temperature.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 3 of 90
M16C/6C Group
1.3
1. Overview
Product List
Table 1.3 lists product information. Figure 1.1 shows the Part No. with Memory Size and Package, and
Figure 1.2 shows the Marking Diagram (Top View).
Table 1.3
Product List
Part No.
R5F36CAMNFA
R5F36CAMNFB
(P)
(D)
R5F36CAMDFA
R5F36CAMDFB
(P)
(D)
R5F36CAKNFA
R5F36CAKNFB
(P)
(P)
R5F36CAKDFA
R5F36CAKDFB
(P)
(P)
R5F36CAENFA
R5F36CAENFB
(P)
(P)
R5F36CAEDFA
R5F36CAEDFB
(P)
(P)
R5F36CA6NFA
R5F36CA6NFB
(P)
(P)
R5F36CA6DFA
R5F36CA6DFB
(P)
(P)
Program
ROM 1
512KB
ROM Capacity
Program
Data flash
ROM 2
16KB
4KB
×2 blocks
RAM
Capacity
31KB
384KB
16KB
4KB
×2 blocks
31KB
256KB
16KB
4KB
×2 blocks
20KB
128KB
16KB
4KB
×2 blocks
12KB
(D): Under development
(P): Planning
Note:
1. Previous package codes are as follows:
PRQP0100JD-B: 100P6F-A
PLQP0100KB-A: 100P6Q-A
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 4 of 90
Package Code
Remarks
PRQP0100JD-B Operating
temperature
PLQP0100KB-A
-20°C to 85°C
PRQP0100JD-B Operating
temperature
PLQP0100KB-A -40°C to 85°C
PRQP0100JD-B Operating
temperature
PLQP0100KB-A
-20°C to 85°C
PRQP0100JD-B Operating
temperature
PLQP0100KB-A -40°C to 85°C
PRQP0100JD-B Operating
temperature
PLQP0100KB-A
-20°C to 85°C
PRQP0100JD-B Operating
temperature
PLQP0100KB-A -40°C to 85°C
PRQP0100JD-B Operating
temperature
PLQP0100KB-A
-20°C to 85°C
PRQP0100JD-B Operating
temperature
PLQP0100KB-A -40°C to 85°C
M16C/6C Group
1. Overview
Part No.
R 5 F 3
6 CA
M D
FB
Package type
FA: Package PRQP0100JD-B (100P6F-A)
FB: Package PLQP0100KB-A (100P6Q-A)
Property Code
D: Operating temperature: -40°C to 85°C
N: Operating temperature: -20°C to 85°C
Memory capacity
Program ROM 1/RAM
M: 512 KB/31 KB
K: 384 KB/31KB
E: 256 KB/20 KB
6: 128 KB/12 KB
M16C/6C Group
16-bit MCU
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part No. with Memory Size and Package
M1 6 C
R 5 F 3 6 C A MD F B
XXXXXXX
Figure 1.2
Marking Diagram (Top View)
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 5 of 90
Type No. (See Figure 1.1 Part No., Memory Size, and Package.)
Seven digit date code
M16C/6C Group
1.4
1. Overview
Block Diagram
Figure 1.3 shows block diagrams.
8
Port P0
8
Port P1
8
8
Port P2
8
Port P3
8
Port P4
Port P5
VCC2 ports
Internal peripheral functions
System clock generator
Timer (16-bit)
UART or
clock synchronous serial I/O
(6 channels)
Outputs (timer A): 5
Inputs (timer B): 6
Multi-master I2C-bus interface
(1 channel)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator (125 kHz)
High-speed on-chip oscillator
Three-phase motor control
circuit
USB module
(USB 2.0 Full speed)
DMAC (4 channels)
USB FIFO
(564 bytes)
CRC arithmetic circuit
(CCITT or CRC-16)
Timer S
Input capture
Output compare
Time measurement
function : 8 channels
Clock generation
function : 8 channels
Voltage detector
Power-on reset
On-chip debugger
Real-time clock
Memory
M16C/60 Series CPU core
Watchdog timer
(15-bit)
R0H
R1H
A/D converter
(10-bit resolution x 26
channels, 2 circuits)
SB
R0L
R1L
USP
R2
R3
ISP
A0
A1
FB
8
Port P8
8
Notes:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.3
(2)
PC
FLG
VCC1 ports
Port P9
RAM
INTB
D/A converter
(8-bit resolution
x 2 circuits)
Port P10
ROM (1)
Block Diagram
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 6 of 90
8
Port P7
8
Port P6
8
Multiplier
P9_6/ANEX1/TXD4/SDA4
P9_5/ANEX0/CLK4
P9_4/DA1/TB4IN/CTS4/RTS4
P9_3/DA0/TB3IN/CTS3/RTS3
P9_2/TB2IN/TXD3/SDA3/ATTACH
P9_1/TB1IN/RXD3/SCL3/D+
P9_0/TB0IN/CLK3/DUVCC
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI/SD/VbusDTCT(1)
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U/CTS5/RTS5
P8_0/TA4OUT/U/RXD5/SCL5
P7_7/TA3IN/CLK5
P7_6/TA3OUT/TXD5/SDA5
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN(1)
P7_0/TXD2/SDA2/SDAMM/TA0OUT(1)
Figure 1.4
Pin Assignment
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 7 of 90
Notes:
1. N-channel open drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Pin names in brackets ( ) represent a single functional signal.
They should not be considered as two separate functional signals.
30
29
28
27
26
25
24
23
21
22
20
19
18
17
99
16
94
95
15
82
14
93
13
91
92
12
90
11
9
10
86
87
8
7
6
4
5
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/RXD4/SCL4
2
3
1
52
51
53
54
55
58
57
56
59
61
60
62
64
63
66
65
68
67
69
71
70
73
72
74
75
76
78
77
79
80
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5/INT3/IDV
P1_6/INT4/IDW
P1_7/INT5/IDU
P2_0/AN2_0/A0, [A0/D0]/OUTC10/INPC10
P2_1/AN2_1/A1, [A1/D1]/OUTC11/INPC11
P2_2/AN2_2/A2, [A2/D2]/OUTC12/INPC12
P2_3/AN2_3/A3, [A3/D3]/OUTC13/INPC13
P2_4/INT6/AN2_4/A4, [A4/D4]/OUTC14/INPC14
P2_5/INT7/AN2_5/A5, [A5/D5]/OUTC15/INPC15
P2_6/AN2_6/A6, [A6/D6]/OUTC16/INPC16
P2_7/AN2_7/A7, [A7/D7]/OUTC17/INPC17
VSS
P3_0/A8
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
M16C/6C Group
1. Overview
Figure 1.4 to Figure 1.5 show pin assignments. Table 1.4 to Table 1.5 list pin names.
(See Note 3)
81
<VCC2>
50
49
83
84
48
85
46
45
47
88
89
M16C/6C Group
44
43
42
PRQP0100JD-B
(100P6F-A)
(top view)
41
40
39
38
37
96
36
97
35
34
98
<VCC1>
33
32
100
31
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WR
P5_1/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/RTCOUT/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
M16C/6C Group
1. Overview
51
52
53
54
55
56
58
57
59
61
60
62
64
63
65
66
67
68
69
72
71
70
73
74
75
P1_3
P1_4
P1_5/INT3/IDV
P1_6/INT4/IDW
P1_7/INT5/IDU
P2_0/AN2_0/A0, [A0/D0]/OUTC10/INPC10
P2_1/AN2_1/A1, [A1/D1]/OUTC11/INPC11
P2_2/AN2_2/A2, [A2/D2]/OUTC12/INPC12
P2_3/AN2_3/A3, [A3/D3]/OUTC13/INPC13
P2_4/INT6/AN2_4/A4, [A4/D4]/OUTC14/INPC14
P2_5/INT7/AN2_5/A5, [A5/D5]/OUTC15/INPC15
P2_6/AN2_6/A6, [A6/D6]/OUTC16/INPC16
P2_7/AN2_7/A7, [A7/D7]/OUTC17/INPC17
VSS
P3_0/A8
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
(See Note 3)
P1_2
P1_1
P1_0
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
76
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/RXD4/SCL4
P9_6/ANEX1/TXD4/SDA4
P9_5/ANEX0/CLK4
93
34
33
94
32
95
96
31
30
50
49
77
<VCC2>
78
48
79
80
81
47
46
45
44
82
83
M16C/6C Group
84
42
85
41
86
40
87
39
38
PLQP0100KB-A
(100P6Q-A)
(top view)
88
89
90
91
92
37
36
35
29
97
<VCC1>
98
99
28
27
26
Pin Assignment
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 8 of 90
25
24
23
21
22
20
19
18
17
16
15
14
13
12
11
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI/SD/VbusDTCT(1)
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U/CTS5/RTS5
P8_0/TA4OUT/U/RXD5/SCL5
P7_7/TA3IN/CLK5
P7_6/TA3OUT/TXD5/SDA5
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
9
10
8
7
6
4
5
2
3
P9_4/DA1/TB4IN/CTS4/RTS4
P9_3/DA0/TB3IN/CTS3/RTS3
P9_2/TB2IN/TXD3/SDA3/ATTACH
P9_1/TB1IN/RXD3/SCL3/D+
P9_0/TB0IN/CLK3/DUVCC
CNVSS
P8_7/XCIN
P8_6/XCOUT
1
100
Notes:
1. N-channel open drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Pin names in brackets ( ) represent a single functional signal.
They should not be considered as two separate functional signals.
Figure 1.5
43
P4_2/A18
P4_3/A19
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WR
P5_1/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/RTCOUT/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/SDAMM/TA0OUT(1)
P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN(1)
P7_2/CLK2/TA1OUT/V
M16C/6C Group
Table 1.4
1. Overview
Pin Names (1/2)
Pin No.
Control Pin
Port
FA
FB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
34
32
P6_4
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
P6_3
P6_2
P6_1
P6_0
P5_7
P5_6
P5_5
P5_4
P5_3
P5_2
P5_1
P5_0
P4_7
P4_6
P4_5
P4_4
I/O Pin for Peripheral Function
Serial interface,
Timer
USB
TXD4/SDA4
CLK4
CTS4/RTS4
TB4IN
CTS3/RTS3
TB3IN
TB2IN
TXD3/SDA3/ATTACH
TB1IN
RXD3/SCL3/D+
TB0IN
CLK3/DUVCC
Interrupt
P9_6
P9_5
P9_4
P9_3
P9_2
P9_1
P9_0
CNVSS
XCIN
XCOUT
RESET
XOUT
VSS
XIN
VCC1
A/D converter,
D/A converter
ANEX1
ANEX0
DA1
DA0
Bus Control
Pin
P8_7
P8_6
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
P7_6
P7_5
P7_4
P7_3
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
NMI
INT2
INT1
INT0
SD
ZP
VbusDTCT
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TA0IN/TB5IN
TA0OUT
CTS5/RTS5
RXD5/SCL5
CLK5
TXD5/SDA5
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RTCOUT
CTS2/RTS2
CLK2
RXD2/SCL2/SCLMM
TXD2/SDA2/SDAMM
TXD1/SDA1
RXD1/SCL1
CLK1
CTS1/RTS1/CTS0/
CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
CTS0/RTS0
RDY/CLKOUT
ALE
HOLD
HLDA
BCLK
RD
BHE
WR
CS3
CS2
CS1
CS0
M16C/6C Group
Table 1.5
Pin No.
1. Overview
Pin Names (2/2)
Control
Pin
Port
FA
FB
Interrupt
51
52
53
54
55
56
57
58
59
60
61
62
63
64
49
50
51
52
53
54
55
56
57
58
59
60
61
62
65
63
P2_7
66
64
P2_6
67
65
P2_5
INT7
68
66
P2_4
INT6
69
67
P2_3
70
68
P2_2
71
69
P2_1
72
70
P2_0
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P10_7
P10_6
P10_5
P10_4
P10_3
P10_2
P10_1
I/O Pin for Peripheral Function
Serial interface,
A/D converter,
Timer
USB
D/A converter
Bus Control Pin
P4_3
P4_2
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
P3_0
A8
VCC2
VSS
INT5
INT4
INT3
OUTC17/
INPC17
OUTC16/
INPC16
OUTC15/
INPC15
OUTC14/
INPC14
OUTC13/
INPC13
OUTC12/
INPC12
OUTC11/
INPC11
OUTC10/
INPC10
IDU
IDW
IDV
KI3
KI2
KI1
KI0
AN2_7
A7, [A7/D7]
AN2_6
A6, [A6/D6]
AN2_5
A5, [A5/D5]
AN2_4
A4, [A4/D4]
AN2_3
A3, [A3/D3]
AN2_2
A2, [A2/D2]
AN2_1
A1, [A1/D1]
AN2_0
A0, [A0/D0]
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
D7
D6
D5
D4
D3
D2
D1
D0
AVSS
P10_0
AN0
VREF
AVCC
P9_7
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RXD4/SCL4
ADTRG
M16C/6C Group
1.5
1. Overview
Pin Functions
Table 1.6
Pin Functions (1/3)
Signal Name
Pin Name
I/O
Power Supply
Description
Power supply
input
VCC1,
VCC2, VSS
I
-
Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2).
Input 0V to VSS.(1)
Analog power
supply input
AVCC, AVSS
I
VCC1
This is the power supply for the A/D converter. Connect the
AVCC pin to VCC1, and connect the AVSS pin to VSS.
RESET
I
VCC1
Driving this pin low resets the MCU.
Reset input
CNVSS
Bus control pins
CNVSS
I
VCC1
Input pin to switch processor modes. After a reset, to start
operating in single-chip mode, connect the CNVSS pin to
VSS via a resistor. To start operating in microprocessor
mode, connect the pin to VCC1.
D0 to D7
I/O
VCC2
Inputs or outputs data (D0 to D7) while accessing an
external area with a separate bus.
A0 to A19
O
VCC2
Outputs address bits A0 to A19.
A0/D0 to
A7/D7
I/O
VCC2
Inputs or outputs data (D0 to D7) and outputs address bits
(A0 to A7) by timesharing, while accessing an external area
with an 8-bit multiplexed bus.
CS0 to CS3
O
VCC2
Outputs chip-select signals CS0 to CS3 to specify an
external area.
WR
BHE
RD
O
VCC2
Outputs WR, BHE, and RD signals.
• Data is written to an external area when WR is driven low.
Data in an external area is read when RD is driven low. An
odd address is accessed when BHE is driven low.
ALE
O
VCC2
Outputs ALE signal to latch address.
HOLD
I
VCC2
The MCU is placed in a hold state while the HOLD pin is
driven low.
HLDA
O
VCC2
In a hold state, HLDA outputs a low-level signal.
VCC2
The MCU bus is placed in a wait state while the RDY pin is
driven low.
RDY
I
Power supply: VCC2 is used to supply power to the external bus associated pins. The dual power supply configuration
allows VCC2 to interface at a different voltage than VCC1.
Note:
1. VCC means VCC1 except as otherwise noted.
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M16C/6C Group
Table 1.7
1. Overview
Pin Functions (2/3)
Pin Name
I/O
Power
Supply
XIN
I
VCC1
Main clock output
XOUT
O
VCC1
Sub clock input
XCIN
I
VCC1
XCOUT
O
VCC1
I/O for a sub clock oscillator. Connect a crystal between
XCIN pin and XCOUT pin. (1) Input an external clock to
XCIN pin and leave XCOUT pin open.
BCLK output
BCLK
O
VCC2
Outputs the BCLK signal.
Clock output
CLKOUT
O
VCC2
Outputs a clock with the same frequency as fC, f1, f8, or
f32.
INT0 to INT2
I
VCC1
INT3 to INT7
I
VCC2
NMI interrupt input
NMI
I
VCC1
Input for the NMI interrupt.
Key input interrupt
input
KI0 to KI3
I
VCC1
Input for the key input interrupt.
TA0OUT to
TA4OUT
I/O
VCC1
I/O for timers A0 to A4 (TA0OUT is N-channel open drain
output).
TA0IN to TA4IN
I
VCC1
Input for timers A0 to A4.
ZP
I
VCC1
Input for Z-phase.
TB0IN to TB5IN
I
VCC1
Input for timers B0 to B5.
U, U, V, V, W, W
O
VCC1
Output for the three-phase motor control timer.
SD
I
VCC1
Forced cutoff input.
IDU, IDV, IDW
I
VCC2
Input for the position data.
RTCOUT
O
VCC1
Output for the real-time clock.
INPC10 to INPC17
I
VCC2
Input for the time measurement function.
VCC2
Output for the waveform generation function.
I
VCC1
Input pins to control data transmission.
RTS0 to RTS5
O
VCC1
Output pins to control data reception.
CLK0 to CLK5
I/O
VCC1
Transmit/receive clock I/O.
RXD0 to RXD5
I
VCC1
Serial data input.
TXD0 to TXD5
O
VCC1
Serial data output. (2)
CLKS1
O
VCC1
Output for the transmit/receive clock multiple-pin output function.
Signal Name
Main clock input
Sub clock output
INT interrupt input
Timer A
Timer B
Three-phase motor
control timer
Real-time clock output
Timer S
OUTC10 to
OUTC17
CTS0 to CTS5
Serial interface
UART0 to UART5
Description
I/O for the main clock oscillator. Connect a ceramic
resonator or crystal between pins XIN and XOUT. (1) Input
an external clock to XIN pin and leave XOUT pin open.
Input for the INT interrupt.
Notes:
1. Contact the oscillator manufacturer regarding the oscillation characteristics.
2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 3 to 5), SDAi, and SCLi can be
selected as CMOS output pins or N-channel open drain output pins.
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Page 12 of 90
M16C/6C Group
Table 1.8
Signal Name
UART0 to
UART5
I2C mode
Multi-master
I2C-bus
interface
USB module
Reference
voltage input
A/D
converter
D/A
converter
I/O ports
1. Overview
Pin Functions (3/3)
Pin Name
I/O
Power
Supply
SDA0 to SDA5
I/O
VCC1
Serial data I/O for I2C mode.(2)
SCL0 to SCL5
I/O
VCC1
Transmit/receive clock I/O for I2C mode.(2)
SDAMM
I/O
VCC1
Serial data I/O (N-channel open drain output).
SCLMM
I/O
VCC1
Transmit/receive clock I/O (N-channel open drain output).
Description
ATTACH
O
UVCC
Output used for D+ 1.5 kΩ pull-up
VbusDTCT
I
UVCC
Input the power supply signal from a host PC
UVCC
I
D+
I/O
UVCC
USB D+ input/output
D-
I/O
UVCC
USB D- input/output
VREF
I
VCC1
Reference voltage input for the A/D and D/A converters.
AN0 to AN7
I
VCC1
AN0_0 to AN0_7
AN2_0 to AN2_7
I
VCC2
ADTRG
I
VCC1
External A/D trigger input.
ANEX0, ANEX1
I
VCC1
Extended analog input for the A/D converter.
DA0, DA1
O
VCC1
Output for the D/A converter.
VCC2
8-bit CMOS I/O ports. A direction register determines whether
each pin is used as an input port or an output port. A pull-up
resistor may be enabled or disabled for input ports in 4-bit
units.
VCC1
8-bit I/O ports having equivalent functions to P0. However,
P7_0, P7_1, and P8_5 are N-channel open drain output ports.
No pull-up resistor is provided. P8_5 is an input port for
verifying the NMI pin level and shares a pin with NMI.
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_0 to P5_7
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_7
P9_0 to P9_7
P10_0 to P10_7
I/O
I/O
Input power supply for pins ATTACH, D+ and D-
Analog input for the A/D converter.
Notes:
1. Contact the oscillator manufacturer regarding the oscillation characteristics.
2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 3 to 5), SDAi, and SCLi can be
selected as CMOS output pins or N-channel open drain output pins.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 13 of 90
M16C/6C Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a
register bank, and there are two register banks.
b31
b15
b8 b7
b0
R2
R0H(high-order bits of R0) R0L (low-order bits of R0)
R3
R1H(high-order bits of R1) R1L (low-order bits of R1)
Data registers (1)
R2
R3
A0
Address registers (1)
A1
FB
b19
b15
Frame base registers (1)
b0
Interrupt table register
INTBL
INTBH
INTBH is the 4 high-order bits of the INTB register
and INTBL is the 16 low-order bits.
b19
b0
Program counter
PC
b15
b0
User stack pointer
USP
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
U I
Flag register
b0
O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note:
1. These registers compose a register bank. There are two register banks.
Figure 2.1
2.1
CPU Register
Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can
be split into high-order (R0H/R1H) and low-order (R0L/R1L) bits to be used separately as 8-bit data
registers.
R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers
R2R0 and R3R1, respectively.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 14 of 90
M16C/6C Group
2.2
2. Central Processing Unit (CPU)
Address Registers (A0 and A1)
A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic, and
logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register that is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.
2.5
Program Counter (PC)
The PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The USP and ISP stack pointers (SP) are each comprised of 16 bits. The U flag is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register used for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register that indicates the CPU state.
2.8.1
Carry Flag (C Flag)
The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z Flag)
The Z flag becomes 1 when an arithmetic operation results in 0. Otherwise, it becomes 0.
2.8.4
Sign Flag (S Flag)
The S flag becomes 1 when an arithmetic operation results in a negative value. Otherwise, it becomes
0.
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.
2.8.6
Overflow Flag (O Flag)
The O flag becomes 1 when an arithmetic operation results in an overflow. Otherwise, it becomes 0.
2.8.7
Interrupt Enable Flag (I Flag)
The I flag enables maskable interrupts.
Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0
when an interrupt request is accepted.
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Page 15 of 90
M16C/6C Group
2.8.8
2. Central Processing Unit (CPU)
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1.
The U flag becomes 0 when a hardware interrupt request is accepted, or the INT instruction of software
interrupt number 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from 0 to 7.
If a requested interrupt has higher priority than IPL, the interrupt request is enabled.
2.8.10
Reserved Areas
Only set these bits to 0. The read value is undefined.
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Page 16 of 90
M16C/6C Group
3.
3.1
3. Address Space
Address Space
Address Space
The M16C/6C Group has a 1 MB address space from 00000h to FFFFFh. Figure 3.1 shows the Address
Space. Areas that can be accessed vary depending on processor mode and the status of each control bit.
Memory expand mode
00000h
SFR
00400h
Internal RAM
Internal RAM is allocated from
address 00400h to higher.
Reserved area
04000h
0D000h
0D800h
0E000h
10000h
Address space
1 Mbyte
External area
SFR
External area
Internal ROM
(data flash)
Internal ROM
(program ROM2)
When data flash is enabled
When program ROM 2
is enabled
14000h
External area
27000h
Reserved area
28000h
External area
D0000h
Reserved area
Internal ROM
(program ROM1)
Program ROM 1 is allocated from
address FFFFFh to lower.
FFFFFh
Notes:
1. Do not access reserved areas.
2. The figure above applies under the following conditions:
- The PM13 bit in the PM1 register is set to 0
(addresses from 04000h to 0CFFFh and from 80000h to CFFFFh are used as external areas)
Figure 3.1
Address Space
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 17 of 90
M16C/6C Group
3.2
3. Address Space
Memory Map
Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to
0D7FFh. Peripheral function control registers are located here. All blank areas within SFRs are reserved.
Do not access these areas.
Internal RAM is allocated from address 00400h higher, with 10 KB of internal RAM allocated from 00400h to
02BFFh. Internal RAM is used not only for data storage, but also for the stack area when subroutines are
called or when an interrupt request is accepted.
The internal ROM is flash memory. Three internal ROM areas are available: data flash, program ROM 1,
and program ROM 2.
The data flash is allocated from 0E000h to 0FFFFh. This data flash area is mostly used for data storage, but
can also store programs.
Program ROM 2 is allocated from 10000h to 13FFFh. Program ROM 1 is allocated from FFFFFh lower, with
the 64-KB program ROM 1 area allocated from address F0000h to FFFFFh.
The special page vectors are allocated from FFE00h to FFFD7h. They are used for the JMPS and JSRS
instructions. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for details.
The fixed vector table for interrupts is allocated from FFFDCh to FFFFFh.
The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table
for interrupts.
Figure 3.2 shows the Memory Map.
00000h
Internal RAM
SFR
00400h
Internal RAM
XXXXXh
Size
Address XXXXXh
12 KB
033FFh
20 KB
053FFh
0D000h
31 KB
07FFFh
0D800h
External area
0E000h
Internal ROM
(data flash)
Internal ROM
(program ROM 2)
Reserved area
10000h
SFR
13000h
13FF0h
13FFFh
On-chip debugger
monitor area
User boot code area
14000h
External area
27000h
Reserved area
28000h
Relocatable vector table
External area
Program ROM 1
Address YYYYYh
Size
128 KB
E0000h
256 KB
C0000h
384 KB
A0000h
512 KB
80000h
256 bytes beginning with the
start address set in the INTB
register
80000h
Reserved area
FFE00h
FFFD8h
YYYYYh
Reserved area
Internal ROM
(program ROM 1)
FFFFFh
Special page vector table
FFFDCh
Fixed vector table
Address for ID code stored
FFFFFh
OFS1 address
Notes:
1. Do not access reserved areas.
2. The figure above applies under the following conditions:
- Memory expansion mode
- The PM10 bit in the PM1 register is 1
(addresses 0E000h to 0FFFFh are used as data flash)
- The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled)
- The PM13 bit in the PM1 register is 1
(all areas in internal RAM, and the program ROM 1 area from 80000h are usable)
Figure 3.2
Memory Map
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 18 of 90
M16C/6C Group
3.3
3. Address Space
Accessible Area in Each Mode
Areas that can be accessed vary depending on processor mode and the status of each control bit. Figure
3.3 shows the Accessible Area in Each Mode.
In single-chip mode, the SFRs, internal RAM, and internal ROM can be accessed.
In memory expansion mode, the SFRs, internal RAM, internal ROM, and external areas can be accessed.
In microprocessor mode, the SFRs, internal RAM, and external areas can be accessed. Allocate ROM to
the fixed vector table from FFFDCh to FFFFFh.
Single-Chip Mode
00000h
Memory Expansion Mode
00000h
SFR
00400h
Internal RAM
SFR
00400h
Internal RAM
Reserved area
0D000h
0D800h
Microprocessor Mode
00000h
Internal RAM
Reserved area
Reserved area
0D000h
SFR
0D800h
Reserved area
0E000h
Internal ROM
(data flash)
0E000h
10000h
Internal ROM
(program ROM 2)
10000h
14000h
SFR
External area
SFR
00400h
0D000h
SFR
0D800h
Internal ROM
(data flash)
External area
Internal ROM
(program ROM 2)
14000h
External area
27000h
27000h
Reserved area
Reserved area
28000h
28000h
Reserved area
External area
80000h
External area
External or
reserved area
Internal ROM
(program ROM 1)
FFFFFh
Internal ROM
(program ROM 1)
FFFFFh
FFFFFh
Notes:
1. Do not access reserved areas.
2. The figure above applies under the following conditions:
Single-chip mode and memory expansion mode
- The PM10 bit in the PM1 register is 1
(addresses 0E000h to 0FFFFh are used as data flash)
- The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled)
- The PM13 bit in the PM1 register is 1
(all areas in internal RAM, and the program ROM 1 area from 80000h are usable)
Microprocessor mode
- The PM10 bit is 0 (addresses 0E000h to 0FFFFh are used as the CS2 area)
- The PRG2C0 bit is 1 (program ROM 2 disabled)
Figure 3.3
Accessible Area in Each Mode
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 19 of 90
M16C/6C Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
4.1
SFRs
An SFR is a control register for a peripheral function. Table 4.1 to Table 4.21 list SFR information.
Table 4.1
SFR Information (1/21) (1)
Address
Register
Symbol
Reset Value
0000h
0001h
0002h
0003h
0004h
Processor Mode Register 0
PM0
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Chip Select Control Register
PM1
CM0
CM1
CSR
0000 0000b (CNVSS pin is low)
0000 0011b (CNVSS pin is high) (2)
0000 1000b
0100 1000b
0010 0000b
01h
PRCR
00h
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
Oscillation Stop Detection Register
CM2
0X00 0010b (3)
Program 2 Area Control Register
PRG2C
XXXX XX00b
Peripheral Clock Select Register
PCLKR
0000 0011b
Clock Prescaler Reset Flag
CPSRF
0XXX XXXXb
Reset Source Determine Register
RSTFR
XX00 001Xb (hardware reset) (4)
0019h
Voltage Detector 2 Flag Register
VCR1
Protect Register
001Ah
Voltage Detector Operation Enable Register
VCR2
001Bh
001Ch
001Dh
001Eh
001Fh
Chip Select Expansion Control Register
PLL Control Register 0
PLLFCK Control Register
Processor Mode Register 2
CSE
PLC0
PLCF
PM2
Notes:
1.
2.
3.
4.
5.
6.
0000 X000b (2)
000X 0000b (2, 5)
001X 0000b (2, 6)
00h
0001 X010b
00h
XX00 0X01b
X: Undefined
The blank areas are reserved. No access is allowed.
Software reset, watchdog timer reset, oscillator stop detect reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect the following
bits and registers: The VCR1 register, the VCR2 register, and bits PM01 and PM00 in the PM0 register.
Oscillator stop detect reset does not affect bits CM20, CM21, and CM27.
The state of bits in the RSTFR register depends on the reset type.
This is the reset value when the LVDAS bit of address OFS1 is 1 during hardware reset.
This is the reset value after voltage monitor 0 reset, power-on reset, and when the LVDAS bit of address OFS1 is 0 during hardware reset.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 20 of 90
M16C/6C Group
Table 4.2
4. Special Function Registers (SFRs)
SFR Information (2/21) (1)
Address
Symbol
Reset Value
40 MHz On-Chip Oscillator Control Register 0
FRA0
XXXX XX00b
Voltage Monitor Function Select Register
VWCE
00h
002Ah
Voltage Monitor 0 Control Register
VW0C
1100 XX10b (2, 3)
1100 XX11b (2, 4)
0020h
0021h
0022h
0023h
0024h
0025h
0026h
Register
0027h
0028h
0029h
002Bh
Voltage Monitor 1 Control Register
VW1C
1000 XX10b (6)
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
Voltage Monitor 2 Control Register
VW2C
1000 0X10b (6)
0042h
INT7 Interrupt Control Register
INT7IC
XX00 X000b
0043h
INT6 Interrupt Control Register
INT6IC
XX00 X000b
0044h
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
Timer B4 Interrupt Control Register
UART1 Bus Collision Detection Interrupt Control Register
Timer B3 Interrupt Control Register
UART0 Bus Collision Detection Interrupt Control Register
INT3IC
XX00 X000b
TB5IC
TB4IC
U1BCNIC
TB3IC
U0BCNIC
XXXX X000b
0045h
0046h
0047h
XXXX X000b
XXXX X000b
0048h
INT5 Interrupt Control Register
INT5IC
0049h
INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
DMA1 Interrupt Control Register
Key Input Interrupt Control Register, A/D Conversion (A/D1) Interrupt Control
Register
A/D Conversion (A/D0) Interrupt Control Register
UART2 Transmit Interrupt Control Register
INT4IC
XX00 X000b
BCNIC
DM0IC
DM1IC
XXXX X000b
XXXX X000b
XXXX X000b
KUPIC, ADEIC
XXXX X000b
ADIC
S2TIC
XXXX X000b
XXXX X000b
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
Notes:
1.
2.
3.
4.
5.
6.
XX00 X000b
X: Undefined
The blank areas are reserved. No access is allowed.
Software reset, watchdog timer reset, oscillator stop detect reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect the following
registers or bit: the VW0C register, and the VW2C3 bit in the VW2C register.
This is the reset value when the LVDAS bit of address OFS1 is 1 during hardware reset
This is the reset value after voltage monitor 0 reset, power-on reset, and when the LVDAS bit of address OFS1 is 0 during hardware reset.
Hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, or voltage monitor 2 reset
Hardware reset, power-on reset, or voltage monitor 0 reset
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 21 of 90
M16C/6C Group
Table 4.3
4. Special Function Registers (SFRs)
SFR Information (3/21) (1)
Address
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
Symbol
Reset Value
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
005Dh
INT0 Interrupt Control Register
INT0IC
XX00 X000b
005Eh
INT1 Interrupt Control Register
INT1IC
XX00 X000b
005Fh
INT2 Interrupt Control Register
INT2IC
XX00 X000b
DM2IC
DM3IC
U5BCNIC
S5TIC
S5RIC
U4BCNIC
RTCTIC
S4TIC
RTCCIC
S4TIC
U3BCNIC
S3TIC
S3RIC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
0080h to 011Fh
Note:
1.
Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
Timer A3 Interrupt Control Register
Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
Timer B1 Interrupt Control Register
Timer B2 Interrupt Control Register
DMA2 Interrupt Control Register
DMA3 Interrupt Control Register
UART5 Bus Collision Detection Interrupt Control Register
UART5 Transmit Interrupt Control Register
UART5 Receive Interrupt Control Register
UART4 Bus Collision Detection Interrupt Control Register
Real-Time Clock Period Interrupt Control Register
UART4 Transmit Interrupt Control Register
Real-Time Clock Compare Interrupt Control Register
UART4 Receive Interrupt Control Register
UART3 Bus Collision Detection Interrupt Control Register
UART3 Transmit Interrupt Control Register
UART3 Receive Interrupt Control Register
USB Interrupt 0 Control Register
USB Interrupt 1 Control Register
USB RESUME Interrupt Control Register
IC/OC Interrupt 0 Control Register
IC/OC Channel 0 Interrupt Control Register
IC/OC Interrupt 1 Control Register
I2C-bus Interface Interrupt Control Register
IC/OC Channel 1 Interrupt Control Register
SCL/SDA Interrupt Control Register
IC/OC Channel 2 Interrupt Control Register
IC/OC Channel 3 Interrupt Control Register
IC/OC Base Timer Interrupt Control Register
USBINT0IC
USBINT1IC
USBRSMIC
ICOC0IC
ICOCH0IC
ICOC1IC,
IICIC
ICOCH1IC,
SCLDAIC
ICOCH2IC
ICOCH3IC
BTIC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 22 of 90
M16C/6C Group
Table 4.4
4. Special Function Registers (SFRs)
SFR Information (4/21) (1)
Address
Register
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h to
013Fh
0140h
A/D1 Register 0
0141h
0142h
A/D1 Register 1
0143h
0144h
A/D1 Register 2
0145h
0146h
A/D1 Register 3
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
A/D1 Trigger Control Register
0153h
0154h
A/D1 Control Register 2
0155h
0156h
A/D1 Control Register 0
0157h
A/D1 Control Register 1
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h to
017Fh
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 23 of 90
Symbol
Reset Value
AD10
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
AD11
AD12
AD13
AD1TRGCON
XXXX 00XXb
AD1CON2
0000 X00Xb
AD1CON0
AD1CON1
0000 0XXXb
0000 X000b
X: Undefined
M16C/6C Group
Table 4.5
4. Special Function Registers (SFRs)
SFR Information (5/21) (1)
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
Note:
1.
Symbol
Reset Value
DMA0 Source Pointer
Register
SAR0
XXh
XXh
0Xh
DMA0 Destination Pointer
DAR0
XXh
XXh
0Xh
DMA0 Transfer Counter
TCR0
XXh
XXh
DMA0 Control Register
DM0CON
0000 0X00b
DMA1 Source Pointer
SAR1
XXh
XXh
0Xh
DMA1 Destination Pointer
DAR1
XXh
XXh
0Xh
DMA1 Transfer Counter
TCR1
XXh
XXh
DMA1 Control Register
DM1CON
0000 0X00b
DMA2 Source Pointer
SAR2
XXh
XXh
0Xh
DMA2 Destination Pointer
DAR2
XXh
XXh
0Xh
DMA2 Transfer Counter
TCR2
XXh
XXh
DMA2 Control Register
DM2CON
0000 0X00b
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 24 of 90
M16C/6C Group
Table 4.6
4. Special Function Registers (SFRs)
SFR Information (6/21) (1)
Address
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
Note:
1.
Symbol
Reset Value
DMA3 Source Pointer
Register
SAR3
XXh
XXh
0Xh
DMA3 Destination Pointer
DAR3
XXh
XXh
0Xh
DMA3 Transfer Counter
TCR3
XXh
XXh
DMA3 Control Register
DM3CON
0000 0X00b
Timer B0-1 Register
TB01
Timer B1-1 Register
TB11
Timer B2-1 Register
TB21
PPWFS1
XXh
XXh
XXh
XXh
XXh
XXh
XXXX X000b
TBCS0
TBCS1
00h
X0h
TCKDIVC0
0000 X000b
TACS0
TACS1
TACS2
00h
00h
X0h
PWMFS
TAPOFS
0XX0 X00Xb
XXX0 0000b
Timer A Output Waveform Change Enable Register
TAOW
XXX0 X00Xb
Three-Phase Protect Control Register
TPRC
00h
Pulse Period/Pulse Width Measurement Mode Function Select Register 1
Timer B Count Source Select Register 0
Timer B Count Source Select Register 1
Timer AB Division Control Register 0
Timer A Count Source Select Register 0
Timer A Count Source Select Register 1
Timer A Count Source Select Register 2
16-Bit Pulse Width Modulation Mode Function Select Register
Timer A Waveform Output Function Select Register
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 25 of 90
M16C/6C Group
Table 4.7
4. Special Function Registers (SFRs)
SFR Information (7/21) (1)
Address
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
Note:
1.
Symbol
Reset Value
Timer B3-1 Register
Register
TB31
Timer B4-1 Register
TB41
Timer B5-1 Register
TB51
PPWFS2
XXh
XXh
XXh
XXh
XXh
XXh
XXXX X000b
Timer B Count Source Select Register 2
Timer B Count Source Select Register 3
TBCS2
TBCS3
00h
X0h
Interrupt Source Select Register 3
Interrupt Source Select Register 2
Interrupt Source Select Register
IFSR3A
IFSR2A
IFSR
00h
00h
00h
AIER
AIER2
XXXX XX00b
XXXX XX00b
Pulse Period/Pulse Width Measurement Mode Function Select Register 2
Address Match Interrupt Enable Register
Address Match Interrupt Enable Register 2
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 26 of 90
M16C/6C Group
Table 4.8
4. Special Function Registers (SFRs)
SFR Information (8/21) (1)
Address
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
Symbol
Reset Value
Address Match Interrupt Register 0
Register
RMAD0
00h
00h
X0h
Address Match Interrupt Register 1
RMAD1
00h
00h
X0h
Address Match Interrupt Register 2
RMAD2
00h
00h
X0h
Address Match Interrupt Register 3
RMAD3
00h
00h
X0h
0220h
Flash Memory Control Register 0
FMR0
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
Flash Memory Control Register 1
Flash Memory Control Register 2
FMR1
FMR2
0000 0001b
(Other than user boot mode)
0010 0001b
(User boot mode)
00X0 XX0Xb
XXXX 0000b
Flash Memory Control Register 6
FMR6
XX0X XX00b
Note:
1.
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 27 of 90
M16C/6C Group
Table 4.9
4. Special Function Registers (SFRs)
SFR Information (9/21) (1)
Address
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
Note:
1.
Register
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
Symbol
Reset Value
U0SMR4
U0SMR3
U0SMR2
U0SMR
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART Transmit/Receive Control Register 2
UCON
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
00XX 0010b
XXh
XXh
X000 0000b
UCLKSEL0
X0h
U1SMR4
U1SMR3
U1SMR2
U1SMR
U1MR
U1BRG
U1TB
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
00XX 0010b
XXh
XXh
UART Clock Select Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U1C0
U1C1
U1RB
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
U2C0
U2C1
U2RB
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 28 of 90
M16C/6C Group
Table 4.10
Address
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (10/21) (1)
Register
UART5 Special Mode Register 4
UART5 Special Mode Register 3
UART5 Special Mode Register 2
UART5 Special Mode Register
UART5 Transmit/Receive Mode Register
UART5 Bit Rate Register
UART5 Transmit Buffer Register
UART5 Transmit/Receive Control Register 0
UART5 Transmit/Receive Control Register 1
UART5 Receive Buffer Register
UART4 Special Mode Register 4
UART4 Special Mode Register 3
UART4 Special Mode Register 2
UART4 Special Mode Register
UART4 Transmit/Receive Mode Register
UART4 Bit Rate Register
UART4 Transmit Buffer Register
UART4 Transmit/Receive Control Register 0
UART4 Transmit/Receive Control Register 1
UART4 Receive Buffer Register
Symbol
Reset Value
U5SMR4
U5SMR3
U5SMR2
U5SMR
U5MR
U5BRG
U5TB
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
U5C0
U5C1
U5RB
U4SMR4
U4SMR3
U4SMR2
U4SMR
U4MR
U4BRG
U4TB
U4C0
U4C1
U4RB
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 29 of 90
M16C/6C Group
Table 4.11
4. Special Function Registers (SFRs)
SFR Information (11/21) (1)
Address
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
Register
Symbol
Reset Value
U3SMR4
U3SMR3
U3SMR2
U3SMR
U3MR
U3BRG
U3TB
S00
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
XXh
S0D0
S1D0
S20
S2D0
S3D0
S4D0
S10
S11
S0D1
S0D2
0000 000Xb
00h
00h
0001 1010b
0011 0000b
00h
0001 000Xb
00h
0000 000Xb
0000 000Xb
Time measurement register, Waveform generation register 0
G1TM0
G1PO0
Time measurement register, Waveform generation register 1
G1TM1
G1PO1
Time measurement register, Waveform generation register 2
G1TM2
G1PO2
Time measurement register, Waveform generation register 3
G1TM3
G1PO3
Time measurement register, Waveform generation register 4
G1TM4
G1PO4
Time measurement register, Waveform generation register 5
G1TM5
G1PO5
Time measurement register, Waveform generation register 6
G1TM6
G1PO6
Time measurement register, Waveform generation register 7
G1TM7
G1PO7
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
0X00XX00b
0X00XX00b
0X00XX00b
0X00XX00b
0X00XX00b
0X00XX00b
0X00XX00b
0X00XX00b
00h
00h
00h
00h
00h
00h
00h
00h
UART3 Special Mode Register 4
UART3 Special Mode Register 3
UART3 Special Mode Register 2
UART3 Special Mode Register
UART3 Transmit/Receive Mode Register
UART3 Bit Rate Register
UART3 Transmit Buffer Register
UART3 Transmit/Receive Control Register 0
UART3 Transmit/Receive Control Register 1
UART3 Receive Buffer Register
I2C0 Data Shift Register
I2C0 Address Register 0
I2C0 Control Register
I2C0 Clock Control Register
I2C0 Start/Stop Condition Control Register
I2C0 Control Register 1
I2C0 Control Register 2
I2C0 Status Register 0
I2C0 Status Register 1
I2C0 Address Register 1
I2C0 Address Register 2
Waveform generation control register 0
Waveform generation control register 1
Waveform generation control register 2
Waveform generation control register 3
Waveform generation control register 4
Waveform generation control register 5
Waveform generation control register 6
Waveform generation control register 7
Time measurement control register 0
Time measurement control register 1
Time measurement control register 2
Time measurement control register 3
Time measurement control register 4
Time measurement control register 5
Time measurement control register 6
Time measurement control register 7
Note:
1.
U3C0
U3C1
U3RB
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 30 of 90
M16C/6C Group
Table 4.12
4. Special Function Registers (SFRs)
SFR Information (12/21) (1)
Address
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
0300h
0301h
0302h
0303h
0304h
0305h
0306h
0307h
0308h
0309h
030Ah
030Bh
030Ch
030Dh
030Eh
030Fh
Register
Reset Value
G1DV
XXh
XXh
00h
00h
00h
00h
00h
00h
XXh
XXh
00h
Waveform output master enable register
G1OER
00h
Timer S I/O control register 0
Timer S I/O control register 1
Interrupt request register
Interrupt enable register 0
Interrupt enable register 1
G1IOR0
G1IOR1
G1IR
G1IE0
G1IE1
00h
00h
XXh
00h
00h
Timer B3/B4/B5 Count Start Flag
TBSR
000X XXXXb
Timer A1-1 Register
TA11
Timer A2-1 Register
TA21
Timer A4-1 Register
TA41
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
XX11 1111b
XX11 1111b
XXh
XXh
XXXX 0000b
Base timer register
G1BT
Base timer control register 0
Base timer control register 1
Time measurement prescaler register 6
Time measurement prescaler register 7
Function enable register
Function select register
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
G1FS
Base timer reset register
G1BTRR
Count source divide register
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Generation Frequency Set Counter
Position-Data-Retain Function Control Register
Note:
1.
Symbol
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
PDRF
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 31 of 90
M16C/6C Group
Table 4.13
4. Special Function Registers (SFRs)
SFR Information (13/21) (1)
Address
0310h
0311h
0312h
0313h
0314h
0315h
0316h
0317h
0318h
0319h
031Ah
031Bh
031Ch
031Dh
031Eh
031Fh
0320h
0321h
0322h
0323h
0324h
0325h
0326h
0327h
0328h
0329h
032Ah
032Bh
032Ch
032Dh
032Eh
032Fh
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
Note:
1.
Symbol
Reset Value
Timer B3 Register
Register
TB3
Timer B4 Register
TB4
Timer B5 Register
TB5
XXh
XXh
XXh
XXh
XXh
XXh
Port Function Control Register
PFCR
0011 1111b
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
TB3MR
TB4MR
TB5MR
00XX 0000b
00XX 0000b
00XX 0000b
Count Start Flag
TABSR
00h
One-Shot Start Flag
Trigger Select Register
Up/Down Flag
ONSF
TRGSR
UDF
00h
00h
00h
Timer A0 Register
TA0
Timer A1 Register
TA1
Timer A2 Register
TA2
Timer A3 Register
TA3
Timer A4 Register
TA4
Timer B0 Register
TB0
Timer B1 Register
TB1
Timer B2 Register
TB2
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
00h
00XX 0000b
00XX 0000b
00XX 0000b
X000 0000b
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 32 of 90
M16C/6C Group
Table 4.14
4. Special Function Registers (SFRs)
SFR Information (14/21) (1)
Address
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
0360h
Register
Real-Time Clock Second Data Register
Real-Time Clock Minute Data Register
Real-Time Clock Hour Data Register
Real-Time Clock Day Data Register
Real-Time Clock Control Register 1
Real-Time Clock Control Register 2
Real-Time Clock Count Source Select Register
Real-Time Clock Second Compare Data Register
Real-Time Clock Minute Compare Data Register
Real-Time Clock Hour Compare Data Register
Pull-Up Control Register 0
Symbol
Reset Value
RTCSEC
RTCMIN
RTCHR
RTCWK
RTCCR1
RTCCR2
RTCCSR
00h
X000 0000b
XX00 0000b
XXXX X000b
0000 X00Xb
X000 0000b
XXX0 0000b
RTCCSEC
RTCCMIN
RTCCHR
X000 0000b
X000 0000b
X000 0000b
PUR0
00h
0361h
Pull-Up Control Register 1
PUR1
0362h
0363h
0364h
0365h
0366h
0367h
0368h
Pull-Up Control Register 2
PUR2
0000 0000b (2)
0000 0010b
00h
Port Control Register
PCR
0000 0XX0b
0369h
NMI/SD Digital Filter Register
NMIDF
XXXX X000b
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
Notes:
1.
2.
X: Undefined
The blank areas are reserved. No access is allowed.
Values after hardware reset, power-on reset, or voltage monitor 0 reset are as follows:
- 00000000b when a low-level signal is input to the CNVSS pin
- 00000010b when a high-level signal is input to the CNVSS pin
Values after voltage monitor 1 reset, voltage monitor 2 reset, software reset, watchdog timer reset, or oscillation stop detect reset are as follows:
- 00000000b when bits PM01 and PM00 in the PM0 register are 00b (single-chip mode).
- 00000010b when bits PM01 and PM00 in the PM0 register are 01b (memory expansion mode) or 11b (microprocessor mode).
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 33 of 90
M16C/6C Group
Table 4.15
4. Special Function Registers (SFRs)
SFR Information (15/21) (1)
Address
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
Notes:
1.
2.
Register
Symbol
Reset Value
Count Source Protection Mode Register
Watchdog Timer Refresh Register
Watchdog Timer Start Register
Watchdog Timer Control Register
CSPR
WDTR
WDTS
WDC
00h (2)
XXh
XXh
00XX XXXXb
DMA2 Source Select Register
DM2SL
00h
DMA3 Source Select Register
DM3SL
00h
DMA0 Source Select Register
DM0SL
00h
DMA1 Source Select Register
DM1SL
00h
X: Undefined
The blank areas are reserved. No access is allowed.
When the CSPROINI bit in the OFS1 address is 0, the reset value is 10000000b.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 34 of 90
M16C/6C Group
Table 4.16
4. Special Function Registers (SFRs)
SFR Information (16/21) (1)
Address
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
Note:
1.
Register
Symbol
Reset Value
SFR Snoop Address Register
CRCSAR
CRC Mode Register
CRCMR
XXXX XXXXb
00XX XXXXb
0XXX XXX0b
CRC Data Register
CRCD
CRC Input Register
CRCIN
A/D0 Register 0
AD00
A/D0 Register 1
AD01
A/D0 Register 2
AD02
A/D0 Register 3
AD03
A/D0 Register 4
AD04
A/D0 Register 5
AD05
A/D0 Register 6
AD06
A/D0 Register 7
AD07
XXh
XXh
XXh
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 35 of 90
M16C/6C Group
Table 4.17
4. Special Function Registers (SFRs)
SFR Information (17/21) (1)
Address
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
0400h to
D0FFh
Note:
1.
Register
Symbol
Reset Value
AD0TRGCON
XXXX 00XXb
A/D0 Control Register 2
AD0CON2
0000 X00Xb
A/D0 Control Register 0
A/D0 Control Register 1
D/A0 Register
AD0CON0
AD0CON1
DA0
0000 0XXXb
0000 X000b
00h
DA1
00h
DACON
XXXX XX00b
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
Port P10 Direction Register
PD10
00h
A/D0 Trigger Control Register
D/A1 Register
D/A Control Register
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 36 of 90
M16C/6C Group
Table 4.18
4. Special Function Registers (SFRs)
SFR Information (18/21) (1)
Address
Register
Symbol
After Reset
D100h
USB interrupt flag register 0
USBIFR0
00h
D101h
USB interrupt flag register 1
USBIFR1
XXX00000b
D102h
USB interrupt flag register 2
USBIFR2
XX000110b
D103h
USB interrupt flag register 3
USBIFR3
XX000110b
D104h
D105h
D106h
D107h
D108h
USB interrupt enable register 0
USBIER0
000000X0b
D109h
USB interrupt enable register 1
USBIER1
XXX00000b
D10Ah
USB interrupt enable register 2
USBIER2
XX000000b
D10Bh
USB interrupt enable register 3
USBIER3
XX000000b
D110h
USB interrupt select register 0
USBISR0
00X000X0b
D111h
USB interrupt select register 1
USBISR1
XXX00000b
D112h
USB interrupt select register 2
USBISR2
XX000000b
D113h
USB interrupt select register 3
USBISR3
XX000000b
D10Ch
D10Dh
D10Eh
D10Fh
D114h
D115h
D116h
D117h
D118h
D119h
D11Ah
D11Bh
D11Ch
D11Dh
D11Eh
D11Fh
D120h
USB endpoint 0 IN data register
USBEPDR0I
XXh
USB endpoint 0 OUT data register
USBEPDR0O
00h
USB endpoint 0 S data register
USBEPDR0S
00h
D121h
D122h
D123h
D124h
D125h
D126h
D127h
D128h
D129h
D12Ah
D12Bh
D12Ch
D12Dh
D12Eh
D12Fh
X: Undefined
Note:
1.
Blanks are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 37 of 90
M16C/6C Group
Table 4.19
4. Special Function Registers (SFRs)
SFR Information (19/21) (1)
Address
D130h
Register
Symbol
After Reset
USB endpoint 1 data register
USBEPDR1
00h
USB endpoint 2 data register
USBEPDR2
XXh
USB endpoint 3 data register
USBEPDR3
XXh
USB endpoint 4 data register
USBEPDR4
00h
USB endpoint 5 data register
USBEPDR5
XXh
USB endpoint 6 data register
USBEPDR6
XXh
D180h
USB endpoint 0 OUT receive data size register
USBEPSZ0O
000XXXXXb
D181h
USB endpoint 1 receive data size register
USBEPSZ1
0XXXXXXXb
D182h
USB endpoint 4 receive data size register
USBEPSZ4
0XXXXXXXb
D131h
D132h
D133h
D134h
D135h
D136h
D137h
D138h
D139h
D13Ah
D13Bh
D13Ch
D13Dh
D13Eh
D13Fh
D140h
D141h
D142h
D143h
D144h
D145h
D146h
D147h
D148h
D149h
D14Ah
D14Bh
D14Ch
D14Dh
D14Eh
D14Fh
D150h to
D17Fh
D183h
D184h
D185h
D186h
D187h
D188h
USB data status register 0
USBDASTS0
XXXXXXX0b
D189h
USB data status register 1
USBDASTS1
XXXXX00Xb
D18Ah
USB data status register 2
USBDASTS2
XXXXX00Xb
D18Bh
D18Ch
D18Dh
D18Eh
D18Fh
X: Undefined
Note:
1.
Blanks are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 38 of 90
M16C/6C Group
Table 4.20
4. Special Function Registers (SFRs)
SFR Information (20/21) (1)
Address
Register
Symbol
After Reset
D190h
USB trigger register 0
USBTRG0
XXh
D191h
USB trigger register 1
USBTRG1
XXh
D192h
USB trigger register 2
USBTRG2
XXh
D198h
USB FIFO clear register 0
USBFCLR0
XXh
D199h
USB FIFO clear register 1
USBFCLR1
XXh
D19Ah
USB FIFO clear register 2
USBFCLR2
XXh
D193h
D194h
D195h
D196h
D197h
D19Bh
D19Ch
D19Dh
D19Eh
D19Fh
D1A0h
USB endpoint stall register 0
USBEPSTL0
XXXXXXX0b
D1A1h
USB endpoint stall register 1
USBEPSTL1
XXXXX000b
D1A2h
USB endpoint stall register 2
USBEPSTL2
XXXXX000b
D1A9h
USB stall status register 1
USBSTLSR1
X000X000b
D1AAh
USB stall status register 2
USBSTLSR2
X000X000b
USBDMAR
XXX00X00b
USB configuration value register
USBCVR
0000X000b
USB control register
USBCTLR
0XX00001b
D1A3h
D1A4h
D1A5h
D1A6h
D1A7h
D1A8h
D1ABh
D1ACh
D1ADh
D1AEh
D1AFh
D1B0h
USB DMA transfer setting register
D1B1h
D1B2h
D1B3h
D1B4h
D1B5h
D1B6h
D1B7h
D1B8h
D1B9h
D1BAh
D1BBh
D1BCh
D1BDh
D1BEh
D1BFh
X: Undefined
Note:
1.
Blanks are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 39 of 90
M16C/6C Group
Table 4.21
4. Special Function Registers (SFRs)
SFR Information (21/21) (1)
Address
D1C0h
Register
USB endpoint information register
Symbol
USBEPIR
After Reset
XXh
D1C1h
D1C2h
D1C3h
D1C4h
D1C5h
D1C6h
D1C7h
D1C8h
D1C9h
D1CAh
D1CBh
D1CCh
USB module control register
D1CDh
D1CEh
D1CFh
X: Undefined
Note:
1.
Blanks are reserved. No access is allowed.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 40 of 90
USBMC
11X10XX0b
M16C/6C Group
4.2
4. Special Function Registers (SFRs)
Notes on SFRs
4.2.1
Register Settings
Table 4.22 lists Registers with Write-Only Bits and registers whose function differs between reading and
writing. Set these registers with immediate values. When establishing the next value by altering the
existing value, write the existing value to the RAM as well as to the register. Transfer the next value to
the register after making changes in the RAM.
Table 4.22
Registers with Write-Only Bits
Register
Symbol
Address
Watchdog Timer Refresh Register
WDTR
037Dh
Watchdog Timer Start Register
WDTS
037Eh
Timer A0 Register
TA0
0327h to 0326h
Timer A1 Register
TA1
0329h to 0328h
Timer A2 Register
TA2
032Bh to 032Ah
Timer A3 Register
TA3
032Dh to 032Ch
Timer A4 Register
TA4
032Fh to 032Eh
Timer A1-1 Register
TA11
0303h to 0302h
Timer A2-1 Register
TA21
0305h to 0304h
Timer A4-1 Register
TA41
0307h to 0306h
Three-Phase Output Buffer Register 0
IDB0
030Ah
Three-Phase Output Buffer Register 1
IDB1
030Bh
Dead Time Timer
DTT
030Ch
ICTB2
030Dh
Timer B2 Interrupt Generation Frequency Set Counter
UART0 Bit Rate Register
U0BRG
0249h
UART1 Bit Rate Register
U1BRG
0259h
UART2 Bit Rate Register
U2BRG
0269h
UART3 Bit Rate Register
U3BRG
02A9h
UART4 Bit Rate Register
U4BRG
0299h
UART5 Bit Rate Register
U5BRG
0289h
UART0 Transmit Buffer Register
U0TB
024Bh to 024Ah
UART1 Transmit Buffer Register
U1TB
025Bh to 025Ah
UART2 Transmit Buffer Register
U2TB
026Bh to 026Ah
UART3 Transmit Buffer Register
U3TB
02ABh to 02AAh
UART4 Transmit Buffer Register
U4TB
029Bh to 029Ah
UART5 Transmit Buffer Register
U5TB
028Bh to 028Ah
I2C0 control register 1
S3D0
02B6h
S10
02B8h
I2C0 status register
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 41 of 90
M16C/6C Group
Table 4.23
4. Special Function Registers (SFRs)
Registers with Write-Only Bits
Symbol
Address
USB endpoint 0 IN data register
Register
USBEPDR0I
D120h
USB endpoint 2 data register
USBEPDR2
D134h
USB endpoint 3 data register
USBEPDR3
D138h
USB endpoint 5 data register
USBEPDR5
D144h
USB endpoint 6 data register
USBEPDR6
D148h
USB trigger register 0
USBTRG0
D190h
USB trigger register 1
USBTRG1
D191h
USB Trigger Register 2
USBTRG2
D192h
USB FIFO Clear Register 0
USBFCLR0
D198h
USB FIFO Clear Register 1
USBFCLR1
D199h
USB FIFO Clear Register 2
USBFCLR2
D19Ah
USB Endpoint Stall Register 0
USBEPSTL0
D1A0h
USB Endpoint Stall Register 1
USBEPSTL1
D1A1h
USB Endpoint Stall Register 2
USBEPSTL2
D1A2h
USBEPIR
D1C0h
USB Endpoint Information Register
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 42 of 90
M16C/6C Group
5.
5. Electrical Characteristics
Electrical Characteristics
5.1
Electrical Characteristics (Common to 3 V and 5 V)
5.1.1
Table 5.1
Absolute Maximum Rating
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rated Value
Unit
−0.3 to 6.5
V
−0.3 to VCC1 + 0.1
V
−0.3 to 6.5
V
RESET, CNVSS
P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7
XIN, UVCC
−0.3 to VCC1 + 0.3
V
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7
−0.3 to VCC2 + 0.3
V
VCC1, VCC2 Supply voltage
VCC1 = AVCC
VCC2
Supply voltage
VCC2
AVCC
Analog supply voltage
VCC1 = AVCC
VI
Input voltage
P7_0, P7_1, P8_5
VO
Output voltage P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7
XOUT, UVCC
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7
P7_0, P7_1, P8_5
Pd
Power consumption
Topr
Operating
ambient
temperature
Tstg
When the microcomputer is operating
Flash program erase
Storage temperature
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 43 of 90
−40°C < Topr ≤ 85°C
−0.3 to 6.5
V
−0.3 to VCC1 + 0.3
V
−0.3 to VCC2 + 0.3
V
−0.3 to 6.5
V
300
mW
−20 to 85/−40 to 85
°C
0 to 60
−65 to 150
°C
M16C/6C Group
5.1.2
5. Electrical Characteristics
Recommended Operating Conditions
Table 5.2
Recommended Operating Conditions (1/3) (1)
Symbol
Standard
Parameter
VCC1,
VCC2
Supply voltage (VCC1 ≥ VCC2)
AVCC
Analog supply voltage
UVCC
USB Supply When USB function is used
Voltage
(When UVCC
pin is input) When USB function is not used
Unit
Min.
Typ.
Max.
When USB function is used
3.0
5.0
5.5
V
When USB function is not used
2.7
5.0
5.5
V
VCC1
V
VCC1 = 3.6 to 5.5V
3.0
3.3
3.6
V
VCC1 = 3.0 to 3.6V
3.0
-
VCC1
V
VCC2 = 2.7 to 5.5V
-
VCC1
-
V
VSS
Supply voltage
0
V
AVSS
Analog supply voltage
0
V
VIH
High input
voltage
VIL
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7
0.8VCC2
VCC2
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(in single-chip mode)
0.8VCC2
VCC2
V
P0_0 to P0_7, P2_0 to P2_7, P3_0
(data input in memory expansion and microprocessor
modes)
0.5VCC2
VCC2
V
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
XIN, RESET, CNVSS
0.8VCC1
VCC1
V
P7_0, P7_1, P8_5
0.8VCC1
6.5
V
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7
0
0.2VCC2
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(in single-chip mode)
0
0.2VCC2
V
P0_0 to P0_7, P2_0 to P2_7, P3_0
(data input in memory expansion and microprocessor
mode)
0
0.16VCC2
V
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
XIN, RESET, CNVSS
0
0.2VCC1
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7
−10.0
mA
High average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
output
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
current
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7
−5.0
mA
Low input
voltage
IOH(peak) High peak
output
current
IOH(avg)
Notes:
1. Referenced to VCC1 = VCC2 = 2.7 to 5.5 V at Topr = −20 to 85°C/-40 to 85°C unless otherwise specified.
2. The average output current is the mean value within 100 ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, and P10 must be 80 mA max. The total IOL(peak) for
ports P3, P4, P5, P6, P7, and P8_0 to P8_5 must be 80 mA max. The total IOH(peak) for ports P0, P1, and P2
must be −40 mA max. The total IOH(peak) for ports P3, P4, and P5 must be −40 mA max. The total IOH(peak) for
ports P6, P7_2 to P7_7 and P8_0 to P8_4 must be −40 mA max. IOH(peak) for ports P8_6, P8_7, P9, and P10
must be −40 mA max.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 44 of 90
M16C/6C Group
Table 5.3
5. Electrical Characteristics
Recommended Operating Conditions (2/3) (1)
Symbol
Standard
Parameter
Min.
Typ.
Max.
Unit
IOL(peak) Low peak
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
output current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
10.0
mA
IOL(avg)
Low average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
output current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
5.0
mA
f(XIN)
Main clock input oscillation frequency
16
MHz
f(XCIN)
Sub-clock oscillation frequency
50
kHz
f(PLL)
PLL clock oscillation frequency
10
32
MHz
f(BCLK)
CPU operation clock
fOCO-S
divided by
16
32
MHz
tSU(PLL)
PLL frequency synthesizer stabilization
wait time
VCC1 = 5.0 V
2
ms
VCC1 = 3.0 V
3
ms
VCC1 = 2.7 V to 5.5 V
2
32.768
VCC1 = 2.7 V to 5.5 V
Notes:
1. Referenced to VCC1 = VCC2 = 2.7 to 5.5 V at Topr = −20 to 85°C/-40 to 85°C unless otherwise specified.
2. The average output current is the mean value within 100 ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, and P10 must be 80 mA max. The total IOL(peak) for
ports P3, P4, P5, P6, P7, and P8_0 to P8_5 must be 80 mA max. The total IOH(peak) for ports P0, P1, and P2
must be −40 mA max. The total IOH(peak) for ports P3, P4, and P5 must be −40 mA max. The total IOH(peak) for
ports P6, P7_2 to P7_7 and P8_0 to P8_4 must be −40 mA max. IOH(peak) for ports P8_6, P8_7, P9, and P10
must be −40 mA max.
Table 5.4
Recommended Operating Conditions (3/3) (1, 2)
Supply ripple is to implement either Vr(VCC1) or dVr(VCC1)/dt, or both of them.
Symbol
Vr(VCC1)
dVr(VCC1)/dt
Standard
Parameter
Supply ripple available voltage
Supply ripple fall gradient
Min.
Typ.
Max.
Unit
VCC1 = 5.0 V
0.5
Vp-p
VCC1 = 3.0 V
0.3
Vp-p
VCC1 = 5.0 V
0.3
V/ms
VCC1 = 3.0 V
0.3
V/ms
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. Referenced to VCC1 = 2.7 to 5.5 V, VSS = 0V and at Topr = −20 to 85°C/-40 to 85°C unless otherwise specified.
VCC1
Figure 5.1
Ripple waveform
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 45 of 90
V r(VCC1)
M16C/6C Group
5.1.3
Table 5.5
5. Electrical Characteristics
A/D Conversion Characteristics
A/D Conversion Characteristics (1, 2, 3)
Symbol
Parameter
Measuring Condition
-
Resolution
INL
Integral non-linearity error 10bit
-
Absolute accuracy
10bit
Standard
Min.
Typ.
Max.
Unit
10
Bits
VCC1 = AN0 to AN7 input,
5.0 V AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
(4)
ANEX0, ANEX1 input
±3
LSB
VCC1 = AN0 to AN7 input,
3.3 V AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
(4)
ANEX0, ANEX1 input
±3
LSB
VCC1 = AN0 to AN7 input,
3.0 V AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
(4)
ANEX0, ANEX1 input
±3
LSB
VCC1 = AN0 to AN7 input,
5.0 V AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
(4)
ANEX0, ANEX1 input
±3
LSB
VCC1 = AN0 to AN7 input,
3.3 V AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
(4)
ANEX0, ANEX1 input
±3
LSB
VCC1 = AN0 to AN7 input,
3.0 V AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
(4)
ANEX0, ANEX1 input
±3
LSB
Notes:
1. Referenced to AVCC = VCC1 = VCC2 = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -20 to 85°C/-40 to 85°C
unless otherwise specified.
2. This applies when using one A/D converter, with the ADSTBY bit for the unused A/D converter set to 0 (A/D
operation stopped (standby)).
3. Use when AVCC = VCC1 = VCC2.
4. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and
connect them to VSS. See Figure 5.2 “A/D accuracy measure circuit”.
AN
Analog input
AN　:　One of the analog input pin
P0 to P10　： I/O pins other than AN
P0 to P10
Figure 5.2
A/D accuracy measure circuit
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 46 of 90
M16C/6C Group
Table 5.6
5. Electrical Characteristics
A/D Conversion Characteristics (1, 2, 3)
Symbol
φAD
Parameter
AD operation clock frequency
Measuring Condition
Standard
Min.
Typ.
Max.
Unit
4.0 V ≤ VREF ≤ AVCC ≤ 5.5 V
2
25
MHz
3.2 V ≤ VREF ≤ AVCC ≤ 5.5 V
2
16
MHz
3.0 V ≤ VREF ≤ AVCC ≤ 5.5 V
2
10
MHz
-
Tolerance level impedance
DNL
Differential non-linearity error
±1
LSB
-
Offset error
±3
LSB
-
Gain error
±3
LSB
tCONV
10-bit conversion time
tSAMP
VREF
VIA
3
1.60
μs
Sampling time
0.60
μs
Reference voltage
3.0
AVCC
V
0
VREF
V
Analog input
VCC1 = 5 V, φAD = 25 MHz
kΩ
voltage(4, 5)
Notes:
1. Referenced to AVCC = VCC1 = VCC2 = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -20 to 85°C/-40 to 85°C
unless otherwise specified.
2. This applies when using one A/D converter, with the ADSTBY bit for the unused A/D converter set to 0 (A/D
operation stopped (standby)).
3. Use when AVCC = VCC1 = VCC2.
4. Do not use A/D converter VCC1 > VCC2.
5.
When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.
5.1.4
Table 5.7
D/A Conversion Characteristics
D/A Conversion Characteristics (1)
Symbol
-
Parameter
Measuring Condition
Standard
Min.
Typ.
Resolution
-
Absolute Accuracy
tSU
Setup Time
RO
Output Resistance
IVREF
Reference Power Supply Input Current
5
Notes 2 and 3
6
Max.
Unit
8
Bits
2.5
LSB
3
μs
8.2
kΩ
1.5
mA
Notes:
1. Referenced to VCC1 = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -20 to 85°C/-40 to 85°C unless
otherwise specified.
2. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h.
3. The current consumption of the A/D converter is not included. Also, the IVREF of the D/A converter will flow even
if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 47 of 90
M16C/6C Group
5.1.5
5. Electrical Characteristics
USB Characteristics
Table 5.8
USB Characteristics (1)
Symbol
VIH
VIL
Input
Characteristics
Parameter
Measuring Condition
HIGH Input Voltage
Figure 5.3, Figure 5.4
Standard
Unit
Min.
Typ.
Max.
2.0
-
-
V
-
-
0.8
V
LOW Input Voltage
VDI
Differential Input Sensitivity
0.2
-
-
V
VCM
Differential Common Mode
Range
0.8
-
2.5
V
VOH
HIGH Output Voltage
Figure 5.3, Figure 5.4
IOH = 200 μA
2.8
-
-
V
VOL
LOW Output Voltage
Figure 5.3, Figure 5.4
IOL = 2 mA
-
-
0.3
V
VCRS
Crossover Voltage
Figure 5.3, Figure 5.4
1.3
-
2.0
V
tR
Rise Time
Figure 5.3, Figure 5.4
4.0
-
20.0
ns
tF
Fall Time
Figure 5.3, Figure 5.4
4.0
-
20.0
ns
tRFM
Rise Time / Fall Time
Matching
Figure 5.3, Figure 5.4
(tR/tF)
90.0
-
111.1
%
ZDRV
Output Resistance
Figure 5.3, Figure 5.4
Includes Rs = 27 Ω
VCC1 = 4.0 to 5.5V, PXXCON = VDDUSBE = 1
28.0
-
44.0
Ω
3.0
3.3
3.6
V
-
VCC1
-
V
UVCC
Isusp
Output
Characteristics
UVCC Output
Voltage
PXXCON = 0
Consumption current of the Internal Power
Supply for USB
VCC1 = 4.0 to 5.5 V
UVCC - VSS 0.33 μF
VCC1 - VSS 0.1 μF
50
μA
Notes:
1.
Referenced to VCC1 = 3.0 to 5.5 V, UVCC = 3.0 to 3.6 V, at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified.
Rising time
D+ D-
90 %
VCRS
Falling time
90 %
10 %
10 %
tR
Figure 5.3
Data Signal Timing Diagram
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 48 of 90
tF
Differential
Date Lines
M16C/6C Group
5. Electrical Characteristics
D+
D-
Figure 5.4
Load Condition
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 49 of 90
RS = 27 Ω
RS = 27 Ω
Test point
Test point
M16C/6C Group
5.1.6
5. Electrical Characteristics
Flash Memory Electrical Characteristics
Table 5.9
CPU Clock When Operating Flash Memory (f(BCLK))
Symbol
Parameter
-
CPU rewrite mode
f(SLO
W_R)
Conditions
Standard
Min.
Typ.
Max.
Unit
10 (1)
MHz
Slow read mode
5(3)
MHz
-
Low current consumption read mode
35
kHz
-
Data flash read
2.7 V ≤ VCC1 ≤ 3.0 V
3.0 V < VCC1 ≤ 5.5 V
16
(2)
MHz
20
(2)
MHz
Notes:
1. Set the PM17 bit in the PM1 register to 1 (one wait).
2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in
the PM1 register to 1 (one wait)
3. Set the PM17 bit in the PM1 register to 1(one wait). A wait is not necessary when using 125 kHz on-chip
oscillator clock or sub clock as the CPU clock source.
Table 5.10
Symbol
Flash Memory (Program ROM 1, 2) Electrical Characteristics
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
-
Program/erase cycles (2, 4, 5)
VCC1 = 3.3 V, Topr = 25°C
-
Two words program time
VCC1 = 3.3 V, Topr = 25°C
150
4000
μs
-
Lock bit program time
VCC1 = 3.3 V, Topr = 25°C
70
3000
μs
-
Block erase time
VCC1 = 3.3 V, Topr = 25°C
0.2
3.0
s
-
Program, erase voltage
2.7
5.5
V
-
Read voltage
2.7
5.5
V
-
Program, erase temperature
0
60
°C
tPS
Flash Memory Circuit Stabilization Wait Time
50
μs
-
Data hold time
(7)
Ambient temperature = 55°C
1,000 (3)
times
20
year
Notes:
1. VCC1 = 2.7 to 5.5 V at Topr = 0 to 60°C (option: -40°C to 85°C), unless otherwise specified.
2. Definition of program and erase cycles
The program and erase cycles refer to the number of per-block erasures.
If the program and erase cycles are n (n=1,000), each block can be erased n times.
For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this
counts as one program and erase cycles. Data cannot be written to the same address more than once without
erasing the block (rewrite prohibited).
3. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be
minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to
retain data on the erasure cycles of each block and limit the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support
representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 50 of 90
M16C/6C Group
Table 5.11
5. Electrical Characteristics
Flash Memory (Data Flash) Electrical Characteristics
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
-
Program/erase cycles (2, 4, 5)
VCC1 = 3.3 V, Topr = 25°C
-
Two words program time
VCC1 = 3.3 V, Topr = 25°C
300
4000
μs
-
Lock bit program time
VCC1 = 3.3 V, Topr = 25°C
140
3000
μs
-
Block erase time
VCC1 = 3.3 V, Topr = 25°C
0.2
3.0
s
-
Program, erase voltage
2.7
5.5
V
-
Read voltage
2.7
5.5
V
-
Program, erase temperature
0
60
°C
tPS
Flash Memory Circuit Stabilization Wait Time
50
μs
-
Data hold
time (7)
Ambient temperature = 55 °C
10,000 (3)
times
20
year
Notes:
1. VCC1 = 2.7 to 5.5 V at Topr = 0 to 60°C unless otherwise specified.
2. Definition of program and erase cycles
The program and erase cycles refer to the number of per-block erasures.
If the program and erase cycles are n (n=10,000), each block can be erased n times.
For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this
counts as one program and erase cycles. Data cannot be written to the same address more than once without
erasing the block (rewrite prohibited).
3. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be
minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the
erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain
data on the erasure cycles of each block and limit the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support
representative.
7.
The data hold time includes time that the power supply is off or the clock is not supplied.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 51 of 90
M16C/6C Group
5.1.7
Table 5.12
Symbol
Vdet0
5. Electrical Characteristics
Voltage Detection
Characteristics
Circuit
and
Power
Supply
Circuit
Electrical
Voltage Detection 0 Circuit Electrical Characteristics
Parameter
Condition
Voltage detection level Vdet0_0 (2)
Voltage detection level Vdet0_2 (2)
-
Voltage detection 0 circuit response
-
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit
operation starts (3)
time(4)
At the falling of VCC from 5 V
to (Vdet 0_0 - 0.1)V
Standard
Unit
Min.
Typ.
Max.
1.60
1.90
2.20
V
2.70
2.85
3.15
V
-
-
200
μs
VC25 = 1, VCC1 = 5.0 V
μA
1.5
100
μs
Notes:
1.
The measurement condition is Topr = −20 to 85°C/−40 to 85°C.
2.
Select the voltage detection level with the VDSEL1 bit in the OFS1 address.
3.
Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VC25 bit in the VCR2
register to 0.
4.
Necessary time until the voltage monitor 0 reset generates after passing through Vdet0.
Table 5.13
Symbol
Voltage Detection 1 Circuit Electrical Characteristics
Parameter
Condition
Vdet1
Voltage detection level Vdet1
-
Hysteresis width at the rising of VCC of Voltage
detection 1 circuit
-
Voltage detection 1 circuit response time(2)
At the falling of VCC from
5 V to (Vdet 1 - 0.1)V
-
Voltage detection circuit self power consumption
VC26 = 1, VCC1 = 5.0 V
td(E-A)
Waiting time until voltage detection circuit operation
starts (3)
When VCC is falling
Standard
Unit
Min.
Typ.
Max.
2.95
3.25
3.55
V
-
0.15
-
V
-
-
200
μs
μA
1.7
100
μs
Notes:
1.
The measurement condition is Topr = −20 to 85°C/−40 to 85°C.
2.
Necessary time until the voltage monitor 1 interrupt request generates after passing through Vdet1.
3.
Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VC26 bit in the VCR2
register to 0.
Table 5.14
Symbol
Voltage Detection 2 Circuit Electrical Characteristics
Parameter
Condition
Vdet2
Voltage detection level Vdet2
-
Hysteresis width at the rising of VCC in voltage detection
2 circuit
-
Voltage detection 2 circuit response time(2)
At the falling of VCC from
5 V to (Vdet 2 - 0.1)V
-
Voltage detection circuit self power consumption
VC27 = 1, VCC1 = 5.0 V
td(E-A)
Waiting time until voltage detection circuit operation
starts (2)
When VCC is falling
Standard
Unit
Min.
Typ.
Max.
3.70
4.00
4.30
V
-
0.15
-
V
-
-
200
μs
μA
1.7
100
μs
Notes:
1.
The measurement condition is Topr = −20 to 85°C/−40 to 85°C.
2.
Necessary time until the voltage monitor 2 interrupt request generates after passing through Vdet2
3.
Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VC27 bit in the VCR2
register to 0.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 52 of 90
M16C/6C Group
Table 5.15
Symbol
trth
5. Electrical Characteristics
Power-On Reset Circuit
Parameter
External power VCC1 rise gradient
Condition
VCC1 = 2.0 to 5.5V
Standard
Min.
2.0
Typ.
Max.
50000
Unit
mV/ms
Notes:
1.
The measurement condition is Topr = −20 to 85°C/ −40 to 85°C, unless otherwise specified.
2.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address to 0.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 53 of 90
M16C/6C Group
5. Electrical Characteristics
Vdet0 (1)
External Power VCC1
Vdet0 (1)
t rth
t rth
0.1 V
Voltage detection 0
circuit response time
tw(por) (2)
Internal
reset signal
1
1
× 32
× 32
fOCO-S
fOCO-S
Notes:
1.
Vdet0 indicates the voltage detection level of the voltage detection 0 circuit.
2.
When using power-on reset, hold the external power VCC1 at or below the valid voltage (0.1 V) during tw(por), and
then turn it on.
tw(por) is 30 s or more when -20 °C ≤ Topr ≤ 85 °C, and 3000 s or more when -40 °C ≤ Topr < -20 °C.
Figure 5.5
Power-On Reset Circuit Electrical Characteristics
Table 5.16
Power Supply Circuit Timing Characteristics
Symbol
Parameter
td(P-R)
Internal power supply stability time when power is on (2)
td(R-S)
td(W-S)
Condition
Standard
Min.
Typ.
Max.
Unit
5
ms
STOP release time
150
μs
Low power mode wait mode release time
150
μs
Notes:
1. The measurement condition is VCC1 = 2.7 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes when power is on.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 54 of 90
M16C/6C Group
5. Electrical Characteristics
Recommended
operation voltage
td(P-R)
Internal power supply stability
time when power is on
Vcc1
td(P-R)
CPU clock
td(R-S)
STOP release time
td(W-S)
Low power mode
wait mode release time
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
CPU clock
(a)
(b)
td(E-A)
Voltage detector
operation start time
td(R-S)
td(W-S)
VC25, VC26, VC27
Voltage detector
Stop
Operate
td(E-A)
Figure 5.6
Power Supply Circuit Timing Diagram
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 55 of 90
M16C/6C Group
5.1.8
5. Electrical Characteristics
Oscillation Circuit Electrical Characteristics
Table 5.17
Symbol
40 MHz On-Chip Oscillator Circuit Electrical Characteristics
Standard
Parameter
Condition
fOCO40M
40 MHz on-chip oscillator frequency
Average frequency in a 10 ms period
2.7 V ≤ VCC1 < 5.5 V
tsu(fOCO40M)
Wait time until 40 MHz on-chip
oscillator stabilizes
Unit
Min.
Typ.
Max.
36
40
44
MHz
2
ms
Note:
1. VCC1 = 2.7 to 5.5 V, Topr = −20 to 85°C/−40 to 85°C, unless otherwise specified.
Table 5.18
Symbol
125 kHz On-Chip Oscillator Circuit Electrical Characteristics
Parameter
fOCO-S
125 kHz on-chip oscillator frequency
tsu(fOCO-S)
Wait time until 125 kHz on-chip oscillator
stabilizes
Condition
Average frequency in a
10 ms period
Standard
Typ.
Max.
100
125
150
kHz
20
μs
Note:
1. VCC1 = 2.7 to 5.5 V, Topr = −20 to 85°C/−40 to 85°C, unless otherwise specified.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 56 of 90
Unit
Min.
M16C/6C Group
5.2
5. Electrical Characteristics
Electrical Characteristics (VCC1 = VCC2 = 5 V)
5.2.1
Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.19
Electrical Characteristics (1)
Symbol
VOH
VOH
VOH
VOL
VOL
VOL
(1, 2)
Measuring
Condition
Parameter
Standard
Min.
Typ. Max.
High output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
voltage
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
IOH = −5 mA
VCC1 − 2.0
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
IOH = −5 mA
VCC2 − 2.0
VCC2
High output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
voltage
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
IOH = −200 μA
VCC1 − 0.3
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
IOH = −200 μA
VCC2 − 0.3
VCC2
IOH = −1 mA
VCC1 − 2.0
VCC1
VCC1 − 2.0
High output voltage
XOUT
HIGHPOWER
LOWPOWER
IOH = −0.5 mA
High output voltage
XCOUT
HIGHPOWER
With no load
applied
2.6
LOWPOWER
With no load
applied
2.2
2.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
IOL = 5 mA
2.0
Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
voltage
P9_0 to P9_7, P10_0 to P10_7
IOL = 200 μA
0.45
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
IOL = 200 μA
0.45
HIGHPOWER
IOL = 1 mA
2.0
LOWPOWER
IOL = 0.5 mA
2.0
HIGHPOWER
With no load
applied
0
LOWPOWER
With no load
applied
0
Low output voltage
XCOUT
V
V
V
IOL = 5 mA
XOUT
V
VCC1
Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
voltage
P9_0 to P9_7, P10_0 to P10_7
Low output voltage
Unit
V
V
V
V
Notes:
1. Referenced to VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C unless otherwise
specified.
2. When VCC1 ≠ VCC2, refer to 5 V or 3 V standard depending on the voltage.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 57 of 90
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.20
Electrical Characteristics (2)
Symbol
(1, 2)
Parameter
Measuring
Condition
Standard
Min.
Typ. Max.
Unit
VT+ - VT- Hysteresis
HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
INT0 to INT7, NMI, ADTRG, CTS0 to CTS5,
SCL0 to SCL5, SDA0 to SDA5, CLK0 to CLK5,
TA0OUT to TA4OUT, KI0 to KI3,
RXD0 to RXD5, SD, SCLMM, SDAMM
0.5
2.0
V
VT+ - VT- Hysteresis
RESET
0.5
2.5
V
IIH
High input
current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
XIN, RESET, CNVSS
VI = 5 V
5.0
μA
IIL
Low input
current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
XIN, RESET, CNVSS
VI = 0 V
−5.0
μA
RPULLUP Pull-up
resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
VI = 0 V
100
kΩ
RfXIN
Feedback resistance XIN
RfXCIN
Feedback resistance XCIN
VRAM
RAM retention voltage
In stop mode
30
1.8
50
1.5
MΩ
8
MΩ
V
Notes:
1. Referenced to VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C unless otherwise
specified.
2. When VCC1 ≠ VCC2, refer to 5 V or 3 V standard depending on the voltage.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 58 of 90
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.21
Symbol
ICC
Electrical Characteristics (3) (1)
Parameter
Power supply
current
Measuring Condition
High-speed
mode
f(BCLK) = 32 MHz
XIN = 4MHz (square wave),
PLL multiplied by 8
In single-chip,
125 kHz on-chip oscillator stop
mode, the output
f(BCLK) =32 MHz, A/D conversion(3)
pin are open and
XIN = 4 MHz (square wave),
other pins are VSS
PLL multiplied by 8
125 kHz on-chip oscillator stop
f(BCLK) = 16 MHz
XIN = 16MHz (square wave),
125 kHz on-chip oscillator stop
40 MHz on-chip Main clock stop
oscillator mode 40 MHz on-chip oscillator on, no division
125 kHz on-chip oscillator stop
125 kHz on-chip Main clock stop
oscillator Low40 MHz on-chip oscillator stop
power mode
125 kHz on-chip oscillator on, no division
FMR22 = 1
Low-power mode f(BCLK) = 32 kHz
In low-power mode,
FMR22 = FMR23 = 1
on flash memory (2)
f(BCLK) = 32 kHz
In low-power mode,
on RAM (2)
Wait mode
Main clock stop
40 MHz on-chip oscillator stop
125 kHz on-chip oscillator on
Peripheral clock operation
Topr = 25°C
Stop mode
Min.
Standard
Unit
Typ. Max.
27.0
mA
27.7
mA
13.0
mA
17.0
mA
500.0
μA
160.0
μA
45.0
μA
21.0
μA
f(XCIN) = 32 kHz (oscillation capacity High)
40 MHz on-chip oscillator stop
125 kHz on-chip oscillator stop
Peripheral clock operation
Topr = 25°C
11.0
μA
f(XCIN) = 32 kHz (oscillation capacity Low)
40 MHz on-chip oscillator stop
125 kHz on-chip oscillator stop
Peripheral clock operation
Topr = 25°C
6.0
μA
Main clock stop
40MHz on-chip oscillator stop
125 kHz on-chip oscillator stop
Peripheral clock stop
Topr = 25°C
2.2
μA
Notes:
1. Referenced to VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C, f(BCLK) = 32 MHz unless
otherwise specified.
2. This indicates the memory in which the program to be executed exists.
3. This applies when using one A/D converter (φAD=25MHz), with the ADSTBY bit for the unused A/D converter
set to 0 (A/D operation stopped (standby)).
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 59 of 90
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
5.2.2
Timing Requirements (Peripheral Functions and Others)
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Table 5.22
External Clock Input (XIN Input) (1)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc
External clock input cycle time
50
ns
tw(H)
External clock input high pulse width
20
ns
tw(L)
External clock input low pulse width
20
tr
External clock rise time
9
ns
tf
External clock fall time
9
ns
Note:
1.
ns
The condition is VCC1 = VCC2 = 3.0 to 5.0 V.
Table 5.23
Timer A Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
100
ns
tw(TAH)
TAiIN input high pulse width
40
ns
tw(TAL)
TAiIN input low pulse width
40
ns
Table 5.24
Timer A Input (Gating Input in Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
400
ns
tw(TAH)
TAiIN input high pulse width
200
ns
tw(TAL)
TAiIN input low pulse width
200
ns
Table 5.25
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
200
ns
tw(TAH)
TAiIN input high pulse width
100
ns
tw(TAL)
TAiIN input low pulse width
100
ns
Table 5.26
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(TAH)
TAiIN input high pulse width
100
ns
tw(TAL)
TAiIN input low pulse width
100
ns
Table 5.27
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
800
ns
tsu(TAIN-TAOUT)
TAiOUT input setup time
200
ns
tsu(TAOUT-TAIN)
TAiIN input setup time
200
ns
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 60 of 90
M16C/6C Group
5. Electrical Characteristics
VCC1 =
Timing Requirements
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Table 5.28
VCC2 = 5 V
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input high pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input low pulse width (counted on one edge)
40
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
200
ns
tw(TBH)
TBiIN input high pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN input low pulse width (counted on both edges)
80
ns
Table 5.29
Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high pulse width
200
ns
tw(TBL)
TBiIN input low pulse width
200
ns
Table 5.30
Timer B Input (Pulse Width Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high pulse width
200
ns
tw(TBL)
TBiIN input low pulse width
200
ns
Table 5.31
Serial Interface
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input high pulse width
100
ns
tw(CKL)
CLKi input low pulse width
100
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi hold time
0
ns
tsu(D-C)
RXDi input setup time
70
ns
th(C-D)
RXDi input hold time
90
ns
Table 5.32
External Interrupt INTi Input
Symbol
ns
80
Parameter
Standard
Min.
Max.
ns
Unit
tw(INH)
INTi input high pulse width
250
ns
tw(INL)
INTi input low pulse width
250
ns
Table 5.33
Reset Input (RESET Input)
Symbol
tw(RSTL)
Parameter
RESET input low pulse width
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 61 of 90
Standard
Min.
10
Max.
Unit
μs
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
VCC1 = VCC2 = 5 V
XIN input
tf
t w(H)
tr
t w(L)
tc
tc(TA)
t w(TAH)
TAiIN input
t w(TAL)
tc(UP)
t w(UPH)
TAiOUT input
t w(UPL)
Two-phase pulse input in event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
t w(TBH)
TBiIN input
t w(TBL)
Figure 5.7
Timing Diagram (1)
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 62 of 90
M16C/6C Group
5. Electrical Characteristics
VCC1=VCC2=5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
tsu(D-C)
td(C-Q)
RXDi
tw(INL)
INTi input
tw(INH)
RESET input
t w(RTSL)
Figure 5.8
Timing Diagram (2)
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 63 of 90
th(C-D)
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
5.2.3
Timing Requirements (Memory Expansion Mode and Microprocessor
Mode)
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Table 5.34
Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data input access time (for setting with no wait)
(Note 1)
ns
tac2(RD-DB)
Data input access time (for setting with 1 to 3 waits)
(Note 2)
ns
tac3(RD-DB)
Data input access time (when accessing multiplex bus area)
(Note 3)
ns
tsu(DB-RD)
Data input setup time
40
ns
tsu(RDY-BCLK)
RDY input setup time
30
ns
tsu(HOLD-BCLK)
HOLD input setup time
40
ns
th(RD-DB)
Data input hold time
0
ns
th(BCLK-RDY)
RDY input hold time
0
ns
th(BCLK-HOLD)
HOLD input hold time
0
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
---------------------- – 45 [ ns ]
f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
( n + 0.5 ) x 10
-------------------------------------- – 45 [ ns ]
f ( BCLK )
3.
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x 10
------------------------------------- – 45 [ ns ]
f ( BCLK )
n is 2 for 2 waits setting, and 3 for 3 waits setting.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 64 of 90
M16C/6C Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
VCC1 = VCC2 = 5 V
(Effective in wait state setting)
BCLK
RD
(Separate bus)
WR
(Separate bus)
RD
(Multiplexed bus)
WR
(Multiplexed bus)
RDY input
tsu(RDY-BCLK)
th(BCLK-RDY)
(Common to wait state and no wait state settings)
BCLK
tsu(HOLD-BCLK)
th(BCLK-HOLD)
HOLD input
HLDA input
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
td(BCLK-HLDA)
td(BCLK-HLDA)
Hi−Z
Note:
1. These pins are high-impedance regardless of PM06 bit in PM0 register and PM11 bit in PM1 register.
Measuring conditions
y VCC1 = VCC2 = 5 V
y Input timing voltage: VIL = 1.0 V, VIH = 4.0 V
y Output timing voltage: VOL = 2.5 V, VOH = 2.5 V
Figure 5.9
Timing Diagram
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 65 of 90
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
5.2.4
Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode (in No Wait State Setting))
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Table 5.35
Memory Expansion Mode and Microprocessor Mode (in No Wait State Setting)
Symbol
Measuring
Condition
Parameter
Standard
Min.
Max.
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
th(RD-AD)
Address output hold time (in relation to RD)
0
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 2)
ns
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
th(BCLK-DB)
Data output hold time (in relation to BCLK) (3)
td(DB-WR)
Data output delay time (in relation to WR)
th(WR-DB)
Data output hold time (in relation to WR)
td(BCLK-HLDA)
HLDA output delay time
25
0
ns
25
0
15
ns
25
ns
25
ns
ns
0
ns
0
(3)
ns
ns
−4
See
Figure 5.10
ns
ns
40
ns
0
ns
(Note 1)
ns
(Note 2)
ns
40
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
---------------------- – 40 [ ns ]
f ( BCLK )
2.
f(BCLK) is 12.5 MHz or less.
Calculated according to the BCLK frequency as follows:
9
0.5x10
---------------------- – 10 [ ns ]
3.
f ( BCLK )
This standard value shows the timing when the output is off, and does not
show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up (pull-down)
resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1−VOL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output
low level is
t = −30 pF × 1 k Ω × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 66 of 90
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DBi
C
M16C/6C Group
5. Electrical Characteristics
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
Figure 5.10
Ports P0 to P10 Measurement Circuit
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 67 of 90
30 pF
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Memory Expansion Mode and Microprocessor Mode
(in no wait state setting)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns(max.)
0ns(min.)
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns(max.)
ADi
BHE
td(BCLK-ALE)
15ns(max.)
0ns(min.)
th(BCLK-ALE)
-4ns(min.)
th(RD-AD)
0ns(min.)
ALE
th(BCLK-RD)
td(BCLK-RD)
25ns(max.)
0ns(min.)
RD
tac1(RD-DB)
(0.5 × tcyc -45)ns(max.)
Hi-Z
DBi
tsu(DB-RD)
th(RD-DB)
40ns(min.)
0ns(min.)
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns(max.)
0ns(min.)
CSi
tcyc
ADi
BHE
td(BCLK-AD)
th(BCLK-AD)
25ns(max.)
0ns(min.)
td(BCLK-ALE)
15ns(max.)
th(BCLK-ALE)
-4ns(min.)
th(WR-AD)
(0.5 × tcyc -10)ns(min.)
td(BCLK-WR)
th(BCLK-WR)
ALE
25ns(max.)
0ns(min.)
WR
td(BCLK-DB)
40ns(max.)
Hi-Z
DBi
td(DB-WR)
(0.5 × tcyc -40)ns(min.)
tcyc =
1
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 5 V
y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V
y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V
Figure 5.11
th(BCLK-DB)
0ns(min.)
Timing Diagram
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 68 of 90
th(WR-DB)
(0.5 × tcyc -10)ns(min.)
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
5.2.5
Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode (in 1 to 3 Waits Setting and When Accessing External Area))
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Table 5.36
Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When
Accessing External Area)
Symbol
Measuring
Condition
Parameter
Standard
Min.
Max.
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0
ns
th(RD-AD)
Address output hold time (in relation to RD)
0
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 2)
ns
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
25
25
ns
ns
-4
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
td(DB-WR)
0
See
Figure 5.10
RD signal output delay time
Data output hold time (in relation to BCLK)
ns
15
td(BCLK-RD)
th(BCLK-DB)
ns
ns
25
ns
0
ns
25
ns
0
(3)
ns
40
ns
0
ns
Data output delay time (in relation to WR)
(Note 1)
ns
th(WR-DB)
Data output hold time (in relation to WR)(3)
(Note 2)
ns
td(BCLK-HLDA)
HLDA output delay time
40
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x 10
------------------------------------- – 40 [ ns ]
f ( BCLK )
2.
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
When n = 1, f(BCLK) is 12.5 MHz or less.
Calculated according to the BCLK frequency as follows:
9
0.5x10
---------------------- – 10 [ ns ]
3.
f ( BCLK )
This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pullup (pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1 − VOL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1kΩ,
hold time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 69 of 90
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M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Memory Expansion Mode and Microprocessor Mode
(in 1 to 3 waits setting and when accessing external area)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns(max.)
0ns(min.)
CSi
tcyc
ADi
BHE
td(BCLK-AD)
th(BCLK-AD)
25ns(max.)
0ns(min.)
td(BCLK-ALE)
15ns(max.)
th(BCLK-ALE)
th(RD-AD)
-4ns(min.)
0ns(min.)
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns(min.)
25ns(max.)
tac2(RD-DB)
{(n+0.5) × t cyc - 45}ns(max.)
RD
Hi-Z
DBi
th(RD-DB)
tsu(DB-RD)
0ns(min.)
40ns(min.)
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns(max.)
0ns(min.)
CSi
tcyc
th(BCLK-AD)
td(BCLK-AD)
0ns(min.)
25ns(max.)
ADi
BHE
td(BCLK-ALE)
15ns(max.)
th(BCLK-ALE)
th(WR-AD)
-4ns(min.)
(0.5 × tcyc -10)ns(min.)
ALE
th(BCLK-WR)
td(BCLK-WR)
0ns(min.)
25ns(max.)
WR
td(BCLK-DB)
th(BCLK-DB)
40ns(max.)
0ns(min.)
Hi-Z
DBi
td(DB-WR)
{(n-0.5) × t cyc - 40}ns(min.)
tcyc =
(0.5 × tcyc -10)ns(min.)
1
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 5 V
y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V
y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V
Figure 5.12
th(WR-DB)
Timing Diagram
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 70 of 90
n: 1 (when 1 wait)
2 (when 2 waits)
3 (when 3 waits)
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
5.2.6
Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode (in 2 or 3 Waits Setting, and When Accessing External Area and
Using Multiplexed Bus))
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Table 5.37
Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus) (5)
Symbol
Parameter
Measuring
Condition
Standard
Min.
Max.
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0
ns
th(RD-AD)
Address output hold time (in relation to RD)
(Note 1)
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 1)
ns
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
th(RD-CS)
th(WR-CS)
25
25
ns
ns
0
ns
Chip select output hold time (in relation to RD)
(Note 1)
ns
Chip select output hold time (in relation to WR)
(Note 1)
ns
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
th(BCLK-DB)
Data output hold time (in relation to BCLK)
0
ns
td(DB-WR)
Data output delay time (in relation to WR)
(Note 2)
ns
th(WR-DB)
Data output hold time (in relation to WR)
(Note 1)
ns
25
ns
25
ns
40
ns
0
See
Figure 5.10
ns
0
ns
td(BCLK-HLDA)
HLDA output delay time
td(BCLK-ALE)
ALE signal output delay time (in relation to BCLK)
th(BCLK-ALE)
ALE signal output hold time (in relation to BCLK)
td(AD-ALE)
ALE signal output delay time (in relation to Address)
(Note 3)
ns
th(AD-ALE)
ALE signal output hold time (in relation to Address)
(Note 4)
ns
td(AD-RD)
RD signal output delay from the end of address
0
ns
td(AD-WR)
WR signal output delay from the end of address
0
tdz(RD-AD)
Address output floating start time
Notes:
1.
Calculated according to the BCLK frequency as follows:
9
0.5x10
---------------------- – 10 [ ns ]
f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
------------------------------------ – 40 [ ns ] n is 2 for 2-wait setting, 3 for 3-wait setting.
3.
Calculated according to the BCLK frequency as follows:
9
0.5x10
---------------------- – 25 [ ns ]
4.
Calculated according to the BCLK frequency as follows:
9
0.5x10
---------------------- – 15 [ ns ]
5.
When using multiplex bus, set f(BCLK) 12.5 MHz or less.
f ( BCLK )
f ( BCLK )
f ( BCLK )
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 71 of 90
40
ns
15
ns
−4
ns
ns
8
ns
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Memory Expansion Mode and Microprocessor Mode
(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus )
Read timing
BCLK
th(BCLK-CS)
td(BCLK-CS)
th(RD-CS)
tcyc
25ns(max.)
0ns(min.)
(0.5 × tcyc -10)ns(min.)
CSi
td(AD-ALE)
(0.5 × tcyc -25ns(min.)
ADi
/DBi
th(ALE-AD)
(0.5 × tcyc -15ns(min.)
Address
Address
Data input
tdz(RD-AD)
8ns(max.)
tsu(DB-RD)
tac3(RD-DB)
{(n-0.5) × tcyc -45}ns(max.) 40ns(min.)
th(RD-DB)
0ns(min.)
td(AD-RD)
td(BCLK-AD)
0ns(min.)
25ns(max.)
th(BCLK-AD)
0ns(min.)
ADi
BHE
td(BCLK-ALE)
15ns(max.)
th(BCLK-ALE)
th(RD-AD)
(0.5 × tcyc -10)ns(min.)
-4ns(min.)
ALE
td(BCLK-RD)
25ns(max.)
th(BCLK-RD)
0ns(min.)
RD
Write timing
BCLK
td(BCLK-CS)
tcyc
25ns(max.)
th(WR-CS)
(0.5 × tcyc -10)ns(min.)
th(BCLK-CS)
0ns(min.)
CSi
td(BCLK-DB)
th(BCLK-DB)
40ns(max.)
ADi
/DBi
Address
0ns(min.)
Address
Data output
td(DB-WR)
{(n-0.5) × t cyc - 40}ns(min.)
td(AD-ALE)
(0.5 × tcyc -25ns(min.)
th(WR-DB)
(0.5 × tcyc -10)ns(min.)
td(BCLK-AD)
th(BCLK-AD)
25ns(max.)
ADi
BHE
td(BCLK-ALE)
15ns(max.)
0ns(min.)
th(BCLK-ALE)
td(AD-WR)
-4ns(min.)
0ns(min.)
th(WR-AD)
(0.5 × tcyc -10)ns(min.)
ALE
th(BCLK-WR)
td(BCLK-WR)
25ns(max.)
0ns(min.)
WR
Measuring conditions
y VCC1 = VCC2 = 5 V
y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V
y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V
Figure 5.13
Timing Diagram
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 72 of 90
n: 2 (when 2 waits)
3 (when 3 waits)
M16C/6C Group
5.3
5. Electrical Characteristics
Electrical Characteristics (VCC1 = VCC2 = 3 V)
5.3.1
Electrical Characteristics
VCC1 = VCC2 = 3 V
Table 5.38
Electrical Characteristics (1)
Symbol
VOH
VOH
VOL
VOL
(1, 2)
Parameter
High
output
voltage
Measuring Condition
Typ.
Max.
P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7
IOH = −1 mA
VCC1 − 0.5
VCC1
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7
IOH = −1 mA
VCC2 − 0.5
VCC2
IOH = −0.1 mA
VCC1 − 0.5
VCC1
VCC1 − 0.5
High output voltage
XOUT
HIGHPOWER
LOWPOWER
IOH = −50 μA
High output voltage
XCOUT
HIGHPOWER
With no load applied
2.6
LOWPOWER
With no load applied
2.2
0.5
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7
IOL = 1 mA
0.5
HIGHPOWER
IOL = 0.1 mA
0.5
LOWPOWER
IOL = 50 μA
0.5
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
XOUT
XCOUT
VT+-VT- Hysteresis HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT7, NMI,
ADTRG, CTS0 to CTS5, SCL0 to SCL5,
SDA0 to SDA5, CLK0 to CLK5,
TA0OUT to TA4OUT, KI0 to KI3,
RXD0 to RXD5, SD, SCLMM, SDAMM
VT+-VT- Hysteresis RESET
High input P0_0 to P0_7, P1_0 to P1_7,
current
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
XIN, RESET, CNVSS
VI = 3 V
V
V
V
IOL = 1 mA
Low output voltage
Unit
VCC1
Low output P6_0 to P6_7, P7_0 to P7_7,
voltage
P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
Low output voltage
IIH
Standard
Min.
0
V
V
V
0
0.2
1.0
V
0.2
1.8
V
4.0
μA
Notes:
1. Referenced to VCC1 = VCC2 = 2.7 to 3.3 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C unless otherwise
specified.
2. When VCC1 ≠ VCC2, refer to 5 V or 3 V standard depending on the voltage.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 73 of 90
M16C/6C Group
Table 5.39
5. Electrical Characteristics
Electrical Characteristics (2) (1, 2)
Symbol
IIL
Parameter
Low input
current
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
XIN, RESET, CNVSS
RPULLUP Pull-up
P0_0 to P0_7, P1_0 to P1_7,
resistance P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7
Measuring Condition
Standard
Min.
Typ.
VI = 0 V
VI = 0 V
50
80
Max.
Unit
−4.0
μA
150
kΩ
RfXIN
Feedback resistance XIN
3.0
MΩ
RfXCIN
Feedback resistance XCIN
16
MΩ
VRAM
RAM retention voltage
In stop mode
1.8
V
Notes:
1. Referenced to VCC1 = VCC2 = 2.7 to 3.3 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C unless otherwise
specified.
2. When VCC1 ≠ VCC2, refer to 5 V or 3 V standard depending on the voltage.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 74 of 90
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
Table 5.40
Symbol
ICC
Electrical Characteristics (3)
Parameter
Power supply
current
(1)
Measuring Condition
High-speed
mode
f(BCLK) = 32 MHz
XIN = 4MHz (square wave),
PLL multiplied by 8
In single-chip,
125 kHz on-chip oscillator stop
mode, the output
f(BCLK) =32 MHz, A/D conversion(3)
pin are open and
XIN = 4 MHz (square wave),
other pins are VSS
PLL multiplied by 8
125 kHz on-chip oscillator stop
f(BCLK) = 16 MHz
XIN = 16MHz (square wave),
125 kHz on-chip oscillator stop
40 MHz on-chip Main clock stop
oscillator mode 40 MHz on-chip oscillator on, no division
125 kHz on-chip oscillator stop
125 kHz on-chip Main clock stop
oscillator Low40 MHz on-chip oscillator stop
power mode
125 kHz on-chip oscillator on, no division
FMR22 = 1
Low-power mode f(BCLK) = 32 kHz
In low-power mode,
FMR22 = FMR23 = 1
on flash memory (2)
f(BCLK) = 32 kHz
In low-power mode,
on RAM (2)
Wait mode
Main clock stop
40 MHz on-chip oscillator stop
125 kHz on-chip oscillator on
Peripheral clock operation
Topr = 25°C
Stop mode
Min.
Standard
Unit
Typ. Max.
27.0
mA
27.7
mA
13.0
mA
17.0
mA
450.0
μA
160.0
μA
40.0
μA
20.0
μA
f(XCIN) = 32 kHz (oscillation capacity High)
40 MHz on-chip oscillator stop
125 kHz on-chip oscillator stop
Peripheral clock operation
Topr = 25°C
8.0
μA
f(XCIN) = 32 kHz (oscillation capacity Low)
40 MHz on-chip oscillator stop
125 kHz on-chip oscillator stop
Peripheral clock operation
Topr = 25°C
6.0
μA
Main clock stop
40 MHz on-chip oscillator stop
125 kHz on-chip oscillator stop
Peripheral clock stop
Topr = 25°C
2.0
μA
Notes:
1. Referenced to VCC1 = VCC2 = 2.7 to 3.3 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C, f(BCLK) = 32 MHz unless
otherwise specified.
2. This indicates the memory in which the program to be executed exists.
3. This applies when using one A/D converter (φAD=25MHz), with the ADSTBY bit for the unused A/D converter
set to 0 (A/D operation stopped (standby)).
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 75 of 90
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
5.3.2
Timing Requirements (Peripheral Functions and Others)
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Table 5.41
External Clock Input (XIN Input) (1)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc
External clock input cycle time
50
ns
tw(H)
External clock input high pulse width
20
ns
tw(L)
External clock input low pulse width
20
tr
External clock rise time
9
ns
tf
External clock fall time
9
ns
Note:
1.
ns
The condition is VCC1 = VCC2 = 2.7 to 3.0 V.
Table 5.42
Timer A Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
150
ns
tw(TAH)
TAiIN input high pulse width
60
ns
tw(TAL)
TAiIN input low pulse width
60
ns
Table 5.43
Timer A Input (Gating Input in Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
600
ns
tw(TAH)
TAiIN input high pulse width
300
ns
tw(TAL)
TAiIN input low pulse width
300
ns
Table 5.44
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
300
ns
tw(TAH)
TAiIN input high pulse width
150
ns
tw(TAL)
TAiIN input low pulse width
150
ns
Table 5.45
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(TAH)
TAiIN input high pulse width
150
ns
tw(TAL)
TAiIN input low pulse width
150
ns
Table 5.46
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
2
μs
TAiOUT input setup time
500
ns
TAiIN input setup time
500
ns
tc(TA)
TAiIN input cycle time
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 76 of 90
M16C/6C Group
5. Electrical Characteristics
VCC1
Timing Requirements
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Table 5.47
= VCC2 = 3 V
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
150
ns
tw(TBH)
TBiIN input high pulse width (counted on one edge)
60
ns
tw(TBL)
TBiIN input low pulse width (counted on one edge)
60
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
300
ns
tw(TBH)
TBiIN input high pulse width (counted on both edges)
120
ns
tw(TBL)
TBiIN input low pulse width (counted on both edges)
120
ns
Table 5.48
Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
TBiIN input high pulse width
300
ns
tw(TBL)
TBiIN input low pulse width
300
ns
Table 5.49
Timer B Input (Pulse Width Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
TBiIN input high pulse width
300
ns
tw(TBL)
TBiIN input low pulse width
300
ns
Table 5.50
Serial Interface
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
300
ns
tw(CKH)
CLKi input high pulse width
150
ns
tw(CKL)
CLKi input low pulse width
150
ns
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi hold time
tsu(D-C)
160
ns
0
ns
RXDi input setup time
100
ns
th(C-D)
RXDi input hold time
90
ns
Table 5.51
External Interrupt INTi Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(INH)
INTi input high pulse width
380
ns
tw(INL)
INTi input low pulse width
380
ns
Table 5.52
Reset Input (RESET Input)
Symbol
tw(RSTL)
Parameter
RESET input low pulse width
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 77 of 90
Standard
Min.
10
Max.
Unit
μs
M16C/6C Group
5. Electrical Characteristics
VCC1 =
Timing Requirements
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
VCC2 = 3 V
VCC1 = VCC2 = 3 V
XIN input
tf
t w(H)
tr
t w(L)
tc
tc(TA)
t w(TAH)
TAiIN input
t w(TAL)
tc(UP)
t w(UPH)
TAiOUT input
t w(UPL)
Two-phase pulse input in event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
t w(TBH)
TBiIN input
t w(TBL)
Figure 5.14
Timing Diagram (1)
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 78 of 90
M16C/6C Group
5. Electrical Characteristics
VCC1=VCC2=3V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
tsu(D-C)
td(C-Q)
RXDi
tw(INL)
INTi input
tw(INH)
RESET input
t w(RTSL)
Figure 5.15
Timing Diagram (2)
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 79 of 90
th(C-D)
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
5.3.3
Timing Requirements (Memory Expansion Mode and Microprocessor
Mode)
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Table 5.53
Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data input access time (for setting with no wait)
(Note 1)
ns
tac2(RD-DB)
Data input access time (for setting with wait)
(Note 2)
ns
tac3(RD-DB)
Data input access time (when accessing multiplex bus area)
(Note 3)
ns
tsu(DB-RD)
Data input setup time
50
ns
tsu(RDY-BCLK)
RDY input setup time
40
ns
tsu(HOLD-BCLK)
HOLD input setup time
50
ns
th(RD-DB)
Data input hold time
0
ns
th(BCLK-RDY)
RDY input hold time
0
ns
th(BCLK-HOLD)
HOLD input hold time
0
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
---------------------- – 60 [ ns ]
f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
( n + 0.5 ) x10
-------------------------------------- – 60 [ ns ]
f ( BCLK )
3.
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
------------------------------------ – 60 [ ns ]
f ( BCLK )
n is 2 for 2 waits setting, 3 for 3 waits setting.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 80 of 90
M16C/6C Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
VCC1 = VCC2 = 3 V
(Effective in wait state setting )
BCLK
RD
(Separate bus)
WR
(Separate bus)
RD
(Multiplexed bus)
WR
(Multiplexed bus)
RDY input
tsu(RDY-BCLK)
th(BCLK-RDY)
(Common to wait state and no wait state settings)
BCLK
tsu(HOLD-BCLK)
th(BCLK-HOLD)
HOLD input
HLDA input
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
td(BCLK-HLDA)
td(BCLK-HLDA)
Hi−Z
Note:
1. These pins are high-impedance regardless PM06 bit in PM0 register, and PM11 bit in PM1 register.
Measuring conditions
y VCC1 = VCC2 = 3 V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.16
Timing Diagram
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 81 of 90
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
5.3.4
Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode (in No Wait State Setting))
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Table 5.54
Memory Expansion and Microprocessor Modes (in No Wait State Setting)
Symbol
Parameter
Measuring
Condition
Standard
Min.
Max.
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
th(RD-AD)
Address output hold time (in relation to RD)
0
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 2)
ns
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
th(BCLK-DB)
Data output hold time (in relation to BCLK) (3)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
HLDA output delay time
30
ns
0
ns
30
ns
0
ns
25
ns
−4
See
Figure 5.17
ns
30
ns
0
ns
30
ns
0
ns
40
ns
0
ns
Data output delay time (in relation to WR)
(Note 1)
ns
Data output hold time (in relation to WR) (3)
(Note 2)
ns
40
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
0.5 x 10
---------------------- – 40 [ ns ] f
f ( BCLK )
2.
f(BCLK) is 12.5 MHz or less.
Calculated according to the BCLK frequency as follows:
9
0.5 x 10
---------------------- – 10 [ ns ]
f ( BCLK )
This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t= −CR × ln(1 − VOL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ,
hold time of output low level is
t = −30 pF × 1 k Ω × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 82 of 90
R
DBi
C
M16C/6C Group
5. Electrical Characteristics
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
Figure 5.17
Ports P0 to P10 Measurement Circuit
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 83 of 90
30 pF
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
Memory Expansion Mode and Microprocessor Mode
(in no wait state setting)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns(max.)
0ns(min.)
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns(max.)
ADi
BHE
td(BCLK-ALE)
25ns(max.)
0ns(min.)
th(BCLK-ALE)
-4ns(min.)
th(RD-AD)
0ns(min.)
ALE
th(BCLK-RD)
td(BCLK-RD)
30ns(max.)
0ns(min.)
RD
tac1(RD-DB)
(0.5 × tcyc -60)ns(max.)
Hi-Z
DBi
tsu(DB-RD)
th(RD-DB)
50ns(min.)
0ns(min.)
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns(max.)
0ns(min.)
CSi
tcyc
ADi
BHE
td(BCLK-AD)
th(BCLK-AD)
30ns(max.)
0ns(min.)
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
-4ns(min.)
th(WR-AD)
(0.5 × tcyc -10)ns(min.)
td(BCLK-WR)
th(BCLK-WR)
ALE
30ns(max.)
0ns(min.)
WR
td(BCLK-DB)
40ns(max.)
Hi-Z
DBi
td(DB-WR)
(0.5 × tcyc -40)ns(min.)
tcyc =
1
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 3 V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.18
th(BCLK-DB)
0ns(min.)
Timing Diagram
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 84 of 90
th(WR-DB)
(0.5 × tcyc -10)ns(min.)
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
5.3.5
Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode (in 1 to 3 Waits Setting and When Accessing External Area))
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Table 5.55
Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When
Accessing External Area)
Symbol
Parameter
Measuring
Condition
Standard
Min.
Max.
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0
ns
th(RD-AD)
Address output hold time (in relation to RD)
0
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 2)
ns
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
th(BCLK-DB)
Data output hold time (in relation to BCLK) (3)
td(DB-WR)
30
ns
30
ns
0
ns
25
ns
-4
See
Figure 5.17
ns
30
ns
0
ns
30
ns
0
ns
40
ns
0
ns
Data output delay time (in relation to WR)
(Note 1)
ns
th(WR-DB)
Data output hold time (in relation to WR) (3)
(Note 2)
ns
td(BCLK-HLDA)
HLDA output delay time
40
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
( n – 0.5 ) x10
------------------------------------ – 40 [ ns ]
f ( BCLK )
2.
When n = 1, f(BCLK) is 12.5 MHz or less.
Calculated according to the BCLK frequency as follows:
9
0.5x10
---------------------- – 10 [ ns ]
f ( BCLK )
3.
This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pullup (pull-down) resistance value.
Hold time of data bus is expressed in
t=−CR × ln(1−VOL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ,
hold time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 85 of 90
R
DBi
C
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
Memory Expansion Mode and Microprocessor Mode
(in 1 to 3 waits setting and when accessing external area)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns(max.)
0ns(min.)
CSi
tcyc
ADi
BHE
td(BCLK-AD)
th(BCLK-AD)
30ns(max.)
0ns(min.)
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
th(RD-AD)
-4ns(min.)
0ns(min.)
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns(min.)
30ns(max.)
tac2(RD-DB)
{(n+0.5) × t cyc-60}ns(max.)
RD
tac2(RD-DB)
{(n+0.5) × t cyc-60}ns(max.)
Hi-Z
DBi
th(RD-DB)
tsu(DB-RD)
0ns(min.)
50ns(min.)
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns(max.)
0ns(min.)
CSi
tcyc
th(BCLK-AD)
td(BCLK-AD)
0ns(min.)
30ns(max.)
ADi
BHE
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
th(WR-AD)
-4ns(min.)
(0.5 × tcyc -10)ns(min.)
ALE
th(BCLK-WR)
td(BCLK-WR)
0ns(min.)
30ns(max.)
WR
td(BCLK-DB)
th(BCLK-DB)
40ns(max.)
0ns(min.)
Hi-Z
DBi
td(DB-WR)
{(n-0.5) × tcyc -40}ns(min.)
tcyc =
(0.5 × tcyc -10)ns(min.)
1
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 3 V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.19
th(WR-DB)
Timing Diagram
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 86 of 90
n: 1 (when 1 wait)
2 (when 2 waits)
3 (when 3 waits)
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
5.3.6
Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode (in 2 or 3 Waits Setting, and When Accessing External Area and
Using Multiplexed Bus))
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Table 5.56
Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus) (5)
Symbol
Parameter
Measuring
Condition
Standard
Min.
Max.
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0
ns
th(RD-AD)
Address output hold time (in relation to RD)
(Note 1)
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 1)
ns
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
th(RD-CS)
th(WR-CS)
50
50
ns
ns
0
ns
Chip select output hold time (in relation to RD)
(Note 1)
ns
Chip select output hold time (in relation to WR)
(Note 1)
ns
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
th(BCLK-DB)
Data output hold time (in relation to BCLK)
0
ns
td(DB-WR)
Data output delay time (in relation to WR)
(Note 2)
ns
th(WR-DB)
Data output hold time (in relation to WR)
(Note 1)
ns
40
ns
40
ns
50
ns
0
See
Figure 5.17
ns
0
ns
td(BCLK-HLDA)
HLDA output delay time
td(BCLK-ALE)
ALE signal output delay time (in relation to BCLK)
th(BCLK-ALE)
ALE signal output hold time (in relation to BCLK)
td(AD-ALE)
ALE signal output delay time (in relation to Address)
(Note 3)
ns
th(AD-ALE)
ALE signal output hold time (in relation to Address)
(Note 4)
ns
td(AD-RD)
RD signal output delay from the end of address
0
ns
td(AD-WR)
WR signal output delay from the end of address
0
tdz(RD-AD)
Address output floating start time
Notes:
1.
Calculated according to the BCLK frequency as follows:
9
0.5x10
---------------------- – 10 [ ns ]
f ( BCLK )
2.
3.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
n is 2 for 2 waits setting, 3 for 3 waits setting.
------------------------------------ – 50 [ ns ]
f ( BCLK )
Calculated according to the BCLK frequency as follows:
9
0.5x10
---------------------- – 40 [ ns ]
f ( BCLK )
4.
Calculated according to the BCLK frequency as follows:
9
0.5x10
---------------------- – 15 [ ns ]
f ( BCLK )
5.
When using multiplexed bus, set f(BCLK) 12.5 MHz or less.
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 87 of 90
40
ns
25
ns
−4
ns
ns
8
ns
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
Memory Expansion Mode and Microprocessor Mode
(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus )
Read timing
BCLK
th(BCLK-CS)
td(BCLK-CS)
th(RD-CS)
(0.5 × tcyc -10)ns(min.)
tcyc
50ns(max.)
0ns(min.)
CSi
td(AD-ALE)
(0.5 × tcyc -40ns(min.)
ADi
/DBi
th(ALE-AD)
(0.5 × tcyc -15ns(min.)
Address
Address
Data input
tdz(RD-AD)
8ns(max.)
tsu(DB-RD)
tac3(RD-DB)
{(n-0.5) × tcyc -60}ns(max.) 50ns(min.)
th(RD-DB)
0ns(min.)
td(AD-RD)
td(BCLK-AD)
0ns(min.)
50ns(max.)
th(BCLK-AD)
0ns(min.)
ADi
BHE
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
th(RD-AD)
(0.5 × tcyc -10)ns(min.)
-4ns(min.)
ALE
td(BCLK-RD)
40ns(max.)
th(BCLK-RD)
0ns(min.)
RD
Write timing
BCLK
td(BCLK-CS)
tcyc
50ns(max.)
th(WR-CS)
(0.5 × tcyc -10)ns(min.)
th(BCLK-CS)
0ns(min.)
CSi
td(BCLK-DB)
th(BCLK-DB)
50ns(max.)
ADi
/DBi
Address
0ns(min.)
Address
Data output
td(DB-WR)
{(n-0.5) × t cyc-50}ns(min.)
td(AD-ALE)
(0.5 × tcyc -40ns(min.)
th(WR-DB)
(0.5 × tcyc -10)ns(min.)
td(BCLK-AD)
th(BCLK-AD)
50ns(max.)
ADi
BHE
td(BCLK-ALE)
25ns(max.)
0ns(min.)
th(BCLK-ALE)
td(AD-WR)
-4ns(min.)
0ns(min.)
th(WR-AD)
(0.5 × tcyc -10)ns(min.)
ALE
th(BCLK-WR)
td(BCLK-WR)
40ns(max.)
0ns(min.)
WR
tcyc =
1
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 3 V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.20
Timing Diagram
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 88 of 90
n: 2 (when 2 waits)
3 (when 3 waits)
M16C/6C Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
The information on the latest package dimensions or packaging may be obtained from “Packages“ on the
Renesas Technology Web site.
JEITA Package Code
P-LQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
Previous Code
100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference Dimension in Millimeters
Symbol
c
E
*2
HE
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
26
1
ZE
Terminal cross section
100
25
Index mark
ZD
y
e
*3
bp
A1
c
A
A2
F
L
x
L1
Detail F
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 89 of 90
e
x
y
ZD
ZE
L
L1
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
M16C/6C Group
Appendix 1. Package Dimensions
JEITA Package Code
P-QFP100-14x20-0.65
RENESAS Code
PRQP0100JD-B
Previous Code
100P6F-A
MASS[Typ.]
1.8g
HD
*1
D
80
51
81
50
HE
*2
E
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
Reference Dimension in Millimeters
Symbol
100
31
30
c
F
A2
Index mark
ZD
A1
A
1
L
*3
e
y
bp
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 90 of 90
x
Detail F
D
E
A2
HD
HE
A
A1
bp
c
e
x
y
ZD
ZE
L
Min Nom Max
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.25 0.3 0.4
0.13 0.15 0.2
10°
0°
0.65
0.13
0.10
0.575
0.825
0.4 0.6 0.8
REVISION HISTORY
Rev.
Date
1.00
Jul 15, 2009
Page
-
M16C/6C Group Datasheet
Description
Summary
First Edition issued.
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