19-5810; Rev 0; 3/11 TION KIT EVALUA BLE IL AVA A Audio Amplifier with Jack Detection Features The MAX97236 is an audio amplifier with volume control and microphone preamplifier intended for use in portable audio systems employing a headphone jack. The audio circuit is powered from a single, dual-mode charge pump, allowing the output signals to be ground referenced, and eliminating the need for large and expensive DC-blocking capacitors. The configuration of a 3.5mm jack is determined by autoconfigure circuitry. The IC’s functional blocks are auto-enabled after the configuration of the jack is determined. S Microphone Amplifier and Bias The audio amplifier is powered from a single 1.8V power supply that reduces overall power consumption. The microphone preamplifier and bias are powered from a separate power-supply input accommodating bias voltages that are greater than 2.4V. S 25-Bump, 2.4mm x 2.3mm, 0.4mm Pitch WLP S 30mW Headphone Amplifier Employs SecondGeneration DirectDrive® with Dual-Mode ChargePump Architecture S Automatic Jack Detection Circuitry S 1.8V Power Supply S 2.4V to 3.6V Microphone Power Supply S Headphone Amplifier Volume Control S Decodes Data from a Passive Multibutton Headset Remote Control DirectDrive is a registered trademark of Maxim Integrated Products, Inc. The automatic jack detection determines when a 3.5mm plug is inserted into the system jack and determines the configuration of the installed load. The configuration of the load is then reported to the system through the I2C interface. Multiple popular jack and load configurations are detectable with this scheme. The IC detects headsets, headphones, and A/V cables. The headphone amplifier is capable of over 35mW into 16I. The device is available in a small, 25-bump WLP package with a 0.4mm pitch and is specified over the extended -40NC to +85NC temperature range. Applications Simplified Block Diagram 1.8V VDD 2.4V TO 3.0V MICVDD HPL TIP HPR RING1 Smartphones Mobile Handsets CHARGE PUMP Notebooks Portable Gaming Devices Tablets Ordering Information PART MAX97236EWA+ TEMP RANGE -40NC to +85NC PINPACKAGE RING2 MAX97236 I2C ADDRESS SDA 0x80 IRQ 25 WLP JACK DETECTION AND CONFIGURATION SCL I2C INTERFACE AND CONTROL SERIAL INTERFACE SLEEVE +Denotes a lead(Pb)-free/RoHS-compliant package. MOUTP MOUTN MIC JACKSW Functional Diagram/Typical Application Circuit appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX97236 General Description MAX97236 Audio Amplifier with Jack Detection ABSOLUTE MAXIMUM RATINGS MOUT+ and MOUT- to PGND...........-0.3V to (VMICVDD + 0.3V) C1P to PGND.........................................-0.3V to (VPVDD + 0.3V) C1N to PGND......................................... (VPVSS - 0.3V) to +0.3V SDA, SCL, EXTCLK, and IRQ to PGND...................-0.3V to +6V Output Short-Circuit Duration.....................................Continuous Continuous Power Dissipation (Mulitlayer Board, TA = +70NC) 25-Bump WLP (derate 19.2mW/NC above +70NC).....1536mW Junction Temperature......................................................+150NC Operating Temperature Range........................... -40NC to +85NC Storage Temperature Range............................. -65NC to +150NC Soldering Temperature (reflow).......................................+230NC VDD to PGND...........................................................-0.3V to +2V MICVDD to PGND.................................................-0.3V to +5.5V PVDD to PGND.......................................... -0.3V to (VDD + 0.3V) PVSS to PGND.........................................................-2V to +0.3V GND to PGND.......................................................-0.1V to +0.1V TIP, RING1, IN_ to PGND...................................... (VPVSS - 0.3V) to (VPVDD + 0.3V) RING2, SLEEVE to PGND....................................... (GND - 0.3V) to (VMICVDD + 0.3V) JACKSW to PGND............... (VPVSS - 0.3V) to (VMICVDD + 0.3V) MBIAS to PGND........................................ -0.3V to (VDD + 0.3V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) Junction-to-Ambient Thermal Resistance (qJA)...............52°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VDD = 1.8V, VMICVDD = 3.0V, VGND = VPGND = 0V, CFLY = CPVDD = CPVSS = 1FF. Typical values tested at TA = +25NC, unless otherwise noted. See the Functional Diagram/Typical Application Circuit.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.62 1.8 1.98 V 1.6 V GENERAL Supply Voltage Range VDD Undervoltage Lockout UVLO IVDD_SDF In jack detect mode, TA = +25NC, fast detect mode, external clock disabled 14 IVDD_SDS In jack detect mode, TA = +25NC, slow detect mode, external clock disabled 14 25 25 FA 2.3 3.9 mA Shutdown Supply Current Sleep Supply Current Quiescent Supply Current Guaranteed by PSRR test Rising VDD, TA = +25NC IVDD_SL IVDD TA = +25NC, state = LRGM SDA, SCL Input Logic-High VIH 1.8V logic compliant VIL 1.8V logic compliant SDA, SCL, EXTCLK Input Leakage Current High IIH TA = +25NC SDA, SCL, EXTCLK Input Leakage Current Low IIL TA = +25NC SDA, SCL Output Logic-Low VOLI2C IOLI2C = 2.3mA IRQ Output High Current IOH VIRQ_OUT = 3.3V, TA = +25NC IRQ Output Logic-Low VOL IOL = 3mA 2 FA TA = +25NC, external clock disabled SDA, SCL Input Logic-Low 25 1.4 V 0.4 V -1 +1 FA -1 +1 FA 0.2 x VDD V 1 FA 0.2 x VDD V Audio Amplifier with Jack Detection (VDD = 1.8V, VMICVDD = 3.0V, VGND = VPGND = 0V, CFLY = CPVDD = CPVSS = 1FF. Typical values tested at TA = +25NC, unless otherwise noted. See the Functional Diagram/Typical Application Circuit.) (Note 2) PARAMETER SYMBOL CONDITIONS EXTCLK Input High Voltage MIN TYP EXTCLK Frequency Range fEXTCLK TA = +25NC 1 D_EXTCLK TA = +25NC 45 Maximum EXTCLK Slew Rate Turn-On Time tON UNITS V EXTCLK Input Low Voltage EXTCLK Duty Cycle MAX 1.4 19.2 fEXTCLK = 1MHz, 0.4V to 1.4V 50 fEXTCLK = 10MHz, 0.4V to 1.4V 5 (Note 3) 1 0.4 V 26 MHz 55 % ns 10 ms JACK DETECTION Turn-On Time tONTIME Jack detect time from insertion to interrupt (Note 4) 500 ms AUDIO AMPLIFIER (Gain = 0dB, Unless Otherwise Noted) Output Offset Voltage Output Power Line Output Voltage Total Harmonic Distortion Plus Noise Signal-to-Noise Ratio Power-Supply Rejection Ratio VOS TA = +25NC, state = LRGM POUT RL = 32I, THD+N = 1%, fIN = 1kHz RL = 16I, THD+N = 1%, fIN = 1kHz 35 1 RL = 10kI THD+N RL = 16I, POUT = 10mW, fIN = 1kHz RL = 16I, POUT = 0.1mW, fIN = 1kHz RL = 10kI, VOUT = 1VRMS, fIN = 1kHz 0.04 Referenced to 32I load, 1VRMS input signal, A-weighted 103 Referenced to 32I load, 1VRMS input signal, A-weighted (gain = -30dB) 85 DC 1.62V to 1.98V, gain = 0dB, TA = +25NC 87 fIN = 217Hz, 100mVP-P ripple, gain = 0dB 78 fIN = 10kHz, 100mVP-P ripple, gain = 0dB 74 SNR PSRR VN Peak Output Current IOUT Minimum Headphone Impedance ZOUT Crosstalk +500 30 VO_LINE A-weighted Output Noise -500 XTALK FV mW VRMS 0.05 % 0.03 dB dB 6 A-weighted, gain = -30dB 1.7 A-weighted, gain = -60dB 1.4 Peak current needed to output the rated typical power 40 mA 12 I RL = 16I, fIN = 1kHz, POUT = 5mW, crosstalk between audio channels, gain = 0dB, with ground sense -51 RL = 32I, fIN = 1kHz, POUT = 25mW, crosstalk between audio channels, gain = 0dB, with ground sense -56 FVRMS dB 3 MAX97236 ELECTRICAL CHARACTERISTICS (continued) MAX97236 Audio Amplifier with Jack Detection ELECTRICAL CHARACTERISTICS (continued) (VDD = 1.8V, VMICVDD = 3.0V, VGND = VPGND = 0V, CFLY = CPVDD = CPVSS = 1FF. Typical values tested at TA = +25NC, unless otherwise noted. See the Functional Diagram/Typical Application Circuit.) (Note 2) PARAMETER Maximum Capacitive Load Drive SYMBOL CL Power Consumption CONDITIONS MIN 470 RL = 10kI, gain < 0dB 200 RL = 32I 200 POUT = 0.5mW, RL = 32I POUT = 4.5mW, RL = 32I, Per channel (Note 5) 4.5 KCP RL = 32I, peak voltage, A-weighted, 32 samples/second Input Capacitance CIN Gain = 6dB Input Impedance ZIN UNITS pF mW 23 Output voltage needed THSH = 0 to toggle the chargeTHSH = 1 pump outputs Click-and-Pop Level MAX 6.8 POUT = 20mW, RL = 32I, (Note 6) Charge-Pump Switch Threshold TYP RL = 10kI, gain R 0dB 0.4 V 0.55 Into shutdown -74 Out of shutdown -74 dBV 150 16 pF 75 kI AUDIO AMPLIFIER VOLUME CONTROL Gain Range +6 dB Maximum Volume Setting From min to max volume setting -60 5.5 6 6.5 dB Minimum Volume Setting -60.5 -60 -59.5 dB Mute Attenuation 80 Channel-to-Channel Gain Matching -0.5 Gain Change per Step dB +0.5 Volume setting -54dB P _VOL P 6dB 1 Volume setting -60dB P _VOL P -54dB 2 dB dB MICROPHONE BIAS MIC Bias Supply Voltage VMICVDD Bias Output Voltage VBIAS Bias Output Current IBIAS_OUT MIC Supply Current Consumption Bias Output Resistance Bias Output Noise 4 Guaranteed by MIC bias PSRR test 2.4 High output voltage 2.4 2.6 2.8 Low output voltage 1.84 2 2.16 RMICBIAS = 2.2kI, high (2.6V) output voltage, TA = +25NC 1.2 IMBIAS RMBIAS VN_BIAS 3.6 V V mA 150 400 MICR = 0b00, VMBIAS = 2.6V, TA = +25NC 2.02 2.2 2.38 MICR = 0b01, VMBIAS = 2.6V, TA = +25NC 2.39 2.6 2.81 MICR = 0b10, VMBIAS = 2.6V, TA = +25NC 2.76 3 3.24 FA kI MICR = 0b11, VMBIAS = 2.6V, TA = +25NC 0.07 With external capacitor, VMBIAS = 2.6V 2.8 FVRMS Audio Amplifier with Jack Detection (VDD = 1.8V, VMICVDD = 3.0V, VGND = VPGND = 0V, CFLY = CPVDD = CPVSS = 1FF. Typical values tested at TA = +25NC, unless otherwise noted. See the Functional Diagram/Typical Application Circuit.) (Note 2) PARAMETER Bias Power-Supply Rejection SYMBOL PSRRMBIAS CONDITIONS RMBIAS = 2.2kI VMICVDD = 2.4V to 3.6V, TA = +25NC MIN TYP 74 90 MAX UNITS dB fIN = 2kHz, 100mVP-P ripple 75 MICROPHONE PREAMPLIFIER MIC Preamp Gain AMIC Supply Current Consumption IDD_MAMP MIC Preamp Noise VN_MAMP Total Harmonic Distortion Plus Noise Gain = high, fIN = 997Hz 23 24 25 Gain = low, fIN = 997Hz 11 12 13 200 300 Input referred (Note 7), gain = 24dB, A-weighted 0.1kHz to 7kHz 3 THD+NMICPRE fIN = 1kHz, VIN = 1VRMS dB FA FV 3 % Low Corner Frequency Response f-3dB Relative to 997Hz 15 Hz High Corner Frequency Response f-3dB Relative to 997Hz > 300 kHz MIC Preamplifier Power-Supply Rejection PSRMAMP Output Common-Mode Voltage VCM_MIC VMICVDD = 2.4V to 3.6V, TA = +25NC, gain = +24dB, RMIC = 500I 74 90 fIN = 2kHz, 100mVP-P ripple (Note 7) 58 Voltage measured from MOUTP or MOUTN to GND 0.8 dB V Input Capacitance CMAMP AC-coupling capacitance 85 pF Input Resistance RMAMP Input resistance 100 MI 10 I Output Impedance ZOUT 6-BIT KEY ENCODER ADC 0.64 V Minimum ADC Course Range Level at which the mic bias must drop to trigger a conversion LSB 10mV 0.128 V Maximum ADC Course Range LSB 10mV 0.64 V Minimum ADC Fine Range LSB 2mV 0 V Maximum ADC Fine Range LSB 2mV 0.128 V ADC Trip Level CHARGE PUMP Oscillator Frequency fOSC1 fOSC2 VOUT = 0V, RL = open, TA = +25NC VOUT = 0.2V, RL = open 78 83 665 88 kHz ESD CHARACTERISTICS ESD Protection Pins connected to the jack: TIP, RING1, RING2, SLEEVE, JACKSW ±2 All other pins ±2 kV 5 MAX97236 ELECTRICAL CHARACTERISTICS (continued) MAX97236 Audio Amplifier with Jack Detection I2C TIMING CHARACTERISTICS (TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz Serial-Clock Frequency fSCL 0 Bus Free Time Between STOP and START Conditions tBUF 1.3 Fs tHD,STA 0.6 Fs SCL Pulse-Width Low tLOW 1.3 Fs SCL Pulse-Width High tHIGH 0.6 Fs Setup Time for a REPEATED START Condition tSU,STA 0.6 Fs Data Hold Time tHD,DAT 0 Data Setup Time tSU,DAT 100 SDA and SCL Receiving Rise Time tR 20 + 0.1CB 300 ns SDA and SCL Receiving Fall Time tF 20 + 0.1CB 300 ns SDA Transmitting Fall Time tF 20 + 0.1CB 250 ns tSU,STO 0.6 400 pF 50 ns Hold Time (REPEATED) START Condition Setup Time for STOP Condition Bus Capacitance CB Pulse Width of Suppressed Spike tSP 0 900 ns ns Fs Note 2: All specifications are 100% tested at TA = +25NC. Temperature limits are guaranteed by design. Note 3: The current listed tON is the time from the system sending the enable signal, after receiving the DDONE signal, to when the amplifier outputs turn on. Note 4: Total turn-on time from jack insert to output enable is dependent upon the search algorithm. Note 5: Power consumption numbers taken with the THRH bit set high, fixing the power-supply switchover threshold at its highest value. Note 6: Power consumption numbers taken with the high efficiency bit set low, fixing the power-supply switchover threshold at its lowest value, providing the least amount of dynamic distortion. Note 7: Tested with RMIC = 6kI in parallel with 5pF connected from SLEEVE to RING2. 6 Audio Amplifier with Jack Detection (VDD = 1.8V, VMICVDD = 3.0V, VGND = VPGND = 0V, CFLY = CPVDD = CPVSS = 1FF.) fIN = 100Hz fIN = 6kHz fIN = 1kHz 5 10 15 20 25 30 0.2 0 0.4 0.6 0.8 1.0 VOUT (VRMS) HEADPHONE AMPLIFIER THD+N vs. FREQUENCY OUTPUT POWER vs. LOAD RESISTANCE VOUT = 1VRMS 0.1 VOUT = 600mVRMS 0.01 0.001 0.1 1 10 45 40 35 20 6dB GAIN 20 0 -10 0dB GAIN -20 10 -30 5 -40 0 -50 100 1000 -30dB GAIN 0.01 0.1 1 10 100 1000 LOAD RESISTANCE (I) FREQUENCY (kHz) TOTAL POWER DISSIPATION vs. TOTAL OUTPUT POWER HEADPHONE CROSSTALK vs. FREQUENCY HEADPHONE AMPLIFIER POWER-SUPPLY REJECTION RATIO vs. FREQUENCY 60 CROSSTALK (dB) 16I 50 40 33I 30 RL = 32I POUT = 25mW FREQ = 1kHz 70 -30 60 -40 10 -60 0 -70 20 40 60 80 TOTAL OUTPUT POWER (mW) 100 VRIPPLE = 200mVP-P RL = 16I 80 -20 50 40 30 -50 20 90 PSRR (dB) 70 -10 100 MAX97236 toc08 0 MAX97236 toc07 80 MAX97236 toc09 FREQUENCY (kHz) 90 0 RL = 32I 30 1% THD+N 10 100 10 25 1 10 GAIN vs. FREQUENCY 30 100 1 40 10% THD+N 15 0.1 FREQUENCY (kHz) 50 0.0001 0.01 1.4 GAIN (dB) 1 1.2 MAX97236 toc05 MAX97236 toc04 RL = 10kI TOTAL POWER DISSIPATION (mW) 0.001 0.001 35 PO = 16mW PO = 1.9mW 0.1 0.01 POUT (mW) 10 0.01 fIN = 1kHz 0.01 0.01 0 0.1 fIN = 6kHz fIN = 100Hz 1 MAX97236 toc06 1 RL = 32I THD+N (%) THD+N (%) 1 0.1 THD+N (%) RL = 10kI OUTPUT POWER PER CHANNEL (mW) THD+N (%) 10 10 MAX97236 toc02 MAX97236 toc01 RL = 32I THD+N vs. FREQUENCY THD+N vs. OUTPUT VOLTAGE 10 MAX97236 toc03 THD+N vs. OUTPUT POWER 100 20 10 0.01 0.1 1 FREQUENCY (kHz) 10 100 0 0.01 0.1 1 10 100 FREQUENCY (kHz) 7 MAX97236 Typical Operating Characteristics Typical Operating Characteristics (continued) (VDD = 1.8V, VMICVDD = 3.0V, VGND = VPGND = 0V, CFLY = CPVDD = CPVSS = 1FF.) HEADPHONE AMPLIFIER TURN-OFF RESPONSE MAX97236 toc10 WIDEBAND OUTPUT SPECTRUM MAX97236 toc11 VSCL 0 VSCL MAX97236 toc12 HEADPHONE AMPLIFIER TURN-ON RESPONSE RBW = 100Hz OUTPUT AMPLITUDE (dBV) -20 VIN VIN VOUT VOUT -40 -60 -80 -100 400µs -120 0.001 40µs/div 0.01 0.1 1 10 100 FREQUENCY (MHz) f = 1kHz VOUT = -50dBV -40 10 RL = 10kI GAIN = 12dB VPVDD VOUT = 600mVRMS 1 THD+N (%) OUTPUT AMPLITUDE (dBV) -20 MAX97236 toc14 MAX97236 toc13 0 MICROPHONE AMPLIFIER THD+N vs. FREQUENCY CLASS H OPERATION -60 VIN -80 MAX97236 toc15 INBAND OUTPUT SPECTRUM VOUT = 100mVRMS 0.1 -100 VPVSS -120 -140 0.1 1 10 0.01 100 0.01 20ms/div 0.1 FREQUENCY (kHz) MICROPHONE PREAMPLIFIER THD+N vs. OUTPUT VOLTAGE 100 MIC GAIN = 12dB 10 THD+N (%) VOUT = 1VRMS fIN = 100Hz 1 fIN = 6kHz MIC GAIN = 24dB fIN = 100Hz 1 fIN = 1kHz fIN = 6kHz 0.1 0.1 0.1 1 FREQUENCY (kHz) 8 0.01 0.01 0.01 0.1 100 10 fIN = 1kHz 1 VOUT = 300mVRMS 100 THD+N (%) MAX97236 toc16 RL = 10kI GAIN = 24dB 0.01 10 MICROPHONE PREAMPLIFIER THD+N vs. OUTPUT VOLTAGE MAX97236 toc17 MICROPHONE AMPLIFIER THD+N vs. FREQUENCY 10 1 FREQUENCY (kHz) 10 100 MAX97236 toc18 0.01 THD+N (%) MAX97236 Audio Amplifier with Jack Detection 0 0.2 0.4 0.6 0.8 VOUT (V) 1.0 1.2 1.4 1.6 0 0.2 0.4 0.6 0.8 1.0 VOUT (VRMS) 1.2 1.4 1.6 Audio Amplifier with Jack Detection (VDD = 1.8V, VMICVDD = 3.0V, VGND = VPGND = 0V, CFLY = CPVDD = CPVSS = 1FF.) MICROPHONE PREAMPLIFIER POWER-SUPPLY REJECTION RATIO vs. FREQUENCY 30 80 50 40 RL = 10kI AV = 24dB RL = J AV = 24dB 20 GAIN (dB) PSRR (dB) 60 RL = J AV = 24dB 25 70 15 10 RL = 10kI AV = 24dB 5 30 0 20 -5 10 -10 0 0.1 0.01 1 10 0.01 100 0.1 10 100 1000 MICROPHONE BIAS vs. MICVDD MICROPHONE BIAS vs. TEMPERATURE 3.0 MAX97236 toc21 3.0 2.5 1 FREQUENCY (kHz) FREQUENCY (kHz) MICBIAS = 2.6V 2.5 MICROPHONE BIAS (V) MICROPHONE BIAS (V) MAX97236 toc20 VRIPPLE = 200mVP-P 2.0 MICBIAS = 2.0V 1.5 1.0 MAX97236 toc22 90 MAX97236 toc19 100 MICROPHONE AMPLIFIER GAIN vs. FREQUENCY VMICBIAS = 2.6V 2.0 VMICBIAS = 2.0V 1.5 1.0 0.5 0.5 0 0 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 2.6 2.8 3.0 3.2 3.4 3.6 MICVDD (V) 9 MAX97236 Typical Operating Characteristics (continued) Audio Amplifier with Jack Detection MAX97236 Pin Configuration TOP VIEW (BUMP SIDE DOWN) MAX97236 1 2 3 4 5 A GND INR INL PVDD JACKSW B I.C. GND IRQ MOUTN TIP C PVSS SCL EXTCLK MOUTP RING1 D C1N SDA PGND MBIAS MICVDD E C1P PGND VDD RING2 SLEEVE + WLP Pin Description 10 BUMP NAME A1, B2 GND Analog Ground FUNCTION A2 INR Right Audio Input A3 INL Left Audio Input A4 PVDD A5 JACKSW B1 I.C. Internally Connected. Leave unconnected. B3 IRQ Interrupt Request Flag. Open-drain, active-low digital output. Pullup with 10kI to system logic voltage. B4 MOUTN B5 TIP C1 PVSS Charge-Pump Negative Output. Bypass to PGND with 1FF. C2 SCL I2C Serial-Clock Input C3 EXTCLK Charge-Pump Positive Output. Bypass to PGND with 1FF. Jack Switch. Connect to the mechanical switch. Negative Microphone Output Left Headphone Output. Connect to the first ring of the four-pole jack. External System Clock Input. All internal digital clocks are derived from EXTCLK. Audio Amplifier with Jack Detection BUMP NAME C4 MOUTP Positive Microphone Output FUNCTION C5 RING1 Jack Input 2/Right Headphone Output. Connect to the first ring of the four-pole jack. D1 C1N Charge-Pump Flying Capacitor Negative Connection. Connect 1FF between C1N and C1P. D2 SDA Serial-Data I/O D3, E2 PGND Power Ground. Ground Return for the charge pump. D4 MBIAS Microphone Bias Capacitor Connection. Connect 1FF to GND. D5 MICVDD E1 C1P Charge-Pump Flying Capacitor Positive Connection. Connect 1FF between C1N and C1P. E3 VDD Main Power-Supply Input. Connect to 1.8V and bypass to GND with 1FF. E4 RING2 E5 SLEEVE Microphone Power-Supply Input. Bypass to GND with 1FF. Microphone Input Headset GND. Connect to the second ring of the four-pole jack. Microphone Input Headset GND. Connect to the sleeve of the four-pole jack. Detailed Description Class H DirectDrive Headphone Amplifier with Dual-Mode Charge Pump The headphone amplifier is optimized for low-power consumption and low noise. A charge pump generates a negative and positive supply voltage that powers the headphone amplifier and eliminates the need for a large output coupling capacitor. The headphone amplifier has volume control from -60dB to +6dB. A single-pole filter, f-3dB = 85kHz, attenuates signals outside the audio band. Dual-Mode Charge Pump The charge pump powers the headphone amplifier. When a headphone load is connected and the audio output signal is small, the charge pump outputs a Q0.9V negative and positive supply voltage. When a large audio signal is applied, the output rails of the charge pump switch to a higher voltage mode, Q1.8V. The higher voltage rails accommodate the higher voltage swing necessary to amplify line level audio signals. The lower voltage rails reduce the power consumption of the headphone amplifier when higher rails are not needed. Class H Operation The Class H amplifier employs a class AB output stage with power-supply voltages that shift based on the output signal needs (Figure 1). The lower power supply rails are used when the output voltage requirements are below the 0.5V threshold. The higher supply rails are used when the output voltage is above the 0.5V threshold, maximizing output power and voltage swing. The switch between available power-supply voltages occurs on a cycle-by-cycle basis. 1.8V 0.9V 32ms PVDD VTH_H OUTPUT VOLTAGE THRESHOLD VTH_L -0.9V PVSS 32ms -1.8V Figure 1. Class H Power-Supply Operation 11 MAX97236 Pin Description (continued) Audio Short-Circuit Protection A short on the right audio output does not shut down the left audio channel. A short on the audio output does not shut down the right audio channel. This ensures that a mono audio plug does not damage the chip, but allows audio to be heard through the other channel output. A short is considered anything below 4I for a time period of 100ms. Ground Sense The headphone amplifier features output ground sensing for improved crosstalk performance. Crosstalk is improved by at least 20dB, between the audio channels, which all share a common jack ground. Figure 2 shows the audio signal path from the filter through the amplifier with volume control and the ground sense. Headphone Amplifier Input Filter The headphone amplifiers employ a lowpass filter to remove out-of-band noise from the audio DAC driving the headphone inputs. The filter attenuates frequencies above 85kHz. Headphone Amplifier Volume Control The IC features a 64-step volume control with a resolution of 1dB/step from +6dB down to -54dB and 2dB/step from -54dB to -60dB. Figure 3 shows the I/O curve of the volume control. Headphone Volume Slewing Volume slewing breaks up large volume changes into the smallest available step size as it goes through each gain level between the initial and final volume setting. Volume slewing also occurs at device turn-on and turn-off when enabled. During turn-on, the volume is set to mute before the output is enabled. Once the output is on, the volume ramps to the programmed level. At turn-off, the volume is ramped to mute before the output is disabled. As briefly described in the last section, the VSEN (volume slew enable) bit decides whether each volume step is used when changing volume settings or whether the final volume setting jumps to the new value after writing. The volume slew enable function is used in conjunction with the zero-crossing detection enable (ZDEN). Examples: VSEN = 0, ZDEN = 0, both functions on: The volume changes one gain step at a time. The gain only changes at the zero crossing of the audio signal. VSEN = 0, ZDEN = 1: The volume changes one gain step at a time. VSEN = 1, ZDEN = 0: New volume is asserted as soon as audio signal has gone through a zero crossing (or 100ms after the last gain change, whichever comes first). VSEN = 1, ZDEN = 1: New volume is asserted as soon as the I2C command is received. Headphone Volume Zero-Crossing Detection Zero-crossing detection is implemented on the headphone amplifier volume control to prevent large glitches when volume changes are made. Instead of making a volume change immediately when requested, the change is made when the audio signal has a zero crossing or after 100ms, whichever comes first. 10 0 MAX97236 IN_ RING1 OR TIP RING2 OR SLEEVE VOLUME SETTING (dB) MAX97236 Audio Amplifier with Jack Detection -10 -20 -30 -40 -50 -60 PGND -70 0 10 20 30 40 50 60 70 STEP NUMBER Figure 2. Headphone Amplifier Signal Path 12 Figure 3. Headphone Volume Control Input/Output Transfer Function Audio Amplifier with Jack Detection Ensure that VMICVDD is greater than the desired microphone bias voltage. The microphone bias line is also used by passive single button and passive multibutton headsets. Microphone Preamplifier A microphone preamplifier provides an additional gain of 12dB or 24dB (programmable) with low input-referred noise and high power-supply rejection. Figure 4 shows the configuration of the microphone bias, amplifier, and microphone. Internal AC-coupling capacitors connect both the microphone output and also the MBIAS line to a differential amplifier, giving improved PSRR. MBIAS MAX97236 Jack Detection and Configuration Algorithm The IC features a detection scheme that senses when a 3.5mm plug is inserted into the system jack. After sensing insertion, a configuration detection algorithm takes over and reads the makeup of the installed plug. Information regarding the makeup of the plug is reported back through the I2C status registers. The device can also be placed in autoconfigure mode. This mode allows the IC to automatically enable the correct functional blocks depending upon the class of cable that has been inserted. Jack Insertion Testing The jack insertion detection uses an inaudible AC waveform output on the jack pins to sense when a load is plugged in. This electrical test is used to verify and work in conjunction with a mechanical switch (JACKSW). The mechanical switch, while not used as the main sensing mechanism, can be used to save system power. When a jack is plugged into a device, the switch at JACKSW is closed. When no jack is plugged in, the switch at JACKSW is open. When the jack switch at JACKSW is working, the electrical polling of the jack can be done less often. A test is done every time a jack is sensed to check if the switch at JACKSW is working correctly. If the IC deems that the switch at JACKSW is broken, the system is flagged. At that point, the system can decide whether to ignore JACKSW results and poll more quickly. Jack Configuration Detection The jack detection and configuration is bounded by certain load resistance and capacitance limitations. The correct detection and configuration cannot be guaranteed outside those limitations. The limitations are shown in Table 1. Table 1 shows each load case that is detectable with the IC’s jack configuration algorithm and which class of cable is found. The status bits of the I2C register (0x01, 0x02, 0x03) report the load found during testing. The functional blocks are set automatically if AUTO = 10 or 01 (register 0x01E bits 0 and 1), according to what class of cable is detected. Figure 4. Microphone Preamplifier Simplified Schematic Table 1. Jack Detection and Configuration Load Limits PARAMETER SYMBOL MIN CCABLE 150 Headphone Load Resistance RHP 12 650 I Headphone Load Inductance LHP 30 1600 FH Audio Line Load Resistance RLINE 6 50 kI Microphone Load Resistance RMIC 0.5 15 kI Cable Shield Capacitance TYP MAX UNITS 500 pF 13 MAX97236 Microphone Bias The IC features a low-noise microphone bias generator and amplifier. The bias voltage resistors are selectable through I2C register 0x09. MAX97236 Audio Amplifier with Jack Detection Case 9 is a special case that requires subsequent testing of the load pins while servicing the left audio load that has been found. In this case only, the status bits report that a line level audio load had been found on TIP while tests continue to run on RING1 and SLEEVE. Once a load is found with one of the subsequent tests, enough information about the cable class is known to stop testing. The status bits reflect what is found, and the signal paths are configured according to the cable class and testing stops. unplug detection method varies, depending on which load is plugged in. Cases with a microphone wait for the microphone bias to fly up to its full value. The audio only headphones wait for SLEEVE to fly up when the jack is removed. For cases with an AV cable and audio only connected, the IC can only rely on JACKSW to sense removal or to wait for user input to shut down audio. The electrical unplug detection (JKIN bit) is not available when the IC is running the jack configuration algorithm, when in FORCE mode, or when in test mode. In those cases, an unplug can only be detected mechanically through the JACKSW bit. Detecting Jack Removal There are two main jack removal detection methods: an electrical method and a mechanical method. The electrical Table 2. Jack Configurations and Status Registers (After DDONE Bit Has Been Reset) CASE NO. 14 CABLE CLASS PINS 1 2 3 4 JACKSW STATE REGISTER 0x00 REGISTER 0x01 REGISTER 0x02 1 Nothing F F F F Short 0x00 0x00 0x00 2 Extension cable C C C C Open 0x84 0x00 0x00 3 Stereo headset (headphones with microphone), GND on P3 L R G M Open 0x8C 0x30 0x01 4 Stereo headset (headphones with microphone), GND on P4 L R M G Open 0x8C 0x30 0x02 5 Line audio cable L R G G Open 0x84 0xC0 0x03 6 Mono headset, GND on P3 L G G M Open 0x8C 0x20 0x01 7 Mono headset, GND on P4 L G M G Open 0x8C 0x20 0x02 8 Mono headset, GND on P3 L L G M Open 0x8C 0x20 0x01 9 Mono headset, GND on P4 L L M G Open 0x8C 0x20 0x02 10 Mono headset, GND on P3 L F G M Open 0x8C 0x20 0x01 11 Mono headset, GND on P4 L F M G Open 0x8C 0x20 0x02 12 Stereo headphones L L G G Open 0x84 0x30 0x03 13 Stereo headphones, right channel open L F G G Open 0x84 0x20 0x03 14 Stereo headphones, left channel open F L G G Open 0x84 0x10 0x03 Audio Amplifier with Jack Detection MAX97236 Key Switch Encoder There are two types of keypads that can be connected to the IC: • A single-button hook switch or MIC switch that grounds out the microphone bias when pressed MIC BIAS • A passive multibutton headset Key Switch Encoder Timing Two registers, 0x15 and 0x16, control the key switch debounce time, tDEB, and delay time, tDELAY. The debounce time, 0x15, is the time from when the switch stops bouncing and when the ADC converts. MAX97236 The delay time, 0x16, is set long to ensure that an unplug event is not encoded as a keypress. See Figure 9. The PRESS Bit The PRESS bit alerts the system to whether the current interrupt was caused by a button press or release. Figure 5. Passive Single-Button Hook Switch SINGLE BUTTON KEYPRESS OR PASSIVE MULTIBUTTON HEADSET (MBH) PLAY/MUTE, NORMAL SPEED MCSW RELEASE IRQ MCSW PRESS IRQ AND REPORT VALUE ADC CONVERT VBIAS GND tDEB tDELAY tDEB tDELAY MCSW RELEASE IRQ SINGLE BUTTON KEYPRESS OR PASSIVE MULTIBUTTON HEADSET (MBH) PLAY/MUTE, FAST SPEED ADC CONVERT tDEB VBIAS tDELAY MCSW PRESS IRQ AND REPORT VALUE GND tDEB tDELAY Figure 6. Single-Button, Passive Multibutton Hook Switch/Microphone Switch Timing 15 MAX97236 Audio Amplifier with Jack Detection Passive Multibutton Headset (MBH) A passive MBH consists of a microphone with numerous switches that connect different value resistors to ground. The switched resistor and the microphone bias resistor set up a voltage-divider that creates a unique voltage. The on-chip ADC then encodes the voltage and reports to the system. A maximum 0.5I resistance between IC pins RING2 and SLEEVE and the headset is required for proper operation of the passive multibutton headset. Figure 7 shows the circuit diagram of a passive MBH. Figure 8 shows the timing for a fast or normal speed keypress on a passive MBH. Note that a keypress develops a voltage that is above ground. The switch that shorts the microphone bias to ground is handled like the hook switch in the previous section. MIC BIAS ADC MAX97236 Figure 7. Passive MBH PASSIVE MULTIBUTTON HEADSET (MBH): OTHER BUTTON, NORMAL SPEED, OR BUTTON HELD KEYPRESS SET KEY AND REPORT VALUE VBIAS KEY RELEASE SET KEY IRQ ADC CONVERT GND tDEB tDELAY tDEB tDELAY KEY RELEASE SET KEY IRQ PASSIVE MULTIBUTTON HEADSET (MBH): OTHER BUTTON, FAST SPEED VBIAS tDEB ADC CONVERT KEYPRESS SET KEY AND REPORT VALUE GND tDEB Figure 8. MBH Timing 16 tDELAY tDELAY Audio Amplifier with Jack Detection JKIN RELEASE IRQ ADC CONVERT VBIAS GND tDEB tDELAY NOTE: ONE INTERRUPT DETERMINED BY THE AUTODETECT CIRCUIT Figure 9. Slow Jack Removal Timing Register and Bit Descriptions Table 3. Register Map REGISTER B7 B6 B5 B4 B3 B2 B1 B0 Status1 JKIN DDONE VOL — MIC_IN JACKSW MCSW MBH 0x00 0x00 R Status2 LINE_L LINE_R HP_L KEY — — 0x01 0x00 R 0x02 0x00 R 0x03 — — HP_R JACKSWINC GND ADDRESS DEFAULT R/W Status3 — — — — — — For Expansion — — — — — — IRQ Mask1 IJKIN IDDONE IVOL — IMIC IMBH 0x04 0x00 R/W IRQ Mask2 ILINE_L ILINE_R IHP_L IHP_R IJACKSW IKEY — — 0x05 0x00 R/W For Expansion — — — — — — — — 0x06 — — — JACKSW IMCSW — Left Volume L=R MUTEL LVOL 0x07 0xC0 R/W Right Volume — MUTER RVOL 0x08 0x40 R/W Microphone — GAIN 0x09 0x00 R/W 0x0A 0x00 R/W 0x0B 0x90 R For Expansion Vendor ID Register MICR BIAS — — For expansion ID — — — — For Expansion For expansion 0x0C 0x00 R/W For Expansion For expansion 0x0D 0x00 R/W For Expansion For expansion 0x0E 0x00 R/W For Expansion For expansion 0x0F 0x00 R/W For Expansion For expansion 0x10 0x00 R/W For Expansion For expansion 0x11 0x00 R/W Keyscan Clock Divider 1 KEY_DIV_HIGH 0x12 0x00 R/W Keyscan Clock Divider 2 KEY_DIV_LOW 0x13 0x00 R/W Keyscan Clock Divider ADC KEY_DIV_ADC 0x14 0x00 R/W Keyscan Debounce KEY_DEB 0x15 0x00 R/W Keyscan Delay KEY_DEL 0x16 0x00 R/W 17 MAX97236 Slow Jack Removal Removing the headphone jack slowly can cause a false trigger of the key switch encoder because the right speaker between RING1 and RING2 shorts between microphone bias and ground. The programmable delay time must be set by the system to mask out this slow removal so that an interrupt does not flag until the JKIN status bit tells the system the jack is unplugged. Figure 9 shows the timing and interrupt reporting for a slow jack removal event. The act of microphone bias flying all the way up is the trigger for a microphone removal event. The Jack Detection and Configuration Algorithm section explains more about sensing jack removal. MAX97236 Audio Amplifier with Jack Detection Table 3. Register Map (continued) REGISTER B7 B6 Passive MBH Keyscan Data PRESS RANGE B5 B4 B3 B2 B1 B0 KEYDATA DC Test Slew Control DC_SLEW State Forcing — — AC Test Control — — For Expansion — — — For Expansion — — FORCE AC_REPEAT_ STATE PULSE_WIDTH_ ADDRESS DEFAULT R/W 0x17 0x00 R 0x18 0x00 R/W — 0x19 0x20 R/W PULSE_AMP_ 0x1A 0x05 R/W — — — — — 0x1B — — — — — — — — 0x1C — — MIC_AMP KS — — 0x1D 0x00 R/W FAST THRH 0x1E 0x00 R/W Enable1 SHDN RESET — MIC_ BIAS Enable2 LFTEN RGHEN VSEN ZDEN AUTO Device Status Registers Registers 0x00 and 0x01 are used to report the makeup of the inserted jack as well as report when a microphone switch has been pressed or the jack has been removed. The IC uses registers 0x00, 0x01, 0x02, and IRQ to report the status of various device functions. The Status_ register bits are set when their respective event occurs. Device status can be determined either by polling registers 0x00, 0x01, and 0x02 or configuring the IRQ to go low when specific events occur. Registers 0x04 and 0x05 determine which bits in the Status_ register trigger IRQ to go low. IRQ is cleared upon reading the register. Table 4. Configuration and Device Status Registers REGISTER BIT 18 DESCRIPTION JKIN Jack Detected JKIN changes state when the jack detect circuit senses a load at the left headphone output and SHDN = high 0 = No load at TIP. 1 = Load detected at TIP. DDONE Jack Configuration Detect Done DDONE changes state when the jack detect algorithm finishes and the jack configuration is known and reported in the status registers 0x00, 0x01, and 0x02. Resets after reading. 0 = Jack detect algorithm is not complete. 1 = Jack detection algorithm is complete. 5 VOL Volume Slew Complete VOL goes high after the headphone volume has slewed to its final programmed value. VOL sets every time a gain change is complete whether the gain change is positive or negative. Ramp the volume down and wait for VOL to set to ensure clickless turn off. Resets after reading. 0 = No volume slewing sequences have completed since any register was last read. 1 = Volume slewing complete. 4 — 7 Status1 0x00 (Read Only) NAME 6 — Audio Amplifier with Jack Detection REGISTER BIT 3 2 NAME MIC_IN JACKSW Status1 0x00 (Read Only) 1 Status2 0x01 (Read Only) MCSW DESCRIPTION Microphone Connected/Disconnected MIC_IN reports when a microphone is connected or removed. Set the MIC_INM interrupt mask to alert the system when the microphone load status has changed. 0 = Microphone is removed. 1 = Microphone is connected. JACKSW Status JACKSW reports the mechanical jack switch status. For an operational mechanical jack switch, JACKSW flags at the same time. If the switch is broken, or if the jack is not plugged in all the way, JACKSW and JKIN do not report the same value. The JACKSW bit also reports when a jack has been removed. Set the PIN5M interrupt mask bit to signal the system when the status of JACKSW changes. 0 = Mechanical jack switch reports no jack is connected. 1 = Mechanical jack switch shows that the jack is connected. Microphone Switch Status MCSW goes high when the microphone bias goes low for the debounce period plus the delay period. This happens when a switch shorts across the microphone, pulling the micbias node down, indicating a keypress from a hook switch, ADC P 4 LSB. Resets after reading. 0 = No change in microphone bias, no switch press. 1 = Microphone bias has been pulled to ground and debounced since the last status read. Debounce time set by KEY_DEB. Delay time set by KEY_DEL. Multibutton Headset Status MBH reports when a keypress from a multibutton headset is ready to be read. Resets after reading. 0 = No active keypress detected. 1 = Active keypress has been detected. 0 MBH 7 LINE_L Line-Level Load on TIP Detected 0 = Line-level load on TIP not detected. 1 = Line-level load on TIP detected. 6 LINE_R Line-Level Load on ROUT Detected 0 = Line-level load on RING1 not detected. 1 = Line-level load on RING1 detected. 5 HP_L Headphone Load on TIP Detected 0 = Headphone load on TIP not detected. 1 = Headphone load on TIP detected. 4 HP_R Headphone Load on RING1 Detected 0 = Headphone load on RING1 not detected. 1 = Headphone load on RING1 detected. 3 JACKSW Incorrect JACKSWINC reports when there are inconsistencies between the mechanical switch and the electrical plug and unplug detection. The exception is when a plug-in occurs and SHDN is LOW. JACKSWINC does NOT clear when the STATUS register is read. JACKSWINC JACKSW is checked at jack plug-in and unplug JACKSWINC is updated when JACKSW is checked. 0 = JACKSW reporting is correct and correlates with JKIN. 1 = JACKSW reporting is not correct and does not correlate with JKIN. 19 MAX97236 Table 4. Configuration and Device Status Registers (continued) MAX97236 Audio Amplifier with Jack Detection Table 4. Configuration and Device Status Registers (continued) REGISTER Status2 0x01 (Read Only) Status3 0x02 (Read Only) BIT NAME 2 KEY 1 — — 0 — — 7 — — 6 — — 5 — — 4 — — 3 — — 2 — — 1 GND 0 20 DESCRIPTION Passive Multibutton Headset KEY Status KEY reports when the passive multibutton has been pressed. Data is available in KEYDATA. See Figure 8. Resets after reading. 0 = No button pressed. 1 = Button has been pressed/released. Debounce and delay times have occurred. Jack Common Location Identifier The two GND bits tell the system whether the jack’s common connection is at RING2 or SLEEVE. GND is also used to indicate when a jack has been removed. 00 = No common connection sensed, jack has been removed or nothing has been inserted yet. 01 = The common jack connection is RING2. 10 = The common jack connection is SLEEVE. 11 = Common on both RING2 and SLEEVE. Audio Amplifier with Jack Detection Table 5. Interrupt Mask Registers REGISTER IRQ Mask1 0x04 IRQ Mask2 0x05 BIT NAME DESCRIPTION Jack Detect Interrupt Enable 0 = Disabled 1 = Enabled 7 IJKIN 6 IDDONE 5 IVOL 4 — 3 IMIC 2 JACKSW 1 IMCSW 0 IMBH 7 ILINE_L Line-Level Load TIP Interrupt Enable 0 = Disabled 1 = Enabled 6 ILINE_R Line-Level Load RING1 Interrupt Enable 0 = Disabled 1 = Enabled 5 IHP_L Headphone Load TIP Interrupt Enable 0 = Disabled 1 = Enabled 4 IHP_R Headphone Load RING1 Interrupt Enable 0 = Disabled 1 = Enabled 3 IJACKSW 2 IKEY 1 — — 0 — — Jack Configuration Detect Done Interrupt Enable 0 = Disabled 1 = Enabled Volume Slew Interrupt Enable 0 = Disabled 1 = Enabled — Microphone Interrupt Enable 0 = Disabled 1 = Enabled JACKSW Status Interrupt Enable 0 = Disabled 1 = Enabled Microphone Switch Interrupt Enable 0 = Disabled 1 = Enabled Multibutton Release Status Interrupt Enable 0 = Disabled 1 = Enabled JACKSW Incorrect Interrupt Enable 0 = Disabled 1 = Enabled KEY Interrupt Enable 0 = Disabled 1 = Enabled 21 MAX97236 Interrupt Mask Registers The Interrupt Mask registers control which status bits flag a system interrupt. Setting an interrupt mask bit causes IRQ to pull low whenever the target status bits set. The IRQ output resets to high, after I2C register is read. MAX97236 Audio Amplifier with Jack Detection Headphone Volume Control Registers The Headphone Volume registers independently control and report the gain of the left and right headphone amplifiers. Set B7 in Register 0x04 to have the right-channel gain track the left-channel gain. Table 6. Headphone Volume Registers REGISTER Left Volume 0x07 BIT NAME DESCRIPTION 7 L=R Left/Right Tracking 0 = The right-channel volume control is independent of the left. 1 = The left and right volume controls track each other allowing for only one register to be written to change both channel volumes. Control both volume controls by writing to LVOL. 6 MUTEL/ MUTER 5 4 Left Volume/ Right Volume 0x07/0x08 3 LVOL/ RVOL 2 1 0 22 Headphone Mute 0 = Disable. 1 = Enable, output is muted. HEX VALUE 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Left/Right Headphone Output Volume Level GAIN (dB) HEX VALUE -60 0x20 -58 0x21 -56 0x22 -54 0x23 -53 0x24 -52 0x25 -51 0x26 -50 0x27 -49 0x28 -48 0x29 -47 0x2A -46 0x2B -45 0x2C -44 0x2D -43 0x2E -42 0x2F -41 0x30 -40 0x31 -39 0x32 -38 0x33 -37 0x34 -36 0x35 -35 0x36 -34 0x37 -33 0x38 -32 0x39 -31 0x3A -30 0x3B -29 0x3C -28 0x3D -27 0x3E -26 0x3F GAIN (dB) -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 Audio Amplifier with Jack Detection Table 7. Microphone Bias and Gain Register REGISTER BIT NAME 7 — 6 GAIN Microphone Preamplifier Gain Select 0 = 12dB 1 = 24dB MICR Microphone Bias Resistor Select 000 = 2.2kI 001 = 2.6kI 010 = 3.0kI 011 = Bypassed 1XX = High impedance (sleep mode) 2 BIAS Microphone Bias Voltage Select 0 = 2.0V 1 = 2.6V 1 — — 0 — — 5 Microphone 0x09 4 3 DESCRIPTION — Vendor ID Register Vendor ID bits are shown in Table 8. Table 8. Vendor ID Register REGISTER BIT NAME DESCRIPTION 7 6 Vendor ID Register 0x0B 5 ID Vendor ID 0x9 = Maxim’s vendor ID 4 3 — 2 — 1 — 0 — — 23 MAX97236 Microphone Bias Control and Gain Register The Microphone Bias Control and Gain register controls which microphone bias voltage and bias resistors are used as well as the microphone amplifier gain. MAX97236 Audio Amplifier with Jack Detection Keyscan Clock Divider Registers The Keyscan Clock Divider register sets the clock frequency that is used for the conversion clock for the keyscan 1kHz generator. Table 9. Keyscan Clock Divider Registers REGISTER BIT NAME 7 6 Keyscan Clock Divider 1/2 0x12/0x13 5 4 3 KEY_DIV_HIGH/ KEY_DIV_LOW 2 1 0 DESCRIPTION Keyscan Clock Divider The keyscan 1kHz clock is generated by dividing down the frequency of EXTCLK. The divider is set with the 16 bits contained within registers 0x12 and 0x13, where 0x12 is the high byte and 0x13 is the low byte. Since 1kHz (1ms) is desired, then: N = fIN/2kHz e.g., fIN = 20MHz, then N = 10,000 e.g., fIN = 1MHz, then N = 500 e.g., fIN = 19.2MHz, then N = 9600 For the low input frequencies, resolution is about 0.2%. Keyscan Divider ADC Register The Keyscan ADC Clock Divider register sets the clock frequency that is used for the conversion clock for the keyscan 6-bit ADC. Table 10. Keyscan ADC Clock Divider Registers REGISTER BIT NAME 7 6 Keyscan Clock Divider ADC 0x14 5 4 3 KEY_DIV_ADC 2 1 0 DESCRIPTION Keyscan ADC Clock Divider The keyscan ADC clock is generated by dividing down the frequency of EXTCLK. The divider is set with the 8 bits contained within register 0x14. Since 100kHz (10Fs) is desired, then: N = fIN/200kHz e.g., fIN = 20MHz, then N = 100 e.g., fIN = 1MHz, then N = 5 e.g., fIN = 19.2MHz, then N = 96 For the low input frequencies, resolution is about 20%. Keyscan Debounce Register The Keyscan Debounce register controls the debounce time when a keypress is detected. See Figure 6. Table 11. Keyscan Clock Divider Registers REGISTER BIT NAME DESCRIPTION 7 6 Keyscan Debounce 0x15 5 4 3 2 1 0 24 KEY_DEB Keyscan Debounce Register Debounce time set from 1ms to 256ms in 1ms increments. The programmed code plus one represents the debounce time directly. tDEB = KEY_DEB + 1 e.g., code 0x13 represents 20ms of debounce. Audio Amplifier with Jack Detection Table 12. Keyscan Delay Register REGISTER BIT NAME DESCRIPTION KEY_DEL Keyscan Delay Register Delay time set from 4ms to 1024ms in 4ms increments. The programmed code plus one multiplied by 4ms represents the delay time. tDELAY = (KEY_DEL + 1) x 4ms e.g., code 0x63 represents 400ms of delay. 7 6 Keyscan Delay 0x16 5 4 3 2 1 0 Passive Multibutton Keyscan Data Register The Keyscan Data register contains the data read from a keypress after the 6-bit ADC encodes the input voltage level. The read keypress could come from a single switch or a passive multibutton device. Table 13. Keyscan Data Register REGISTER Passive MBH Keyscan Data 0x17 (Read Only) BIT NAME DESCRIPTION 7 PRESS Release Tells if a KEY status was PRESS or RELEASE. 0 = Key release. 1 = Keypress. 6 RANGE 0 = Coarse range. 1 = Fine range. 5 4 3 2 1 KEYDATA Keyscan Data B6–B0 are read-only bits that contain the data read from a passive keypress that shorts the microphone to ground. There is a coarse range (10mV/LSB) and a fine range (2mV/LSB). See Figure 7 and the Passive Multibutton Headset (MBH) section. 0 25 MAX97236 Keyscan Delay Register The Keyscan Delay register sets the timeout that the microphone button press is masked from the system. At the end of the delay time, the IC checks to see if a microphone is still present. If the microphone is present, the system is alerted by setting the MCSW bit in the status register flagging an interrupt if IMCSW is set. If the microphone is not present after the delay time, the system is flagged with an interrupt by setting MICROPHONE_IN signifying that the microphone has been removed and no keypress was made. MAX97236 Audio Amplifier with Jack Detection Ramp Test Slew Control The ramp test slew control programs the period of the jack configuration algorithm’s ramp test. Slow slew rates ensure test inaudibility, but increase test time to complete the configuration algorithm. Table 14. Ramp Test Slew Control REGISTER BIT NAME DESCRIPTION 7 6 DC Test Slew Control 0x18 5 4 3 DC_SLEW 2 DC Slew Control Program the DC test slew rate from 5.12ms to 1305.6ms in 5.12ms steps. Recommend value to be used is 0x04 to 0x08. 1 0 Load State Forcing Use the Load State Forcing register to force a state and ignore the results of the jack detection algorithm. It forces the required blocks to be on (bypassing the Enable registers). Table 15. Load State Forcing REGISTER State Forcing 0x19 26 BIT NAME 7 — — DESCRIPTION 6 — — 5 FORCE Load State Force Enable 0 = Forces the IC into a configuration defined by 0b4–0b0. 1 = State forcing disabled. Audio Amplifier with Jack Detection REGISTER BIT NAME DESCRIPTION State Value Bits 0b4–0b0 programs the configuration of the IC. The columns show all the possible configurations. 4 CODE [B4:B0] 3 State Forcing 0x19 STATE 2 1 0 STATE (F = Float, L = Left Audio, R = Right Audio, G = Ground, M = Microphone) 0x01 FFFF 0x02 LRGM 0x03 LRMG 0x07 LRGG_AC 0x08 LRGF 0x09 LFGF 0x0A FRGF 0x0C LGGM 0x0D LGMG 0x0E LLGM 0x0F LLMG 0x10 LFGM 0x11 LFMG 0x12 LRGG_DC 0x13 LFGG 0x14 FRGG 27 MAX97236 Table 15. Load State Forcing (continued) MAX97236 Audio Amplifier with Jack Detection Pulse Test Hardware Settings The Jack Detect Test Hardware Settings register programs the amplitude and width of the pulse used in the jack detection tests and jack insertion algorithm. Table 16. Jack Detect Test Hardware Settings REGISTER AC Test Control 0x1A BIT NAME 7 6 — — DESCRIPTION 5 AC_REPEAT1 4 AC_REPEAT0 3 PULSE_WIDTH1 2 PULSE_WIDTH0 1 PULSE_AMP1 0 PULSE_AMP0 — — AC_Repeat 00 = 1, 01 = 3, 10 = 5, 11 = 7. Programs number of pulses sent for each jack detection test. Pulse Width 00 = 50Fs, 01 = 100Fs, 10 = 150Fs, 11 = 300Fs. Test 1 and 4 pulse width is fixed at 10Fs. Pulse Amplitude For tests 1 and 4, pulse amplitude is 00 = 25mV, 01 = 50mV, 10 = 100mV, 11 = 200mV. Tests 6, 7, and 8 pulse amplitude is 00 = 37mV, 01 = 75mV, 10 = 150mV, 11 = 220mV. Enable Registers The Enable_ registers contain all of the bits that control the separate functional blocks for the IC. The system can either directly control these bits, or it can allow the IC to automatically configure itself and report in the Enable_ register which blocks are enabled. When the AUTO bits (B1, B0) are set to 01 or 10, the Enable_ registers are read-only (except the SHDN and SLEEP bits). The block enable bits need to be set to sense a jack removal. The jack removal circuitry is active after the jack configurations detect algorithm has completed. Table 17. Enable Registers REGISTER BIT NAME DESCRIPTION 7 SHDN Full Device Shutdown Control SHDN turns the IC on and off. When SHDN is low, the device is in shutdown mode and the jack insertion detect circuitry is active. Pull SHDN high to turn on the device and run the jack configuration detect algorithm. Typically, SHDN is held low until the system gets an interrupt from the IC, indicating that a jack has been inserted. The system then pulls SHDN high. 0 = The IC is in shutdown mode with jack detection circuitry active. 1 = The IC is active. The jack configuration algorithm runs immediately after a load has been detected. 6 RESET RESET Jack Detection Cycle RESET (low g high g low) to repeat the jack detection and configuration algorithm. Enable1 0x1D 28 Audio Amplifier with Jack Detection REGISTER BIT NAME 5 — Enable1 0x1D DESCRIPTION — MIC_BIAS Microphone Bias Enable/Status Set MIC_BIAS to enable the microphone block. This bit is read-only when AUTO (0b0 or 0b1) is set. 0 = Microphone bias is disabled. 1 = Microphone bias is enabled. MIC_AMP Microphone Amplifier Enable/Status Set MIC_AMP to enable the microphone amplifier. This bit is read-only when AUTO (0b0 or 0b1) is set. 0 = Microphone amplifiers are disabled. 1 = Microphone amplifiers are enabled. 2 KS Keyscan Enable/Status KS enables the circuitry that decodes passive multibutton keypad or simple microphone switch. This bit is read only when AUTO (0b0 or 0b1) is set. 0 = Keyscan ADC is disabled. 1 = Keyscan ADC is enabled. 1 — — 0 — 4 3 7 6 — LFTEN Left Headphone Enable/Status Set LFTEN to enable the left channel of the DirectDrive headphone amplifier. This bit is read-only when AUTO (0b0 or 0b1) is set. 0 = Headphone amplifier left channel is disabled. 1 = Headphone amplifier left channel is enabled. RGHEN Right Headphone Enable/Status Set RGHEN to enable the left channel of the DirectDrive headphone amplifier. This bit is read-only when AUTO (B0) is set. 0 = Headphone amplifier right channel is disabled. 1 = Headphone amplifier right channel is enabled. Enable2 0x1E MAX97236 Table 17. Enable Registers (continued) 29 MAX97236 Audio Amplifier with Jack Detection Table 17. Enable Registers (continued) REGISTER BIT 5 4 3 NAME DESCRIPTION VSEN Volume Adjustment Slewing Volume changes are smoothed by stepping through intermediate steps. VSEN also ensures that the volume automatically ramps from the minimum setting to the programmed value at turn-on and back to the minimum value at turn-off. 0 = Enabled. 1 = Disabled. ZDEN Zero-Crossing Detection ZDEN holds volume changes until there is a zero-crossing in the audio signal. This reduces clicks during volume changes (zipper noise). If no zero-crossing is detected within 100ms, the volume change is forced. 0 = Enabled. 1 = Disabled. FAST Jack Insertion Polling Speed A fast polling speed tests for a jack insertion 3 times per second, while a slow polling speed tests for jack insertion every 2 seconds. Setting the polling speed to slow mode saves shutdown power consumption while the mechanical JACKSW switch is operational. 0 = Slow polling mode, 2s delay between polls. 1 = Fast polling mode, 333ms delay between polls. THRH Class H Threshold Select THRH selects the threshold at which the power supplies switch from Q0.9V to Q1.8V. A higher threshold allows the IC’s output stage to be powered from Q0.9V for a higher percentage of the audio waveform, decreasing power dissipation at the expense of dynamic distortion. 0 = Low threshold. 1 = High threshold. AUTO Automatic Mode Select Set AUTO to allow the IC to enable functional blocks depending on the load. In auto mode, the user merely reads the status of registers 0x1D and 0x1E to find out what blocks are enabled. Setting AUTO makes bits register 0x1D and 0x01E read-only (except SHDN and SLEEP). Clear AUTO to give the system control of what functional blocks are active. The user needs to allow the jack configuration detect algorithm to complete before enabling functional blocks. 00 = User controls which functional blocks are on. Registers 0x1D and 0x1E are R/W. 01 = The IC enables functional blocks automatically depending on the results of the jack configuration detect algorithm after SHDN is set. 10 = The IC enables functional blocks automatically depending on the results of the jack configuration detect algorithm regardless of whether SHDN is set. SHDN must go to high to enable audio playback. Enable2 0x1E 2 1 0 30 Audio Amplifier with Jack Detection MAX97236 SDA tBUF tSU,STA tSU,DAT tHD,STA tHD,DAT tLOW tSP tSU,STO SCL tHIGH tHD,STA tR tF REPEATED START CONDITION START CONDITION STOP CONDITION START CONDITION Figure 10. I2C Interface Timing Diagram I2C Serial Interface The IC features an I2C/SMBusK-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the IC and the master at clock rates up to 400kHz. Figure 10 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the IC by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the IC is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the IC transmits the proper slave address followed by a series of nine SCL pulses. The IC transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500I, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500I, is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the IC from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals. See the START and STOP Conditions section. START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 11). A START condition from the master signals the beginning of a transmission to the IC. The master terminates transmission and frees the bus by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The IC recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. S Sr P SCL SDA Figure 11. START, STOP, and REPEATED START Conditions SMBus is a trademark of Intel Corp. 31 MAX97236 Audio Amplifier with Jack Detection Slave Address The slave address is defined as the 7 most significant bits (MSBs) followed by the read/write bit. The IC has an address of 0x80. The 7 most significant bits are 100000. Setting the read/write bit to 1 (slave address = 0x81) configures the IC for read mode. Setting the read/write bit to 0 (slave address = 0x80) configures the IC for write mode. The address is the first byte of information sent to the IC after the START condition. Acknowledge The acknowledge bit (ACK) is a clocked ninth bit that the IC uses to handshake receipt each byte of data when in write mode (Figure 12). The IC pulls down SDA during the entire master-generated ninth clock pulse if the previous byte is successfully received. Monitoring ACK CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL 2 1 8 allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master retries communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the IC is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not-acknowledge is sent when the master reads the final byte of data from the IC, followed by a STOP condition. Write Data Format A write to the IC includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 13 illustrates the proper frame format for writing one byte of data to the IC. Figure 14 illustrates the frame format for writing n bytes of data to the IC. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the IC. The IC acknowledges receipt of the address byte during the master-generated 9th SCL pulse. 9 NOT ACKNOWLEDGE The second byte transmitted from the master configures the IC’s internal register address pointer. The pointer tells the IC where to write the next byte of data. An acknowledge pulse is sent by the IC upon receipt of the address pointer data. SDA ACKNOWLEDGE Figure 12. Acknowledge ACKNOWLEDGE FROM MAX97236 B7 ACKNOWLEDGE FROM MAX97236 SLAVE ADDRESS S B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX97236 0 REGISTER ADDRESS A DATA BYTE A R/W A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 13. Writing One Byte of Data to the IC ACKNOWLEDGE FROM MAX97236 ACKNOWLEDGE FROM MAX97236 S SLAVE ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX97236 0 A R/W REGISTER ADDRESS ACKNOWLEDGE FROM MAX97236 A DATA BYTE 1 B7 B6 B5 B4 B3 B2 B1 B0 A 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 14. Writing n Bytes of Data to the IC 32 DATA BYTE n 1 BYTE A P Audio Amplifier with Jack Detection frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from register 0x00. The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the IC’s slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The IC then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The IC acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 15 illustrates the frame format for reading one byte from the IC. Figure 16 illustrates the frame format for reading multiple bytes from the IC. The first byte transmitted from the IC is the content of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous ACKNOWLEDGE FROM MAX97236 ACKNOWLEDGE FROM MAX97236 S SLAVE ADDRESS 0 A A REGISTER ADDRESS R/W NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX97236 Sr SLAVE ADDRESS REPEATED START 1 R/W A DATA BYTE A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 15. Reading One Byte of Data from the IC S SLAVE ADDRESS 0 ACKNOWLEDGE FROM MAX97236 ACKNOWLEDGE FROM MAX97236 ACKNOWLEDGE FROM MAX97236 A REGISTER ADDRESS R/W A REPEATED START Sr SLAVE ADDRESS 1 R/W A DATA BYTE A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 16. Reading n Bytes of Data from the IC 33 MAX97236 The third byte sent to the IC contains the data that is written to the chosen register. An acknowledge pulse from the IC signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. The master signals the end of transmission by issuing a STOP condition. Register addresses greater than 0x0C are reserved. Do not write to these addresses. MAX97236 Audio Amplifier with Jack Detection Applications Information Power Modes The power modes of the IC are controlled by the SHDN bit. The three power modes include detection, normal operating, and standby. Detection mode occurs when no jack has been plugged in, SHDN = RESET = 0. Once a jack is plugged in and detected, the IC enters normal operating mode after SHDN transitions from 0 to 1. While in normal operating mode, pull SHDN low to put the device in standby mode. Pull RESET high then low to reset the jack detection and configuration. Standby mode leaves the key encoder active to pick up a keypress event if the IC has completed jack detection prior to standby mode. A weak pullup voltage is put across the microphone to look for a hook switch press. Once a keypress event occurs, an interrupt flags, and the IC enters detection mode after SHDN transitions high. MVDD power domain: Power Domains Microphone bias, switches, ESD, and jack detection tests 2 to 9. VDD power domain: Charge pump, digital block, ADC, mic amp, and jack detection test 1. Power-Up/-Down Sequence The IC needs VDD and MVDD to operate correctly. until SHDN is pulled high. After the configuration is detected, the IC waits for the system to turn on the appropriate enable bits. • AUTO = 0x01: The IC detects a jack plug-in and set JKIN, but does not run the configuration detect until SHDN is pulled high. After the configuration detect is run, the IC automatically sets the appropriate enable bits to be able to drive all loads for the found cable. • AUTO = 0x02: The IC detects a jack plug-in, sets JKIN, and automatically runs the configuration detect. After the configuration detect is run, the IC automatically sets the appropriate enable bits to be able to drive all loads for the found cable. However, the amplifiers do not actually turn on until SHDN is pulled high. The IC completes detection and waits in standby mode until SHDN is pulled high. Ensure that RESET = 0 to enable the jack detect plug-in test signal. Power-Up, AUTO = 0x00 or 0x01: 1) Set IDDONE and IJACKSW and IJKIN so that an interrupt flags when something is plugged in and the detection is done. 2) Wait for IRQ. 3) Wait for JACKSW to set. 4) Pull SHDN high. 5) Detection is done when DDONE sets. If AUTO = 0x00: Turning off one supply voltage during a mode might prevent proper operation of the IC. 1) Read the Status registers to find out what was detected. The power-up sequence is: 3) System sets the appropriate enable bits. • Apply VDD 4) Set the volume register to the appropriate setting if audio is present. • Apply MVDD • Set AUTO to 01 (register 0x1E, bit 0) There are a few different ways to power-up/-down depending on how autonomous you want the IC to operate and whether the jack is plugged in or not. The AUTO bits are in register 0x1E, bits 0 and 1. The three methods for getting the IC running are: • AUTO = 0x00: The IC detects a jack plug-in and set JKIN, but does not run the configuration detect 34 2) System makes a decision about what to enable. If AUTO = 0x01: 1) Read the Status registers to find out what was detected. 2) The appropriate enable bits automatically set. 3) Read the Enable1 and Enable2 registers to see what was turned on. 4) Set the volume register to the appropriate setting if audio is present. Audio Amplifier with Jack Detection 1) Wait for JKIN to set. 2) Detection runs automatically, so wait for DDONE to set. 3) Read the Status registers to find out what was detected. 4) The IC is automatically placed in standby mode after detection is done. 5) Pull SHDN high to turn on the IC. 6) The appropriate enable bits were automatically set because AUTO = 0x02. 7) Read the Enable1 and Enable2 registers to see what was turned on. When AUTO = 0x01 or 0x02, the IC automatically enables the required blocks according to what has been detected. In case AUTO = 0x00, it is required that all the correct blocks are enabled for unplug detection to work properly. Table 18 correlates the status bits with the enable bits for the blocks that are (need to be) enabled for proper operation. Power-Down, All AUTO Settings: If audio is playing and VSEN = 0: 1) Set the headphone volume register mute bits or set code 0x00 as the volume. 2) Set the headphone volume register mute bits or set code 0x00 as the volume, and the amplifiers mute immediately. 3) Pull SHDN to 0 to go to standby mode; the current jack case is remembered. Cycle RESET (low ➝ high ➝ low) to run jack detection and configuration again. PCB Layout and Grounding Proper layout and grounding are essential for optimum performance. Use large traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance, as well as route heat away from the device. Good grounding improves audio performance, minimizes crosstalk between channels, and prevents switching noise from coupling into the audio signal. Connect PGND and GND together at a single point on the PCB. Route PGND and all traces that carry switching transients away from GND, and the traces and components in the audio signal path. Place the charge-pump capacitors as close as possible to the device. Bypass PVDD and PVSS with a 1FF capacitor to PGND. Place the bypass capacitors as close as possible to the device. 2) The VOL bit is set when the volume slew is done. Make sure IVOL is set so that an interrupt is flagged. Route the pins that connect to the jack on wide, lowimpedance traces whenever possible. RING2 or SLEEVE ends up being the load’s ground connection; ground impedance causes excess crosstalk and noise pickup. 3) Pull SHDN low to go into standby mode; the current jack case is remembered. Cycle RESET (low ➝ high ➝ low) to run jack detection and configuration again. Route the EXTCLK traces away from low-level audio input nodes and the microphone bias bypass connection to keep the audio as noise free as possible. If audio is not playing: PGND and GND pins need to have as low an impedance connection to the ground plane. This means liberal use of vias and a solid ground plane. 1) Set VSEN = 1 to disable volume slewing. If this is not done, the volume slew down at a rate of 1ms per volume step. Table 18. Status Bits Relation to Enable Bits STATUS BIT ENABLE BIT MIC_IN MIC_BIAS MIC_AMP KS LINE_L LFTEN LINE_R RGHEN HP_L LFTEN HP_R RGHEN The maximum resistance between the pins TIP and RING1 to the headphone jack should not exceed 3I. The maximum resistance between RING2 and SLEEVE to the headphone jack should be 0.5I or better. RING2 or SLEEVE is used as the common connector in a headset or headphone. Any impedance on this path decreases crosstalk performance. Power-Supply Bypassing A bulk 10FF capacitor is required for proper chargepump operation. The capacitors are readily available in 0603 packages in the necessary voltage rating. Bypass VDD to PGND with 10FF. 35 MAX97236 Power-Up, AUTO = 0x02: MAX97236 Audio Amplifier with Jack Detection Component Selection and Layout Capacitance values of 1FF are recommended. Larger value capacitors can be used to lower power-supply ripple. Do not use charge-pump caps greater than 3.3FF. See Table 19 for a detailed description for each component value. Charge-Pump Capacitors The charge pump requires three capacitors: PVDD, PVSS, and the flying capacitor between C1N and C1P. It is recommended that these all remain the same value. Table 19. Recommended Component Values COMPONENT RECOMMENDED VALUE DETAILS Charge-pump capacitors 1FF, X5R, 6.3V or greater voltage rating or better The capacitor needs low ESR to achieve the required chargepump output impedance. If the charge-pump output impedance is too high, the headphone amplifier cannot deliver the stated output power. A larger capacitor does not completely charge in one switching cycle. A smaller capacitor does not hold enough charge. Thus, it is highly recommended to use the suggested value. VDD capacitor C1: 1FF to 10FF, X5R, 6.3V or better C2: 0.01nF to 0.1FF, X5R, 6.3V minimum C1: A smaller values helps on the ESD robustness. C2: Is not a must-have capacitor, but still recommended. This capacitor helps improve the RF immunity of the IC. Audio input capacitors 1FF, 6.3V, X5R or better Lower capacitance creates a highpass filter due to the input impedance of the IC. Microphone input capacitors 1FF, 6.3V, X5R or better — EMI filter capacitors 33pF — EMI filter ferrite bead Murata BLM15BB220 — Chip Information PROCESS: BiCMOS 36 Audio Amplifier with Jack Detection 2.4V TO 3.6V 1.8V VDD MVDD PVDD INL TIP PVDD VDD C1P C1N PVSS CHARGE PUMP RING1 GND SENSE PVDD RING2 PVSS SLEEVE INR JACKSW PVSS MVDD MAX97236 MOUTP TO JACK MECH SW MOUTN JACK DETECTION AND CONFIGURATION 2.2kI/2.6kI/3kI SDA SCL IRQ I2C MIC BIAS SELECT INTERFACE AND CONTROL HP VOL CONTROL MIC SENSE MIC BIAS MBIAS ADC I.C. EXTCLK GND PGND 37 MAX97236 Functional Diagram/Typical Application Circuit MAX97236 Audio Amplifier with Jack Detection Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 25-Bump WLP W252G2+1 21-0453 Refer to Application Note 1891 PIN 1 INDICATOR E MARKING COMMON DIMENSIONS 1 A A3 A 0.64 0.05 A1 0.19 0.03 0.45 REF A2 AAAA D A1 A2 0.05 S S TOP VIEW 0.025 BASIC A3 A See Note 7 SIDE VIEW E1 SE b 0.27 D1 1.60 E1 1.60 e 0.40 BASIC SD 0.00 BASIC SE 0.00 BASIC 0.03 e B E E SD D C D1 B A 1 2 3 4 5 A b 0.05 M S D DEPOPULATED BUMPS PKG. CODE MIN MAX MIN MAX W252D2+1 2.25 2.36 2.25 2.36 NONE W252F2+1 2.02 2.16 2.02 2.16 NONE W252G2+1 2.32 2.44 2.22 2.34 NONE W252H2+1 2.41 2.44 2.41 2.44 NONE AB BOTTOM VIEW NOTES: 1. Terminal pitch is defined by terminal center to center value. 2. Outer dimension is defined by center lines between scribe lines. 3. All dimensions in millimeter. 4. Marking shown is for package orientation reference only. 5. Tolerance is ± 0.02 unless specified otherwise. 6. All dimensions apply to PbFree (+) package codes only. 7. Front - side finish can be either Black or Clear. - DRAWING NOT TO SCALE - 38 TITLE APPROVAL PACKAGE OUTLINE 25 BUMPS, WLP PKG. 0.4mm PITCH DOCUMENT CONTROL NO. 21-0453 REV. D 1 1 Audio Amplifier with Jack Detection REVISION NUMBER REVISION DATE 0 3/11 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products 39 Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX97236 Revision History