19-0527; Rev 0; 5/06 KIT ATION EVALU E L B AVAILA 10-Bit, 11Msps, Full-Duplex Analog Front-End DA4 DA5 DA6 19 AD6 QDP 53 18 AD5 17 AD4 REFIN 54 EXPOSED PADDLE (GND) 16 AD3 15 AD2 REFN 56 4 5 6 7 8 9 10 11 12 13 14 AD1 3 AD0 2 GND 1 QAP T5677-1 DA7 20 AD7 QDN 52 QAN 56 Thin QFN-EP** 21 AD8 VDD 51 VDD MAX19711ETN+ *All devices are specified over the -40°C to +85°C operating range. **EP = Exposed paddle. +Denotes lead-free package. DA8 22 AD9 MAX19711 GND 50 CLK T5677-1 DA9 23 OGND IDP 49 GND 56 Thin QFN-EP** DOUT 24 OVDD IDN 48 GND MAX19711ETN DIN 25 DA0 VDD 47 IAN PKG CODE SCLK VDD 26 DA1 DAC1 46 IAP PIN-PACKAGE CS/WAKE GND VDD 27 DA2 DAC2 45 COM 55 Ordering Information PART* 28 DA3 DAC3 44 VDD CDMA Data Cards Portable Communication Equipment 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ADC1 43 REFP CDMA Handsets TOP VIEW VDD Applications Pin Configuration ADC2 The MAX19711 is an ultra-low-power, highly integrated mixed-signal analog front-end (AFE) ideal for CDMA communication applications operating in full-duplex (FD) mode. Optimized for high dynamic performance and ultra-low power, the device integrates a dual 10-bit, 11Msps receive (Rx) ADC; dual 10-bit, 11Msps transmit (Tx) DAC with CDMA baseband filters; three fast-settling 12-bit aux-DAC channels for ancillary RF front-end control; and a 10-bit, 333ksps housekeeping aux-ADC. The typical operating power in FD mode is 37.5mW/42.7mW at a 4.915MHz/11MHz clock frequency. The Rx ADCs feature 54.8dB SNR and 74.2dBc SFDR at 1.875MHz input frequency with an 11MHz clock frequency. The analog I/Q input amplifiers are fully differential and accept 1.024V P-P full-scale signals. Typical I/Q channel matching is ±0.01° phase and ±0.01dB gain. The Tx DACs with CDMA lowpass filters feature -3dB cutoff frequency of 1.3MHz and > 64dBc stopband rejection at fIMAGE = 4.285MHz at fCLK = 4.915MHz. The analog I-Q full-scale output voltage range is selectable at ±410mV or ±500mV differential. The output DC commonmode voltage is selectable from 0.86V to 1.36V. The I/Q channel offset is adjustable to optimize radio lineup sideband/carrier suppression. Typical I-Q channel matching is ±0.03dB gain and ±0.07° phase. Two independent 10-bit parallel, high-speed digital buses used by the Rx ADC and Tx DAC allow fullduplex operation for frequency-division duplex applications. The Rx ADC and Tx DAC can be disabled independently to optimize power management. A 3-wire serial interface controls power-management modes, the aux-DAC channels, and the aux-ADC channels. The MAX19711 operates on a single 2.7V to 3.3V analog supply and 1.8V to 3.3V digital I/O supply. The MAX19711 is specified for the extended (-40°C to +85°C) temperature range and is available in a 56-pin, thin QFN package. The Selector Guide at the end of the data sheet lists other pin-compatible versions in this AFE family. For time-division duplex (TDD) applications, refer to the MAX19705–MAX19708 AFE family of products. Features ♦ Dual 10-Bit, 11Msps Rx ADC and Dual 10-Bit, 11Msps Tx DAC ♦ Ultra-Low Power 37.5mW/42.7mW at fCLK = 4.915MHz/11MHz, FD Mode 24.3mW at fCLK = 11MHz, Slow Rx Mode 34.5mW at fCLK = 11MHz, Slow Tx Mode Low-Current Standby and Shutdown Modes ♦ Integrated CDMA Filters with > 64dBc Stopband Rejection ♦ Programmable Tx DAC Common-Mode DC Level and I/Q Offset Trim ♦ Excellent Dynamic Performance SNR = 54.8dB at fIN = 1.875MHz (Rx ADC) SFDR = 75dBc at fOUT = 620kHz (Tx DAC) ♦ Three 12-Bit, 1µs Aux-DACs ♦ 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and Data Averaging ♦ Excellent Gain/Phase Match ±0.01° Phase, ±0.01dB Gain (Rx ADC) at fIN = 1.87MHz ♦ Multiplexed Parallel Digital I/O ♦ Serial-Interface Control ♦ Versatile Power-Control Circuits Shutdown, Standby, Idle, Tx/Rx Disable ♦ Miniature 56-Pin Thin QFN Package (7mm x 7mm x 0.8mm) THIN QFN NOTE: THE PIN 1 INDICATOR IS “+” FOR LEAD-FREE DEVICES. Functional Diagram and Selector Guide appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX19711 General Description MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End ABSOLUTE MAXIMUM RATINGS VDD to GND, OVDD to OGND ..............................-0.3V to +3.6V GND to OGND.......................................................-0.3V to +0.3V IAP, IAN, QAP, QAN, IDP, IDN, QDP, QDN, DAC1, DAC2, DAC3 to GND .....................-0.3V to VDD ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V) REFP, REFN, REFIN, COM to GND ...........-0.3V to (VDD + 0.3V) AD0–AD9, DA0–DA9, SCLK, DIN, CS/WAKE, CLK, DOUT to OGND .........................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 56-Pin Thin QFN-EP (derate 27.8mW/°C above +70°C) 2.22W Thermal Resistance θJA ..................................................36°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP 3.0 MAX UNITS POWER REQUIREMENTS Analog Supply Voltage VDD 2.7 Output Supply Voltage OVDD 1.8 VDD Supply Current V V FD mode: fCLK = 11MHz, fOUT = 620kHz on both DAC channels; fIN = 1.87MHz on both ADC channels; aux-DACs ON and at midscale, aux-ADC ON 14.25 FD mode: fCLK = 4.915MHz, fOUT = 620kHz on both DAC channels; fIN = 1.87MHz on both ADC channels; auxDACs ON and at midscale, aux-ADC ON 12.5 SPI2-Tx mode: fCLK = 11MHz, fOUT = 620kHz on both DAC channels; Rx ADC OFF; aux-DACs ON and at midscale, auxADC ON 11.5 14 SPI1-Rx mode: fCLK = 11MHz, fIN = 1.87MHz on both ADC channels; Tx DAC OFF (Tx DAC outputs at 0V); aux-DACs ON and at midscale, aux-ADC ON 8.1 10 SPI4-Tx mode: fCLK = 11MHz, fOUT = 620kHz on both DAC channels; Rx ADC ON (output tri-stated); aux-DACs ON and at midscale, aux-ADC ON 14.1 16.5 SPI3-Rx mode: fCLK = 11MHz, fIN = 1.87MHz on both channels; Tx DAC ON (Tx DAC outputs at midscale); aux-DACs ON and at midscale, aux-ADC ON 13.8 16.5 Standby mode: CLK = 0 or OVDD; aux-DACs ON and at midscale, aux-ADC ON 2 3.3 VDD _______________________________________________________________________________________ 17 4 mA 10-Bit, 11Msps, Full-Duplex Analog Front-End ELECTRICAL CHARACTERISTICS (continued) PARAMETER SYMBOL CONDITIONS MIN TYP Idle mode: fCLK = 11MHz; aux-DACs ON and at midscale, aux-ADC ON VDD Supply Current Shutdown mode: CLK = 0 or OVDD, auxADC OFF 0.5 FD mode: fCLK = 11MHz, fOUT = 620kHz on both DAC channels; fIN = 1.87MHz on both ADC channels; aux-DACs ON and at midscale, aux-ADC ON 1.5 MAX UNITS 7 mA 5 µA mA OVDD Supply Current SPI1-Rx and SPI3-Rx modes: fCLK = 11MHz, fIN = 1.87MHz on both ADC channels; DAC input bus tri-stated; auxDACs ON and at midscale, aux-ADC ON 1.4 SPI2-Tx and SPI4-Tx modes: fCLK = 11MHz, fOUT = 620kHz on both DAC channels; ADC output bus tri-stated; auxDACs ON and at midscale, aux-ADC ON 80 Standby mode: CLK = 0 or OVDD; auxDACs ON and at midscale, aux-ADC ON 0.1 Idle mode: fCLK = 11MHz; aux-DACs ON and at midscale, aux-ADC ON 18.5 Shutdown mode: CLK = 0 or OVDD, auxADC OFF 0.1 µA Rx ADC DC ACCURACY Resolution 10 Bits Integral Nonlinearity INL ±0.8 Differential Nonlinearity DNL ±0.5 Offset Error Residual DC offset error Gain Error Includes reference error DC Gain Matching Offset Matching Gain Temperature Coefficient Power-Supply Rejection -5 ±0.2 LSB LSB +5 %FS %FS -5 ±0.9 +5 -0.15 ±0.04 +0.15 dB ±9 LSB ±30 ppm/°C Offset (VDD ±5%) ±0.2 Gain (VDD ±5%) ±0.08 Differential or single-ended inputs ±0.512 V VDD / 2 V 490 kΩ 5 pF LSB Rx ADC ANALOG INPUT Input Differential Range VID Input Common-Mode Voltage Range VCM Input Impedance RIN CIN Switched capacitor load _______________________________________________________________________________________ 3 MAX19711 (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 11 MHz Rx ADC CONVERSION RATE Maximum Clock Frequency fCLK Data Latency (Note 2) Channel IA 5 Channel QA 5.5 Clock Cycles Rx ADC DYNAMIC CHARACTERISTICS (Note 3) Signal-to-Noise Ratio SNR fIN = 1.875MHz 53.3 fIN = 3MHz fIN = 1.875MHz 54.8 dB 54.8 53.2 54.8 Signal-to-Noise and Distortion SINAD Spurious-Free Dynamic Range SFDR Total Harmonic Distortion THD Third-Harmonic Distortion HD3 Intermodulation Distortion IMD fIN1 = 1.7MHz, AIN1 = -7dBFS; fIN2 = 900kHz, AIN2 = -7dBFS -71 dBc Third-Order Intermodulation Distortion IM3 fIN1 = 1.7MHz, AIN1 = -7dBFS; fIN2 = 900kHz, AIN2 = -7dBFS -75 dBc 3.5 ns fIN = 3MHz fIN = 1.875MHz 64.5 74.2 fIN = 3MHz 78.3 fIN = 1.875MHz -72.1 fIN = 3MHz dBc -63.5 -75 fIN = 1.875MHz -82.8 fIN = 3MHz -78.3 Aperture Delay Aperture Jitter Overdrive Recovery Time dB 54.7 1.5x full-scale input dBc dBc 2 psRMS 2 ns -89 dB Rx ADC INTERCHANNEL CHARACTERISTICS Crosstalk Rejection fINX,Y = 1.8MHz, AINX,Y = -0.5dBFS, fINY,X = 1MHz, AINY,X = -0.5dBFS (Note 4) Amplitude Matching fIN = 1.8MHz, AIN = -0.5dBFS (Note 5) ±0.01 dB Phase Matching fIN = 1.8MHz, AIN = -0.5dBFS (Note 5) ±0.01 Degrees Tx PATH DC ACCURACY Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL Residual DC Offset Full-Scale Gain Error 4 VOS 10 Bits ±0.55 Guaranteed monotonic (Note 6) LSB -0.9 ±0.4 +0.9 TA ≥ +25°C -5 ±0.5 +5 TA < +25°C -7 ±0.5 +7 VFS = 410mV -50 ±9 +50 VFS = 500mV -52 ±9 +52 _______________________________________________________________________________________ LSB mV mV 10-Bit, 11Msps, Full-Duplex Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Tx PATH DYNAMIC PERFORMANCE Corner Frequency fC Passband Ripple Group Delay Variation in Passband Error-Vector Magnitude EVM -3dB corner 1.3 1.60 MHz DC to 640kHz 1.05 0.16 0.3 dBP-P DC to 640kHz DC to 700kHz 50 2 ns % 64 dBc fIMAGE = 4.285MHz, fOUT = 630kHz, fCLK = 4.915MHz Stopband Rejection Spot relative to 100kHz Baseband Attenuation 56 2MHz 21.5 4MHz 49 5MHz 58 10MHz 90 20MHz 90 (Note 2) dB DAC Conversion Rate fCLK In-Band Noise Density ND fOUT = 630kHz, fCLK = 4.915MHz -115 11 dBFS/Hz Third-Order Intermodulation Distortion IM3 fOUT1 = 620kHz, fOUT2 = 640kHz -77 dBc 10 pV•s 75 dBc Glitch Impulse MHz Spurious-Free Dynamic Range to Nyquist SFDR fOUT = 620kHz Total Harmonic Distortion to Nyquist THD fOUT = 620kHz -75 Signal-to-Noise Ratio to Nyquist SNR fOUT = 620kHz 55.9 dB 92 dB 61.5 -61.5 dBc Tx PATH INTERCHANNEL CHARACTERISTICS I-to-Q Output Isolation fOUTX,Y = 500kHz, fOUTY,X = 620kHz Gain Mismatch Between I and Q Channels Measured at DC, VFS = 410mV or 500mV Clock Leakage fOUT = 620kHz -90 dBc Phase Mismatch Between I and Q Channels fOUT = 620kHz ±0.07 Degrees 800 Ω -0.36 Differential Output Impedance ±0.03 +0.36 dB Tx PATH ANALOG OUTPUT Full-Scale Output Voltage Output Common-Mode Voltage VFS VCOMD Bit E7 = 0 (default) ±410 Bit E7 = 1 ±500 mV Bits CM1 = 0, CM0 = 0 (default) 1.28 1.36 1.45 Bits CM1 = 0, CM0 = 1 1.13 1.2 1.30 Bits CM1 = 1, CM0 = 0 0.99 1.06 1.15 Bits CM1 = 1, CM0 = 1 0.79 0.86 0.95 V _______________________________________________________________________________________ 5 MAX19711 ELECTRICAL CHARACTERISTICS (continued) MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Rx ADC–Tx DAC ADC: fINI = fINQ = 1.8MHz, DAC: fOUTI = fOUTQ = 620kHz Receive Transmit Isolation 85 dB AUXILIARY ADC (ADC1, ADC2) Resolution Full-Scale Reference N VREF 10 AD1 = 0 (default) AD1 = 1 At DC Input-Leakage Current Measured at unselected input from 0 to VREF Includes reference error, AD1 = 0 V VDD Analog Input Range Analog Input Impedance Bits 2.048 0 to VREF V 500 kΩ ±0.1 -5 µA Gain Error GE Zero-Code Error ZE ±2 mV Differential Nonlinearity DNL ±0.6 LSB Integral Nonlinearity INL ±0.6 LSB 210 µA ±1.25 LSB Supply Current +5 %FS AUXILIARY DACs (DAC1, DAC2, DAC3) Resolution N 12 Integral Nonlinearity INL From code 100 to code 4000 Differential Nonlinearity DNL Guaranteed monotonic from code 100 to code 4000 (Note 6) Output-Voltage Low VOL RL > 200kΩ Output-Voltage High VOH RL > 200kΩ -1.0 Bits ±0.65 +1.2 LSB 0.2 V 2.57 V 4 Ω Settling Time DC output at midscale From code 1024 to code 3072, within ±10 LSB 1 µs Glitch Impulse From code 0 to code 4095 24 nV•s DC Output Impedance Rx ADC–Tx DAC TIMING CHARACTERISTICS CLK Rise to Channel-I Output Data Valid tDOI Figure 3 (Note 6) 4.9 7.9 11.5 ns CLK Fall to Channel-Q Output Data Valid tDOQ Figure 3 (Note 6) 6.1 9.1 13.2 ns I-DAC DATA to CLK Fall Setup Time tDSI Figure 3 (Note 6) 10 ns Q-DAC DATA to CLK Rise Setup Time tDSQ Figure 6 (Note 6) 10 ns CLK Fall to I-DAC Data Hold Time tDHI Figure 6 (Note 6) 0 ns 6 _______________________________________________________________________________________ 10-Bit, 11Msps, Full-Duplex Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER CLK Rise to Q-DAC Data Hold Time SYMBOL tDHQ CONDITIONS Figure 6 (Note 6) MIN TYP MAX 0 CLK Duty Cycle ns 50 CLK Duty-Cycle Variation Digital Output Rise/Fall Time 20% to 80% UNITS % ±15 % 2.4 ns SERIAL-INTERFACE TIMING CHARACTERISTICS (Figures 7 and 9, Note 6) Falling Edge of CS/WAKE to Rising Edge of First SCLK Time tCSS 10 ns DIN to SCLK Setup Time tDS 10 ns DIN to SCLK Hold Time tDH 0 ns SCLK Pulse-Width High tCH 25 ns SCLK Pulse-Width Low tCL 25 ns SCLK Period tCP 50 ns SCLK to CS/WAKE Setup Time tCS 10 ns CS/WAKE High Pulse Width tCSW 80 ns CS/WAKE High to DOUT Active High tCSD Bit AD0 set 200 ns Bit AD0 set, no averaging, fCLK = 11MHz, CLK divider = 4 4.3 µs 200 ns CS/WAKE High to DOUT Low (Aux-ADC Conversion Time) tCONV DOUT Low to CS/WAKE Setup Time tDCS Bit AD0, AD10 set SCLK Low to DOUT Data Out tCD Bit AD0, AD10 set CS/WAKE High to DOUT High Impedance tCHZ Bit AD0, AD10 set 14.5 200 ns ns MODE-RECOVERY TIMING CHARACTERISTICS (Figure 8) Shutdown Wake-Up Time tWAKE,SD From shutdown to Rx mode, ADC settles to within 1dB SINAD 500 From shutdown to Tx mode, DAC settles to within 10 LSB error 26 From aux-ADC enable to aux-ADC start conversion 10 From shutdown to aux-DAC output valid 28 From shutdown to FD mode, ADC settles to within 1dB SINAD, DAC settles to within 10 LSB error 500 µs _______________________________________________________________________________________ 7 MAX19711 ELECTRICAL CHARACTERISTICS (continued) MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Idle Wake-Up Time (With CLK) Standby Wake-Up Time SYMBOL tWAKE,ST0 tWAKE,ST1 CONDITIONS MIN TYP From idle to Rx mode with CLK present during idle, ADC settles to within 1dB SINAD 6.8 From idle to Tx mode with CLK present during idle, DAC settles to 10 LSB error 5.0 From idle to FD mode, ADC settles to within 1dB SINAD, DAC settles to within 10 LSB error 6.8 From standby to Rx mode, ADC settles to within 1dB SINAD 7.2 From standby to Tx mode, DAC settles to 10 LSB error 21.8 From standby to FD mode, ADC settles to within 1dB SINAD, DAC settles to within 10 LSB error 21.8 MAX UNITS µs µs Enable Time from Tx to Rx, Fast Mode tENABLE,RX ADC settles to within 1dB SINAD 0.1 µs Enable Time from Rx to Tx, Fast Mode tENABLE,TX DAC settles to within 10 LSB error 1 µs Enable Time from Tx to Rx, Slow Mode tENABLE,RX ADC settles to within 1dB SINAD 6.8 µs Enable Time from Rx to Tx, Slow Mode tENABLE,TX DAC settles to within 10 LSB error 5 µs INTERNAL REFERENCE (VREFIN = VDD; VREFP, VREFN, VCOM levels are generated internally) Positive Reference VREFP - VCOM 0.256 V Negative Reference VREFN - VCOM -0.256 V VCOM VDD / 2 VDD / 2 VDD / 2 - 0.15 + 0.15 V Maximum REFP/REFN/COM Source Current ISOURCE 2 mA Maximum REFP/REFN/COM Sink Current ISINK 2 mA Differential Reference Output VREF Common-Mode Output Voltage Differential Reference Temperature Coefficient 8 REFTC VREFP - VREFN +0.490 +0.512 ±30 _______________________________________________________________________________________ +0.534 V ppm/°C 10-Bit, 11Msps, Full-Duplex Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BUFFERED EXTERNAL REFERENCE (external VREFIN = 1.024V applied; VREFP, VREFN, VCOM levels are generated internally) Reference Input Voltage VREFIN 1.024 V 0.512 V VCOM VDD / 2 V Maximum REFP/REFN/COM Source Current ISOURCE 2 mA Maximum REFP/REFN/COM Sink Current ISINK 2 mA Differential Reference Output VDIFF Common-Mode Output Voltage VREFP - VREFN REFIN Input Current -0.7 µA REFIN Input Resistance 500 kΩ DIGITAL INPUTS (CLK, SCLK, DIN, CS/WAKE, DA9–DA0) Input High Threshold VINH Input Low Threshold VINL Input Leakage DIIN Input Capacitance 0.7 x OVDD V 0.3 x OVDD CLK, SCLK, DIN, CS/WAKE = OGND or OVDD -1 +1 DA9–DA0 = OVDD -1 +1 DA9–DA0 = OGND -5 +5 DCIN 5 V µA pF DIGITAL OUTPUTS (AD9–AD0, DOUT) Output-Voltage Low VOL ISINK = 200µA Output-Voltage High VOH ISOURCE = 200µA Tri-State Leakage Current ILEAK Tri-State Output Capacitance COUT 0.2 x OVDD 0.8 x OVDD V V -1 +1 5 µA pF Note 1: Specifications from TA = +25°C to +85°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Note 2: The minimum clock frequency (fCLK) for the MAX19711 is 2MHz (typ). The minimum aux-ADC sample rate clock frequency (ACLK) is determined by fCLK and the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK > 2MHz / 128 = 15.6kHz. The aux-ADC conversion time does not include the time to clock the serial data out of DOUT. The maximum conversion time (for no averaging, NAVG = 1) will be tCONV (max) = (12 x 1 x 128) / 2MHz = 768µs. Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude of the digital outputs. SINAD and THD are calculated using HD2 through HD6. Note 4: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel FFT test tones. Note 5: Amplitude and phase matching are measured by applying the same signal to each channel, and comparing the two output signals using a sine-wave fit. Note 6: Guaranteed by design and characterization. _______________________________________________________________________________________ 9 MAX19711 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11.8MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) -40 -50 -60 6 5 2 4 -30 3 -40 -50 -60 6 -70 5 2 4 -20 -30 3 -40 -50 -60 -80 -80 -90 -90 -90 -100 -100 -100 1 2 3 4 5 0 1 2 3 4 5 0 2 3 4 5 FREQUENCY (MHz) Rx ADC CHANNEL-QA TWO-TONE FFT PLOT Rx ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT FREQUENCY -10 -20 57 QA 55 -30 57 MAX19711 toc05 fIN1 = 1.7472412MHz fIN2 = 1.8394287MHz AIN1 = AIN2 = -7dBFS IMD = -68dBc QA 55 SNR (dB) -50 fIN2 - fIN1 -70 -80 53 SINAD (dB) 53 -40 -60 1 FREQUENCY (MHz) 0 AMPLITUDE (dBFS) -80 FREQUENCY (MHz) MAX19711 toc04 0 fIN2 - fIN1 -70 MAX19711 toc06 -70 -20 fIN1 = 1.7472412MHz fIN2 = 1.8394287MHz AIN1 = AIN2 = -7dBFS IMD = -70dBc -10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -30 0 MAX19711 toc02 -20 Rx ADC CHANNEL-IA TWO-TONE FFT PLOT FUNDAMENTAL fIN = 1.875MHz AIN = -0.515dBFS SINAD = 54.69dB SNR = 54.745dB THD = -73.643dBc SFDR = 78.292dBc -10 AMPLITUDE (dBFS) FUNDAMENTAL fIN = 1.875MHz AIN = -0.552dBFS SINAD = 54.845dB SNR = 54.887dB THD = -76.159dBc SFDR = 79.81dBc -10 0 MAX19711 toc01 0 Rx ADC CHANNEL-QA FFT PLOT (8192 SAMPLES) MAX19711 toc03 Rx ADC CHANNEL-IA FFT PLOT (8192 SAMPLES) IA 51 IA 51 49 49 47 47 -90 45 -100 0 1 2 3 4 25 50 75 100 125 150 175 200 225 0 25 50 75 100 125 150 175 200 225 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) Rx ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY Rx ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT AMPLITUDE 80 SFDR (dBc) 70 65 QA 60 IA 75 65 QA 60 25 50 75 100 125 150 175 200 225 ANALOG INPUT FREQUENCY (MHz) IA 40 35 QA 30 25 50 0 50 45 70 55 55 fIN = 1.875MHz 55 SNR (dB) IA 60 MAX19711 toc08 MAX19711 toc07 85 MAX19711 toc09 FREQUENCY (MHz) 75 10 45 0 5 80 -THD (dBc) MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End 20 0 25 50 75 100 125 150 175 200 225 ANALOG INPUT FREQUENCY (MHz) -25 -20 -15 -10 -5 ANALOG INPUT AMPLITUDE (dBFS) ______________________________________________________________________________________ 0 10-Bit, 11Msps, Full-Duplex Analog Front-End fIN = 1.875MHz 55 70 40 35 60 55 50 25 45 20 40 -25 -20 -15 -10 -5 0 -25 -20 -15 -10 -5 fIN = 1.875MHz IA -25 0 QA -20 -15 -10 -5 0 ANALOG INPUT AMPLITUDE (dBFS) ANALOG INPUT AMPLITUDE (dBFS) Rx ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING FREQUENCY Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. SAMPLING FREQUENCY Rx ADC TOTAL HARMONIC DISTORTION vs. SAMPLING FREQUENCY 55.5 56.0 IA fIN = 1.875MHz 55.5 55.0 85 MAX19711 toc14 fIN = 1.875MHz IA MAX19711 toc15 ANALOG INPUT AMPLITUDE (dBFS) MAX19711 toc13 56.0 fIN = 1.875MHz IA 80 54.5 QA 54.0 -THD (dBc) 55.0 SINAD (dB) 54.5 QA 75 70 54.0 53.5 QA 65 53.5 53.0 53.0 4 5 6 7 8 9 10 11 12 60 2 3 4 5 6 7 8 9 10 11 12 3 4 5 6 7 8 9 10 11 12 SAMPLING FREQUENCY (MHz) SAMPLING FREQUENCY (MHz) Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING FREQUENCY Rx ADC SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. CLOCK DUTY CYCLE QA 85 65.0 62.5 60.0 80 70 SNR (dB) 75 IA 65 60 55 fIN = 1.875MHz IA 4 5 6 7 8 9 10 11 12 SAMPLING FREQUENCY (MHz) 62.5 57.5 55.0 55.0 52.5 QA 50.0 fIN = 1.875MHz 60.0 57.5 IA 52.5 QA 50.0 47.5 47.5 45.0 45.0 42.5 42.5 40.0 3 65.0 MAX19711 toc18 fIN = 1.875MHz 2 2 SAMPLING RATE (MHz) SINAD (dB) 90 3 MAX19711 toc16 2 MAX19711 toc17 SNR (dB) QA 65 IA QA 30 85 80 75 70 65 60 55 50 45 40 35 30 25 20 SFDR (dBc) IA -THD (dBc) SINAD (dB) 45 SFDR (dBc) fIN = 1.875MHz 75 50 Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT AMPLITUDE MAX19711 toc12 80 MAX19711 toc10 60 Rx ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT AMPLITUDE MAX19711 toc11 Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT AMPLITUDE 40.0 35 40 45 50 55 CLOCK DUTY CYCLE (%) 60 65 35 40 45 50 55 60 65 CLOCK DUTY CYCLE (%) ______________________________________________________________________________________ 11 MAX19711 Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11.8MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11.8MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) QA 45 50 55 60 65 QA 0.50 0.25 QA 0 -0.25 -0.50 IA -0.75 -1.00 35 40 45 50 55 60 -40 65 -15 10 35 60 CLOCK DUTY CYCLE (%) TEMPERATURE (°C) Rx ADC GAIN ERROR vs. TEMPERATURE Tx PATH SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING FREQUENCY Tx PATH SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY 90 MAX19711 toc22 1.75 fOUT = 620kHz 85 1.50 QD 85 1.00 0.75 QD 80 SFDR (dBc) SFDR (dBc) 1.25 75 70 ID 85 90 80 QA 0.50 75 70 65 65 60 60 ID IA 55 0 10 35 60 55 2 85 Tx PATH SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT AMPLITUDE 5 6 7 8 9 10 11 100 MAX19711 toc25 0 fOUT = 610kHz ID -10 AMPLITUDE (dBFS) 70 60 50 QD 30 fOUT = 640kHz -20 -40 -50 HD2 HD3 -70 -80 -50 -10 0 HD2 HD3 -60 -70 -80 -90 -20 800 -40 -100 -30 700 -30 -100 -40 600 fOUT = 640kHz -20 10 OUTPUT AMPLITUDE (dBFS) 500 -10 -90 -50 400 0 20 -60 300 Tx PATH CHANNEL-QD SPECTRAL PLOT -30 -60 200 OUTPUT FREQUENCY (MHz) Tx PATH CHANNEL-ID SPECTRAL PLOT 90 40 4 SAMPLING FREQUENCY (MHz) TEMPERATURE (°C) 80 3 AMPLITUDE (dBFS) -15 MAX19711 toc26 -40 MAX19711 toc27 0.25 12 0.75 CLOCK DUTY CYCLE (%) 2.00 GAIN ERROR (%FS) IA MAX19711 toc24 40 1.00 MAX19711 toc23 35 fIN = 1.875MHz MAX19711 toc21 IA 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 OFFSET ERROR (%FS) fIN = 1.875MHz MAX19711 toc20 MAX19711 toc19 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 Rx ADC OFFSET ERROR vs. TEMPERATURE Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE SFDR (dBc) -THD (dBc) Rx ADC TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE SFDR (dBc) MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End 0.20 1.34 2.48 3.62 FREQUENCY (MHz) 4.76 5.90 0.20 1.34 2.48 3.62 FREQUENCY (MHz) ______________________________________________________________________________________ 4.76 5.90 10-Bit, 11Msps, Full-Duplex Analog Front-End fIMAGE -50 -60 -70 -40 fIMAGE -50 -60 -70 -20 -40 -50 -70 -90 -90 -100 -100 -100 2.12 3.08 4.04 -80 0.20 5.00 1.16 2.12 3.08 4.04 FREQUENCY (MHz) Tx PATH CHANNEL-QD TWO-TONE SPECTRAL PLOT SUPPLY CURRENT vs. SAMPLING FREQUENCY fOUT1 = 546kHz, fOUT2 = 647kHz -20 16 5.00 0.20 1.34 2.48 3.62 4.76 5.90 FREQUENCY (MHz) Rx ADC INTEGRAL NONLINEARITY 1.00 MAX19711 toc32 FREQUENCY (MHz) -10 fOUT1 = fOUT2 -60 -90 0 fIN = 1.875MHz, fOUT = 630kHz FD MODE 15 0.75 0.50 -30 14 -50 fOUT1 + fOUT2 -60 0.25 INL (LSB) IVDD (mA) -40 13 0 -0.25 12 -70 -0.50 -80 11 -0.75 -90 -100 -1.00 10 1.34 2.48 3.62 4.76 2 5.90 4 5 6 7 8 9 TRANSMIT FILTER FREQUENCY RESPONSE -60 0.4 0.4 0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 1 FREQUENCY (MHz) 10 0 -0.2 -80 -100 0.6 DNL (LSB) INL (LSB) -40 Tx PATH DIFFERENTIAL NONLINEARITY 0.8 MAX19711 toc35 MAX19711 toc34 0.6 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE Tx PATH INTEGRAL NONLINEARITY 0.8 -20 0.1 0 10 11 12 SAMPLING FREQUENCY (MHz) FREQUENCY (MHz) 0 3 MAX19711 toc36 0.20 AMPLITUDE (dB) -30 -80 1.16 fOUT = 546kHz, fOUT2 = 647kHz MAX19711 toc30 0 -10 -80 0.20 AMPLITUDE (dBFS) -30 AMPLITUDE (dBFS) -40 fOUT = 630kHz, fCLK = 4.915kHz -20 MAX19711 toc31 AMPLITUDE (dBFS) -30 -10 AMPLITUDE (dBFS) fOUT = 630kHz, fCLK = 4.915kHz Tx PATH CHANNEL-ID TWO-TONE SPECTRAL PLOT MAX19711 toc29 -10 -20 0 MAX19711 toc28 0 Tx PATH CHANNEL-QD SPECTRAL PLOT WITH IMAGE REJECTION MAX19711 toc33 Tx PATH CHANNEL-ID SPECTRAL PLOT WITH IMAGE REJECTION 0 128 256 384 512 640 768 896 1024 DIGITAL INPUT CODE 0 128 256 384 512 640 768 896 1024 DIGITAL INPUT CODE ______________________________________________________________________________________ 13 MAX19711 Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11.8MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11.8MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE TRANSMIT FILTER PASSBAND RIPPLE 0 0.510 0.505 1.0 -0.02 0.5 -0.04 -0.06 -0.10 -1.0 -0.12 -1.5 -15 10 35 60 -2.0 0 85 0.3 0.6 0.9 1.2 0 FREQUENCY (MHz) TEMPERATURE (°C) 0.6 AUX-ADC DIFFERENTIAL NONLINEARITY 0.8 MAX19711 toc41 2.0 MAX19711 toc40 0.8 DIGITAL INPUT CODE AUX-ADC INTEGRAL NONLINEARITY AUX-DAC DIFFERENTIAL NONLINEARITY 1.0 1.5 0.6 1.0 0.4 0.5 0.2 0 -0.2 0 -0.5 -0.4 -0.6 -0.8 -1.0 -0.4 -1.5 -0.6 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 DIGITAL INPUT CODE DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE AUX-DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT AUX-DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT AUX-DAC SETTLING TIME 3.0 MAX19711 toc43 3.0 2.5 OUTPUT VOLTAGE (V) 2.5 2.0 1.5 1.0 0.5 0 0.001 -0.8 0 512 1024 1536 2048 2560 3072 3584 4096 MAX19711 toc44 0 0 -0.2 -2.0 -1.0 STEP FROM CODE 1024 TO CODE 3072 1V/div 2.0 CS/WAKE 1.5 500mV/div 1.0 AUX-DAC OUTPUT 0.5 0.01 0.1 1 10 OUTPUT SOURCE CURRENT (mA) 14 DNL (LSB) INL (LSB) DNL (LSB) 0.4 0.2 512 1024 1536 2048 2560 3072 3584 4096 MAX19711 toc42 -40 0 -0.5 -0.08 -0.14 0.500 1.5 100 MAX19711 toc45 AMPLITUDE (dB) VREFP - VREFN (V) 0.515 MAX19711 toc39 0.02 INL (LSB) VREFP - VREFN AUX-DAC INTEGRAL NONLINEARITY 2.0 MAX19711 toc38 0.04 MAX19711 toc37 0.520 OUTPUT VOLTAGE (V) MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End 0 0.001 0.01 0.1 1 10 100 400ns/div OUTPUT SINK CURRENT (mA) ______________________________________________________________________________________ 10-Bit, 11Msps, Full-Duplex Analog Front-End PIN NAME FUNCTION 1 REFP Positive Reference Voltage Input Terminal. Bypass with a 0.33µF capacitor to GND as close to REFP as possible. 2, 8, 11, 39, 41, 47, 51 VDD Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 3 IAP Channel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP. Channel-IA Negative Analog Input. For single-ended operation, connect IAN to COM. 4 IAN 5, 7, 12, 40, 50 GND Analog Ground. Connect all GND pins to ground plane. 6 CLK Conversion Clock Input. Clock signal for both receive ADCs and transmit DACs. 9 QAN Channel-QA Negative Analog Input. For single-ended operation, connect QAN to COM. 10 QAP Channel-QA Positive Analog Input. For single-ended operation, connect signal source to QAP. 13–22 AD0–AD9 23 OGND Output-Driver Ground 24 OVDD Output-Driver Power Supply. Supply range from +1.8V to VDD. Bypass OVDD to OGND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 25–34 DA0–DA9 35 DOUT 36 DIN 37 SCLK Receive ADC Digital Outputs. AD9 is the most significant bit (MSB) and AD0 is the least significant bit (LSB). Transmit DAC Digital Inputs. DA9 is the most significant bit (MSB) and DA0 is the least significant bit (LSB). DA0–DA9 are internally pulled up to OVDD. Aux-ADC Digital Output 3-Wire Serial-Interface Data Input. Data is latched on the rising edge of SCLK. 3-Wire Serial-Interface Clock Input 3-Wire Serial-Interface Chip-Select/WAKE Input. When the MAX19711 is in shutdown, CS/WAKE controls the wake-up function. See the Wake-Up Function section. 38 CS/WAKE 42 ADC2 Selectable Auxiliary ADC Analog Input 2 43 ADC1 Selectable Auxiliary ADC Analog Input 1 44 DAC3 Auxiliary DAC3 Analog Output (VOUT = 0 at Power-Up) 45 DAC2 Auxiliary DAC2 Analog Output (VOUT = 0 at Power-Up) 46 DAC1 48 IDN Tx Path Channel-ID Differential Negative Output 49 IDP Tx Path Channel-ID Differential Positive Output 52 QDN Tx Path Channel-QD Differential Negative Output 53 QDP Tx Path Channel-QD Differential Positive Output 54 REFIN Reference Input. Connect to VDD for internal reference. 55 COM Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor. 56 REFN Negative Reference Voltage Input Terminal. Rx ADC conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a 0.33µF capacitor. — EP Auxiliary DAC1 Analog Output (AFC DAC, VOUT = 1.1V at Power-Up) Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane. Detailed Description The MAX19711 integrates a dual, 10-bit Rx ADC and a dual, 10-bit Tx DAC with CDMA baseband filters while providing ultra-low power and high dynamic performance at 11Msps conversion rate. The Rx ADC analog input amplifiers are fully differential and accept 1.024VP-P full-scale signals. The Tx DAC analog outputs are fully differential with selectable ±410mV or ±500mV full-scale output, selectable common-mode DC level, and adjustable channel ID–QD offset trim. ______________________________________________________________________________________ 15 MAX19711 Pin Description MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End The MAX19711 integrates three 12-bit auxiliary DACs (aux-DACs) and a 10-bit, 333ksps auxiliary ADC (auxADC) with 4:1 input multiplexer. The aux-DAC channels feature 1µs settling time for fast AGC, VGA, and AFC level setting. The aux-ADC features data averaging to reduce processor overhead and a selectable clockdivider to program the conversion rate. power management through the 3-wire interface. The MAX19711 operates from a single 2.7V to 3.3V analog supply and a 1.8V to 3.3V digital supply. Dual 10-Bit Rx ADC The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel IA and 5.5 clock cycles for channel QA. The ADC full-scale analog input range is ±VREF with a VDD / 2 (±0.8V) common-mode input range. VREF is the difference between VREFP and VREFN. See the Reference Configurations section for details. The MAX19711 includes a 3-wire serial interface to control operating modes and power management. The serial interface is SPI™ and MICROWIRE™ compatible. The MAX19711 serial interface selects shutdown, idle, standby, FD, transmit (Tx), and receive (Rx) modes, as well as controls aux-DAC and aux-ADC channels. The MAX19711 features two independent, high-speed, 10-bit buses for the Rx ADC and Tx DAC, which allow full-duplex (FD) operation for frequency-division duplex applications. Each bus can be disabled to optimize Input Track-and-Hold (T/H) Circuits Figure 1 displays a simplified diagram of the Rx ADC input track-and-hold (T/H) circuitry. Both ADC inputs MICROWIRE is a trademark of National Semiconductor Corp. SPI is a trademark of Motorola, Inc. INTERNAL BIAS COM S5a S2a C1a S3a S4a IAP OUT C2a S4c S1 OUT IAN S4b C1b C2b S3b S5b S2b INTERNAL BIAS COM INTERNAL BIAS COM HOLD CLK HOLD TRACK TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS S5a S2a C1a S3a S4a QAP OUT C2a S4c S1 MAX19711 OUT QAN S4b C1b C2b S3b S2b INTERNAL BIAS S5b COM Figure 1. Rx ADC Internal T/H Circuits 16 ______________________________________________________________________________________ 10-Bit, 11Msps, Full-Duplex Analog Front-End DIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL INPUT (LSB) OFFSET BINARY (AD0–AD9) VREF x 512/512 511 (+Full Scale - 1 LSB) 11 1111 1111 1023 VREF x 511/512 510 (+Full Scale - 2 LSB) 11 1111 1110 1022 VREF x 1/512 +1 10 0000 0001 513 VREF x 0/512 0 (Bipolar Zero) 10 0000 0000 512 -VREF x 1/512 -1 01 1111 1111 511 -VREF x 511/512 -511 (-Full Scale +1 LSB) 00 0000 0001 1 -VREF x 512/512 -512 (-Full Scale) 00 0000 0000 0 2 x VREF 1 LSB = 1024 VREF latch, the total clock-cycle latency is 5 clock cycles for channel IA and 5.5 clock cycles for channel QA. VREF = VREFP - VREFN VREF VREF 11 1111 1111 11 1111 1110 11 1111 1101 10 0000 0001 10 0000 0000 01 1111 1111 (COM) VREF OFFSET BINARY OUTPUT CODE (LSB) OUTPUT DECIMAL CODE 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 -512 -511 -510 -509 -1 0+ 1 +509 +510 +511 +512 (COM) INPUT VOLTAGE (LSB) Figure 2. Rx ADC Transfer Function (IAP, QAP, IAN, and QAN) can be driven either differentially or single-ended. Match the impedance of IAP and IAN, as well as QAP and QAN, and set the input signal common-mode voltage within the VDD / 2 (±800mV) Rx ADC range for optimum performance. Rx ADC System Timing Requirements Figure 3 shows the relationship between the clock, analog inputs, and the resulting output data. Channels IA and QA are sampled on the rising edge of the clock signal (CLK) and the resulting data is multiplexed at the AD0–AD9 outputs. Channel IA data is updated on the rising edge and channel QA data is updated on the falling edge of CLK. Including the delay through the output Digital Output Data (AD0–AD9) AD0–AD9 are the Rx ADC digital logic outputs of the MAX19711. The logic level is set by OVDD from 1.8V to VDD. The digital output coding is offset binary (Table 1). Keep the capacitive load on the digital outputs AD0–AD9 as low as possible (< 15pF) to avoid large digital currents feeding back into the analog portion of the MAX19711 and degrading its dynamic performance. Buffers on the digital outputs isolate the outputs from heavy capacitive loads. Adding 100Ω resistors in series with the digital outputs close to the MAX19711 will help improve ADC performance. Refer to the MAX19711EVKIT schematic for an example of the digital outputs driving a digital buffer through 100Ω series resistors. During SHDN, IDLE, STBY, SPI2, and SPI4 states, digital outputs AD0–AD9 are tri-stated. Dual 10-Bit Tx DAC and Transmit Path The dual 10-bit digital-to-analog converters (Tx DACs) operate with clock speeds up to 11MHz. The Tx DAC digital inputs, DA0–DA9, are multiplexed on a single 10-bit transmit bus. The voltage reference determines the Tx path full-scale voltage at IDP, IDN and QDP, QDN analog outputs. See the Reference Configurations section for setting the reference voltage. Each Tx path output channel integrates a lowpass filter tuned to meet the CDMA spectral mask requirements. The CDMA filters are tuned for 1.3MHz cutoff frequency and > 64dBc image rejection at fIMAGE = 4.285MHz, fOUT = 630kHz, and fCLK = 4.915MHz. See Figure 4 for an illustration of the filter frequency response. Buffer amplifiers follow the CDMA filters. The amplifier outputs (IDN, IDP, QDN, QDP) are biased at an adjustable common-mode DC level and designed to drive a differen- ______________________________________________________________________________________ 17 MAX19711 Table 1. Rx ADC Output Codes vs. Input Voltage MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End 5.5 CLOCK-CYCLE LATENCY (CHQ) 5 CLOCK-CYCLE LATENCY (CHI) IA QA tCLK tCL tCH CLK tDOQ D0–D9 tDOI D0Q D1I D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q Figure 3. Rx ADC System Timing Diagram Table 2. Tx Path Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC = 1.024V, External Reference Mode VREFDAC = VREFIN, VFS = 410 for 820mVP-P Full Scale and VFS = 500 for 1VP-P Full Scale) DIFFERENTIAL OUTPUT VOLTAGE (V) OFFSET BINARY (DA0–DA9) INPUT DECIMAL CODE 1023 × (VFS ) VREFDAC 1024 1023 11 1111 1111 1023 (VFS ) VREFDAC 1024 × 1021 1023 11 1111 1110 1022 (VFS ) VREFDAC 1024 × 3 1023 10 0000 0001 513 (VFS ) VREFDAC 1024 × 1 1023 10 0000 0000 512 (VFS ) −VREFDAC 1024 × 1 1023 01 1111 1111 511 (VFS ) −VREFDAC 1024 × 1021 1023 00 0000 0001 1 (VFS ) −VREFDAC 1024 × 1023 1023 00 0000 0000 0 tial input stage with ≥ 70kΩ input impedance. This simplifies the analog interface between RF quadrature upconverters and the MAX19711. Many RF upconverters require a 0.86V to 1.36V common-mode bias. The MAX19711 common-mode DC bias eliminates discrete level-setting resistors and code-generated level shifting while preserving the full dynamic range of each Tx DAC. The Tx DAC differential analog outputs cannot be used in single-ended mode because of the internally generated common-mode DC level. Table 2 shows the 18 Tx path output voltage vs. input codes. Table 11 shows the selection of DC common-mode levels. See Figure 5 for an illustration of the Tx DAC analog output levels. The buffer amplifiers also feature a programmable fullscale output level of ±410mV or ±500mV and independent DC offset trim on each ID–QD channel. Both features are configured through the SPI interface. The DC offset correction is used to optimize sideband and carrier suppression in the Tx signal path (see Tables 8 and 10). ______________________________________________________________________________________ 10-Bit, 11Msps, Full-Duplex Analog Front-End MAX19711 AMPLITUDE DAC sin(x)/x RESPONSE OCCUPIED CHANNEL CDMA FILTER RESPONSE 0dB -3dB Tx PATH: SFDR = 75dBc THD = -75dBc SNR = 55.9dB -15dB -49.3dB -56dB (min) -57.1dB FREQ (MHz) 0.63 CHANNEL EDGE 1.3 fC 4.285 fIMAGE 4.915 fCLK NOT TO SCALE Figure 4. TD-SCDMA Filter Frequency Response Tx DAC Timing Figure 6 shows the relationship among the clock, input data, and analog outputs. Channel ID data is latched on the falling edge of the clock signal, and channel QD data is latched on the rising edge of the clock signal, at which point both ID and QD outputs are simultaneously updated. 3-Wire Serial Interface and Operation Modes The 3-wire serial interface controls the MAX19711 operation modes as well as the three 12-bit aux-DACs and the 10-bit aux-ADC. Upon power-up, program the MAX19711 to operate in the desired mode. Use the 3wire serial interface to program the device for shutdown, idle, standby, FD, Rx, Tx, aux-DAC controls, or aux-ADC conversion. A 16-bit data register sets the mode control as shown in Table 3. The 16-bit word is composed of four control bits (A3–A0) and 12 data bits (D11–D0). Data is shifted in MSB first (D11) and LSB last (A0) format. Table 4 shows the MAX19711 power-management modes. Table 5 shows the SPI-controlled Tx, Rx, and FD modes. The serial interface remains active in all modes. SPI Register Description Program the control bits, A3–A0, in the register as shown in Table 3 to select the operating mode. Modify A3–A0 bits to select from ENABLE-16, Aux-DAC1, Aux-DAC2, AuxDAC3, IOFFSET, QOFFSET, COMSEL, Aux-ADC, ENABLE-8, and WAKEUP-SEL modes. ENABLE-16 is the default operating mode (see Table 6). This mode allows for shutdown, idle, and standby states as well as switching between FAST, SLOW, Rx and Tx modes. Tables 4 and 5 show the required SPI settings for each mode. In ENABLE-16 mode, the aux-DACs have independent control bits E4, E5, and E6, bit E7 sets the Tx path fullscale outputs, and bit E9 enables the aux-ADC. Table 7 shows the auxiliary DAC enable codes. Table 8 shows the full-scale output selection. Table 9 shows the auxiliary ADC enable code. Bits E11 and E10 are reserved. Program bits E11 and E10 to logic-low. Bits E3 and E8 are not used. Modes Aux-DAC1, Aux-DAC2, and Aux-DAC3 select the aux-DAC channels named DAC1, DAC2, and DAC3 and hold the data inputs for each DAC. Bits _D11–_D0 are the data inputs for each aux-DAC and can be programmed through SPI. The MAX19711 also includes two 6-bit registers that can be programmed to adjust the offsets for the Tx path ID and QD channels independently (see Table 10). Use the COMSEL mode to select the output common-mode voltage with bits CM1 and CM0 (see Table 11). Use Aux-ADC mode to start the auxiliary ADC conversion (see the 10-Bit, 333ksps Auxiliary ADC section for details). Use ENABLE-8 mode for faster enable and switching between shutdown, idle, and standby states as well as switching between FAST, SLOW, Rx and Tx modes and the FD mode. The WAKEUP-SEL register selects the operating mode that the MAX19711 is to enter immediately after coming out of shutdown (Table 12). See the Wake-Up Function section for more information. ______________________________________________________________________________________ 19 MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End MAX19711 EXAMPLE: CDMA FILTER Tx DAC I-CH Tx RFIC INPUT REQUIREMENTS • DC COMMON-MODE BIAS = 1.0V (MIN), 1.2V (TYP) 0° 90° • BASEBAND INPUT = ±410mV DC-COUPLED CDMA FILTER Tx DAC Q-CH FULL SCALE = 1.265V COMMON-MODE LEVEL VCOMD = 1.06V SELECT CM1 = 1, CM0 = 0 VCOMD = 1.06V VFS = ±410mV ZERO SCALE = 0.855V 0V Figure 5. Tx DAC Common-Mode DC Level at IDN, IDP or QDN, QDP Differential Outputs CLK tDHQ tDSQ D0–D9 Q: N - 2 Q: N - 1 I: N - 1 tDSI Q: N I: N I: N + 1 tDHI ID N-2 N-1 N QD N-2 N-1 N Figure 6. Tx DAC System Timing Diagram 20 ______________________________________________________________________________________ 10-Bit, 11Msps, Full-Duplex Analog Front-End D11 REGISTER NAME D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (LSB) ENABLE-16 E11 = 0 Reserved E10 = 0 Reserved E9 — E7 E6 E5 E4 — E2 E1 E0 0 0 0 0 Aux-DAC1 1D11 1D10 1D9 1D8 1D7 1D6 1D5 1D4 1D3 1D2 1D1 1D0 0 0 0 1 Aux-DAC2 2D11 2D10 2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D1 2D0 0 0 1 0 Aux-DAC3 3D11 3D10 3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2 3D1 3D0 0 0 1 1 IOFFSET — — — — — — IO5 IO4 IO3 IO2 IO1 IO0 0 1 0 0 QOFFSET — — — — — — QO5 QO4 QO3 QO2 QO1 QO0 0 1 0 1 COMSEL — — — — — — — — — — CM1 CM0 0 1 1 0 Aux-ADC AD11 = 0 Reserved AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 1 1 1 ENABLE-8 — — — — — — — — — E2 E1 E0 1 0 0 0 WAKEUP-SEL — — — — — — — — — W2 W1 W0 1 0 0 1 AD0 — = Not used. Table 4. Power-Management Modes ADDRESS DATA BITS MODE A3 A2 A1 A0 E9* 1 0000 (16-Bit Mode) or 1000 (8-Bit Mode) X** X** E2 0 0 0 E1 0 0 1 E0 0 1 0 SHDN FUNCTION (POWER MANAGEMENT) DESCRIPTION COMMENT SHUTDOWN Rx ADC = OFF Tx DAC = OFF (TX DAC outputs at 0V) Aux-DAC = OFF Aux-ADC = OFF CLK = OFF REF = OFF Device is in complete shutdown. IDLE Rx ADC = OFF Tx DAC = OFF (TX DAC outputs at 0V) Aux-DAC = Last State CLK = ON REF = ON Fast turn-on time. Moderate idle power. STANDBY Rx ADC = OFF Tx DAC = OFF (TX DAC outputs at 0V) Aux-DAC = Last State CLK = OFF REF = ON Slow turn-on time. Low standby power. IDLE STBY X = Don’t care. *Bit E9 is not available in 8-bit mode. **In IDLE and STBY modes, the Aux-ADC can be turned on or off. ______________________________________________________________________________________ 21 MAX19711 Table 3. MAX19711 Mode Control MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End Table 5. MAX19711 Tx, Rx, and FD Control Using SPI Commands ADDRESS A3 A2 A1 DATA BITS A0 E2 0 1 0000 (16-Bit Mode) and 1000 (8-Bit Mode) 1 1 1 E1 1 0 0 1 1 E0 1 0 1 0 1 MODE FUNCTION (Tx-Rx SWITCHING SPEED) DESCRIPTION COMMENT SLOW Rx Mode: Rx ADC = ON Rx Bus = Enabled Tx DAC = OFF (Tx DAC outputs at 0V) Tx Bus = OFF (all inputs are pulled high) Slow transition to Tx mode from this mode. Low power. SLOW Tx Mode: Rx ADC = OFF Rx Bus = Tri-state Tx DAC = ON Tx Bus = ON Slow transition to Rx mode from this mode. Low power. FAST Rx Mode: Rx ADC = ON Rx Bus = Enabled Tx DAC = ON (Tx DAC outputs at midscale) Tx Bus = OFF (all inputs are pulled high) Fast transition to Tx mode from this mode. Moderate power. FAST Tx Mode: Rx ADC = ON Rx Bus = Tri-state Tx DAC = ON Tx Bus = ON Fast transition to Rx mode from this mode. Moderate power. FAST FD Mode: Rx ADC = ON Rx Bus = ON Tx DAC = ON Tx Bus = ON Default Mode Fast transition to any mode. Moderate power. SPI1-Rx SPI2-Tx SPI3-Rx SPI4-Tx FD Shutdown mode offers the most dramatic power savings by shutting down all the analog sections (including the reference) of the MAX19711. In shutdown mode, the Rx ADC digital outputs are in tri-state mode, the Tx DAC digital inputs are internally pulled to OV DD, and the Tx DAC outputs are at 0V. When the Rx ADC outputs transition from tri-state to active mode, the last converted word is placed on the digital output bus. The Tx DAC previously stored data is lost when coming out of shutdown mode. The wake-up time from shutdown mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal refer- 22 ence mode and buffered external reference mode, the wake-up time is typically 500µs to enter Rx mode, 26µs to enter Tx mode, and 500µs to enter FD mode. In all operating modes the Tx DAC inputs DA0–DA9 are internally pulled to OVDD. To reduce the supply current of the MAX19711 in shutdown mode do not pull DA0–DA9 low. This consideration is especially important in shutdown mode to achieve the lowest quiescent current. In idle mode, the reference and clock distribution circuits are powered, but all other functions are off. The ______________________________________________________________________________________ 10-Bit, 11Msps, Full-Duplex Analog Front-End MAX19711 Table 6. MAX19711 Default (Power-On) Register Settings REGISTER NAME D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 (MSB) 15 14 13 12 11 10 9 8 7 6 5 0 0 0 0 1 1 1 0 0 Aux-ADC = ON — VFS = ±410mV 0 1 1 0 1 0 ENABLE-16 Aux-DAC1 — Aux-DAC1 to Aux-DAC3 = ON 0 0 FD mode 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC1 output set to 1.1V Aux-DAC2 0 0 0 0 0 0 0 0 0 0 0 0 DAC2 output set to 0V Aux-DAC3 0 0 DAC3 output set to 0V 0 0 IOFFSET — — — — — — QOFFSET — — — — — — COMSEL — — — — — — — — — — 0 0 0 0 0 0 0 0 0 Aux-ADC 0 ENABLE-8 — — — — — — — — — WAKEUP-SEL — — — — — — — — — No offset on channel ID 0 0 0 0 No offset on channel QD VCOMD = 1.36V 0 0 1 1 Aux-ADC = ON, Conversion = IDLE, Aux-ADC REF = 2.048V, MUX = ADC1, Averaging = 1, Clock Divider = 1, DOUT = Disabled 1 FD mode 1 1 1 Wake-up state = FD mode Table 8. Tx Path Full-Scale Select (ENABLE-16 Mode) Table 7. Aux-DAC Enable Table (ENABLE-16 Mode) E6 E5 E4 Aux-DAC3 Aux-DAC2 Aux-DAC1 E7 Tx-PATH OUTPUT FULL SCALE 0 0 0 ON ON ON 0 (Default) ±410mV 0 0 1 ON ON OFF 1 ±500mV 0 1 0 ON OFF ON 0 1 1 ON OFF OFF 1 0 0 OFF ON ON 1 0 1 OFF ON OFF 1 1 0 OFF OFF ON E9 1 1 1 OFF OFF OFF 0 (Default) Aux-ADC is Powered ON 0 0 0 1 Aux-ADC is Powered OFF Default mode Table 9. Aux-ADC Enable Table (ENABLE-16 Mode) SELECTION ______________________________________________________________________________________ 23 MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End Table 10. Offset Control Bits for ID and QD Channels (IOFFSET or QOFFSET Mode) BITS IO5–IO0 WHEN IN IOFFSET MODE, BITS QO5–QO0 WHEN IN QOFFSET MODE IO5/QO5 IO4/QO4 IO3/QO3 IO2/QO2 IO1/QO1 IO0/QO0 OFFSET 1 LSB = (VFSP-P / 1023) 1 1 1 1 1 1 -31 LSB 1 1 1 1 1 0 -30 LSB 1 1 1 1 0 1 -29 LSB • • • • • • • • • • • • • • • • • • • • • 1 0 0 0 1 0 -2 LSB 1 0 0 0 0 1 -1 LSB 1 0 0 0 0 0 0mV 0 0 0 0 0 0 0mV (Default) 0 0 0 0 0 1 1 LSB 0 0 0 0 1 0 2 LSB • • • • • • • • • • • • • • • • • • • • • 0 1 1 1 0 1 29 LSB 0 1 1 1 1 0 30 LSB 0 1 1 1 1 1 31 LSB Note: For transmit full-scale select of ±410mV: 1 LSB = (820mVP-P / 1023) = 0.8016mV. For transmit full scale select of ±500mV: 1 LSB = (1VP-P / 1023) = 0.9775mV. Table 11. Common-Mode Select (COMSEL Mode) CM1 CM0 Tx PATH OUTPUT COMMON MODE (V) 0 0 1.36 (Default) 0 1 1.20 1 0 1.15 1 1 0.86 Rx ADC outputs AD0–AD9 are forced to tri-state. The Tx DAC DA0–DA9 inputs are internally pulled to OVDD, while the Tx DAC outputs are at 0V. The wake-up time is 6.8µs to enter Rx mode, 5µs to enter Tx mode, and 6.8µs to enter FD mode. When the Rx ADC outputs transition from tri-state to active, the last converted word is placed on the digital output bus. In standby mode, the reference is powered but all other device functions are off. The wake-up time from standby mode is 7.2µs to enter Rx mode, 21.8µs to enter Tx mode, and 21.8µs to enter FD mode. When the Rx ADC outputs transition from tri-state to active, the last converted word is placed on the digital output bus. 24 Table 12. WAKEUP-SEL Register W2 W1 W0 POWER MODE AFTER WAKE-UP (WAKE-UP STATE) 0 0 0 Invalid Value. This value is ignored when inadvertently written to the WAKEUP-SEL register. 0 0 1 IDLE 0 1 0 STBY 0 1 1 SPI1-SLOW Rx 1 0 0 SPI2-SLOW Tx 1 0 1 SPI3-FAST Rx 1 1 0 SPI4-FAST Tx 1 1 1 FD (Default) FAST and SLOW Rx and Tx Modes The MAX19711 features FAST and SLOW modes for switching between Rx and Tx operation. In FAST Tx mode, the Rx ADC core is powered on but the ADC digital outputs AD0–AD9 are tri-stated. The Tx DAC digital bus is active and the DAC core is fully operational. ______________________________________________________________________________________ 10-Bit, 11Msps, Full-Duplex Analog Front-End In FAST mode, the switching time from Tx to Rx, or Rx to Tx is minimized because the converters are on and do not have to recover from a power-down state. In FAST mode, the switching time from Rx to Tx is 1µs and Tx to Rx is 0.1µs. Power consumption is higher in FAST mode because both Tx and Rx cores are always on. In SLOW Tx mode, the Rx ADC core is powered off and the ADC digital outputs AD0–AD9 are tri-stated. The Tx DAC digital bus is active and the DAC core is fully operational. In SLOW Rx mode, the Tx DAC core is powered off. The Tx path outputs are set to 0. In SLOW Rx mode, the Tx DAC input bus is disconnected from the DAC core and DA0–DA9 are internally pulled to OVDD. The Rx ADC digital bus is active and the ADC core is fully operational. The switching times for SLOW modes are 5µs for Rx to Tx and 6.8µs for Tx to Rx. Power consumption in SLOW Tx mode is 34.5mW, and 24.3mW in SLOW Rx mode. Power consumption in FAST Tx mode is 42.3mW, and 41.4mW in FAST Rx mode. FD Mode The MAX19711 features an FD mode, which is ideal for applications supporting frequency-division duplex. In FD mode, both Rx ADC and Tx DAC, as well as their respective digital buses, are active and the device can receive and transmit simultaneously. Switching from FD mode to Rx (0.1µs) or Tx (1µs) modes is fast since the on-board converters are already powered. Consequently, power consumption in this mode is the maximum of all operating modes. In FD mode the MAX19711 consumes 42.75mW. Wake-Up Function The MAX19711 uses the SPI interface to control the operating modes of the device including the shutdown and wake-up functions. Once the device has been placed in shutdown through the appropriate SPI command, the first pulse on CS/WAKE performs a wake-up function. At the first rising edge of CS/WAKE, the MAX19711 is forced to a preset operating mode determined by the WAKEUP-SEL register. This mode is termed the wake-up state. If the WAKEUP-SEL register has not been programmed, the wake-up state for the MAX19711 is FD mode by default (Tables 6, 12). The WAKEUP-SEL register cannot be programmed with W2 = 0, W1 = 0, and W0 = 0. If this value is inadvertently written to the device, it is ignored and the register continues to store its previous value. Upon wake-up, the MAX19711 enters the power mode determined by the WAKEUP-SEL register, however, all other settings (Tx DAC offset, Tx DAC common-mode voltage, aux-DAC settings, aux-ADC state) are restored to their values prior to shutdown. The only SPI line that is monitored by the MAX19711 during shutdown is CS/WAKE. Any information transmitted to the MAX19711 concurrent with the CS/WAKE wake-up pulse is ignored. SPI Timing The serial digital interface is a standard 3-wire connection CS/WAKE, SCLK, DIN) compatible with SPI/QSPI™/ MICROWIRE/DSP interfaces. Set CS/WAKE low to enable the serial data loading at DIN or output at DOUT. Following a CS/WAKE high-to-low transition, data is shifted synchronously, most significant bit first, on the rising edge of the serial clock (SCLK). After 16 bits are loaded into the serial input register, data is transferred to the latch when CS/WAKE transitions high. CS/WAKE must transition high for a minimum of 80ns before the next write QSPI is a trademark of Motorola, Inc. tCSW CS/WAKE tCP tCSS tCS SCLK tCH tDS DIN tCL tDH MSB LSB Figure 7. Serial-Interface Timing Diagram ______________________________________________________________________________________ 25 MAX19711 In FAST Rx mode, the Tx path (DAC core and Tx filter) is powered on. The Tx path outputs are set to midscale. In this mode, the Tx DAC input bus is disconnected from the DAC core and DA0–DA9 are internally pulled to OVDD. The Rx ADC digital bus is active and the ADC core is fully operational. MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End sequence. SCLK can idle either high or low between transitions. Figure 7 shows the detailed timing diagram of the 3-wire serial interface. Mode-Recovery Timing Figure 8 shows the mode-recovery timing diagram. tWAKE is the wake-up time when exiting shutdown, idle, or standby mode and entering Rx, Tx, or FD mode. tENABLE is the recovery time when switching between either Rx or Tx mode. tWAKE or tENABLE is the time for the Rx ADC to settle within 1dB of specified SINAD performance and Tx DAC settling to 10 LSB error. tWAKE and tENABLE times are measured after either the 16-bit serial command is latched into the MAX19711 by a CS/WAKE transition high. In FAST mode, the recovery time is 0.1µs to switch to Rx mode and 1µs to switch to Tx mode. System Clock Input (CLK) Both the Rx ADC and Tx DAC share the CLK input. The CLK input accepts a CMOS-compatible signal level set by OVDD from 1.8V to VDD. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). Specifically, sampling occurs on the rising edge of the clock signal, requiring this edge to provide the lowest possible jitter. Any significant clock jitter limits the SNR performance of the on-chip Rx ADC as follows: ⎛ ⎞ 1 SNR = 20 × log ⎜ ⎟ 2 × π × f × t ⎝ IN AJ ⎠ where fIN represents the analog input frequency and tAJ is the time of the clock jitter. Clock jitter is especially critical for undersampling applications. Consider the clock input as an analog input and route away from any analog input or other digital signal lines. The MAX19711 clock input operates with an OV DD / 2 voltage threshold and accepts a 50% ±15% duty cycle. When the clock signal is stopped at CLK input (CLK = 0V or OVDD), all internal registers hold their last value and the MAX19711 saves the last power-management mode or Tx/Rx/FD command. All converter circuits (Rx ADC, Tx DAC, aux-ADC, and aux-DACs) hold their last value. When the clock signal is restarted at CLK, allow 7.2µs (clock wake-up time) for the internal clock circuitry to settle before updating the Tx DAC, reading a valid Rx ADC conversion result, or starting an aux-ADC conversion. This ensures the converters (Rx ADC, Tx DAC, aux-ADC) meet all dynamic performance specifications. The aux-DAC channels are not dependent on CLK, so they may be updated when CLK is idle. 12-Bit, Auxiliary Control DACs The MAX19711 includes three 12-bit aux-DACs (DAC1, DAC2, DAC3) with 1µs settling time for controlling variable-gain amplifier (VGA), automatic gain-control (AGC), and automatic frequency-control (AFC) functions. The aux-DAC output range is 0.2V to 2.57V as defined by VOH - VOL. During power-up, the VGA and AGC outputs (DAC2 and DAC3) are at zero. The AFC DAC (DAC1) is at 1.1V during power-up. The aux-DACs can be independently controlled through the SPI bus, except during SHDN mode where the aux-DACs are turned off completely and the output voltage is set to zero. In STBY and IDLE modes the aux-DACs maintain the last value. On wake-up from SHDN, the aux-DACs resume the last values. Loading on the aux-DAC outputs should be carefully observed to achieve specified settling time and stability. The capacitive load must be kept to a maximum of 5pF including package and trace capacitance. The CS/WAKE SCLK DIN 16-BIT SERIAL DATA INPUT AD0–AD9 ADC DIGITAL OUTPUT SINAD SETTLES TO WITHIN 1dB tWAKE,SD,ST_ TO Rx MODE OR tENABLE,RX ID/QD DAC ANALOG OUTPUT SETTLES TO 10 LSB ERROR tWAKE,SD,ST_ TO Tx MODE OR tENABLE,TX Figure 8. Mode-Recovery Timing Diagram 26 ______________________________________________________________________________________ 10-Bit, 11Msps, Full-Duplex Analog Front-End 10-Bit, 333ksps Auxiliary ADC The MAX19711 integrates a 333ksps, 10-bit aux-ADC with an input 4:1 multiplexer. In the aux-ADC mode register, setting bit AD0 begins a conversion with the auxiliary ADC. Bit AD0 automatically clears when the conversion is complete. Setting or clearing AD0 during a conversion has no effect (see Table 13). Bit AD1 determines the internal reference of the auxiliary ADC (see Table 14). Bits AD2 and AD3 determine the auxiliary ADC input source (see Table 15). Bits AD4, AD5, and AD6 select the number of averages taken when a single start-convert command is given. The conversion time increases as the number of averages increases (see Table 16). The conversion clock can be divided down from the system clock by properly setting bits AD7, AD8, and AD9 (see Table 17). The aux-ADC output data can be written out of DOUT by setting bit AD10 high (see Table 18). The aux-ADC features a 4:1 input multiplexer to allow measurements on four input sources. The input sources are selected by AD3 and AD2 (see Table 15). Two of the multiplexer inputs (ADC1 and ADC2) can be connected to external sources such as an RF power detector like the MAX2208 or temperature sensor like the MAX6613. The other two multiplexer inputs are internal Table 13. Auxiliary ADC Convert connections to VDD and OVDD that monitor the powersupply voltages. The internal VDD and OVDD connections are made through integrated dividers that yield VDD / 2 and OVDD / 2 measurement results. The auxADC voltage reference can be selected between an internal 2.048V bandgap reference or VDD (see Table 14). The VDD reference selection is provided to allow measurement of an external voltage source with a fullscale range extending beyond the 2.048V level. The input source voltage range cannot extend above VDD. The conversion requires 12 clock edges (1 for input sampling, 1 for each of the 10 bits, and 1 at the end for loading into the serial output register) to complete one conversion cycle (when no averaging is being done). Each conversion of an average (when averaging is set greater than 1) requires 12 clock edges. The conversion clock is generated from the system clock input (CLK). An SPI-programmable divider divides the system clock by the appropriate divisor (set with bits AD7, AD8, and AD9; see Table 17) and provides the conversion clock to the auxiliary ADC. The auxiliary ADC has a maximum conversion rate of 333ksps. The maximum conversion clock frequency is 4MHz (333ksps x 12 clocks). Choose the proper divider value to keep the conversion clock frequency under 4MHz, based upon Table 16. Auxiliary ADC Averaging AD6 AD5 AD4 Aux-ADC AVERAGING 0 0 0 1 Conversion (No Averaging) (Default) 0 0 1 Average of 2 Conversions 0 1 0 Average of 4 Conversions 0 1 1 Average of 8 Conversions 0 0 Average of 16 Conversions AD0 SELECTION 1 0 Aux-ADC Idle (Default) 1 0 1 Average of 32 Conversions Aux-ADC Start-Convert 1 1 X Average of 32 Conversions 1 X = Don’t care. Table 14. Auxiliary ADC Reference AD1 SELECTION 0 Internal 2.048V Reference (Default) 1 Internal VDD Reference Table 15. Auxiliary ADC Input Source Table 17. Auxiliary ADC Clock (CLK) Divider AD9 AD8 AD7 Aux-ADC CONVERSION CLOCK 0 0 0 CLK Divided by 1 (Default) 0 0 1 CLK Divided by 2 0 1 0 CLK Divided by 4 AD3 AD2 Aux-ADC INPUT SOURCE 0 1 1 CLK Divided by 8 0 0 ADC1 (Default) 1 0 0 CLK Divided by 16 0 1 ADC2 1 0 1 CLK Divided by 32 1 0 VDD / 2 1 1 0 CLK Divided by 64 1 1 OVDD / 2 1 1 1 CLK Divided by 128 ______________________________________________________________________________________ 27 MAX19711 resistive load must be greater than 200kΩ. If capacitive loading exceeds 5pF, then add a 10kΩ resistor in series with the output. Adding the series resistor helps drive larger load capacitance (< 15pF) at the expense of slower settling time. MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End Table 18. Auxiliary ADC Data Output Mode AD10 SELECTION 0 Aux-ADC Data is Not Available on DOUT (Default) 1 Aux-ADC Enters Data Output Mode Where Data is Available on DOUT the system CLK frequency supplied to the MAX19711 (see Table 17). The total conversion time (tCONV) of the auxiliary ADC can be calculated as t CONV = (12 x N AVG x N DIV) / f CLK; where N AVG is the number of averages (see Table 16), NDIV is the CLK divisor (see Table 17), and fCLK is the system CLK frequency. Reading DOUT from the Aux-ADC DOUT is normally in a high-impedance condition. Upon setting the auxiliary ADC start conversion bit (bit AD0), DOUT becomes active and goes high, indicating that the aux-ADC is busy. When the conversion cycle is complete (including averaging), the data is placed into an output register and DOUT goes low, indicating that the output data is ready to be driven onto DOUT. When bit AD10 is set (AD10 = 1), the aux-ADC enters a data output mode where data is available at DOUT on the next low assertion of CS/WAKE. The auxiliary ADC data is shifted out of DOUT (MSB first) with the data transitioning on the falling edge of the serial clock (SCLK). Since a DOUT read requires 16 bits, DOUT holds the value of the last conversion data bit for the last 6 bits (6 least significant bits) following the aux-ADC conversion data. DOUT enters a high-impedance state when CS/WAKE is deasserted high. When bit AD10 is cleared (AD10 = 0), the aux-ADC data is not available on DOUT (see Table 18). After the aux-ADC completes a conversion, the data result is loaded to an output register waiting to be shifted out. No further conversions are possible until data is shifted out. This means that if the first conversion command sets AD10 = 0, AD0 = 1, then it cannot be followed by conversion commands setting AD10 = 0, AD0 = 1 or AD10 = 1, AD0 = 1. If this sequence of commands is inadvertently used then DOUT is disabled. To resume normal operation set AD0 = 0. The fastest method to perform sequential conversions with the aux-ADC is by sending consecutive commands setting AD10 = 1, AD0 = 1. With this sequence the CS/WAKE falling edge shifts data from the previous conversion on to DOUT and the rising edge of CS/WAKE loads the next conversion command at DIN. Allow enough time for each conversion to complete before sending the next conversion command. See Figure 9 for single and continuous conversion examples. DIN can be written independent of DOUT state. A 16bit instruction at DIN updates the device configuration. To prevent modifying internal registers while reading data from DOUT, hold DIN at a high state (only applies if sequential aux-ADC conversions are not executed). This effectively writes all ones into address 1111. Since address 1111 does not exist, no internal registers are affected. Reference Configurations The MAX19711 features an internal precision 1.024Vbandgap reference that is stable over the entire powersupply and temperature ranges. The REFIN input provides two modes of reference operation. The voltage at REFIN (VREFIN) sets the reference operation mode (Table 19). In internal reference mode, connect REFIN to V DD. VREF is an internally generated 0.512V ±4% reference level. COM, REFP, and REFN are low-impedance outputs with VCOM = VDD / 2, VREFP = VDD / 2 + VREF / 2, and VREFN = VDD / 2 - VREF / 2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. In buffered external reference mode, apply 1.024V ±10% at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with V COM = V DD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 VREFIN / 4. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. In this mode, the Tx path full-scale output is proportional to the external reference. For example, if the VREFIN is increased by 10% (max), the Tx path fullscale output is also increased by 10% or ±451mV. Table 19. Reference Modes VREFIN 28 REFERENCE MODE > 0.8V x VDD Internal Reference Mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. 1.024V ±10% Buffered External Reference Mode. An external 1.024V ±10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN / 2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. ______________________________________________________________________________________ 10-Bit, 11Msps, Full-Duplex Analog Front-End MAX19711 1. SINGLE AUX-ADC CONVERSION WITH CONVERSION DATA READOUT AT A LATER TIME tCSD CS/WAKE SCLK 1 DIN 0 tCD 16 0 1 0 1 1 1 16 1 1 0 16 1 0 0 1 1 tCHZ 1 10 1 D9 AUX-ADC REGISTER ADDRESS DOUT TRANSITIONS FROM HIGH IMPEDANCE TO LOGICHIGH INDICATING START OF CONVERSION D0 D0 HELD CONVERSION RESULT DATA BIT D0 IS HELD FOR THE SIX LEAST SIGNIFICANT BITS FIRST FALLING EDGE OF CS/WAKE AFTER DOUT IS ENABLED STARTS SHIFTING THE AUX-ADC CONVERSION DATA ON THE FALLING EDGE OF SCLK AD10 = 1, AD0 = 0, AUX-ADC IDLE (NO CONVERSION), DOUT ENABLED AND CONVERSION DATA IS SHIFTED OUT ON NEXT CS/WAKE FALLING EDGE DOUT TRANSITIONS LOW INDICATING END OF CONVERSION, DATA IS AVAILABLE AND CAN BE SHIFTED OUT IF DOUT IS ENABLED, AD0 CLEARED D1 AUX-ADC REGISTER ADDRESS IF AUX-ADC CONVERSION DOES NOT NEED TO BE READ IMMEDIATELY, THE SPI INTERFACE IS FREE AND CAN BE USED FOR OTHER FUNCTIONS, SUCH AS HOUSEKEEPING AUX-DAC ADJUSTMENT, ETC. 16 DIN SET HIGH DURING SINGLE READ DOUT AD10 = 0, AD0 = 1, PERFORM CONVERSION, DOUT DISABLED 11 DOUT TRANSITIONS TO HIGH-IMPEDANCE 10 BIT AUX-ADC CONVERSION RESULT IS SHIFTED OUT ON DOUT ON THE FALLING EDGE OF SCLK MSB FIRST 2. CONTINUOUS AUX-ADC CONVERSIONS tCONV CS/WAKE tDCS SCLK 1 DIN 0 0 1 0 1 1 16 1 1 0 10 D9 DOUT 11 1 D1 12 13 14 15 16 1 1 0 1 1 1 0 D0 D0 HELD 10 11 1 D9 D1 12 13 14 15 16 1 0 1 1 1 D0 AD10 = 1, AD0 = 1, PERFORM CONVERSION, DOUT ENABLED AD10 = 1, AD0 = 1, PERFORM CONVERSION, DOUT ENABLED AD10 = 1, AD0 = 1, PERFORM CONVERSION, DOUT ENABLED AUX-ADC REGISTER ADDRESS FIRST 10 BIT AUX-ADC CONVERSION RESULT IS SHIFTED OUT ON DOUT ON THE FALLING EDGE OF SCLK MSB FIRST SECOND 10 BIT AUX-ADC CONVERSION RESULT IS SHIFTED OUT ON DOUT ON THE FALLING EDGE OF SCLK MSB FIRST DOUT TRANSITIONS HIGH INDICATING START OF SECOND CONVERSION DOUT TRANSITIONS HIGH INDICATING START OF THIRD CONVERSION DOUT TRANSITIONS LOW INDICATING END OF SECOND CONVERSION, DATA IS AVAILABLE AND CAN BE SHIFTED OUT IF DOUT IS ENABLED, AD0 CLEARED DOUT TRANSITIONS LOW INDICATING END OF THIRD CONVERSION, DATA IS AVAILABLE AND CAN BE SHIFTED OUT IF DOUT IS ENABLED, AD0 CLEARED DOUT TRANSITIONS FROM HIGH IMPEDANCE TO LOGICHIGH INDICATING START OF FIRST CONVERSION DOUT TRANSITIONS LOW INDICATING END OF FIRST CONVERSION, DATA IS AVAILABLE AND CAN BE SHIFTED OUT IF DOUT IS ENABLED, AD0 CLEARED D0 HELD Figure 9. Aux-ADC Conversions Timing Applications Information Using Balun Transformer AC-Coupling An RF transformer (Figure 10) provides an excellent solution to convert a single-ended signal source to a fully differential signal for optimum ADC performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. A 1:1 transformer can be used, or a step-up transformer can be selected to reduce the drive requirements. In general, the MAX19711 provides better SFDR and THD with fully differential input signals than single-ended signals, especially for high input frequencies. In differential ______________________________________________________________________________________ 29 MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End 25Ω IAP 0.1μF IDP VOUT 22pF VIN COM 0.33μF MAX19711 0.1μF IDN QDP VOUT IAN 25Ω 22pF MAX19711 25Ω QAP 0.1μF QDN 22pF VIN 0.33μF Figure 11. Balun Transformer-Coupled Differential-to-SingleEnded Output Drive for Tx DAC 0.1μF REFP QAN 25Ω 22pF 1kΩ VIN 0.1μF RISO 50Ω IAP 100Ω Figure 10. Balun Transformer-Coupled Single-Ended-toDifferential Input Drive for Rx ADC CIN 22pF 1kΩ COM REFN mode, even-order harmonics are lower as both inputs (IAP, IAN, QAP, QAN) are balanced, and each of the Rx ADC inputs only requires half the signal swing compared to single-ended mode. Figure 11 shows an RF transformer converting the MAX19711 Tx DAC differential analog outputs to single-ended. 0.1μF RISO 50Ω IAN 100Ω CIN 22pF REFP MAX19711 Using Op-Amp Coupling Drive the MAX19711 Rx ADC with op amps when a balun transformer is not available. Figures 12 and 13 show the Rx ADC being driven by op amps for AC-coupled single-ended and DC-coupled differential applications. Amplifiers such as the MAX4454 and MAX4354 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. The op-amp circuit shown in Figure 13 can also be used to interface with the Tx DAC differential analog outputs to provide gain or buffering. The Tx DAC differential analog outputs cannot be used in single-ended mode because of the internally generated common-mode level. Also, the Tx DAC analog outputs are designed to drive a differential input stage with input impedance ≥ 30 VIN 0.1μF 1kΩ RISO 50Ω QAP 100Ω 1kΩ REFN CIN 22pF 0.1μF RISO 50Ω 100Ω QAN CIN 22pF Figure 12. Single-Ended Drive for Rx ADC ______________________________________________________________________________________ 10-Bit, 11Msps, Full-Duplex Analog Front-End MAX19711 R4 600Ω R5 600Ω RISO 22Ω R1 600Ω IAN CIN 5pF MAX19711 R2 600Ω R3 600Ω R6 600Ω R7 600Ω R8 600Ω R9 600Ω COM RISO 22Ω CIN 5pF R10 600Ω IAP R11 600Ω Figure 13. Rx ADC DC-Coupled Differential Drive 70kΩ. If single-ended outputs are desired, use an amplifier to provide differential-to-single-ended conversion and select an amplifier with proper input commonmode voltage range. CDMA Application Figure 14 illustrates a typical CDMA application circuit. The MAX19711 is designed to interface directly with the MAX2504 and MAX2584 radio front-ends to provide a complete “RF-to-Bits” front-end solution. The MAX19711 provides several features that allow direct interface to the MAX2584 and MAX2504: • Integrated Tx filters reduce component count, lower cost, and meet CDMA spectral mask requirements • Programmable DC common-mode Tx output levels eliminate discrete DC-level-shifting components while preserving Tx DAC full dynamic range • Optimized Tx full-scale output level eliminates discrete amplifiers for ID–QD gain control • Tx-ID–QD offset correction eliminates discrete trim DACs for offset trim to improve sideband/carrier suppression • 1µs settling time aux-DACs for VGA and AGC control allow fast, accurate Tx power and Rx gain control Grounding, Bypassing, and Board Layout The MAX19711 requires high-speed board layout design techniques. Refer to the MAX19711 EV kit data sheet for a board layout reference. Place all bypass capacitors as close to the device as possible, preferably on the same side of the board as the device, using surface-mount devices for minimum inductance. Bypass VDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF capacitor. Bypass OVDD to OGND with a 0.1µF ceramic capacitor in parallel with a 2.2µF capacitor. Bypass REFP, REFN, and COM each to GND with a 0.33µF ceramic capacitor. Bypass REFIN to GND with a 0.1µF capacitor. Multilayer boards with separated ground and power planes yield the highest level of signal integrity. Use a split ground plane arranged to match the physical location of the analog ground (GND) and the digital outputdriver ground (OGND) on the device package. Connect the MAX19711 exposed backside paddle to the GND plane. Join the two ground planes at a single point so the noisy digital ground currents do not interfere with the analog ground plane. The ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead, or a direct short. ______________________________________________________________________________________ 31 MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End VDD = 2.7V TO 3.3V OVDD = 1.8V TO VDD DATA MUX AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 DATA MUX DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 IAP 10-BIT ADC IAN MAX2584 ZIF RECEIVER QAP 10-BIT ADC AGC QAN IDP CDMA FILTER MAX2504 DIRECT MODULATOR PA DETECT VGA 10-BIT DAC IDN QDP QDN 10-BIT DAC CDMA FILTER SYSTEM CLOCK PROGRAMMABLE OFFSET/GAIN/CM DAC1 12-BIT AUX-DAC TCXO DAC2 SERIAL INTERFACE AND SYSTEM CONTROL 12-BIT AUX-DAC DAC3 DIGITAL BASEBAND ASIC CLK CS/WAKE SCLK DIN DOUT 1.024V REFERENCE BUFFER 12-BIT AUX-DAC REFIN REFP COM REFN ADC1 10-BIT AUX-ADC TEMPERATURE MEASURE ADC2 MAX19711 VDD / 2 OVDD / 2 GND OGND Figure 14. Typical Application Circuit for CDMA Radio Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital system’s ground plane (e.g., downstream output buffer or DSP ground plane). 32 Route high-speed digital signal traces away from sensitive analog traces. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90° turns. ______________________________________________________________________________________ 10-Bit, 11Msps, Full-Duplex Analog Front-End MAX19711 Dynamic Parameter Definitions 7 ADC and DAC Static Parameter Definitions 6 ADC Offset Error Ideally, the midscale transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point. DAC Offset Error Offset error (Figure 15a) is the difference between the ideal and actual offset point. The offset point is the output value when the digital input is midscale. This error affects all codes by the same amount and usually can be compensated by trimming. ADC Gain Error Ideally, the ADC full-scale transition occurs at 1.5 LSB below full scale. The gain error is the amount of deviation between the measured transition point and the ideal transition point with the offset error removed. 5 4 AT STEP 011 (0.5 LSB) 3 2 AT STEP 001 (0.25 LSB) 1 0 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE Figure 15a. Integral Nonlinearity 6 ANALOG OUTPUT VALUE Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes (ADC) and a monotonic transfer function (ADC and DAC) (DAC Figure 15b). ANALOG OUTPUT VALUE Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the device are measured using the best-straight-line fit (DAC Figure 15a). 1 LSB 5 DIFFERENTIAL LINEARITY ERROR (-0.25 LSB) 4 3 1 LSB 2 DIFFERENTIAL LINEARITY ERROR (+0.25 LSB) 1 0 000 001 010 011 100 101 DIGITAL INPUT CODE Figure 15b. Differential Nonlinearity ADC Dynamic Parameter Definitions Aperture Jitter Figure 16 shows the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 16). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error) and results directly from the ADC’s resolution (N bits): SNR(max) = 6.02 x N + 1.76 (in dB) CLK ANALOG INPUT tAD tAJ SAMPLED DATA (T/H) T/H TRACK HOLD TRACK Figure 16. T/H Aperture Timing ______________________________________________________________________________________ 33 MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise and Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: ENOB = (SINAD - 1.76) / 6.02 Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: ⎡ (V22 + V32 + V42 + V52 + V62 THD = 20 x log ⎢ V1 ⎢⎣ )⎤ ⎥ ⎥⎦ where V1 is the fundamental amplitude and V2–V6 are the amplitudes of the 2nd- through 6th-order harmonics. Third Harmonic Distortion (HD3) HD3 is defined as the ratio of the RMS value of the third harmonic component to the fundamental input signal. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) IMD is the total power of the intermodulation products relative to the total input power when two tones, fIN1 and fIN2, are present at the inputs. The intermodulation products are (fIN1 ± fIN2), (2 ✕ fIN1), (2 ✕ fIN2), (2 ✕ fIN1 ± fIN2), (2 ✕ fIN2 ± fIN1). The individual input tone levels are at -7dBFS. 34 3rd-Order Intermodulation (IM3) IM3 is the power of the worst 3rd-order intermodulation product relative to the input power of either input tone when two tones, fIN1 and fIN2, are present at the inputs. The 3rd-order intermodulation products are (2 x fIN1 ± fIN2), fIN2 (2 ✕ fIN2 ± fIN1). The individual input tone levels are at -7dBFS. Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ±5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in such a way that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. Note that the T/H performance is usually the limiting factor for the small-signal input bandwidth. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as the fullpower bandwidth frequency. DAC Dynamic Parameter Definitions Total Harmonic Distortion THD is the ratio of the RMS sum of the output harmonics up to the Nyquist frequency divided by the fundamental: ⎡ (V22 + V32 + ...+ Vn2 ) THD = 20 x log ⎢ V1 ⎢ ⎣ ⎤ ⎥ ⎥ ⎦ where V1 is the fundamental amplitude and V2 through Vn are the amplitudes of the 2nd through nth harmonic up to the Nyquist frequency. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component up to the Nyquist frequency excluding DC. ______________________________________________________________________________________ 10-Bit, 11Msps, Full-Duplex Analog Front-End PART SAMPLING RATE (Msps) MAX19710 7.5 INTEGRATED CDMA Tx FILTERS No MAX19711 11 Yes MAX19712 22 No MAX19713 45 No Functional Diagram VDD = 2.7V TO 3.3V IAP QAP QDP QDN DATA MUX DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 SYSTEM CLOCK CLK 10-BIT ADC QAN IDN DATA MUX AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 10-BIT ADC IAN IDP OVDD = 1.8V TO VDD CDMA FILTER 10-BIT DAC 10-BIT DAC CDMA FILTER PROGRAMMABLE OFFSET/GAIN/CM DAC1 12-BIT AUX-DAC DAC2 12-BIT AUX-DAC SERIAL INTERFACE AND SYSTEM CONTROL DOUT 1.024V REFERENCE BUFFER 12-BIT AUX-DAC DAC3 ADC1 ADC2 CS/WAKE SCLK DIN REFIN REFP REFN COM 10-BIT AUX-ADC MAX19711 VDD / 2 OVDD / 2 GND OGND ______________________________________________________________________________________ 35 MAX19711 Selector Guide Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) E DETAIL A 32, 44, 48L QFN.EPS MAX19711 10-Bit, 11Msps, Full-Duplex Analog Front-End (NE-1) X e E/2 k e D/2 CL (ND-1) X e D D2 D2/2 b L E2/2 e E2 CL L L1 CL k DETAIL B CL L L e A1 A2 e A PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm 21-0144 E 1 2 PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm 21-0144 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products Springer Printed USA is a registered trademark of Maxim Integrated Products, Inc.