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Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI LSIs 2002.04.18 Ver. 6.0 M5M5V416CWG -55HI, -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM DESCRIPTION FEATURES The M5M5V416CWG is a f amily of low v oltage 4-Mbit static RAMs organized as 262144-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.18µm CMOS technology . The M5M5V416C is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5V416CWG is packaged in a CSP (chip scale package), with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball) and ball pitch of 0.75mm. It giv es the best solution f or a compaction of m ounting area as well as f lexibility of wiring pattern of printed circuit boards. Single 2.7~3.6V power supply Small stand-by current: 0.2µA (3.00V, ty p.) No clocks, No ref resh Data retention supply v oltage =2.0V All inputs and outputs are TTL compatible. Easy memory expansion by S1#, S2, BC1# and BC2# Common Data I/O Three-state outputs: OR-tie capability OE# prev ents data contention in the I/O bus Process technology : 0.18µm CMOS Package: 48ball 7.0mm x 8.5mm CSP Operating temperature I-version Activ e current Ratings (max. @3.6V) Icc1 25°C 40°C Voltage 25°C 40°C 70°C 85°C (3.0V, ty p.) Stand-by c urrent Version, Power Supply Part name Access time max. 55ns M5M5V416CWG -55HI 2.7 ~ 3.6V -40 ~ +85°C 0.2 70ns M5M5V416CWG -70HI ( µA ) * Typical(3.0V) 0.4 3.0V 1.0 2.0 10 20 3.3V 1.5 2.5 10 20 3.6V 2.5 4.0 10 20 30mA (10MHz) 5mA (1MHz) * Typical parameter indicates the value for the center of distribution, and not 100% tested. PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 A BC1# OE# A0 A1 A2 S2 B DQ16 BC2# A3 A4 S1# DQ1 C DQ14 DQ15 A5 A6 DQ2 DQ3 D GND DQ13 A17 A7 DQ4 VCC E VCC DQ12 NC or GND A16 DQ5 GND F DQ11 DQ10 A14 A15 DQ7 DQ6 G DQ9 N.C. A12 A13 W# DQ8 H NC A8 A9 A10 A11 N.C. Pin Function A0 ~ A17 Address input DQ1 ~ DQ16 Data input / output Chip select input 1 S1# S2 Chip select input 2 W# Write control input OE# Output enable input BC1# Lower By te (DQ1 ~ 8) BC2# Upper By te (DQ9 ~ 16) Vcc Power supply GND Ground supply Outline: 48FJA NC: No Connection *Don't connect E3 ball to voltage level more than 0V. 1 MITSUBISHI LSIs 2002.04.18 Ver. 6.0 M5M5V416CWG -55HI, -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION The M5M5V416CWG is organized as 262144-words by 16-bit. These dev ices operate on a single +2.7~3.6V power supply , and are directly TTL compatible to both input and output. Its f ully s t atic circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1# , BC2# , S1#, S2 , W# and OE#. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W# ov erlaps with the low lev el BC1# and/or BC2# and the low lev el S1# and the high lev el S2. The address(A0~A17) must be set up bef ore the write cy c le and must be stable during the entire cy c le. A read operation is executed by s etting W# at a high lev el and OE# at a low lev el while BC1# and/or BC2# and S1# and S2 are in an activ e state(S1#=L,S2=H). When setting BC1# at the high lev el and other pins are in an activ e stage , upper-by t e are in a selectable mode in which both reading and writing are enabled, and lower-by t e are in a non-selectable mode. And when setting BC2# at a high lev el and other pins are in an activ e stage, lowerby t e are in a selectable mode and upper-by te are in a non-selectable mode. BLOCK DIAGRAM When setting BC1# and BC2# at a high lev el or S1# at a high lev el or S2 at a low lev el, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and memory expansion by BC1#, BC2# and S1#, S2. The power supply c urrent is reduced as low as 0.2µA(25°C, ty pical), and the memory data can be held at +2V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode. FUNCTION TABLE S1# S2 BC1# BC2# W# OE# DQ9~16 Icc Standby High-Z High-Z X L X X X X H H X X X X Non selection High-Z High-Z Standby X X H H X X Non selection High-Z High-Z Standby High-Z Activ e H L X Din L H L Write Dout High-Z Activ e L H L H H L Read L H L H H H High-Z High-Z Activ e L H H L L X High-Z Din Activ e Write L H H L H L High-Z Dout Activ e Read High-Z High-Z Activ e L H H L H H L H L L L X Din Din Activ e Write L H L L H L Dout Dout Activ e Read L H H High-Z High-Z Activ e L H L (note) "H" and "L" in this table mean VIH and VIL, respectiv ely . "X" in this table should be "H" or "L". Mode DQ1~8 Non selection A0 DQ 1 A1 MEMORY ARRAY DQ 8 262144 WORDS x 16 BITS A 16 - DQ 9 A 17 S1# CLOCK GENERATOR DQ 16 S2 BC1# BC2# Vcc W# GND OE# 2 MITSUBISHI LSIs 2002.04.18 Ver. 6.0 M5M5V416CWG -55HI, -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Parameter T stg Units Ratings -0.5 * ~ +4.6 -0.3 * ~ Vcc + 0.3 0 ~ Vcc 700 With respect to GND Supply v oltage Input v oltage With respect to GND Output v oltage With respect to GND Power dissipation Operating temperature Ta Conditions Ta=25°C I-v ersion Storage temperature V mW - 40 ~ +85 °C - 65 ~ +150 °C * -3.0V in case of AC (Pulse width < 30ns) DC ELECTRICAL CHARACTERISTICS Symbol V IH V IL V OH V OL II IO Parameter ( Vcc=2.7 ~ 3.6V, unless noted. ) Limits Conditions Min 2.2 -0.2 * 2.4 High-lev el input v oltage Low-lev el input v oltage High-level output voltage Low-lev el output v oltage Input leakage current Output leakage current I OH= -0.5mA I OL=2mA V I =0 ~ Vcc BC1# and BC2# < 0.2V, S1# < 0.2V, S2 > Vcc-0.2V other inputs < 0.2V or > Vcc-0.2V Output - open (duty 100%) f = 10MHz Activ e supply c urrent Icc 2 ( AC,TTL lev el ) BC1# and BC2# =V IL , S1# =V IL ,S2=V IH other pins =V IH or V IL Output - open (duty 100%) ( MOS lev el ) S2 > Vcc - 0.2V, other inputs = 0 ~ Vcc (2) S2 < 0.2V, other inputs = 0 ~ Vcc (3) BC1# and BC2# > Vcc - 0.2V ( TTL lev el ) 0.4 ±1 ±1 50 10 50 f = 10MHz 30 5 30 f = 1MHz - 5 ~ +25°C 3.0V 3.3V 3.6V - 0.2 10 1.0 1.5 2.5 ~ +40°C 3.0V 3.3V 3.6V - 0.4 2.0 2.5 4.0 ~ +70°C 3.0V~3.6V - - ~ +85°C 3.0V~3.6V S1# < 0.2V, S2 > Vcc - 0.2V other inputs = 0 ~ Vcc Icc 4 Stand by s upply current 0.4 - f = 1MHz (1) S1# > Vcc - 0.2V, Icc 3 Stand by s upply current Max BC1# and BC2# =VIH or S1# =VIH or S2=VIL Other inputs= 0 ~ Vcc Note 1: Direction for current flowing into IC is indicated as positive (no mark) Units Vcc+0.2V BC1# and BC2# =VIH or S1# =VIH or S2=VIL or OE# =VIH, VI/O=0 ~ Vcc Icc 1 Activ e supply c urrent ( AC,MOS lev el ) Ty p V µA mA µA 10 - - 20 - - 0.5 mA * -1.0V in case of AC (Pulse width < 30ns) Note 2: Typical parameter indicates the value for the center of distribution at 3.00V, and is not 100% tested. CAPACITANCE Symbol CI CO Parameter (Vcc=2.7 ~ 3.6V, unless noted. ) Conditions Min Input capacitance V I=GND, VI=25mVrms, f =1MHz Output capacitance V O= GND,VO=25mVrms, f =1MHz Limits Ty p Max 10 10 Units pF 3 MITSUBISHI LSIs 2002.04.18 Ver. 6.0 M5M5V416CWG -55HI, -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS (Vcc=2.7 ~ 3.6V, unless noted. ) 1TTL 2.7~3.6V Input pulse V IH=2.4V, V IL=0.2V Input rise time and f all time 5ns Supply v oltage Ref erence lev el V OH=V OL=1.50V DQ CL Transition is measured ±200mV from steady state voltage.(for ten,tdis) Including scope and jig capacitance Fig.1,CL=30pF CL=5pF (for ten,tdis) Output loads Fig.1 Output load (2) READ CYCLE Limits t CR t a(A) t a(S1) t a(S2) t a(BC1) t a(BC2) t a(OE) t dis (S1) t dis (S2) t dis (BC1) t dis (BC2) t dis (OE) t en(S1) t en(S2) t en(BC1) t en(BC2) t en(OE) t V(A) 55HI Parameter Symbol Read cy cle time Address access time Chip select 1 access time Chip select 2 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time af t er S1# high Output disable time af t er S2 low Output disable time af t er BC1# high Output disable time af t er BC2# high Output disable time af t er OE# high Output enable time af ter S1# low Output enable time af ter S2 high Output enable time af ter BC1# low Output enable time af ter BC2# low Output enable time af ter OE# low Data v alid time after address Limits Min 55 70HI Max Min 70 Units Max 70 70 70 70 70 35 25 25 25 25 25 55 55 55 55 55 30 20 20 20 20 20 10 10 5 5 5 10 10 10 5 5 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Symbol t CW t w(W) t su(A) t su(A-WH) t su(BC1) t su(BC2) t su(S1) t su(S2) t su(D) t h(D) t rec (W) t dis (W) t dis (OE) t en(W) t en(OE) Parameter Write cy cle time Write pulse width Address setup time Address setup time with respect to W# By te control 1 setup time By te control 2 setup time Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recov ery time Output disable time f rom W# low Output disable time f rom OE# high Output enable time f rom W# high Output enable time f rom OE# low Limits Limits 55HI 70HI Min 55 45 0 50 50 50 50 50 30 0 0 Max Min 70 55 0 60 60 60 60 60 35 0 0 20 20 Units Max 25 25 5 5 5 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 MITSUBISHI LSIs 2002.04.18 Ver. 6.0 M5M5V416CWG -55HI, -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle t CR A 0~17 t v (A) t a(A) t a(BC1) or t a(BC2) BC1#,BC2# (Note3) t dis (BC1) or t dis (BC1) (Note3) t a(S1) S1# (Note3) t dis (S1) (Note3) t dis (S2) (Note3) t a(S2) S2 (Note3) t a (OE) OE# (Note3) t en (OE) W# = "H" lev el DQ 1~16 Write cycle (W# control mode ) t dis (OE) t en (BC1) t en (BC2) t en (S1) t en (S2) (Note3) VALID DATA t CW A 0~17 t su (BC1) or t su (BC2) BC1#,BC2# (Note3) (Note3) t su (S1) S1# (Note3) (Note3) S2 t su (S2) (Note3) (Note3) OE# t su (A) t su (A-WH) t w (W) t rec (W) t dis (W) W# t en (OE) t en (W) t dis (OE) DQ 1~16 DATA IN STABLE t su (D) t h (D) 5 MITSUBISHI LSIs 2002.04.18 Ver. 6.0 M5M5V416CWG -55HI, -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (BC# control mode) t CW A 0~17 t su (A) t su (BC1) or t su (BC2) t rec (W) BC1#,BC2# S1# (Note3) (Note3) S2 (Note3) W# (Note3) (Note5) (Note4) (Note3) (Note3) t su (D) DQ 1~16 t h (D) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1# low, S2 high ov erlaps BC1# and/or BC2# low and W# low. Note 5: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the f alling edge of S1# or rising edge of S2, the outputs are maintained in the high impedance state. Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode. 6 MITSUBISHI LSIs 2002.04.18 Ver. 6.0 M5M5V416CWG -55HI, -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (S1# control mode) t CW A 0~17 BC1#,BC2# (Note3) t su (A) t su (S1) t rec (W) (Note3) S1# S2 (Note3) (Note3) (Note5) W# (Note4) (Note3) t su (D) t h (D) (Note3) DATA IN STABLE DQ 1~16 Write cycle (S2 control mode) t CW A 0~17 BC1#,BC2# (Note3) t su (A) t su (S2) t rec (W) (Note3) S1# S2 (Note3) (Note3) (Note5) W# (Note4) (Note3) DQ 1~16 t su (D) t h (D) (Note3) DATA IN STABLE 7 MITSUBISHI LSIs 2002.04.18 Ver. 6.0 M5M5V416CWG -55HI, -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Vcc Parameter Test conditions Min Byte control input BC1# & BC2# 2.2V < Vcc(PD) V I (S2) Chip select input S1# 2.2 Power down supply c urrent other inputs = 0 ~ Vcc (2) S2 < 0.2V, other inputs = 0 ~ Vcc (3) BC1# and BC2# > Vcc - 0.2V S1# < 0.2V, S2 > Vcc - 0.2V other inputs = 0 ~ Vcc t su (PD) t rec (PD) - 0.05 ~ +40°C - 0.1 1.5 ~ +70°C - - 7.5 ~ +85°C - - 15 V µA Note 7: Typical parameter of Icc(PD) indicates the value for the center of distribution at 2.0V, and not 100% tested. (2) TIMING REQUIREMENTS Symbol ~ +25°C 0.2 0.8 Chip select input S2 (1) S1# > Vcc - 0.2V, (PD) V Vcc(PD) Vcc=2.0V Icc V Vcc(PD) 2.0V < Vcc(PD) < 2.2V Units V 2.2 2.0V < Vcc(PD) < 2.2V 2.2V < Vcc(PD) V I (S1) Max 2.0 (PD) Power down supply voltage V I (BC) Limits Ty p Limits Parameter Test conditions Min Ty p Max 0 5 Power down set up time Power down recov ery t ime Units ns ms (3) TIMING DIAGRAM BC# control mode On the BC# control mode, the lev el of S1# and S2 must be f ixed at S1# , S2 > Vcc-0.2V or S2 < 0.2V. Vcc t su (PD) 2.7V 2.7V t rec (PD) 2.2V 2.2V BC1# BC2# BC1# , BC2# > Vcc-0.2V S1# control mode On the S1# mode, the lev el of S2 must be f ixed at S2 > Vcc-0.2V or S2 < 0.2V. Vcc t su (PD) 2.7V 2.7V t rec (PD) 2.2V 2.2V S1# > Vcc-0.2V S1# S2 control mode Vcc 2.7V S2 t su (PD) 2.7V t rec (PD) 0.2V 0.2V S2 < 0.2V 8 Keep safety first in your circuit designs! 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