19-5241; Rev 0; 4/10 TION KIT EVALUA BLE IL AVA A Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO The MAX17117 includes a high-performance step-up regulator, a 350mA low-dropout (LDO) linear regulator, a high-speed operational amplifier, and a high-voltage level-shifting scan driver with gate-shading control. The device is optimized for thin-film transistor (TFT) liquidcrystal display (LCD) applications. The step-up DC-DC converter provides the regulated supply voltage for panel source-driver ICs. The high 1.2MHz switching frequency allows the use of ultra-small inductors and ceramic capacitors. The current-mode control architecture provides a fast-transient response to pulsed loads typical of source driver loads. The step-up regulator features an adjustable soft-start and an adjustable cycle-by-cycle current limit. S High-Performance Operational Amplifier 200mA Output Short-Circuit Current 40V/µs Slew Rate 16MHz, -3dB Bandwidth Low-Dropout Linear Regulator High-Accuracy Output Voltage (1.0%) S High-Voltage Drivers with Scan Logic +35V to -15V Outputs 40V Maximum Voltage Swing Gate-Shading Control S Thermal-Overload Protection S 32-Pin, 5mm x 5mm, Thin QFN Package Simplified Operating Circuit The high-current operational amplifier is designed to drive the LCD backplane (VCOM). The amplifier features high output current (Q200mA typ), fast slew rate (40V/Fs typ), wide bandwidth (16MHz typ), and rail-to-rail inputs and outputs. The MAX17117 is available in a 32-pin, 5mm x 5mm, thin QFN package with a maximum thickness of 0.8mm for thin LCD panels. MAX17117ETJ+ TEMP RANGE PIN-PACKAGE -40NC to +85NC 32 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. VGHON VIN VMAIN LX PGND FB COMP LDOADJ SS AGND (EP) LINEAR REGULATOR LDOO VLOGIC DTS MAX17117 GATESHADING TIMING CONTROL OPAS OUT OP TO VCOM BACKPLANE POS VGHON GHON ST STH CK1 CKH1 CK3 CKH3 CKH5 CK5 S1 SYSTEM S3 S5 SCAN DRIVER AND GATE-SHADING CONTROL LOGIC Applications Notebook Computer Displays Features RO CK2 CKH2 CK4 CKH4 PANEL CKH6 CK6 S 2.3V to 5.5V IN Supply-Voltage Range S 1.2MHz Current-Mode Step-Up Regulator Fast-Transient Response High-Accuracy Reference (1%) Integrated 16V, 2A, 200mI MOSFET High Efficiency (> 85%) Adjustable Cycle-by-Cycle Current Limit SETUP CONTROLLER ENA Ordering Information PART VVGL IN The low-voltage LDO linear regulator has an integrated 0.8I pass element and can provide at least 350mA. The output voltage is accurate within Q1%. The high-voltage, level-shifting scan driver with gateshading control is designed to drive the TFT panel gate drivers. Its seven outputs swing 40V (maximum) between +35V (maximum) and -15V (minimum) and can swiftly drive capacitive loads. MAX17117 General Description S2 S4 S6 RE VGLC VVGL VGL ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX17117 Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO ABSOLUTE MAXIMUM RATINGS IN, ENA, FB, COMP, SS, DTS, LDOADJ, ST, CK1–CK6, LDOO to AGND................................-0.3V to +7.5V PGND to AGND.....................................................-0.3V to +0.3V LX, OPAS to PGND................................................-0.3V to +18V GHON to PGND.....................................................-0.3V to +45V VGL to PGND........................................................ -20V to +0.3V GHON to VGL..................................................................... +45V STH, CKH1–CKH6, VGLC, RO, RE to VGL..........................................-0.3V to (VGHON + 0.3V) OUT, POS to PGND...............................-0.3V to (VOPAS + 0.3V) GHON and VGL RMS Current Rating...................................0.8A VGLC, STH, and CKH1–CKH6 RMS Current Rating............0.8A LX, PGND RMS Current Rating.............................................1.6A Continuous Power Dissipation (TA = +70NC) 32-Pin TQFN (derate 24.9mW/NC above +70NC)........1990mW Operating Temperature Range........................... -40NC to +85NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +160NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = +3V, Circuit of Figure 1, VOPAS = +8.5V, VGHON = +24V, VVGL = -6.2V, VST = VCK_ = 0V, TA = 0NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER CONDITIONS MAX UNITS 5.5 V 2.00 2.20 V VFB = 1.3V, LX not switching 1.0 2.5 VFB = 1.2V, LX switching 2.5 5 IN Standby Current VENA = VVGL = 0V, VIN = 5.5V, VGHON = 4V 0.7 2 mA GHON Standby Current VENA = VVGL = 0V, VIN = 5.5V, VGHON = 4V 100 200 FA OPAS Standby Current VENA = VVGL = 0V, VIN = 5.5V, VGHON = 4V 20 50 FA Thermal Shutdown Temperature rising 145 OPAS rising 16.5 17 18 V 1000 1200 1400 kHz 91 94 97 % V IN Input Voltage Range IN Undervoltage-Lockout Threshold IN Quiescent Current MIN TYP 2.3 VIN rising, typical hysteresis = 150mV 1.80 170 mA NC STEP-UP REGULATOR Output Voltage Range OPAS Overvoltage Threshold VIN Operating Frequency Oscillator Maximum Duty Cycle 15 FB Regulation Voltage No load 1.227 1.240 1.252 FB Fault-Trip Level Falling edge 1.05 1.10 1.15 Fault-Trigger Delay FB Load Regulation 160 V V ms 0 < ILOAD < full load -0.2 FB Line Regulation VIN = 2.5V to 5.5V, TA = +25NC 0.1 0.25 %/V FB Input-Bias Current VFB = 1.24V, TA = +25NC 65 200 nA FB Transconductance DICOMP = Q2.5FA, FB = COMP 75 160 280 FS 2 2.4 A LX On-Resistance RENA = 10kW, duty cycle = 60% ILX = 1A 1.6 200 500 mI LX Input-Bias Current VLX = 13.5V, TA = +25NC LX Current Limit Current-Sense Transresistance Soft-Start Pullup Current % 10 20 FA 0.10 0.20 0.30 V/A 2 4 6 FA 2 _______________________________________________________________________________________ Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO (VIN = +3V, Circuit of Figure 1, VOPAS = +8.5V, VGHON = +24V, VVGL = -6.2V, VST = VCK_ = 0V, TA = 0NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER CONDITIONS MIN TYP MAX UNITS 15 V 0.8 1.2 mA VCOM BUFFER OPAS Voltage Range 5 OPAS Supply Current VPOS = VOPAS/2, no load OUT Voltage Swing High IOUT = 5mA OUT Voltage Swing Low IOUT = 5mA VOPAS - 100 VOPAS - 50 Sourcing, short to VOPAS/2 - 1V 100 200 Sinking, short to VOPAS/2 + 1V 100 200 POS Input-Bias Current VPOS = VOPAS/2, TA = +25NC -50 POS Input-Offset Voltage VOUT = VOPAS/2 -15 OUT Short-Circuit Current 50 Gain-Bandwidth Product -3dB Bandwidth RLOAD = 10kI, CLOAD = 10pF Slew Rate 5V pulse applied to POS, OUT measured from 10% to 90% 10 mV 100 mV mA +50 +15 nA mV 8 MHz 16 MHz 40 V/Fs HIGH-VOLTAGE SCAN DRIVER GHON Voltage Range 12 35 V VGL Voltage Range -15 -3 V 40 V 550 FA GHON-to-VGL Voltage Range VGHON - VVGL GHON Supply Current CK1 through CK6 and ST low VGL Supply Current CK1 through CK6 and ST low Output Impedance Low STH, CKH_, VGLC, IOUT = -20mA 80 I Output Impedance High STH, CKH_, VGLC, IOUT = +20mA 80 I CKH1, CKH3, CKH5, IRE = 10mA 100 CKH2, CKH4, CKH6, IRO = 10mA 100 Gate-Shading Switch Resistance RO, RE Resistance Range Propagation Delay from ST Rising Edge to STH Rising Edge 350 -500 -300 FA 100 I I CLOAD = 100pF, RLOAD = 0I 100 200 ns Propagation Delay from ST CLOAD = 100pF, RLOAD = 0I Falling Edge to STH Falling Edge 100 200 ns Propagation Delay from CK_ Rising Edge to CKH_ Rising Edge CLOAD = 100pF, RLOAD = 0I 100 200 ns Propagation Delay from CK_ Falling Edge to CKH_ Falling Edge CLOAD = 100pF, RLOAD = 0I 100 200 ns STH, VGLC, CKH_ Rise Time CLOAD = 5nF, RLOAD = 0I; VGHON = 30V, VVGL = -10V; measured from 10% to 90% 0.5 1 Fs STH, VGLC, CKH_ Fall Time CLOAD = 5nF, RLOAD = 0I; VGHON = 30V, VVGL = -10V; measured from 10% to 90% 0.5 1 Fs 100 kHz STH, CKH_ Operating Frequency CLOAD = 5nF, RLOAD = 0I Range _______________________________________________________________________________________ 3 MAX17117 ELECTRICAL CHARACTERISTICS (continued) MAX17117 Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO ELECTRICAL CHARACTERISTICS (continued) (VIN = +3V, Circuit of Figure 1, VOPAS = +8.5V, VGHON = +24V, VVGL = -6.2V, VST = VCK_ = 0V, TA = 0NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER CONDITIONS MIN TYP MAX UNITS 100 150 mV 10 15 µA 10 50 I 1.240 1.265 V 100 150 mV GATE-SHADING TIMING CONTROL Gate-Shading Detection Threshold DTS falling Gate-Shading Detection Current VDTS = 0.5V DTS Switch Resistance VDTS = 1.3V, IDTS = 1mA 5 DTS Rising Edge Threshold 1.215 DTS Falling Edge Threshold LDO LDOO Output Voltage Range VIN V Dropout Voltage VIN = 3.3V, VLDOADJ = 1.1V, ILDOO = 350mA 1.8 300 500 mV LDOO Line Regulation VIN = 2.8V to 5.5V, VLDOO = 2.5V, ILDOO = 100mA 0.1 0.3 %/V LDOO Load Regulation VLDOO = 2.5V, ILDOO = 1mA to 300mA LDOO Current Limit VLDOADJ = 1.0V LDOADJ Feedback Voltage LDOADJ Input-Bias Current 0.2 0.5 %/V 0.4 0.62 0.8 A 1.227 1.240 1.252 V 100 200 nA VLDOADJ = 1.3V, TA = +25NC DIGITAL INPUTS ST, CK_ Input High Level 1.8V < VLDOO < 5.5V ST, CK_ Input Low Level 1.8V < VLDOO < 5.5V ENA Input Logic-High Level 1.8V < VLDOO < 3.0V VLDOO > 3.0V ENA Input Logic-Low Level 0.7 x VLDOO V 0.3 x VLDOO 0.7 x VLDOO V 2.1 V 0.3 x VLDOO 1.8V < VLDOO < 3.0V VLDOO > 3.0V ENA Resistor Range V 0 V 0.8 V 200 kI ELECTRICAL CHARACTERISTICS (VIN = +3V, Circuit of Figure 1, VOPAS = +8.5V, VGHON = +24V, VVGL = -6.2V, VST = VCK_ = 0V, TA = -40NC to +85NC, unless otherwise noted.) PARAMETER CONDITIONS IN Input Voltage Range IN Undervoltage-Lockout Threshold IN Quiescent Current VIN rising, typical hysteresis = 150mV MIN MAX UNITS 2.3 TYP 5.5 V 1.80 2.20 V VFB = 1.3V, LX not switching 2.5 mA VFB = 1.2V, LX switching 5 IN Standby Current VENA = VVGL = 0V, VIN = 5.5V, VGHON = 4V 2 mA GHON Standby Current VENA = VVGL = 0V, VIN = 5.5V, VGHON = 4V 160 FA OPAS Standby Current VENA = VVGL = 0V, VIN = 5.5V, VGHON = 4V 50 FA Thermal Shutdown Temperature rising 145 4 _______________________________________________________________________________________ NC Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO (VIN = +3V, Circuit of Figure 1, VOPAS = +8.5V, VGHON = +24V, VVGL = -6.2V, VST = VCK_ = 0V, TA = -40NC to +85NC, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS STEP-UP REGULATOR Output Voltage Range OPAS Overvoltage Threshold OPAS rising Operating Frequency Oscillator Maximum Duty Cycle VIN 15 V 16.5 18 V 1000 1400 kHz 91 97 % V FB Regulation Voltage No load 1.227 1.252 FB Fault-Trip Level Falling edge 1.05 1.15 V FB Line Regulation VIN = 2.5V to 5.5V, TA = +25NC 0.3 %/V FB Input-Bias Current VFB = 1.3V, TA = +25NC 200 nA FB Transconductance DICOMP = Q2.5FA, FB = COMP 75 280 FS LX Current Limit VFB = 1.2V, duty cycle = 60% 1.6 2.4 A LX On-Resistance ILX = 1A 500 mI LX Input-Bias Current VLX = 13.5V, TA = +25NC Current-Sense Transresistance Soft-Start Pullup Current 20 FA 0.10 0.30 V/A 2 6 FA VCOM BUFFER OPAS Voltage Range 5 OPAS Supply Current VPOS = VOPAS/2, no load OUT Voltage Swing High IOUT = 5mA OUT Voltage Swing Low IOUT = 5mA 15 V 1.2 mA VOPAS - 100 mV 100 mV Sourcing, short to VOPAS/2 - 1V 100 Sinking, short to VOPAS/2 + 1V 100 POS Input-Bias Current VPOS = VOPAS/2, TA = +25NC -50 +50 nA POS Input-Offset Voltage VOUT = VOPAS/2 -15 +15 mV Slew Rate 5V pulse applied to POS, OUT measured from 10% to 90% 10 OUT Short-Circuit Current mA V/Fs HIGH-VOLTAGE SCAN DRIVER GHON Voltage Range 12 VGL Voltage Range -15 35 V -3 V GHON-to-VGL Voltage Range VGHON - VVGL 40 V GHON Supply Current CK1 through CK6 and ST low 550 FA VGL Supply Current CK1 through CK6 and ST low Output Impedance Low STH, CKH_, VGLC, IOUT = -20mA 80 I Output Impedance High STH, CKH_, VGLC, IOUT = +20mA 80 I CKH1, CKH3, CKH5, IRE = 10mA 100 CKH2, CKH4, CKH6, IRO = 10mA 100 Gate-Shading Switch Resistance RO, RE Resistance Range Propagation Delay from ST Rising Edge to STH Rising Edge -500 FA 100 CLOAD = 100pF, RLOAD = 0I I I 200 ns _______________________________________________________________________________________ 5 MAX17117 ELECTRICAL CHARACTERISTICS (continued) MAX17117 Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO ELECTRICAL CHARACTERISTICS (continued) (VIN = +3V, Circuit of Figure 1, VOPAS = +8.5V, VGHON = +24V, VVGL = -6.2V, VST = VCK_ = 0V, TA = -40NC to +85NC, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS Propagation Delay from ST CLOAD = 100pF, RLOAD = 0I Falling Edge to STH Falling Edge 200 ns Propagation Delay from CK_ Rising Edge to CKH_ Rising Edge CLOAD = 100pF, RLOAD = 0I 200 ns Propagation Delay from CK_ Falling Edge to CKH_ Falling Edge CLOAD = 100pF, RLOAD = 0I 200 ns STH, VGLC, CKH_ Rise Time CLOAD = 5nF, RLOAD = 0I; VGHON = 30V, VVGL = -10V; measured from 10% to 90% 1 Fs STH, VGLC, CKH_ Fall Time CLOAD = 5nF, RLOAD = 0I; VGHON = 30V, VVGL = -10V; measured from 10% to 90% 1 Fs 100 kHz 100 150 mV 10 15 µA 50 I STH, CKH_ Operating Frequency CLOAD = 5nF, RLOAD = 0I Range GATE-SHADING TIMING CONTROL Gate-Shutdown Detection Threshold DTS falling Gate-Shutdown Detection Current VDTS = 0.5V DTS Switch Resistance VDTS = 1.3V, IDTS = 1mA DTS Rising Edge Threshold 5 1.210 DTS Falling Edge Threshold 1.265 V 150 mV LDO LDOO Output Voltage Range VIN V Dropout Voltage VIN = 3.3V, VLDOADJ = 1.1V, ILDOO = 350mA 1.8 500 mV LDOO Line Regulation VIN = 2.8V to 5.5V, VLDOO = 2.5V, ILDOO = 100mA 0.3 %/V LDOO Load Regulation VLDOO = 2.5V, ILDOO = 1mA to 300mA 0.5 LDOO Current Limit VLDOADJ = 1.0V %/V A LDOADJ Feedback Voltage LDOADJ Input-Bias Current 0.4 0.8 1.227 1.252 V 200 nA VLDOADJ = 1.3V, TA = +25NC DIGITAL INPUTS ST, CK_ Input High Level 1.8V < VLDOO < 5.5V ST, CK_ Input Low Level 1.8V < VLDOO < 5.5V ENA Input Logic-High Level 1.8V < VLDOO < 3.0V VLDOO > 3.0V ENA Input Logic-Low Level 0.7 x VLDOO 0.3 x VLDOO 0.7 x VLDOO V V 2.1 0.3 x VLDOO 1.8V < VLDOO < 3.0V VLDOO > 3.0V ENA Resistor Range V V 0.8 0 6 _______________________________________________________________________________________ 200 kI Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO STEP-UP REGULATOR LINE REGULATION vs. INPUT VOLTAGE VIN = 2.3V VIN = 3.0V 60 0.10 IMAIN = 0mA 0.10 VIN = 5.0V 0 MAX17117 toc03 MAX17117 toc02 IMAIN = 200mA 0.15 0.05 50 -0.10 VIN = 2.3V -0.20 -0.30 VIN = 3.0V -0.40 VMAIN = 8.5V 0 40 10 1 100 -0.50 2.7 2.3 1000 3.1 LOAD CURRENT (mA) 3.5 3.9 4.3 4.7 5.1 5.5 1 10 IN VOLTAGE (V) 2.5 1000 STEP-UP REGULATOR LOAD-TRANSIENT RESPONSE (20mA TO 300mA) MAX17117 toc05 MAX17117 toc04 3.0 100 LOAD CURRENT (mA) STEP-UP CONVERTER PEAK INDUCTOR CURRENT LIMIT vs. RENA VLX 10V/div 0V INDUCTOR CURRENT 2.0 1A/div 0A 1.5 VMAIN 0V VIN = 3.3V VMAIN = 8.5V VLDO = 2.5V L1 = 10µH 1.0 200mA/div 50 L1 = 10µH RCOMP = 56.2kI CCOMP = 1000pF 20mA 0.5 0 (AC-COUPLED) 200mV/div IMAIN 100 150 200 250 100µs/div RENA (kI) STEP-UP REGULATOR PULSED LOAD-TRANSIENT RESPONSE (20mA TO 1A) MAX17117 toc06 0.10 0V VLX 10V/div 0A INDUCTOR CURRENT 500mA/div 0V VMAIN (AC-COUPLED) 100mV/div IMAIN 1A/div 20mA 10µs/div L1 = 10µH RCOMP = 56.2kI CCOMP = 1000pF VIN = 5.0V 0 MAX17117 toc07 LDO OUTPUT LOAD REGULATION vs. LOAD CURRENT LOAD-REGULATION ERROR (%) PEAK INDUCTOR CURRENT LIMIT (A) EFFICIENCY (%) 80 70 0.20 LINE REGULATION (%) VIN = 5.0V 90 0.25 MAX17117 toc01 100 STEP-UP REGULATOR OUTPUT LOAD REGULATION vs. LOAD CURRENT LOAD-REGULATION ERROR (%) STEP-UP REGULATOR EFFICIENCY vs. LOAD CURRENT -0.10 VIN = 3.0V -0.20 -0.30 -0.40 -0.50 1 10 100 1000 LOAD CURRENT (mA) _______________________________________________________________________________________ 7 MAX17117 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) POWER-UP SEQUENCE (CK1 AND ST CONNECTED TO VLDO) LDO LINE REGULATION vs. INPUT VOLTAGE MAX17117 toc09 MAX17117 toc08 0.15 0.12 LINE REGULATION (%) MAX17117 Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO 0V 0V 0V 0.09 ILDO = 250mA 0V 0V 0.06 VIN 5V/div VLDO 5V/div VMAIN 10V/div VGHON 20V/div VVGL 10V/div VSTH 0V 0.03 ILDO = 100mA 50V/div VCKH1 0V 0V 0 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 50V/div VVGLC 20V/div 40ms/div IN VOLTAGE (V) OPERATIONAL AMPLIFIER LOAD-TRANSIENT RESPONSE OPERATIONAL AMPLIFIER LARGE-SIGNAL STEP RESPONSE MAX17117 toc10 MAX17117 toc11 VVCOM (AC-COUPLED) 1V/div VPOS 2V/div 0V 0mV VVCOM 2V/div IVCOM 100mA/div 0mA 0V 2µs/div 200ns/div OPERATIONAL AMPLIFIER SMALL-SIGNAL STEP RESPONSE CKH_ OUTPUT WAVEFORMS WITH LOGIC INPUT AND GATE-SHADING CONTROL MAX17117 toc12 MAX17117 toc13 VPOS (AC-COUPLED) 100mV/div 0mV VCK1 5V/div VCK2 5V/div VDTS 2V/div 0V 0V 0V VVCOM (AC-COUPLED) 100mV/div 0mV VCKH1 20V/div 0V VCKH2 20V/div 0V 200ns/div 4µs/div 8 _______________________________________________________________________________________ Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO FB COMP OPAS POS OUT RO GHON VGL 24 23 22 21 20 19 18 17 TOP VIEW 16 PGND 25 STH LX 26 15 CKH1 ENA 27 14 CKH2 13 CKH3 12 CKH4 11 CKH5 10 CKH6 9 VGLC IN 28 MAX17117 LDOO 29 LDOADJ 30 DTS 31 EP + 1 2 3 4 5 6 7 8 CK5 CK4 CK3 CK2 CK1 ST CK6 RE SS 32 THIN QFN Pin Description PIN NAME 1–5, 7 CK5–CK1, CK6 FUNCTION 6 ST Start-Pulse, Level-Shifter Logic-Level Input 8 RE Gate-Shading Discharge for CKH2, CKH4, and CKH6 9 VGLC VGL Voltage Output 10–15 CKH6–CKH1 Level-Shifter Outputs 16 STH Start-Pulse Level-Shifter Output 17 VGL Gate-Off Supply. VGL is the negative supply voltage for the STH, CKH1–CKH6, and VGLC high-voltage driver outputs. Bypass to PGND with a minimum of 0.1FF ceramic capacitor. 18 GHON 19 RO 20 OUT Operational Amplifier Output 21 POS Operational Amplifier Noninverting Input 22 OPAS Operational Amplifier Supply Input. Connect to VMAIN (Figure 1) and bypass to AGND with a 0.1FF or greater ceramic capacitor. 23 COMP Compensation for Error Amplifier. Connect a series RC from this pin to AGND. Typical values are 56kI and 1000pF. 24 FB Level-Shifter Logic-Level Inputs Gate-On Supply. GHON is the positive supply voltage for the STH, CKH1–CKH6, and VGLC highvoltage scan-driver outputs. Bypass to PGND with a minimum of 0.1FF ceramic capacitor. Gate-Shading Discharge for CKH1, CKH3, and CKH5 Step-Up Regulator Feedback. Reference voltage is 1.24V nominal. Connect the midpoint of an external resistor-divider to FB and minimize trace area. Set VMAIN according to VMAIN = 1.24V (1 + R1/R2). _______________________________________________________________________________________ 9 MAX17117 Pin Configuration MAX17117 Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO Pin Description (continued) PIN NAME FUNCTION 25 PGND 26 LX 27 ENA Chip-Enable Control and OCP Set Input. When ENA = low, the step-up converter and op amp are disabled, the LDO remains active, and the level-shifter outputs are high impedance. 28 IN Step-Up Regulator and Low-Dropout Regulator Supply. Bypass IN to AGND with a 1FF or greater ceramic capacitor. Power Ground. Source connection of the internal step-up regulator power switch. Switching Node. Connect inductor/catch diode here and minimize trace area for lowest EMI. 29 LDOO 30 LDOADJ 31 DTS Gate-Shading Discharge Time Adjust 32 SS Step-Up Regulator Soft-Start Control — EP Exposed Backside Pad. Connect to the analog ground plane for proper electrical and thermal performance. Internal Linear Regulator Output. Bypass LDOO to AGND with a 1FF capacitor. Linear Regulator Feedback Input. Reference voltage is 1.24V nominal. 10 ������������������������������������������������������������������������������������� Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO 0.22µF D2 86.6I VVGL -6.0V, 10mA 0.1µF 2.2µF D5 6.2V, 200mW L1 10µH D1 8.5V, 200mA IN ENA C5 10µF C4 10µF LX R1 102kI FB LDOADJ COMP RCOMP 56.2kI CCOMP 1000pF SS LDOO VLOGIC DTS MAX17117 R2 17.4kI CSS 0.33µF AGND (EP) C1 1µF CSET 100pF C6 10µF PGND R6 49.9kI RSET 29.4kI VMAIN C3 10µF C2 1µF R5 51.1kI D4 0.1µF 0.22µF VIN RENA 62kI OPAS 0.1µF OUT TO VCOM BACKPLANE R3 56.2kI GHON VGHON VGHON 23V, 25mA POS 0.1µF R4 56.2kI STH ST CKH1 CK1 CKH3 CK3 CKH5 CK5 RO SYSTEM R0 1kI PANEL CK2 CKH2 CK4 CKH4 CK6 CKH6 RE RE 1kI VGL VVGL 0.1µF VGLC Figure 1. Typical Application Circuit ______________________________________________________________________________________ 11 MAX17117 D3 0.1µF MAX17117 Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO Table 1. Component List DESIGNATION DESCRIPTION C1, C2 1FF ±10%, 16V X5R ceramic capacitors (0603) Murata GRM188R61C105K TDK C1608X5R1C105K C3 10FF Q10%, 10V X5R ceramic capacitor (0805) TDK C2012X5R1A106K Murata GRM21BR61A106K C4, C5, C6 D1 D2, D3, D4 10FF Q10%, 16V X5R ceramic capacitors (1206) Murata GRM31CR61C106K TDK C3216X5R1C106K 1A, 30V Schottky diode (S-Flat) Central CMMSH1-40 LEAD FREE Nihon EP10QY03 Toshiba CRS02 (TE85L, Q, M) 200mA, 100V dual diodes (SOT23) Fairchild MMBD4148SE (Top Mark: D4) Central CMPD7000+ (Top Mark: C5C) D5 6.2V, 200mW zener diode (SOD-323) ROHM UDZSTE-176.2B Fairchild MM3Z6V2B L1 10FH, 1.85A, 74.4mI inductor (6mm x 6mm x 3mm) Sumida CDRH5D28RHPNP-100M Typical Application Circuit The MAX17117 typical application circuit (Figure 1) generates a +8.5V source-driver supply and approximately +23V and -6V gate-driver supplies for TFT displays. The input voltage range for the IC is from +2.3V to +5.5V, but the circuit in Figure 1 is designed to run from 2.5V to 3.6V. Table 1 lists the recommended components and Table 2 lists the component suppliers. Detailed Description The MAX17117 includes a high-performance step-up regulator, a 350mA low-dropout (LDO) linear regulator, a high-speed operational amplifier, and a high-voltage, level-shifting scan driver with gate-shading control. Figure 2 shows the functional diagram. Step-Up Regulator The step-up regulator employs a peak current-mode control architecture with a fixed 1.2MHz switching frequency that maximizes loop bandwidth and provides a fast-transient response to pulsed loads found in source drivers of TFT LCD panels. The high switching frequency allows the use of low-profile inductors and ceramic capacitors to minimize the thickness of LCD panel designs. The integrated high-efficiency MOSFET reduces the number of external components required. The output voltage can be set from VIN to 15V with an external resistive voltage-divider. Table 2. Component Suppliers SUPPLIER WEBSITE Central Semiconductor Corp. www.centralsemi.com Fairchild Semiconductor www.fairchildsemi.com Murata Electronics North America, Inc. www.murata-northamerica.com Nihon Inter Electronics Corp. www.niec.co.jp ROHM Co., Ltd. www.rohm.com Sumida Corp. www.sumida.com TDK Corp. www.component.tdk.com Toshiba America Electronic Components, Inc. www.toshiba.com/taec 12 ������������������������������������������������������������������������������������� Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO VVGL VMAIN VIN IN LX PGND ENA FB SET-UP CONTROLLER LDOADJ COMP SS AGND (EP) LINEAR REGULATOR LDOO VLOGIC MAX17117 GATESHADING TIMING CONTROL DTS OPAS OUT OP SDTS VGHON TO VCOM BACKPLANE POS GHON ST STH CK1 CKH1 CK3 CKH3 CK5 CKH5 S1 SYSTEM S3 S5 CK2 SCAN DRIVER AND GATESHADING CONTROL LOGIC RO PANEL CKH2 CKH4 CK4 CKH6 CK6 S2 S4 S6 RE VGLC VVGL VGL Figure 2. Functional Diagram ______________________________________________________________________________________ 13 MAX17117 VGHON MAX17117 Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO The regulator controls the output voltage and the power delivered to the output by modulating the duty cycle (D) of the internal power MOSFET in each switching cycle. The duty cycle of the MOSFET is approximated by: V − VIN D ≈ MAIN VMAIN Figure 3 shows the step-up regulator block diagram. An error amplifier compares the signal at FB to 1.24V and changes the COMP output. The voltage at COMP determines the current trip point each time the internal MOSFET turns on. As the load varies, the error amplifier sources or sinks current to the COMP output accordingly to produce the inductor peak current necessary to service the load. To maintain stability at high duty cycles, a slope compensation signal is summed with the currentsense signal. On the rising edge of the internal clock, the controller sets a flip-flop, turning on the n-channel MOSFET and applying the input voltage across the inductor. The current through the inductor ramps up linearly, storing energy in its magnetic field. Once the sum of the current-feedback signal and the slope compensation exceed the COMP voltage, the controller resets the flip-flop and turns off the MOSFET. Since the inductor current is continuous, a transverse potential develops across the inductor that turns on the diode (D1). The voltage across the inductor then becomes the difference between the output voltage and the input voltage. This discharge condition forces the current through the inductor to ramp back down, transferring the energy stored in the magnetic field to the output capacitor and the load. The MOSFET remains off for the rest of the clock cycle. Undervoltage Lockout (UVLO) The UVLO circuit compares the input voltage at IN with the UVLO threshold (2.0V typ) to ensure that the input voltage is high enough for reliable operation. The 150mV (typ) hysteresis prevents supply transients from causing a restart. Once the input voltage exceeds the UVLO rising threshold, startup begins. When the input voltage falls below the UVLO falling threshold, the controller turns off the main step-up regulator. LX CLOCK LOGIC AND DRIVER PGND ILIM COMPARATOR ILIMIT SLOPE COMP 1.2MHz OSCILLATOR TO FAULT LOGIC PWM COMPARATOR CURRENT SENSE FB 1.10V FAULT COMPARATOR ERROR AMP 1.24V COMP Figure 3. Step-Up Regulator Block Diagram 14 ������������������������������������������������������������������������������������� Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO Overcurrent Protection The step-up regulator features an adjustable cycleby-cycle current limit. The inductor current is sensed through the LX switch during the LX switch on-time. If the peak inductor current rises above the current-limit threshold set by RENA, the LX switch immediately turns off until the next switching cycle, effectively limiting the peak-inductor current each cycle. Soft-Start The soft-start feature effectively limits the inrush current at startup by slowly raising the regulation voltage of the step-up converter’s feedback pin (VFB) at a rate determined by the selection of the soft-start capacitor (CSS). At startup, once ENA is pulled high through RENA, an internal 4FA (typ) current source begins to charge the soft-start capacitor (CSS), slowly bringing up the voltage at the soft-start pin (VSS). VFB follows VSS for VSS < 1.24V. Once VSS exceeds 1.24V, VFB remains at 1.24V, allowing VMAIN to reach its full regulation voltage. Fault Protection During steady-state operation, the MAX17117 monitors the FB voltage. If the FB voltage falls below 1.1V (typ), the MAX17117 activates an internal fault timer. If there is a continuous fault more than 160ms (typ), the MAX17117 sets the fault latch, turning off all outputs except LDOO. Once the fault condition is removed, cycle the input voltage to clear the fault latch and reactivate the device. The fault-detection circuit is disabled during the soft-start time. Operational Amplifier The MAX17117 has an operational amplifier that is typically used to drive the LCD backplane (VCOM) or the gamma-correction-divider string. The operational amplifier features Q200mA (typ) output short-circuit current, 40V/Fs (typ) slew rate, and 16MHz (typ) bandwidth. While the op amp is a rail-to-rail input and output design, its accuracy is significantly degraded for input voltages within 1V of its supply rails (OPAS and AGND). Short-Circuit Current Limit The operational amplifier limits short-circuit current to approximately Q200mA (typ) if the output is directly shorted to OPAS or to AGND. If the short-circuit condition persists, the junction temperature of the IC rises until it reaches the thermal-shutdown threshold (+170NC typ). Once the junction temperature reaches the thermal-shutdown threshold, an internal thermal sensor immediately shuts down all outputs until the input voltage is cycled off, then on again. Driving Pure Capacitive Loads The operational amplifier is typically used to drive the LCD backplane (VOUT) or the gamma-correction-divider string. The LCD backplane consists of a distributed series capacitance and resistance, a load that can be easily driven by the operational amplifier. However, if the operational amplifier is used in an application with a pure capacitive load, steps must be taken to ensure stable operation. As the operational amplifier’s capacitive load increases, the amplifier’s bandwidth decreases and gain peaking increases. A 5I to 50I small resistor placed between VOUT and the capacitive load reduces peaking, but also reduces the gain. An alternative method of reducing peaking is to place a series RC network (snubber) in parallel with the capacitive load. The RC network does not continuously load the output or reduce the gain. Typical values of the resistor are between 100I and 200I and the typical value of the capacitor is 10pF. High-Voltage Scan Driver The high-voltage, level-shifting scan driver with gateshading control is designed to drive the TFT panel gate drivers. Its seven outputs swing 40V (maximum) between +35V (maximum) and -15V (minimum) and can swiftly drive capacitive loads. The driver outputs (STH, CKH_) swing between their power-supply rails (GHON and VGL), according to the input logic levels on their corresponding inputs (ST, CK_) except during a gateshading period. During a gate-shading period, a CKH_ output driver becomes high impedance and an internal switch connected between the CKH_ output’s capacitive load and either RO or RE closes (S1–S6) whenever the state of its corresponding CK_ input is logic-low. This allows part of an output’s GHON-to-VGL transition to be completed by partially discharging its capacitive load through an external resistor attached to either RO or RE for a duration set by the gate-shading period. See Figure 4. ______________________________________________________________________________________ 15 MAX17117 Overvoltage Protection The MAX17117 monitors OPAS for an overvoltage condition. If the OPAS voltage is above 17V (typ), the MAX17117 disables the gate driver of the step-up regulator and prevents the internal MOSFET from switching. The OPAS overvoltage condition does not set the fault latch. MAX17117 Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO If the gate-shading control is enabled, a gate-shading period is initiated by a falling edge of a CK_ input whenever VDTS is less than 100mV. Once the gate-shading period is initiated, a switch across CSET (SDTS) opens, allowing CSET to be charged through RSET. Once VDTS reaches 1.24V, SDTS closes to discharge CSET, the gate-shading period is terminated, and the CKH_ output states are directly determined by their corresponding CK_ input logic states again. Once a gate-shading period is initiated, VDTS must charge to 1.24V and subsequently discharge back below 100mV, before the next CK_ falling can activate a new gate-shading period. By configuring RSET and CSET as shown in Figure 1, the gate-shading period time duration is determined by RSET and CSET and VLDOO (see the Setting the Gate-Shading Period Time Duration section). The gate-shading control can be disabled by removing RSET. If RSET is removed, the states of the CKH_ outputs are always determined by their corresponding CK_ input logic states. See Figure 5. Low-Dropout Linear Regulator (LDO) The MAX17117 has an integrated 0.8I pass element and can provide at least 350mA. The output voltage is accurate within Q1%. Thermal-Overload Protection When the junction temperature exceeds TJ = +170NC (typ), a thermal sensor activates a fault-protection latch, which shuts down all outputs, allowing the IC to cool down. All outputs remain off until the IC cools and the input voltage is cycled below, then back above the IN UVLO threshold. The thermal-overload protection protects the IC in the event of fault conditions. For continuous operation, do not exceed the absolute maximum junction temperature rating of TJ = +150NC. CKH1 CK1 CKH3 CK2 CKH5 CK3 CK4 S1 S3 CK5 S5 CK6 LDOO LEVEL SHIFTER AND GATE-SHADING LOGIC RO MAX17117 RO CKH2 LDO CKH4 RSET CKH6 DTS CSET SDTS S2 S4 S6 RE RE Figure 4. Scan-Driver Block Diagram 16 ������������������������������������������������������������������������������������� Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO 0 CK2 0 CK3 0 CK4 0 CK5 0 CK6 0 1.24V DTS 0 CKH1 0 CKH2 0 CKH3 0 CKH4 0 CKH5 0 CKH6 0 Figure 5. Scan-Driver Operation with Gate-Shading Control Enabled ______________________________________________________________________________________ 17 MAX17117 CK1 MAX17117 Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO Design Procedure Main Step-Up Regulator Inductor Selection The minimum inductance value, peak current rating, and series resistance are factors to consider when selecting the inductor. These factors influence the converter’s efficiency, maximum output-load capability, transientresponse time, and output-voltage ripple. Physical size and cost are also important factors to be considered. The maximum output current, input voltage, output voltage, and switching frequency determine the inductor value. Very high-inductance values minimize the current ripple and therefore reduce the peak current, which decreases core losses in the inductor and I2R losses in the entire power path. However, large inductor values also require more energy storage and more turns of wire, which increase physical size and can increase I2R losses in the inductor. Low-inductance values decrease the physical size but increase the current ripple and peak current. Finding the best inductor involves choosing the best compromise among circuit efficiency, inductor size, and cost. The equations used here include a constant called LIR, which is the ratio of the inductor peak-to-peak ripple current to the average DC inductor current at the full-load current. The best trade-off between inductor size and circuit efficiency for step-up regulators generally has an LIR between 0.3 and 0.5. However, depending on the AC characteristics of the inductor core material and ratio of inductor resistance to other power-path resistances, the best LIR can shift up or down. If the inductor resistance is relatively high, more ripple can be accepted to reduce the number of turns required and increase the wire diameter. If the inductor resistance is relatively low, increasing inductance to lower the peak current can decrease losses throughout the power path. If extremely thin high-resistance inductors are used, as is common for LCD panel applications, the best LIR can increase to between 0.5 and 1.0. Once a physical inductor is chosen, higher and lower values of the inductor should be evaluated for efficiency improvements in typical operating regions. In Figure 1, the LCD’s gate-on and gate-off supply voltages are generated from two unregulated charge pumps driven by the step-up regulator’s LX node. The additional load on LX must therefore be considered in the inductance and current calculations. The effective maximum output current, IMAIN(EFF), becomes the sum of the maximum load current of the step-up regulator’s output plus the contributions from the positive and negative charge pumps: IMAIN(EFF) = IMAIN(MAX) + n VN × I VN + (n VP + 1) × I VP where IMAIN(MAX) is the maximum step-up output current, nVN is the number of negative charge-pump stages, nVP is the number of positive charge-pump stages, IVN is the negative charge-pump output current, and IVP is the positive charge-pump output current, assuming the initial pump source for IVP is VMAIN. Calculate the approximate inductor value using the typical input voltage (VIN), the maximum output current (IMAIN(EFF)), the expected efficiency (ETYP) taken from an appropriate curve in the Typical Operating Characteristics, the desired switching frequency (fOSC), and an estimate of LIR based on the above discussion: V L = IN V MAIN 2 VMAIN − VIN η TYP IMAIN(EFF) × fOSC LIR Choose an available inductor value from an appropriate inductor family. Calculate the maximum DC input current at the minimum input voltage VIN(MIN) using conservation of energy and the expected efficiency at that operating point (EMIN) taken from an appropriate curve in the Typical Operating Characteristics: IIN(DC,MAX) = IMAIN(EFF) × VMAIN VIN(MIN) × ηMIN Calculate the ripple current at that operating point and the peak current required for the inductor: IRIPPLE = ( VIN(MIN) × VMAIN − VIN(MIN) ) L × VMAIN × fOSC I IPEAK = IIN(DC,MAX) + RIPPLE 2 The inductor’s saturation current rating and the MAX17117 LX current limit should exceed IPEAK and the inductor’s DC current rating should exceed IIN(DC,MAX). For good efficiency, choose an inductor with less than 0.1I series resistance. Considering the typical application circuit, the maximum load current (IMAIN(MAX)) is 200mA, with an 8.5V output and a typical input voltage of 3.3V. The effective full-load step-up current is: IMAIN(EFF) = 200mA + 1× 10mA + (2 + 1) × 25mA = 285mA 18 ������������������������������������������������������������������������������������� Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO 2 3.3V 8.5V − 3.3V 0.85 L= ≈ 9.7µH 8.5V 0.285A × 1.2MHz 0.2 A 10FH inductor is chosen. Then, using the circuit’s minimum input voltage (3.0V) and estimating efficiency of 83% at that operating point: IIN(DC,MAX) = 0.285A × 8.5V ≈ 0.973A 3V × 0.83 The ripple current and the peak current at that input voltage are: IRIPPLE = 3V × (8.5V − 3V) 10µH × 8.5V × 1.2MHz IPEAK = 0.973A + ≈ 0.162A 0.162A = 1.05A 2 Peak Inductor Current-Limit Setting Connecting RENA between the ENA pin and the LDOO output, as shown in Figure 1, allows the inductor peak current limit to be adjusted up to 2A max by choosing the appropriate RENA resistor with the following equation: RENA ≈ (VLDOO − 1.25V)(80000) I OCP The above threshold set by RENA varies depending on the step-up converter’s input voltage, output voltage, and duty cycle. Place RENA close to the IC such that the connection between RENA and the ENA pin is as short as possible. Output Capacitor Selection The total output-voltage ripple has two components: the capacitive ripple caused by the charging and discharging of the output capacitance, and the ohmic ripple due to the capacitor’s equivalent series resistance (ESR): VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) V I − VIN VRIPPLE(C) ≈ MAIN MAIN C OUT VMAINfOSC and: VRIPPLE(ESR) ≈ IPEAKR ESR(COUT) where IPEAK is the peak inductor current (see the Inductor Selection section). For ceramic capacitors, the output-voltage ripple is typically dominated by VRIPPLE(C). The voltage rating and temperature characteristics of the output capacitor must also be considered. Input-Capacitor Selection The input capacitor (C3) reduces the current peaks drawn from the input supply and reduces noise injection into the IC. A 10FF ceramic capacitor is used in the typical application circuit (Figure 1) because of the high source impedance seen in typical lab setups. Actual applications usually have much lower source impedance since the step-up regulator often runs directly from the output of another regulated supply. Rectifier Diode The MAX17117 high switching frequency demands a high-speed rectifier. Schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. In general, a 1A Schottky diode complements the internal MOSFET well. Output-Voltage Selection The output voltage of the main step-up regulator is adjusted by connecting a resistive voltage-divider from the output (VMAIN) to AGND with the center tap connected to FB (see Figure 1). Select R2 in the 10kI to 50kI range. Calculate R1 with the following equation: V R1 = R2 × MAIN − 1 VREF Place R1 and R2 close to the IC such that the connections between these components and the FB pin are kept as short as possible. Loop Compensation Choose RCOMP to set the high-frequency integrator gain for fast-transient response. Choose CCOMP to set the integrator zero to maintain loop stability. For low-ESR output capacitors, use the following equations to obtain stable performance and good transient response: 1.45k × VIN × VMAIN × C OUT R COMP ≈ L × IMAIN(MAX) C COMP ≈ 40 × VMAIN× L × IMAIN(MAX) (VIN ) 2 × R COMP To further optimize transient response, vary RCOMP in 20% steps and CCOMP in 50% steps while observing transient-response waveforms. ______________________________________________________________________________________ 19 MAX17117 Choosing an LIR of 0.2 and estimating efficiency of 85% at this operating point: MAX17117 Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO Operational Amplifier Output Voltage Using the buffer configuration as shown in Figure 1, the output voltage of the operational amplifier is adjusted by connecting a resistive voltage-divider from the output (VMAIN) to AGND with the center tap connected to POS (see Figure 1). Select R3 in the 10kI to 100kI range. Calculate R4 with the following equation: V R3 = R4 × 1 − MAIN VOUT Applications Information Power Dissipation Place R3 and R4 close to the IC such that the connections between these components and the POS pin are kept as short as possible. LDO Output Voltage The output voltage of the LDO is adjusted by connecting a resistive voltage-divider from the output (VLDOO) to AGND with the center tap connected to LDOADJ (see Figure 1). Select R6 in the 10kI to 50kI range. Calculate R5 with the following equation: V R5 = R6 × LDOO − 1 1.24V Place R5 and R6 close to the IC such that the connections between these components and the LDOADJ pin are kept as short as possible. Connect a 1FF low ESR capacitor between LDOO and AGND to ensure stability and to provide good outputtransient performance. Scan Driver Setting the Gate-Shading Period Time Duration To set the gate-shading period time duration, configure RSET and CSET as shown in Figure 1. Choose a CSET value greater than 35pF, then calculate the required RSET value that gives the desired gate-shading period time duration with the following equation: R SET = Gate-Shading Discharge Resistors For proper operation, choose RO and RE discharge resistors that are greater than 100I. Place RO and RE close to the IC such that the connections between these components and their respective pins are kept as short as possible. −t 1.24V ln1 − × C SET V LDOO Increase or decrease CSET as needed and repeat the above calculation to achieve the desired gate-shading period time duration, while ensuring CSET remains greater than 35pF and RSET is within the 8kI to 100kI range. Place RSET and CSET close to the IC such that the connections between these components and the DTS pin are kept as short as possible. An IC’s maximum power dissipation depends on the thermal resistance from the die to the ambient environment and the ambient temperature. The thermal resistance depends on the IC package, PCB copper area, other thermal mass, and airflow. The MAX17117, with its exposed backside paddle soldered to 1in2 of PCB copper, can dissipate approximately 1990mW into +70NC still air. More PCB copper, cooler ambient air, and more airflow increase the possible dissipation, while less copper or warmer air decreases the IC’s dissipation capability. The major components of power dissipation are the power dissipated in the stepup regulator and the power dissipated by the operational amplifiers. The MAX17117’s largest on-chip power dissipation occurs in the step-up switch, the VCOM amplifier, the CKH_ level shifters, and the LDO. Step-Up Regulator The largest portions of the power dissipated by the step-up regulator are the internal MOSFET, the inductor, and the output diode. If the step-up regulator with 3.3V input and 285mA output has approximately 85% efficiency, approximately 5% of the power is lost in the internal MOSFET, approximately 3% in the inductor, and approximately 5% in the output diode. The remaining few percent are distributed among the input and output capacitors and the PCB traces. If the input power is approximately 2.85W, the power lost in the internal MOSFET is approximately 143mW. Operational Amplifier The power dissipated in the operational amplifier depends on the output current, the output voltage, and the supply voltage: PD SOURCE = I VCOM_SOURCE × (VAVDD − VVCOM ) PD SINK = I VCOM_SINK × VVCOM where IVCOM_SOURCE is the output current sourced by the operational amplifier, and IVCOM_SINK is the output current that the operational amplifier sinks. In a typical 20 ������������������������������������������������������������������������������������� Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO LDO The power dissipated in the LDO depends on the LDO’s output current, input voltage, and output voltage: PD LDO = ILDOO × (VIN − VLDOO ) Scan-Driver Outputs The power dissipated by the six CKH_ scan-driver outputs depends on the scan frequency, the capacitive load on each output, and the difference between the GHON and VGL supply voltages: PD SCAN = 6 × fSCAN × C PANEL × (VGHON − VVGL ) 2 If the scan frequency is 50kHz, the load of the six CKH_ outputs is 3.4nF, and the supply voltage difference is 30V, then the power dissipated is 0.92W. PCB Layout and Grounding Careful PCB layout is important for proper operation. Use the following guidelines for good PCB layout: • M inimize the area of high-current loops by placing the inductor, output diode, and output capacitors near the input capacitors and near LX and PGND. The highcurrent input loop goes from the positive terminal of the input capacitor to the inductor, to the IC’s LX pin, out of PGND, and to the input capacitor’s negative terminal. The high-current output loop is from the positive terminal of the input capacitor to the inductor, to the output diode (D1), to the positive terminal of the output capacitors, reconnecting between the output capacitor and input capacitor ground terminals. Connect these loop components with short, wide connections. Avoid using vias in the high-current paths. If vias are unavoidable, use many vias in parallel to reduce resistance and inductance. • C reate a power ground island (PGND) consisting of the input and output capacitor grounds, PGND pin, and any charge-pump components. Connect all these together with short, wide traces or a small ground plane. Maximizing the width of the power ground traces improves efficiency and reduces output-voltage ripple and noise spikes. Create an analog ground plane (AGND) consisting of all the feedback-divider ground connections; the operational-amplifier-divider ground connection; the OPAS bypass capacitor ground connection; the COMP, SS, and SET capacitor ground connections; and the device’s exposed backside pad. Connect the AGND and PGND islands by connecting the PGND pin directly to the exposed backside pad. Make no other connections between these separate ground planes. • P lace the feedback voltage-divider resistors as close as possible to their respective feedback pins. The divider’s center trace should be kept short. Placing the resistors far away causes the feedback trace to become an antenna that can pick up switching noise. Care should be taken to avoid running the feedback trace near LX or the switching nodes in the charge pumps. • P lace the IN pin bypass capacitor as close as possible to the device. The ground connections of the IN bypass capacitor should be connected directly to AGND at the backside pad of the IC. • M inimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. • M inimize the size of the LX node while keeping it wide and short. Keep the LX node away from the feedback node and analog ground. Use DC traces as a shield if necessary. Refer to the MAX17117 Evaluation Kit for an example of proper board layout. Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 32 TQFN-EP T3255N+1 21-0140 ______________________________________________________________________________________ 21 MAX17117 case where the supply voltage is 8.5V and the output voltage is 4.25V with an output source current of 30mA, the power dissipated is 128mW. MAX17117 Internal-Switch Boost Regulator with Integrated 7-Channel Scan Driver, Op Amp, and LDO Revision History REVISION NUMBER REVISION DATE 0 4/10 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 © 2010 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.