datasheet

Rev. 1.0, May. 2013
MZ-7PD512
MZ-7PD256
MZ-7PD128
Samsung SSD 840 PRO Series.
datasheet
DISCLAIMER
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or otherwise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2013 Samsung Electronics Co., Ltd. All rights reserved.
COPYRIGHT ⓒ 2013
This material is copyrighted by Samsung Electronics. Any unauthorized reproduction, use or disclosure of
this material, or any part thereof, is strictly prohibited and is a violation under copyright law.
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MZ-7PD512
MZ-7PD256
MZ-7PD128
Rev. 1.0
datasheet
840 PRO Series
Revision History
Revision No.
1.0
History
Final version
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Draft Date
Remark
Editor
May. 13. 2013
Final
WH Yang
MZ-7PD512
MZ-7PD256
MZ-7PD128
datasheet
Rev. 1.0
840 PRO Series
1.0 General Description .................................................................................................................................................... 5
2.0 Mechanical Specification ........................................................................................................................................... 6
2.1 Physical dimensions and Weight ............................................................................................................................ 6
3.0 Product Specifications ............................................................................................................................................... 7
3.1 System Interface and Configuration ........................................................................................................................ 7
3.2 System performance ........................................................................................................................................7
3.3 Drive Capacity ..................................................................................................................................................7
3.4 Supply Voltage..................................................................................................................................................7
3.5 System Power Consumption ............................................................................................................................7
3.6 System Reliability.............................................................................................................................................8
3.7 Environmental Specifications............................................................................................................................8
4.0 Electrical Interface Specification ................................................................................................................................ 9
4.1 Pin Assignments ..............................................................................................................................................9
5.0 Command Descriptions.............................................................................................................................................. 10
5.1 Supported ATA Commands..............................................................................................................................10
5.2 SECURITY FEATURE Set ..................................................................................................................................... 11
5.2.1 SECURITY mode default setting...................................................................................................................... 11
5.2.2 Initial setting of the user password................................................................................................................... 11
5.2.3 SECURITY mode operation from power-on..................................................................................................... 11
5.2.4 Lost Password.................................................................................................................................................. 11
5.3 SMART FEATURE Set (B0h) ................................................................................................................................. 11
5.3.1 Sub Command ................................................................................................................................................. 11
5.3.1.1 S.M.A.R.T. Read Attribute Values (sub-command D0h) ........................................................................... 11
5.3.1.2 S.M.A.R.T. Read Attribute Thresholds (sub-command D1h)..................................................................... 11
5.3.1.3 S.M.A.R.T. Enable/Disable Attribute Autosave (sub-command D2h) ........................................................ 12
5.3.1.4 S.M.A.R.T. Save Attribute Values (sub-command D3h) ............................................................................ 12
5.3.1.5 S.M.A.R.T. Execute Off-line Immediate (sub-command D4h) ................................................................... 12
5.3.1.6 S.M.A.R.T. Selective self-test routine ........................................................................................................ 13
5.3.1.7 S.M.A.R.T. Read Log Sector (sub-command D5h) ................................................................................... 14
5.3.1.8 S.M.A.R.T. Write Log Sector (sub-command D6h).................................................................................... 14
5.3.1.9 S.M.A.R.T. Enable Operations (sub-command D8h)................................................................................. 14
5.3.1.10 S.M.A.R.T. Disable Operations (sub-command D9h).............................................................................. 14
5.3.1.11 S.M.A.R.T. Return Status (sub-command DAh) ...................................................................................... 15
5.3.1.12 S.M.A.R.T. Enable/Disable Automatic Off-line (sub-command DBh) ...................................................... 15
5.3.2 Device Attribute Data Structure........................................................................................................................ 16
5.3.2.1 Data Structure Revision Number ............................................................................................................... 16
5.3.2.2 Individual Attribute Data Structure ............................................................................................................. 17
5.3.2.3 Off-Line Data Collection Status ................................................................................................................. 18
5.3.2.4 Self-test execution status........................................................................................................................... 18
5.3.2.5 Total time in seconds to complete off-line data collection activity ............................................................. 18
5.3.2.6 Current segment pointer ............................................................................................................................ 18
5.3.2.7 Off-line data collection capability ............................................................................................................... 18
5.3.2.8 S.M.A.R.T. Capability ................................................................................................................................ 19
5.3.2.9 Error logging capability .............................................................................................................................. 19
5.3.2.10 Self-test failure check point...................................................................................................................... 19
5.3.2.11 Self-test completion time ......................................................................................................................... 19
5.3.2.12 Data Structure Checksum........................................................................................................................ 19
5.3.3 Device Attribute Thresholds data structure .................................................................................................... 19
5.3.3.1 Data Structure Revision Number ............................................................................................................... 19
5.3.3.2 Individual Thresholds Data Structure......................................................................................................... 20
5.3.3.3 Attribute ID Numbers ................................................................................................................................. 20
5.3.3.4 Attribute Threshold .................................................................................................................................... 20
5.3.3.5 Data Structure Checksum.......................................................................................................................... 20
5.3.4 S.M.A.R.T. Log Directory ................................................................................................................................. 20
5.3.5 S.M.A.R.T. error log sector .............................................................................................................................. 21
5.3.5.1 S.M.A.R.T. error log version ...................................................................................................................... 21
5.3.5.2 Error log pointer ......................................................................................................................................... 21
5.3.5.3 Device error count ..................................................................................................................................... 21
5.3.5.4 Error log data structure .............................................................................................................................. 21
5.3.5.5 Command data structure ........................................................................................................................... 22
5.3.5.6 Error data structure22
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5.3.6 Self-test log structure ....................................................................................................................................... 23
5.3.7 Selective self-test log data structure ................................................................................................................ 23
5.3.8 Error reporting .................................................................................................................................................. 24
6.0 SATA II Optional Feature........................................................................................................................................... 24
6.1 Power Segment Pin P11 ........................................................................................................................................ 24
6.2 Asynchronous Signal Recovery.............................................................................................................................. 24
7.0 Identify Device Data .......................................................................................................................................... 25
8.0 Product Line up .................................................................................................................................................. 27
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Rev. 1.0
840 PRO Series
1.0 General Description
The Samsung SSD 840 PRO is a high-performance SSD (Solid State Drive) designed for power users. Through 100% in-house design and manufacturing, the Samsung SSD 840 PRO Series provides exceptional performance and unrivaled reliability throughout its entire lifetime and under extremely
heavy workloads.
The Samsung 840 PRO Series SSD introduces three important hardware features for business: Worldwide Name (WWN), LED Indicator support, and
hardware-based AES-256 bit Full Disk Encryption(FDE).The first two of these features make it easier to integrate the 840 PRO SSD into server and storage systems. The third, hardware-based AES Encryption, helps safeguard data against attack by encrypting all information on the disk at the hardware
level without performance degradation.In addition to the hardware features mentioned above, Samsung's Magician software makes it much easier for IT
managers to monitor drive health and plan hardware replacement cycles.
Density
- 128GB, 256GB and 512GB are available
Form Factor
- 2.5" Type (100x69.85x6.8mm)
* For the thickness size, drive label thickness was included
Host interface
- Serial ATA interface of 6.0Gbps
- Compliant with ATA/ATAPI-8 Standard
- Power Saving Modes: DIPM
- Support NCQ : Up to 32 depth
- Asynchronous Signal Recovery
- Support TRIM command (regires OS support)
Performance
- Host transfer rate: 600 MB/s
- Sequential Read : Up to 540 MB/s (512/256/128GB)
- Sequential Write : Up to 520 MB/s (512/256GB)
Up to 390 MB/s (128GB)
* Actual performance may vary depending on use conditions and
environment
** Notes :
1. System Configuration:
Intel Core [email protected] 3.4GHz, 4GB DDR3 SDRAM (2GBx2)
1333Mbps; ASUS motherboard with Intel 7 Series Z77 Chipset,
Windows 7 Ultimate x64 SP1; IRST 11.2, MA performance
guide pre-condition.
2. Performance measured using Crystal disk Mark 3.01c
3. Drive was connected as secondary.
Encryption
- AES 256-bit Full Disk Encryption.
- Class0 SED (Self Encryption Drive)
* User can set HDD password in BIOS setup mode.
Temperature
- Operating : 0°C to 70°C
- Non-Operating : -55°C to 95°C
Shock
- Shock
. Non Operating : 1500G, duration 0.5, 3axis
- Vibration
. Non Operating 20~2000Hz, 20G
* Applicable only for cased product
MTBF
- 1,500,000 Hours
Weight
- 128/256/512GB : Max 54g
Warranty
- 5 years limited warranty.
* For enterprise applications, 5 years limited warranty assumes a
maximum average workload of 40GB/day (calculated based on host
writes and on the industry standard of 3-month data retention).
Workloads in excess of 40GB/day are not covered under warranty.
** For enterprise usage, a minimum of 6.7% over-provisioning (OP)
is recommended.
Power Consumption
- Average : 0.069W**(Typical)
- Idle : 0.054W (Typical, DIPM ON), 0.349W (Typical, DIPM OFF)
* All the data was measured thru Mobile Mark 2007.
** DIPM enabled value
*** Power consumption measured with MobileMark 2007 in Windows7.
Values calculated using laptop PC and represent system-level power
consumption.
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840 PRO Series
2.0 Mechanical Specification
2.1 Physical dimensions and Weight
Physical dimensions and Weight gram
Model
Height (mm)
Width (mm)
Length (mm)
Weight ()
128/256/512GB
6.80±0.20
69.85±0.25
100 ±0.25
Max 54
Figure 2-1. Physical dimension
Figure 2-2. Outer Image
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Rev. 1.0
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840 PRO Series
3.0 Product Specifications
3.1 System Interface and Configuration
 Burst read/write rate is 600 MB/sec (6.0 Gb/sec).
 Compliant with ATA-8 Standard
3.2 System performance
Read / Write
MZ-7PD128
Sequential Read
MZ-7PD256
MZ-7PD512
Up to 530 MB/s
Sequential Write
4KB Random Read (QD32)
Up to 540 MB/s
Up to 390 MB/s
Up to 520 MB/s
Up to 520 MB/s
Max. 97,000 IOPS
Max. 100,000 IOPS
Max. 100,000 IOPS
4KB Random Write (QD32)
Max. 90,000 IOPS
4KB Random Read (QD1)
Max. 9,800 IOPS
Max. 9,900 IOPS
4KB Random Write (QD1)
Max. 9,900 IOPS
Max. 31,000 IOPS
* Actual performance may vary depending on use conditions and environment
* NOTE :
1. System Configuration : Intel Core [email protected] 3.4GHz, 4GB DDR3 SDRAM (2GBx2) 1333Mbps; ASUS motherboard with Intel 7 Series Z77 Chipset,
Windows 7 Ultimate x64 SP1; IRST 11.2, MA performance guide pre-condition.
2. Performance measured using IO Meter 2008 and Crystal disk Mark
3. Measurements are performed on whole LBA range
4. Write cache enabled
5. 1MB/sec = 1,048,576 bytes/sec was used in sequential performance
3.3 Drive Capacity
MZ-7PD128
Unformatted Capacity
User-Addressable Sectors
MZ-7PD256
MZ-7PD512
128 GB
256 GB
512 GB
250,069,680
500,118,192
1,000,215,216
Bytes per Sector
512 Bytes
NOTE :
1 Megabyte (MB) = 1 Million bytes; 1 Gigabyte (GB) = 1 Billion bytes
* Actual usable capacity may be less (due to formatting, partitioning, operating system, applications or otherwise)
3.4 Supply Voltage
Item
Requirements
5V + 5%
Allowable voltage
Allowable noise/ripple
100mV p-p or less
3.5 System Power Consumption
Power
Typical
128GB
0.069W
256GB
0.069W
512GB
0.069W
NOTE :
* All the data was measured thru Mobile Mark 2007.
** DIPM enabled value
*** Power consumption measured with MobileMark 2007 in Windows7.
Values calculated using laptop PC and represent system - level power consumption.
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Rev. 1.0
datasheet
840 PRO Series
3.6 System Reliability
MTBF
1,500,000 Hours
3.7 Environmental Specifications
Features
Operating
Non-Operating
Temperature
0°C to 70°C
-55°C to 95°C
Humidity
5% to 95%, non-condensing
Vibration
Non Operating 20~2000Hz, 20G
Shock
Non Operating 1500G, duration 0.5, 3axis
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4.0 Electrical Interface Specification
4.1 Pin Assignments
No.
Signal
Plug Connector pin definition
S1
GND
S2
A+
S3
A-
S4
GND
S5
B-
S6
B+
S7
GND
2nd mate
Differential signal A from Phy
2nd mate
Differential signal B from Phy
2nd mate
Key and spacing separate signal and power segments
Power
P1
V33
3.3V power (Unused)
P2
V33
3.3V power (Unused)
P3
DEVSLP
Enter/Exit DevSleep
P4
GND
1st mate
P5
GND
2nd mate
P6
GND
2nd mate
P7
V5
5V power, pre-charge, 2nd mate
P8
V5
5V power
P9
V5
5V power
P10
GND
2nd mate
P11
DAS/DSS
P12
GND
1st mate
P13
V12
12V power, pre-charge, 2nd mate (Unused)
P14
V12
12V power (Unused)
P15
V12
12V power (Unused)
Device Activity Signal / Disable Staggered Spin up
NOTE :
Uses 5V power only. 3.3V and 12V power are not used.
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Rev. 1.0
datasheet
840 PRO Series
5.0 Command Descriptions
5.1 Supported ATA Commands
Command Name
Command Code
(Hex)
Command Name
Command Code
(Hex)
CHECK POWER MODE
E5h
SLEEP
E6h
DATA SET MANAGEMENT
06h
SMART
B0h
DOWNLOAD MICROCODE
92h
STANDBY
E2h
DOWNLOAD MICROCODE DMA
93h
STANDBY IMMEDIATE
E0h
EXECUTE DEVICE DIAGNOSTIC
90h
WRITE BUFFER
E8h
FLUSH CACHE
E7h
WRITE DMA
CAh
FLUSH CACHE EXT
EAh
WRITE DMA EXT
35h
IDENTIFY DEVICE
ECh
WRITE DMA FUA EXT
3Dh
IDLE
E3h
WRITE DMA WITHOUT RETRY
CBh
IDLE IMMEDIATE
E1h
WRITE FPDMA QUEUED
61h
INITIALIZE DEVICE PARAMETERS
91h
WRITE LOG DMA EXT
57h
NOP
00h
WRITE LOG EXT
3Fh
READ BUFFER
E4h
WRITE MULTIPLE
C5h
READ BUFFER DMA
E9h
WRITE MULTIPLE EXT
39h
READ DMA
C8h
WRITE MULTIPLE FUA EXT
CEh
READ DMA EXT
25h
WRITE SECTORS
30h
READ DMA WITHOUT RETRIES
C9h
WRITE SECTORS EXT
34h
READ FPDMA QUEUED
60h
WRITE SECTORS WITHOUT RETRY
31h
READ LOG DMA EXT
47h
WRITE UNCORRECTABLE EXT
45h
READ LOG EXT
2Fh
READ MULTIPLE
C4h
READ MULTIPLE EXT
29h
READ NATIVE MAX ADDRESS
F8h
READ NATIVE MAX ADDRESS EXT
27h
READ SECTORS
20h
READ SECTORS EXT
24h
READ SECTORS WITHOUT RETRY
21h
READ VERIFY SECTORS
40h
READ VERIFY SECTORS EXT
42h
READ VERIFY SECTORS WITHOUT RETRY
41h
RECEIVE FPDMA QUEUED
65h
SECURITY DISABLE PASSWORD
F6h
SECURITY ERASE PREPARE
F3h
SECURITY ERASE UNIT
F4h
SECURITY FREEZE LOCK
F5h
SECURITY SET PASSWORD
F1h
SECURITY UNLOCK
F2h
SEEK
70h
SEND FPDMA QUEUED
64h
SET MAX ADDRESS
F9h
SET MAX ADDRESS EXT
37h
SET MULTIPLE MODE
C6h
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5.2 SECURITY FEATURE Set
The Security mode features allow the host to implement a security password system to prevent unauthorized access to the disk drive.
5.2.1 SECURITY mode default setting
The 840 PRO is shipped with master password set to 20h value (ASCII blanks) and the lock function disabled.
The system manufacturer/dealer may set a new master password by using the SECURITY SET PASSWORD command, without enabling the lock function.
5.2.2 Initial setting of the user password
When a user password is set, the drive automatically enters lock mode after the next power cycle.
5.2.3 SECURITY mode operation from power-on
In locked mode, the 840 PRO rejects media access commands until a SECURITY UNLOCK command is successfully completed.
5.2.4 Lost Password
If the user password is lost and High level security is set, the drive does not allow the user to access any data.
However, the drive can be unlocked using the master password.
If the user password is lost and Maximum security level is set, it is impossible to access data.
However, the drive can be unlocked using the ERASE UNIT command with the master password. The drive will erase all user data and unlock the drive.
5.3 SMART FEATURE Set (B0h)
The SMART Feature Set command provides access to the Attribute Values, the Attribute Thresholds, and other low level sub-commands that can be used
for logging and reporting purposes and to accommodate special user needs. The SMART Feature Set command has several separate sub-commands
which are selectable via the device's Features Register when the SMART Feature Set command is issued by the host. In order to select a sub-command
the host must write the sub-command code to the device's Features Register before issuing the SMART Feature Set command.
5.3.1 Sub Command
In order to select a sub-command the host must write the sub-command code to the device's Features Register before issuing the S.M.A.R.T. Function
Set command. The sub-commands and their respective codes are listed below.
Sub-command
Code
SMART READ DATA
D0h
sub-command
Code
SMART WRITE LOG
D6h
SMART READ ATTRIBUTE THRESHOLDS
D1h
SMART ENABLE OPERATIONS
D8h
SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE
D2h
SMART DISABLE OPERATIONS
D9h
SMART SAVE ATTRIBUTE VALUES
D3h
SMART RETURN STATUS
DAh
SMART EXECUTE OFF-LINE IMMIDIATE
D4h
SMART ENABLE/ DISABLE AUTOMATIC OFF-LINE
DBh
SMART READ LOG
D5h
5.3.1.1 S.M.A.R.T. Read Attribute Values (sub-command D0h)
This sub-command returns the device's Attribute Values to the host. Upon receipt of the S.M.A.R.T. Read Attribute Values sub-command from the host,
the device asserts BSY, saves any updated Attribute Values to the Attribute Data sectors, asserts DRQ, clears BSY, asserts INTRQ, and then waits for the
host to transfer the 512 bytes of Attribute Value information from the device via the Data Register.
5.3.1.2 S.M.A.R.T. Read Attribute Thresholds (sub-command D1h)
This sub-command returns the device's Attribute Thresholds to the host. Upon receipt of the S.M.A.R.T. Read Attribute Thresholds sub-command from
the host, the device reads the Attribute Thresholds from the Attribute Threshold sectors and then waits for the host to transfer the 512 bytes of Attribute
Thresholds information from the device.
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5.3.1.3 S.M.A.R.T. Enable/Disable Attribute Autosave (sub-command D2h)
This sub-command enables and disables the attribute auto save feature of the device. The S.M.A.R.T. Enable/Disable Attribute Autosave sub-command
allows the device to automatically save its updated Attribute Values to the Attribute Data Sector at the timing of the first transition to Active idle mode and
after 15 minutes after the last saving of Attribute Values. This sub-command causes the auto save feature to be disabled. The state of the Attribute Autosave feature—either enabled or disabled—will be preserved by the device across the power cycle.
A value of 00h—written by the host into the device's Sector Count Register before issuing the S.M.A.R.T. Enable/Disable Attribute Autosave sub-command—will cause this feature to be disabled. Disabling this feature does not preclude the device from saving Attribute Values to the Attribute Data sectors
during some other normal operation such as during a power-up or a power-down.
A value of F1h—written by the host into the device's Sector Count Register before issuing the S.M.A.R.T. Enable/Disable Attribute Autosave sub-command—will cause this feature to be enabled. Any other nonzero value written by the host into this register before issuing the S.M.A.R.T. Enable/Disable
Attribute Autosave sub-command will not change the current Autosave status. The device will respond with the error code specified in Table 7-9:
“S.M.A.R.T. Error Codes” on page 30.
The S.M.A.R.T. Disable Operations sub-command disables the auto save feature along with the device's S.M.A.R.T. operations.
Upon the receipt of the sub-command from the host, the device asserts BSY, enables or disables the Autosave feature, clears BSY, and asserts INTRQ.
5.3.1.4 S.M.A.R.T. Save Attribute Values (sub-command D3h)
This sub-command causes the device to immediately save any updated Attribute Values to the device's Attribute Data sector regardless of the state of the
Attribute Autosave feature. Upon receipt of the S.M.A.R.T. Save Attribute Values sub-command from the host, the device asserts BSY, writes any updated
Attribute Values to the Attribute Data sector, clears BSY, and asserts INTRQ.
5.3.1.5 S.M.A.R.T. Execute Off-line Immediate (sub-command D4h)
This sub-command causes the device to immediately initiate the set of activities that collect Attribute data in an offline mode (off-line routine) or execute a
self-test routine in either captive or off-line mode. The LBA Low register shall be set to specify the operation to be executed.
LBA Low
Sub-command
00h
Execute S.M.A.R.T. off-line data collection routine immediately
01h
Execute S.M.A.R.T. Short self-test routine immediately in off-line mode
02h
Execute S.M.A.R.T. Extended self-test routine immediately in off-line mode
03h
Reserved
04h
Execute S.M.A.R.T. Selective self-test routine immediately in off-line mode
40h
Reserved
7Fh
Abort off-line mode self-test routine
81h
Execute S.M.A.R.T. short self-test routine immediately in captive mode
82h
Execute S.M.A.R.T. Extended self-test routine immediately in captive mode
84h
Execute S.M.A.R.T. selective self-test routine immediately in captive mode
C0h
Reserved
Off-line mode: The device executes command completion before executing the specified routine. During execution of the routine the device will not set BSY nor clear DRDY. If
the device is in the process of performing its routine and is interrupted by a new command from the host, the device will abort or suspend its routine and service the host within
two seconds after receipt of the new command. After servicing the interrupting command, the device will resume its routine automatically or not start its routine depending on
the interrupting command.
Captive mode: When executing self-test in captive mode, the device sets BSY to one and executes the specified self-test routine after receipt of the command. At the end of
the routine, the device sets the execution result in the Self-test execution status byte (see Table 7-1: “Device Attribute Data Structure” on page 23) and ATA registers and then
executes the command completion. See definitions below.
Status
Set ERR to one when the self-test has failed
Error
Set ABRT to one when the self-test has failed
LBA Low
Set to F4h when the self-test has failed
LBA High
Set to 2Ch when the self-test has failed
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5.3.1.6 S.M.A.R.T. Selective self-test routine
When the value in the LBA Low register is 4 or 132, the Selective self-test routine shall be performed. This self-test routine shall include the initial tests
performed by the Extended self-test routine plus a selectable read scan. The host shall not write the Selective self-test log while the execution of a Selective self-test command is in progress.
The user may choose to do read scan only on specific areas of the media. To do this, user shall set the test spans desired in the Selective self-test log and
set the flags in the Feature flags field of the Selective self-test log to indicate do not perform off-line scan. In this case, the test spans defined shall be read
scanned in their entirety. The Selective self-test log is updated as the self-test proceeds indicating test progress. When all specified test spans have been
completed, the test is terminated and the appropriate self-test execution status is reported in the SMART READ DATA response depending on the occurrence of errors. Figure on page 21 shows an example of a Selective self-test definition with three test spans defined. In this example, the test terminates
when all three test spans have been scanned.
After the scan of the selected spans described above, a user may wish to have the rest of media read scanned as an off-line scan. In this case, the user
shall set the flag to enable off-line scan in addition to the other settings. If an error occurs during the scanning of the test spans, the error is reported in the
self-test execution status in the SMART READ DATA response and the off-line scan is not executed. When the test spans defined have been scanned,
the device shall then set the offline scan pending and active flags in the Selective self-test log to one, the span under test to a value greater than five, the
self-test execution status in the SMART READ DATA response to 00h, set a value of 03h in the off-line data collection status in the SMART READ DATA
response and shall proceed to do an off-line read scan through all areas not included in the test spans. This off-line read scan shall completed as rapidly
as possible, no pauses between block reads, and any errors encountered shall not be reported to the host. Instead error locations may be logged for
future reallocation. If the device is powered-down before the off-line scan is completed, the off-line scan shall resume when the device is again powered
up. From power-up, the resumption of the scan shall be delayed the time indicated in the Selective self-test pending time field in the Selective self-test log.
During this delay time the pending flag shall be set to one and the active flag shall be set to zero in the Selective self-test log. Once the time expires, the
active flag shall be set to one, and the off-line scan shall resume. When the entire media has been scanned, the off-line scan shall terminate, both the
pending and active flags shall be cleared to zero, and the off-line data collection status in the SMART READ DATA response shall be set to 02h indicating
completion.
During execution of the Selective self-test, the self-test executions time byte in the Device SMART Data Structure may be updated but the accuracy may
not be exact because of the nature of the test span segments. For this reason, the time to complete off-line testing and the self-test polling times are not
valid. Progress through the test spans is indicated in the selective self-test log.
A hardware or software reset shall abort the Selective self-test except when the pending bit is set to one in the Selective self-test log (see 7.3.7). The
receipt of a SMART EXECUTE OFF-LINE IMMEDIATE command with 0Fh, Abort off-line test routine, in the LBA Low register shall abort Selective selftest regardless of where the device is in the execution of the command. If a second self-test is issued while a selective self-test is in progress, the selective self-test is aborted and the newly requested self-test is executed.
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5.3.1.7 S.M.A.R.T. Read Log Sector (sub-command D5h)
This command returns the indicated log sector contents to the host. Sector count specifies the number of sectors to be read from the specified log. The
log transferred by the drive shall start at the first sector in the specified log, regardless of the sector count requested. Sector number indicates the log sector to be returned as described in the following Table.
Log sector address
Content
00h
Log directory
RO
01h
SMART error log
RO
02h
Comprehensive SMART error log
RO
Reserved
RO
06h
SMART self-test log
RO
08h
Reserved
RO
04h-05h
09h
Selective self-test log
RW
Reserved
RO
80h-9Fh
Host vendor specific
R/W
A0h-FFh
Reserved
VS
0Ah-7Fh
RO - Log is read only by the host.
R/W - Log is read or written by the host.
VS - Log is vendor specific thus read/write ability is vendor specific.
5.3.1.8 S.M.A.R.T. Write Log Sector (sub-command D6h)
This command writes 512 bytes of data to the specified log sector. The 512 bytes of data are transferred at a command and the LBA Low value shall be
set to one. The LBA Low shall be set to specify the log sector address. If a Rea Only log sector is specified, the device returns ABRT error.
5.3.1.9 S.M.A.R.T. Enable Operations (sub-command D8h)
This sub-command enables access to all S.M.A.R.T. capabilities within the device. Prior to receipt of a S.M.A.R.T. Enable Operations sub-command, Attribute Values are neither monitored nor saved by the device. The state of S.M.A.R.T.—either enabled or disabled—will be preserved by the device across
power cycles. Once enabled, the receipt of subsequent S.M.A.R.T. Enable Operations sub-commands will not affect any of the Attribute Values. Upon
receipt of the S.M.A.R.T. Enable Operations sub-command from the host, the device asserts BSY, enables S.M.A.R.T. capabilities and functions, clears
BSY, and asserts INTRQ.
5.3.1.10 S.M.A.R.T. Disable Operations (sub-command D9h)
This sub-command disables all S.M.A.R.T. capabilities within the device including the device's attribute auto save feature. After receipt of this sub-command the device disables all S.M.A.R.T. operations. Non self-preserved Attribute Values will no longer be monitored. The state of S.M.A.R.T.—either
enabled or disabled—is preserved by the device across power cycles. Note that this sub-command does not preclude the device's power mode attribute
auto saving.
Upon receipt of the S.M.A.R.T. Disable Operations sub-command from the host, the device asserts BSY, disables S.M.A.R.T. capabilities and functions,
clears BSY, and asserts INTRQ.
After receipt of the device of the S.M.A.R.T. Disable Operations sub-command from the host, all other S.M.A.R.T. sub-commands—with the exception of
S.M.A.R.T. Enable Operations—are disabled, and invalid and will be aborted by the device—including the S.M.A.R.T. Disable Operations sub-command— returning the error code as specified in Table 7-9: “S.M.A.R.T. Error Codes” on page 30.
Any Attribute Values accumulated and saved to volatile memory prior to receipt of the S.M.A.R.T. Disable Operations command will be preserved in the
device's Attribute Data Sectors. If the device is re-enabled, these Attribute Values will be updated, as needed, upon receipt of a S.M.A.R.T. Read Attribute
Values or a S.M.A.R.T. Save Attribute Values command.
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5.3.1.11 S.M.A.R.T. Return Status (sub-command DAh)
This sub-command is used to communicate the reliability status of the device to the host's request. Upon receipt of the S.M.A.R.T. Return Status subcommand the device asserts BSY, saves any updated Attribute Values to the reserved sector, and compares the updated Attribute Values to the Attribute
Thresholds.
If the device does not detect a Threshold Exceeded Condition, or detects a Threshold Exceeded Condition but involving attributes are advisory, the device
loads 4Fh into the LBA Mid register, C2h into the LBA High register, clears BSY, and asserts INTRQ.
If the device detects a Threshold Exceeded Condition for pre failure attributes, the device loads F4h into the LBA Mid register, 2Ch into the LBA High register, clears BSY, and asserts INTRQ. Advisory attributes never result in a negative reliability condition.
5.3.1.12 S.M.A.R.T. Enable/Disable Automatic Off-line (sub-command DBh)
This sub-command enables and disables the optional feature that cause the device to perform the set of off-line data collection activities that automatically collect attribute data in an off-line mode and then save this data to the device's nonvolatile memory. This sub-command may either cause the device
to automatically initiate or resume performance of its off-line data collection activities or cause the automatic off-line data collection feature to be disabled.
This sub-command also enables and disables the off-line read scanning feature that cause the device to perform the entire read scanning with defect
reallocation as the part of the off-line data collection activities.
The Sector Count register shall be set to specify the feature to be enabled or disabled:
Sector Count
00h
F8h
Feature Description
Disable Automatic Off-line
Enable Automatic Off-line
A value of zero written by the host into the device's Sector Count register before issuing this sub-command shall cause the automatic off-line data collection feature to be disabled. Disabling this feature does not preclude the device from saving attribute values to nonvolatile memory during some other normal operation such as during a power-on, during a power-off sequence, or during an error recovery sequence.
A value of F8h written by the host into the device's Sector Count register before issuing this sub-command shall cause the automatic Off-line data collection feature to be enabled.
Any other non-zero value written by the host into this register before issuing this sub-command is vendor specific and will not change the current Automatic Off-Line Data Collection and Off-line Read Scanning status. However, the device may respond with the error code specified in Table 7-9:
“S.M.A.R.T. Error Codes” on page 30.
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5.3.2 Device Attribute Data Structure
The following defines the 512 bytes that make up the Attribute Value information. This data structure is accessed by the host in its entirety using the
S.M.A.R.T. Read Attribute Values sub-command.
Byte
Descriptions
0~1
Data structure revision number
2~361
1st - 30th Individual attribute data
362
Off-line data collection status
363
Self-test execution status
364~365
Total time in seconds to complete off-line data collection activity
366
Vendor Specific
367
Off-line data collection capability
368-369
SMART capability
370
Error logging capability
7-1
Reserved
0
1=Device error logging supported
371
Self-test failure check point
372
Short self-test routine recommended polling time (in minutes)
373
Extended self-test routine recommended polling time (in minutes)
374-510
Reserved
511
Data structure checksum
[Table 7-1] Device Attribute Data Structure
5.3.2.1 Data Structure Revision Number
The Data Structure Revision Number identifies which version of this data structure is implemented by the device.
This revision number will be set to 0005h. This revision number identifies both the Attribute Value and Attribute
Threshold Data structures.
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5.3.2.2 Individual Attribute Data Structure
The following defines the 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure.
Byte
0
Descriptions
Attribute ID number 01-FFh
Status flag
bit 0 (pre-failure/advisory bit)
bit 0 = 0 : If attribute value is less than the threshold, the drive is in advisory condition.
Product life period may expired.
bit 0 = 1 : If attribute value is less than the threshold, the drive is in pre-failure condition.
The drive may have failure.
bit 1 (on-line data collection bit)
bit 1 = 0 : Attribute value will be changed during off-line data collection operation.
bit 1 = 1 : Attribute value will be changed during normal operation.
bit 2 (Performance Attribute bit)
bit 3 (Error rate Attribute bit)
bit 4 (Event Count Attribute bit)
bit 5 (Self-Preserving Attribute bit)
bit 6-15 Reserved
Attribute value 01h-FDh *1
00h, FEh, FFh = Not in use
01h = Minimum value
64h = Initial value
Fdh = Maximum value
1~2
3
4
Worst Ever normalized Attribute Value
(valid values from 01h-FEh)
5~10
Raw Attribute Value
Attribute specific raw data
(FFFFFFh - reserved as saturated value)
11
Reserved (00h)
*1 For ID = 199 CRC Error Count
Attribute ID Numbers: Any non zero value in the Attribute ID Number indicates an active attribute. The device supports following Attribute ID Numbers.
The names marked with (*) indicate that the corresponding Attribute Values is fixed value for compatibility.
ID
5
9
12
177
179
181
182
183
187
190
195
199
235
241
Attribute Name
Reallocated Sector Count
Power-on Hours
Power-on Count
Wear Leveling Count
Used Reserved Block Count (total)
Program Fail Count (total)
Erase Fail Count (total)
Runtime Bad Count (total)
Uncorrectable Error Count
Airflow Temperature
ECC Error Rate
CRC Error Count
POR Recovery Count
Total LBA Written
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5.3.2.3 Off-Line Data Collection Status
The value of this byte defines the current status of the off-line activities of the device. Bit 7 indicates an Automatic Off-line Data Collection Status.
Bit 7 Automatic Off-line Data Collection Status
0
Automatic Off-line Data Collection is disabled.
1
Automatic Off-line Data Collection is enabled.
Bits 0–6 represent a hexadecimal status value reported by the device.
Value
Definition
0
Off-line data collection never started.
2
All segments completed without errors. In this case the current segment pointer is equal to the total segments required.
3
Off-line activity in progress.
4
Off-line data collection is suspended by the interrupting command.
5
Off-line data collecting is aborted by the interrupting command.
6
Off-line data collection is aborted with a fatal error.
5.3.2.4 Self-test execution status
Bit
0-3
4-7
Definition
Percent Self-test remaining. An approximation of the percent of the self-test routine remaining until completion given in ten
percent increments. Valid values are 0 through 9.
Current Self-test execution status.
0
The self-test routine completed without error or has never been run.
1
The self-test routine was aborted by the host.
2
The self-test routine was interrupted by the host with a hard or soft reset.
3
The device was unable to complete the self-test routine due to a fatal error or unknown test error.
4
The self-test routine was completed with an unknown element failure.
5
The self-test routine was completed with an electrical element failure.
6
The self-test routine was completed with a servo element failure.
7
The self-test routine was completed with a read element failure.
15
The self-test routine is in progress.
5.3.2.5 Total time in seconds to complete off-line data collection activity
This field tells the host how many seconds the device requires to complete the off-line data collection activity.
5.3.2.6 Current segment pointer
This byte is a counter indicating the next segment to execute as an off-line data collection activity. Because the number of segments is 1, 01h is always
returned in this field.
5.3.2.7 Off-line data collection capability
Bit
0
1
2
3
4
5
6
7
Definition
Execute Off-line Immediate implemented bit
0 S.M.A.R.T. Execute Off-line Immediate sub-command is not implemented
1 S.M.A.R.T. Execute Off-line Immediate sub-command is implemented
Enable/disable Automatic Off-line implemented bit
0 S.M.A.R.T. Enable/disable Automatic Off-line sub-command is not implemented
1 S.M.A.R.T. Enable/disable Automatic Off-line sub-command is implemented
Abort/restart off-line by host bit
0
The device will suspend off-line data collection activity after an interrupting command and resume it after a vendor
specific event
1 The device will abort off-line data collection activity upon receipt of a new command Bit Definition
Off-line Read Scanning implemented bit
0 The device does not support Off-line Read Scanning
1 The device supports Off-line Read Scanning
Self-test implemented bit
0 Self-test routing is not implemented
1 Self-test routine is implemented
Reserved (0)
Selective self-test routine is not implemented
0 Selective self-test routine is not implemented
1 Selective self-test routine is implemented
Reserved (0)
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840 PRO Series
5.3.2.8 S.M.A.R.T. Capability
This word of bit flags describes the S.M.A.R.T. capabilities of the device. The device will return 03h indicating that the device will save its Attribute Values
prior to going into a power saving mode and supports the S.M.A.R.T. ENABLE/DISABLE ATTRIBUTE AUTOSAVE command.
Bit
Definition
0
Pre-power mode attribute saving capability. If bit = 1, the device will save its Attribute Values prior to going into a power
saving mode (Standby or Sleep mode).
1
Attribute auto save capability. If bit = 1, the device supports the S.M.A.R.T. ENABLE/ DISABLE ATTRIBUTE AUTOSAVE
command.
2-15
Reserved (0)
5.3.2.9 Error logging capability
Bit
7-1
0
Definition
Reserved (0)
The Error Logging support bit. If bit = 1, the device supports the Error Logging
5.3.2.10 Self-test failure check point
This byte indicates the section of self-test where the device detected a failure.
5.3.2.11 Self-test completion time
These bytes are the minimum time in minutes to complete the self-test.
5.3.2.12 Data Structure Checksum
The Data Structure Checksum is the 2's compliment of the result of a simple 8-bit addition of the first 511 bytes in the data structure.
5.3.3 Device Attribute Thresholds data structure
The following defines the 512 bytes that make up the Attribute Threshold information. This data structure is accessed by the host in its entirety using the
S.M.A.R.T. Read Attribute Thresholds. All multi byte fields shown in these data structures follow the ATA/ATAPI-6 specification for byte ordering, that is,
that the least significant byte occupies the lowest numbered byte address location in the field.
The sequence of active Attribute Thresholds will appear in the same order as their corresponding Attribute Values.
Byte
0~1
2~361
362 ~ 379
380 ~ 510
511
Descriptions
Data structure revision number
1st - 30th Individual attribute data
Reserved
Vendor specific
Data structure checksum
[Table 7-2] Device Attribute Thresholds Data Structure
5.3.3.1 Data Structure Revision Number
This value is the same as the value used in the Device Attributes Values Data Structure.
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5.3.3.2 Individual Thresholds Data Structure
The following defines the 12 bytes that make up the information for each Threshold entry in the Device Attribute Thresholds Data Structure. Attribute
entries in the Individual Threshold Data Structure are in the same order and correspond to the entries in the Individual Attribute Data Structure.
Byte
Descriptions
0
Attribute ID Number (01h to FFh)
1
Attribute Threshold (for comparison with Attribute Values from 00h to FFh)
00h - "always passing" threshold value to be used for code test purposes
01h - minimum value for normal operation
FDh - maximum value for normal operation
FEh - invalid for threshold value
FFh - "always failing" threshold value to be used for code test purposes
2~11
Reserved (00h)
5.3.3.3 Attribute ID Numbers
Attribute ID Numbers supported by the device are the same as Attribute Values Data Structures.
5.3.3.4 Attribute Threshold
These values are preset at the factory and are not meant to be changeable. However, the host might use the "S.M.A.R.T. Write Attribute Threshold" subcommand to override these preset values in the Threshold sectors.
5.3.3.5 Data Structure Checksum
The Data Structure Checksum is the 2's compliment of the result of a simple 8-bit addition of the first 511 bytes in the data structure.
5.3.4 S.M.A.R.T. Log Directory
The following defines the 512 bytes that make up the S.M.A.R.T. Log Directory. The S.M.A.R.T. Log Directory is on S.M.A.R.T. Log Address zero and is
defined as one sector long.
Byte
0~1
Descriptions
S.M.A.R.T. Logging Version
2
Number of sectors in the log at log address 1
3
Reserved
4
Number of sectors in the log at log address 2
5
Reserved
...
510
Number of sectors in the log at log address 255
511
Reserved
[Table 7-3] S.M.A.R.T. Log Directory
The value of the S.M.A.R.T. Logging Version word shall be 01h. The logs at log addresses 80-9Fh are defined as 16 sectors long.
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5.3.5 S.M.A.R.T. error log sector
The following defines the 512 bytes that make up the S.M.A.R.T. error log sector. All multibyte fields shown in these data structures follow the ATA/ATAPI6 specifications for byte ordering.
Byte
Descriptions
0
S.M.A.R.T. error log version
1
Error log pointer
2-91
1st error log data structure
92-181
2nd error log data structure
182-271
3rd error log data structure
272-361
4th error log data structure
362-451
5th error log data structure
452-453
Device error count
454-510
Reserved
511
Data structure checksum
[Table 7-4] S.M.A.R.T. error log sector
5.3.5.1 S.M.A.R.T. error log version
This value is set to 01h.
5.3.5.2 Error log pointer
This points to the most recent error log data structure. Only values 1 through 5 are valid.
5.3.5.3 Device error count
This field contains the total number of errors. The value will not roll over.
5.3.5.4 Error log data structure
The data format of each error log structure is shown below.
Byte
Descriptions
n ~ n+11
1st command data structure
n+12 ~ n+23
2nd command data structure
n+24 ~ n+35
3rd command data structure
n+36 ~ n+47
4th command data structure
n+48 ~ n+59
5th command data structure
n+60 ~ n+89
Error data structure
[Table 7-5] Error log data structure
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5.3.5.5 Command data structure
Data format of each command data structure is shown below.
Byte
Descriptions
n
Content of the Device Control register when the Command register was written
n+1
Content of the Features Control register when the Command register was written
n+2
Content of the Sector Count Control register when the Command register was written
n+3
Content of the LBA Low register when the Command register was written
n+4
Content of the LBA Mid register when the Command register was written
n+5
Content of the LBA High register when the Command register was written
n+6
Content of the Device/Head register when the Command register was written
n+7
Content written to the Command register
n+8
Timestamp
n+9
Timestamp
n+10
Timestamp
n+11
Timestamp
[Table 7-6] Command data structure
Timestamp shall be the time since power-on in milliseconds when command acceptance occurred. This timestamp may wrap around.
5.3.5.6 Error data structure
Data format of error data structure is shown below.
Byte
Descriptions
n
Reserved
n+1
Content written to the Error register after command completion occurred.
n+2
Content written to the Sector Count register after command completion occurred.
n+3
Content written to the LBA Low register after command completion occurred.
n+4
Content written to the LBA Mid register after command completion occurred.
n+5
Content written to the LBA High register after command completion occurred.
n+6
Content written to the Device/Head register after command completion occurred.
n+7
Content written to the Status register after command completion occurred.
n+8 - n+26
Extended error information
n+27
State
n+28
Life Timestamp (least significant byte)
n+29
Life Timestamp (most significant byte)
[Table 7-7] Error data structure
Extended error information will be vendor specific.
State field contains a value indicating the device state when command was issued to the device.
Value
State
x0h
Unknown
x1h
Sleep
x2h
Standby
x3h
Active/Idle with BSY cleared to zero
x4h
Executing SMART off-line or self-test
x5h-xAh
Reserved
xBh-xFh
Vendor unique
The value of x is vendor specific and may be different for each state.
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5.3.6 Self-test log structure
The following defines the 512 bytes that make up the Self-test log sector.
Byte
Byte
0~1
Data structure revision
n*24+2
Self-test number
n*24+3
Self-test execution status
n*24+4~n*24+5
Life timestamp
n*24+6
Self-test failure check point
n*24+7~n*24+10
LBA of first failure
n*24+11~n*24+25
Vendor specific
...
...
506~507
Vendor specific
508
Self-test log pointer
509~510
Reserved
511
Data structure checksum
[Table 7-8] Self-test log data structure
NOTE :
N is 0 through 20
The data structure contains the descriptor of the Self-test that the device has performed. Each descriptor is 24 bytes long and the self-test data structure is capable to contain
up to 21 descriptors. After 21 descriptors has been recorded, the oldest descriptor will be overwritten with the new descriptor. The self-test log pointer points to the most recent
descriptor. When there is no descriptor, the value is 0. When there are descriptor(s), the value is 1 through 21.
5.3.7 Selective self-test log data structure
The Selective self-test log is a log that may be both written and read by the host. This log allows the host to select the parameters for the self-test and to
monitor the progress of the self-test. The following table defines the contents of the Selective self-test log which is 512 bytes long. All multi-byte fields
shown in these data structures follow the specifications for byte ordering.
Byte
0-1
Description
Read/Write
Data structure revision
R/W
2-9
Starting LBA for test span 1
R/W
10-17
Ending LBA for test span 1
R/W
18-25
Starting LBA for test span 2
R/W
26-33
Ending LBA for test span 2
R/W
34-41
Starting LBA for test span 3
R/W
42-49
Ending LBA for test span 3
R/W
50-57
Starting LBA for test span 4
R/W
58-65
Ending LBA for test span 4+
R/W
66-73
Starting LBA for test span 5
R/W
74-81
Ending LBA for test span 5
R/W
82-337
Reserved
Reserved
338-491
Vendor specific
Vendor specific
492-499
Current LBA under test
Read
500-501
Current span under test
Read
502-503
Feature flags
R/W
504-507
Vendor Specific
Vendor specific
508-509
Selective self-test pending time
R/W
510
Reserved
Reserved
511
Data structure checksum
R/W
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Rev. 1.0
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840 PRO Series
5.3.8 Error reporting
The following table shows the values returned in the Status and Error Registers when specific error conditions are encountered by a device.
Error condition
Status Register
Error Register
A S.M.A.R.T. FUNCTION SET command was received by the device without the required key being
loaded into the LBA High and LBA Mid registers.
51h
04h
A S.M.A.R.T. FUNCTION SET command was received by the device with a sub-command value in the
Features Register that is either invalid or not supported by this
device.
51h
04h
A S.M.A.R.T. FUNCTION SET command sub-command other than S.M.A.R.T. ENABLE OPERATIONS
was received by the device while the device was in a "S.M.A.R.T. Disabled" state.
51h
04h
The device is unable to read its Attribute Values or Attribute Thresholds data structure
51h
10h or 04h
The device is unable to write to its Attribute Values data structure.
51h
10h or 40h
[Table 7-9] SMART Error Codes
6.0 SATA II Optional Feature
6.1 Power Segment Pin P11
Pin P11 of the power segment of the device connector may be used by the device to provide the host with an activity indication and it may be used by the
host to indicate whether staggered spinup should be used. To accomplish both of these goals, pin P11 acts as an input from the host to the device prior to
PHYRDY for staggered spin-up control and then acts as an output from the device to the host after PHYRDY for activity indication. The activity indication
provided by pin P11 is primarily for use in backplane applications.
A host may only support one pin P11 feature, either receiving activity indication or staggered spin-up disable control. If a host supports receiving activity
indication via pin P11, then the host shall not use pin P11 to disable staggered spin-up. If a host does not support receiving activity indication via pin P11,
then the host may use pin P11 to disable staggered spin-up.
6.2 Asynchronous Signal Recovery
Phys may support asynchronous signal recovery for those applications where the usage model of device insertion into a receptacle does not apply. When
signal is lost, both the host and the device may attempt to recover the signal. A host or device shall determine loss of signal as represented by a transition
from PHYRDY to PHYRDYn, which is associated with entry into states LSI: NoCommErr or LS2:NoComm within the Link layer. Note that negation of
PHYRDY does not always constitute a loss of signal. Recovery of the signal is associated with exit from state LS2:NoComm. If the device attempts to
recover the signal before the host by issuing a COMINIT, the device shall return its signature following completion of the OOB sequence which included
COMINIT. If a host supports asynchronous signal recovery, when the host receives an unsolicited COMINIT, the host shall issue a COMRESET to the
device. When a COMRESET is sent to the device in response to an unsolicited COMINIT, the host shall set the Status register to 7Fh and shall set all
other Shadow Command Block Registers to FFh. When the COMINIT is received in response to the COMRESET which is associated with entry into state
HP2B:HR_AwaitNoCOMINIT, the Shadow Status register value shall be updated to either FFh or 80h to reflect that a device is attached.
- 24 -
MZ-7PD512
MZ-7PD256
MZ-7PD128
datasheet
7.0 Identify Device Data
Word
128GB
256GB
512GB
0
0040h
0040h
0040h
General information
Description
1
3FFFh
3FFFh
3FFFh
Obsolete
2
C837h
C837h
C837h
Specific configuration
3
0010h
0010h
0010h
Obsolete
4-5
0000h
0000h
0000h
Retired
6
003Fh
003Fh
003Fh
Obsolete
Reserved for the Compact Flash Association
7-8
0000h
0000h
0000h
9
0000h
0000h
0000h
Retired
10 -19
XXXXh
XXXXh
XXXXh
Serial Number (ATA string)
20 - 21
0000h
0000h
0000h
Retired
22
0000h
0000h
0000h
Obsolete
23 - 26
XXXXh
XXXXh
XXXXh
Firmware revision (ATA string)
27- 46
XXXXh
XXXXh
XXXXh
Model number
47
8010h
8010h
8010h
Number of sectors on multiple commands
48
4000h
4000h
4000h
Trusted Computing feature set options
49
2F00h
2F00h
2F00h
Capabilities
50
4000h
4000h
4000h
Capabilities
51 - 52
0200h
0200h
0200h
Obsolete
Field Validity
53
0007h
0007h
0007h
54
3FFFh
3FFFh
3FFFh
Obsolete
55
0010h
0010h
0010h
Obsolete
56
003Fh
003Fh
003Fh
Obsolete
57
FC10h
FC10h
FC10h
58
00FBh
00FBh
00FBh
Obsolete
59
F110h
F110h
F110h
60
C2B0h
FFFFh
FFFFh
Multiple sector setting
61
0EE7h
0FFFh
0FFFh
62
0000h
0000h
0000h
63
0007h
0007h
0007h
Multi-word DMA transfer
64
0003h
0003h
0003h
Flow control PIO transfer modes supported
Total number of user addressable logical sectors for 28-bit commands
65
0078h
0078h
0078h
Minimum Multi word DMA transfer cycle time per word
66
0078h
0078h
0078h
Manufacturer's recommended Multi word DMA transfer cycle time
67
0078h
0078h
0078h
Minimum PIO transfer cycle time without flow control
68
0078h
0078h
0078h
Minimum PIO transfer cycle time with IORDY flow control
69
4E30h
4E30h
4E30h
Additional supported
70-74
0000h
0000h
0000h
Reserved
75
001Fh
001Fh
001Fh
Queue depth
76
850Eh
850Eh
850Eh
Serial ATA capabilities
77
00C6h
00C6h
00C6h
Reserved for future Serial ATA definition
78
016Ch
016Ch
016Ch
Serial ATA features supported
79
0040h
0040h
0040h
Seral ATA features enabled
80
03FCh
03FCh
03FCh
Major version number
81
0039h
0039h
0039h
Minor version number
82
746Bh
746Bh
746Bh
Commands and feature sets supported
83
7D01h
7D01h
7D01h
Commands and feature sets supported
84
4163h
4163h
4163h
Commands and feature sets supported
Commands and feature sets supported or enabled
85
7469h
7469h
7469h
86
BC01h
BC01h
BC01h
Commands and feature sets supported or enabled
87
4163h
4163h
4163h
Commands and feature sets supported or enabled
88
407Fh
407Fh
407Fh
Ultra DMA transfer
- 25 -
Rev. 1.0
840 PRO Series
MZ-7PD512
MZ-7PD256
MZ-7PD128
Word
128GB
datasheet
256GB
512GB
Rev. 1.0
840 PRO Series
Description
89
0001h
0001h
0001h
Time required for Normal Erase mode SECURITY ERASE UNIT command
90
0001h
0001h
0001h
Time required for an Enhanced Erase mode SECURITY ERASE UNIT command
91
0000h
0000h
0000h
Current advanced power management value
92
FFFEh
FFFEh
FFFEh
Master Password Revision Code
93
0000h
0000h
0000h
Hardware reset result
94
0000h
0000h
0000h
Obsolete
95
0000h
0000h
0000h
Stream Minimum Request Size
96
0000h
0000h
0000h
Streaming Transfer Time - DMA
97
0000h
0000h
0000h
Streaming Access Latency - DMA and PIO
98-99
0000h
0000h
0000h
Streaming Performance Granularity (DWord)
100
C2B0h
32B0h
12B0h
Total Number of User Addressable Logical Sectors for 48-bit commands (QWord)
101
0EE7h
1DCFh
3B9Eh
Total Number of User Addressable Logical Sectors for 48-bit commands (QWord)
102-103
0000h
0000h
0000h
Total Number of User Addressable Logical Sectors for 48-bit commands (QWord)
104
0000h
0000h
0000h
Streaming Transfer Time - PIO
105
0008h
0008h
0008h
Maximum number of 512-byte data blocks of LBA Range Entries per DATA SET MANAGEMENT command
106
4000h
4000h
4000h
Physical sector size / logical sector size
107
0000h
0000h
0000h
Inter-seek delay for ISO 7779 standard acoustic testing
108
5002h
5002h
5002h
World wide name
109
5385h
5385h
5385h
World wide name
110
0000h
0000h
0000h
World wide name
111
0000h
0000h
0000h
World wide name
112-116
0000h
0000h
0000h
Reserved
117-118
0000h
0000h
0000h
Logical sector size (Dword)
119
401Eh
401Eh
401Eh
Commands and feature sets supported
120
401Ch
401Ch
401Ch
Commands and feature sets supported or enabled
121-126
0000h
0000h
0000h
Reserved for expanded supported and enabled settings
127
0000h
0000h
0000h
Obsolete
128
002Xh
002Xh
002Xh
Security status
129-159
0000h
0000h
0000h
Vendor specific
160
0000h
0000h
0000h
CFA power mode
161-167
0000h
0000h
0000h
Reserved for the Compact Flash Association
168
0000h
0000h
0000h
Reserved
DATA SET MANAGEMENT is supported
169
0001h
0001h
0001h
170-173
2020h
2020h
2020h
Additional Product Identifier (ATA string)
174-175
0000h
0000h
0000h
Reserved
176-205
0000h
0000h
0000h
Current media serial number (ATA string)
206
003Dh
003Dh
003Dh
SCT Command Transport
207-208
0000h
0000h
0000h
Reserved for CE-ATA
209
4000h
4000h
4000h
Alignment of logical blocks within a physical block
210-211
0000h
0000h
0000h
Write-Read-Verify Sector Count Mode 3
212-213
0000h
0000h
0000h
Write-Read-Verify Sector Count Mode 2
214-216
0000h
0000h
0000h
Obsolete
217
0001h
0001h
0001h
Nominal media rotation rate
218
0000h
0000h
0000h
Reserved
219
0000h
0000h
0000h
Obsolete
220-221
0000h
0000h
0000h
Write-Read Verify mode
222
107Fh
107Fh
107Fh
Transport major version number
223
0000h
0000h
0000h
Transport minor version number
224-229
0000h
0000h
0000h
Reserved
230-233
0000h
0000h
0000h
Extended Number of User Addressable Sectors
234
0000h
0000h
0000h
Minimum number of 512-byte data blocks per DOWNLOAD MICROCODE command for mode 03h
235
0800h
0800h
0800h
Maximum number of 512-byte data blocks per DOWNLOAD MICROCODE command for mode 03h
236-254
0000h
0000h
0000h
Reserved
255
XXXXh
XXXXh
XXXXh
Integrity word
- 26 -
MZ-7PD512
MZ-7PD256
MZ-7PD128
datasheet
Rev. 1.0
840 PRO Series
8.0 Product Line up
Model Name
Density
MZ-7PD128
128GB
Type
2.5" Drive only Packing
2.5" Bulk
MZ-7PD256
2.5" Drive only Packing
256GB
2.5" Bulk
MZ-7PD512
2.5" Drive only Packing
512GB
2.5" Bulk
- End of document -
- 27 -
Model Code
MZ-7PD128BW
MZ-7PD128B/KR
MZ-7PD128Z
MZ-7PD256BW
MZ-7PD256B/KR
MZ-7PD256Z
MZ-7PD512BW
MZ-7PD512B/KR
MZ-7PD512Z