21012v-dsh-001-a (2)

M21012V
Quad Multi-Rate Video Reclocker
(SD-SDI, HD-SDI, 2x HD-SDI interim device)
Data Sheet
21012V-DSH-001-A, 7/11/03
Mindspeed Technologies™
Preliminary Information
M21012V
Quad Multi-Rate Video Reclocker (SD-SDI, HD-SDI, 2x HD-SDI interim device)
Contents
Quad Multi-Rate Video Reclocker (SD-SDI, HD-SDI, 2x HD-SDI interim device). . . . . . . . . . . . . . . . . . . . . . 4
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 1. M21012V Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
M21012V Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 1: Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2: High-speed Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3: Control / Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. M21012V Pinout Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
General Specifications: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6: Power DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input/Output Level Specifications:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7: CMOS I/O Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8: High-Speed Input Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9: PCML (Positive Current Mode Logic) Output Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . 11
Table 10: LVPECL (Low Voltage Positive Emitter Coupled Logic) Output Electrical Specifications. . . . . . . 11
Table 11: Adaptive Input Equalization Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 12: Output Pre-Emphasis Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RCLK Performance Specifications: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 13: Reference Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 14: RCLK High-Speed Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 15: RCLK Output Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 16: RCLK Alarm Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
21012V-DSH-001-A, 7/11/03
Mindspeed Technologies™
Preliminary Information
Page 2 of 29
M21012V
Quad Multi-Rate Video Reclocker (SD-SDI, HD-SDI, 2x HD-SDI interim device)
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Internal Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
High-Speed I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 17: Output Interface and Level Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 18: Output Interface and Recommended AVDD_I/O Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RCLK Reference Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Multifunction Pins Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 19: Multifunction Pins Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Multifunction pins: Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Multifunction pins: JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 21: Multifunction Pins for JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 20: Multifunction Pins for Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
General Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input Deterministic Jitter Attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RCLK Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RCLK Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Multi-Rate RCLK Bit Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 22: Valid Input Data Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Interface Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 23: Register Table Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 24: Register Table Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
General and Global Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Individual RCLK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3. 68 Pin Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4. 72 Pin Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
21012V-DSH-001-A, 7/11/03
Mindspeed Technologies™
Preliminary Information
Page 3 of 29
M21012V
Quad Multi-Rate Video Reclocker (SD-SDI, HD-SDI, 2x HD-SDI interim device)
Key Features
• Four independent reclockers, each running between
143 Mbps and 3.0 Gbps
Applications
• Serial Digital Video Applications
(SD-SDI, HD-SDI, 2x HD-SDI)
•
Signal conditioning features for superior performance on
trace lengths of up to 60"
•
Video Routers
•
Video Editors
•
Input interface to CML, and LVPECL
•
Video Muxes/Demuxes
•
Typical Total Power Consumption as low as 405 mW with
all channels running
•
Video Repeaters
•
SMPTE 292M and 256M compliant
•
Cable Equalization
Product Description
The M21012V is a high-performance quad multi-rate video reclocker (RCLK) array, optimized for multi-lane video applications.
Each RCLK operates independently at bit rates between 143 Mbps and 3.0 Gbps, allowing maximum flexibility in system design.
Signal conditioning features include adaptive input equalization and output pre-emphasis, allowing robust reception and
transmission of signals to other devices up to 60" away.
User-selectable input interface types allow DC-coupled input to CML and LVPECL. The outputs can also be DC-coupled to CML
and LVPECL.
Frequency acquisition is accomplished with an external reference clock. The built-in frequency synthesizer allows multi-rate
operation, while operating with a single reference clock.
The device can be controlled through an I2C interface. The I2C interface allows complete control of the device features.
Ordering Information
Name
Number
Quad Multi-Rate Video Reclocker
(SD-SDI, HD-SDI, 2x HD-SDI interim device)
Package Data
M21012V-11P
72-terminal, 10 mm, MLF
Revision History
Revision
A
21012V-DSH-001-A, 7/11/03
Date
07/11/03
Comments
Original release.
Mindspeed Technologies™
Preliminary Information
Page 4 of 29
Cout0P/N
Cout1P/N
Cout2P/N
Cout3P/N
-
xRegu _En
Selectable CML,
LVPECL Output Buffer +
Pre- Emphasis
xJTAG _En
Voltage
Regulator
Dout0P/N
Dout1P/N
Dout2P/N
Dout3P/N
RefClkP/N
VddT0/1
Din3P/N
JTAG
RCLK Array
Din2P/N
Input Buffer
Din1P/N
VddT2/3
Din0P/N
Adapative Input Equalization
Multifunction Pin Array
Serial Interface
xLOL [3:0]
xRST
Out_Mode[1:0]
CTRL_Mode[1:0]
MF[11:0]
M21012V
Figure 1. M21012V Block Diagram
21012V-DSH-001-A, 7/11/03
Mindspeed Technologies™
Page 5 of 29
M21012V
M21012V Pin List
Table 1: Power Pins
Pin Name
Vss
AVDD_I/O
AVDD_Core
DVDD_I/O
DVDD_Core
Function
Type
Chip ground
Analog I/O positive supply
Analog core positive supply
Digital I/O positive supply
Digital core positive supply
Power
Power
Power
Power
Power
Notes:
1. If internal regulator is enabled, connect all of the AVDD_Core and/or DVDD_Core pins together to a common floating plane and bypass to Vss. If internal regulator
is NOT enabled, it is recommended that all AVDD_Core pins be tied to a plane at 1.2V, that is bypassed to ground. DVDD_Core can be tied to this plane or separately decoupled.
2. Chip ground (Vss) is not brought out to pins, it is brought out to paddle at the bottom of the package.
Table 2: High-speed Signal Pins
Pin Name
Function
Din0P/N
Din1P/N
Din2P/N
Din3P/N
VddT0/1
VddT2/3
Dout0P/N
Dout1P/N
Dout2P/N
Dout3P/N
Cout0P/N
Cout1P/N
Cout2P/N
Cout3P/N
Serial data input for RCLK 0
Serial data input for RCLK 1
Serial data input for RCLK 2
Serial data input for RCLK 3
Termination pin for Din0/1
Termination pin for Din2/3
Serial data output for RCLK 0
Serial data output for RCLK 1
Serial data output for RCLK 2
Serial data output for RCLK 3
Serial clock output for RCLK 0
Serial clock output for RCLK 1
Serial clock output for RCLK 2
Serial clock output for RCLK 3
Default
Type
50 Ω pull up to AVddT0/1
50 Ω pull up to AVddT0/1
50 Ω pull up to AVddT2/3
50 Ω pull up to AVddT2/3
Terminate to AVDD_I/O
Terminate to AVDD_I/O
50 Ω pull up to AVDD_I/O
50 Ω pull up to AVDD_I/O
50 Ω pull up to AVDD_I/O
50 Ω pull up to AVDD_I/O
50 Ω pull up to AVDD_I/O
50 Ω pull up to AVDD_I/O
50 Ω pull up to AVDD_I/O
50 Ω pull up to AVDD_I/O
I-CML/LVPECL
I-CML/LVPECL
I-CML/LVPECL
I-CML/LVPECL
Power
Power
O-CML/LVPECL
O-CML/LVPECL
O-CML/LVPECL
O-CML/LVPECL
O-CML/LVPECL
O-CML/LVPECL
O-CML/LVPECL
O-CML/LVPECL
Table 3: Control / Interface Pins
Pin Name
MF[11:0]
CTRL_Mode[1:0]
Out_Mode[1:0]
xRST
xJTAG_En
xRegu_En
RefClkP/N
xLOL[0]
xLOL[1]
xLOL[2]
xLOL[3]
21012V-DSH-001-A, 7/11/03
Function
Multifunction pins for serial interface, and JTAG
Enable serial interface
Selects output data format (00b = PCML)
Hardware reset (L = reset)
Enable JTAG testing blocks (L = enable). JTAG pins device of
MF
Enables built-in voltage regulator (L = enable)
Reference clock differential inputs
Loss of lock for RCLK 0 (L = LOL)
Loss of lock for RCLK 1 (L = LOL)
Loss of lock for RCLK 2 (L = LOL)
Loss of lock for RCLK 3 (L = LOL)
Mindspeed Technologies™
Default
Type
Internal pull up
Internal pull up
Internal pull down
Internal pull up
Internal pull up
I-CMOS
I-CMOS
I-CMOS
I-CMOS
I-CMOS
Internal pull down
Internal pull down
No internal pull up/down
No internal pull up/down
No internal pull up/down
No internal pull up/down
I-CMOS
I-AC Coupled
O-Open Drain
O-Open Drain
O-Open Drain
O-Open Drain
Page 6 of 29
Dout3N
Dout3P
AVDD_Core
Cout2N
AVDD_Core
Cout2P
Dout2N
Dout2P
AVDD_I/O
AVDD_I/O
Dout1N
Dout1P
AVDD_Core
Cout1N
Cout1P
AVDD_Core
Dout0N
Dout0P
M21012V
Cout0N
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1
54
2
53
Cout3P
Cout0P
3
52
Cout3N
MF[0]
4
51
MF[9]
MF[1]
5
50
MF[8]
AVDD_I/O
AVDD_I/O
CTRL_Mode[1]
9
46
N/C
DVDD_I/O
10
45
RefClkP
DVDD_Core
11
44
RefClkN
MF[10]
12
43
Out_Mode[1]
MF[4]
13
42
Out_Mode[0]
MF[5]
14
41
MF[7]
MF[6]
15
40
xRST
MF[11]
16
39
xLOL[3]
38
37
26 27 28 29 30 31 32 33 34 35 36
xLOL[2]
xLOL[1]
Din3N
Din1P
xRegu_En
VddT0/1
DVDD_Core
AVDD_Core
Din0P
xLOL[0]
17
18
19 20 21 22 23 24 25
Din0N
xJTAG_En
Din3P
N/C
AVDD_Core
47
DVDD_Core
8
VddT2/3
CTRL_Mode[0]
AVDD_I/O
N/C
Din2N
48
Din2P
7
AVDD_Core
49
MF[3]
AVDD_Core
6
N/C
Din1N
MF[2]
Figure 2. M21012V Pinout Diagram (Top View)
21012V-DSH-001-A, 7/11/03
Mindspeed Technologies™
Page 7 of 29
M21012V
General Specifications:
Table 4: Absolute Maximum Ratings
Symbol
Parameter
DVDD_I/O
AVDD_I/O
AVDD_Core2
DVDD_Core2
Tst
ESD
ESD
ESD
Digital I/O power
Analog I/O power
Analog core power
Digital core power
Storage temperature
Human body model (low-speed pins)
Human body model (high-speed pins)
Charged device model
Minimum
Maximum
Units
0
0
0
0
–65
1500
1000
150
3.6
3.6
1.5
1.5
+150
—
—
—
V
V
V
V
°C
V
V
V
Notes:
1. No damage.
2. Apply voltage to core pins only if internal regulator is disabled. If enabled, pins should be floating with by-pass to Vss.
Table 5: Recommended Operating Conditions
Parameter
DVDD_I/O: Digital I/O power
AVDD_I/O: Analog I/O power
AVDD_Core: Analog core power
DVDD_Core: Digital core power
Ambient temperature
Junction to ambient thermal resistance
Notes
Symbol
Minimum
Typical
Maximum
Units
3
3
1, 3
1, 3
2
2
DVDD_I/O
AVDD_I/O
AVDD_Core
DVDD_Core
Ta
θja
—
—
—
—
-40
—
1.8/2.5/3.3
1.8/2.5/3.3
1.2
1.2
—
24
—
—
—
—
85
—
V
V
V
V
C
C/W
Notes:
1. Only if AVDD_Core and DVDD_Core are provided from external source and internal regulator is disabled xRegu_En = H.
2. Based on preliminary evaluations.
3. Typical value +/- 5% is acceptable.
21012V-DSH-001-A, 7/11/03
Mindspeed Technologies™
Page 8 of 29
M21012V
Table 6: Power DC Electrical Specifications
Symbol
Idd
Pdiss
Pdiss
Idd_core
Idd_io
Pdiss
Pdiss
Idd
Pdiss
Idd
Pdiss
Parameter
Case 1: current consumption for output swing
= 500 mV CML, internal regulator = on, clock
outputs = off
Power dissipation at 1.8V
Power dissipation at 3.3V
Case 2: output swing = 500 mV CML,
internal regulator = off, clock outputs = off
Core current consumption
Input/Output buffers current consumption
Power dissipation at 1.2V core, 1.8V I/O
Power dissipation at 1.2V core, 3.3V I/O
Case 3: current consumption for output swing
= 1600 mV LVPECL, internal regulator = on,
clock outputs = off
Power dissipation at 3.3V
Case 4: current consumption for output swing
= 1600 mV LVPECL, internal regulator = on,
clock outputs = on
Power dissipation at 3.3V
Notes
Minimum
Typical
Maximum
Units
1
—
310
360
mA
—
—
—
—
560
1.0
650
1.2
mW
W
—
300
60
470
560
mA
mA
mW
mW
1
—
—
—
—
260
50
405
480
1
—
420
480
mA
2
—
1.4
1.6
W
1
—
610
700
mA
2
—
2.0
2.3
W
Notes:
1. Specified at recommended operating conditions – see Table 5.
2. Exceeds maximum permissible junction temperature at 85C ambient. Thermal design, such as airflow, needs to be considered for this case.
21012V-DSH-001-A, 7/11/03
Mindspeed Technologies™
Page 9 of 29
M21012V
Input/Output Level Specifications:
Table 7: CMOS I/O Electrical Specifications
Symbol
Parameter
Notes
Minimum
Typical
Maximum
Units
VOH
VOL
IOH
IOL
VIH
VIL
IIH
IIL
tr
tf
Output logic high IOH = –3 mA
Output logic low IOL = 24 mA
Output current (logic high)
Output current (logic low)
Input logic high
Input logic low
Input current (logic high)
Input current (logic low)
Output rise time (20-80%)
Output fall time (20-80%)
Input capacitance of MF10 & MF11 in
two-wire serial mode
2
2
—
—
—
—
—
—
—
—
0.8 x DVDD_I/O
—
–10
0
0.75 x DVDD_I/O
0
–100
–100
—
—
DVDD_I/O
0.0
—
—
—
—
—
—
—
—
—
0.2 x DVDD_I/O
0
10
3.6
0.25 x DVDD_I/O
100
100
5
5
V
V
mA
mA
V
V
µA
µA
ns
ns
3
—
—
10
pF
C2wire
Notes:
1. Specified at recommended operating conditions – see Table 5.
2. DVDD_I/O can be chosen independently from AVDD_I/O.
3. Two-wire serial output mode can drive 500 pF.
Table 8: High-Speed Input Electrical Specifications
Parameter
Notes
Minimum
Typical
Maximum
Units
—
3,4
—
—
—
143
50
Vss
—
Vss-400
—
—
—
—
—
3000
2000
AVDD_I/O
AVDD_I/O + 400
—
Mbps
mV
mV
mV
mV
—
—
—
600
mV
—
—
—
5
6
45
—
—
—
—
50
–15.0
–5.0
—
—
55
—
—
25
70
Ω
dB
dB
mA
mA
Input bit rate
Input differential voltage (P-P)
Input common-mode voltage
Maximum input high voltage
Minimum input low voltage
Maximum common-mode voltage to VddTx/y voltage
difference
Input termination to VddTx/y
Input return loss (40 MHz to 2.5 GHz)
Input return loss (2.5 GHz to 5 GHz)
Maximum DC input current: long-term
Maximum DC input current: temporary
Notes:
1. Specified at recommended operating conditions - see Table 5.
2. Designed for seamless interface to PCML.
3. Example 1200 mVpp differential = 600 mVpp for each single-ended terminal.
4. Minimum input level defined as error free operation at 10-12 BER.
5. Computed as the current through 50 ohms from the voltage difference between the input voltage common mode to VddTx/y.
6. Temporary defined as no damage when shorted to Vss for no longer than 1 year.
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M21012V
Table 9: PCML (Positive Current Mode Logic) Output Electrical Specifications
Parameter
Notes
Minimum
Typical
Maximum
Units
—
—
—
2
—
2
—
2
—
—
—
143
—
AVDD_I/O – 25
500
AVDD_I/O – 25
900
AVDD_I/O – 25
1100
45
—
—
—
100
—
600
—
1000
—
1200
50
–15.0
–5.0
3000
130
AVDD_I/O
700
AVDD_I/O
1100
AVDD_I/O
1300
55
—
—
Mbps
ps
mV
mV
mV
mV
mV
mV
Ω
dB
dB
Output bit rates
Rise/Fall time (20-80%) for all levels
Low swing: output logic high
Low swing: differential
Medium swing: output logic high
Medium swing: differential
High swing: output logic high
High swing: differential
Output termination to AVDD_I/O
Output return loss (40 MHz to 2.5 GHz)
Output return loss (2.5 GHz to 5 GHz)
Notes:
1. Specified at recommended operating conditions – see Table 5.
2. Example 1200 mV P-P differential = 600 mV P-P for each single-ended terminal.
3. All output swings defined with pre-emphasis off.
Table 10: LVPECL (Low Voltage Positive Emitter Coupled Logic) Output Electrical Specifications
Parameter
Notes
Minimum
Typical
Maximum
Units
—
—
2
2
—
—
—
143
—
AVDD_I/O – 1.0
1400
45
—
—
—
100
AVDD_I/O – 0.95
1600
50
–15.0
–5.0
3000
130
AVDD_I/O – 0.81
1800
55
—
—
Mbps
ps
V
mV
Ω
dB
dB
Output bit rates
Rise/Fall time (20-80%)
Output logic high
Differential swing
Output termination to AVDD_I/O
Output return loss (40 MHz to 2.5 GHz)
Output return loss (2.5 GHz to 5 GHz)
Notes:
1. Specified at recommended operating conditions – see Table 5.
2. Specifications apply for AVDD_I/O = 3.3V only.
3. All output swings defined with pre-emphasis off.
Table 11: Adaptive Input Equalization Performance Specifications
Parameter
Input bit rates
Maximum error-free distance on FR4 at 2.97 Gbps
Maximum error-free distance on FR4 at 1.485 Gbps
Adaptive equalization response time
Notes
Minimum
Typical
Maximum
Units
—
2, 3
2, 3
5
1
—
—
—
—
—
—
10
3.0
60
72
—
Gbps
in
in
µs
Notes:
1. Specified at recommended operating conditions – see Table 5.
2. Performance measured on standard FR4 backplane such as standards provided by TYCO for 10GE XAUI.
3. Measured with PCML driver WITHOUT output pre-emphasis at a minimum launch voltage of 900 mVpp output swing at beginning of line. Error-free for BER <
10-12.
4. Combined adaptive equalization + output pre-emphasis performance will be better than individual performance, but less than the sum of the two lengths.
5. Input equalization has biggest effect for bit-rates greater than 1 Gbps.
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M21012V
Table 12: Output Pre-Emphasis Performance Specifications
Parameter
Output bit rates
Maximum error-free distance on FR4 at 2.97 Gbps
Maximum error-free distance on FR4 at 1.485 Gbps
Notes
Minimum
Typical
Maximum
Units
—
2
2
1
—
—
—
—
—
3.0
40
60
Gbps
in
in
Notes:
1. Specified at recommended operating conditions – see Table 5.
2. Performance measured on standard FR4 backplane such as standards provided by TYCO for 10GE XAUI.
3. Measured with PCML receiver without input equalization, using PCML output driver at 1200 mVpp output swing at beginning of line. Error-free for BER < 10-12.
4. Combined adaptive equalization + output pre-emphasis performance will be better than individual performance, but less than the sum of the two lengths.
5. Output Pre-emphasis equalization has biggest effect for bit-rates greater than 1 Gbps.
RCLK Performance Specifications:
Table 13: Reference Clock Input
Parameter
Input frequency (Refclk_ctrl[3:1] = 000b)
Input frequency (Refclk_ctrl[3:1] = 001b)
Input frequency (Refclk_ctrl[3:1] = 010b)
Input frequency (Refclk_ctrl[3:1] = 011b)
Input frequency (Refclk_ctrl[3:1] = 100b)
Input frequency (Refclk_ctrl[3:1] = 101b)
Input frequency (Refclk_ctrl[3:1] = 110b)
Input differential voltage (P-P)
Input common-mode voltage
Input frequency stability tolerance
Differential termination
Internal pull-down to Vss
Maximum DC input current
Notes
Minimum
Typical
Maximum
Units
—
—
—
—
—
—
—
2,3
3
—
3
—
—
10
20
40
80
120
160
320
100
250
—
—
—
—
14.14
—
—
—
—
—
—
—
—
—
100
100K
—
25
50
100
200
300
400
800
1600
AVDD_I/O
100
—
—
15
MHz
MHz
MHz
MHz
MHz
MHz
MHz
mV
mV
ppm
Ω
Ω
mA
Notes:
1. Specified at recommended operation conditions - see Table 5.
2. Example 1200 mVpp differential = 600 mVpp for each single-ended terminal.
3. Input can accept a CMOS single-ended input when differential N terminal is connected to P-side common mode, or decoupled with large enough capacitor. CMOS
input will then see an effective 100 Ohm load.
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M21012V
Table 14: RCLK High-Speed Performance
Parameter
Notes
Minimum
Typical
Maximum
Units
—
—
—
—
—
—
2,3,6
2,4
5
5
2
1
500
250
167
125
—
—
—
—
—
—
2
0.4
3.0
1.5
750
375
250
188
—
—
100
50
Gbps
Gbps
Mbps
Mbps
Mbps
Mbps
ms
ms
ns
ns
Input data rate for divider ratio = 1
Input data rate for divider ratio = 2
Input data rate for divider ratio = 4
Input data rate for divider ratio = 8
Input data rate for divider ratio = 12
Input data rate for divider ratio = 16
Initialization time
Frequency acquisition time
Phase lock time with 100 ppm delta F
Phase lock time with 0 ppm delta F
Notes:
1. Specified at recommended operating conditions – see Table 5.
2. Assume that reference is within +/-100 ppm of desired data-rate.
3. Time after power up, reset, or bit-rate change.
4. Time from application of valid data to lock within +/-20% of lock phase.
5. Defined as when phase settles to within 20% of lock phase.
6. After reset (master or soft), initialization takes place, then frequency acquisition.
Table 15: RCLK Output Performance
Parameter
Output data jitter (rms)
Output data jitter (pp)
Falling-edge-of-clock to data-transition delay
Output clock jitter (rms)
Output clock jitter (pp)
Notes
Minimum
Typical
Maximum
Units
2
2
3
2
2
—
—
-25
—
—
—
—
—
—
—
14
80
25
14
80
mUI
mUI
ps
mUI
mUI
Notes:
1. Specified at recommended operating conditions – see Table 5.
2. Measured with output pre-emphasis disabled, input equalization disabled.
3. Specified for positive clock output.
Table 16: RCLK Alarm Performance
Parameter
Notes
Minimum
Typical
Maximum
Units
xLOL decision time
xLOL assertion frequency threshold (xLOL = H to L)
xLOL de-assertion frequency threshold (xLOL = L to
H)
2
2,3
10
±185
420
±1950
3275
±250000
µs
ppm
2,3
±120
±1450
±250000
ppm
Notes:
1. Specified at recommended operating conditions – see Table 5.
2. Actual values are set with the LOL windows, the typical values are the default values. Minimum and maximum values represent the dynamic range.
3. Assume that reference is +/-100 ppm of operating frequency.
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M21012V
Pin Descriptions
Conventions
Throughout this data sheet, physical pins will be denoted in bold italic print. An array of pins can be called by each individual
pin name (e.g. MF0, MF1, MF2, MF3, and MF6) or as an array (e.g. MF[6,3:0]). The M21012V control is accessed through
registers that employ an 8-bit address and an 8-bit data scheme. Registers are denoted in italic print (e.g. Testregister) and
individual bits within the register will be called out as Testregister[4:3] to denote the 4th and 3rd bits of the register Testregister,
where bit 0 is the LSB and bit 7 is the MSB. Many functions of the device are bit mapped within a register; if the status of the
other bits are uncertain, it is recommended that the user reads the value from the register before writing, to assure only the
desired bits change. Writing in the same value to the bits within a register does not cause glitches to the unchanged features.
The address for the registers as well as its functions can be found in detail in Table 23 and Table 24. The purpose of the
text descriptions is to highlight the features of the registers. If there is a conflict, Table 23 and Table 24 take precedence
over the text description. For redundant items, such as the RCLK number, the registers will have a nomenclature of Testreg_0
for RCLK 0, Testreg_1 for RCLK 1, and so on. For general reference, the text will denote such registers as Testreg_N where
N can vary from 0 to 3. Numbers not immediately followed by a ‘b’ or ‘h’ are decimal values, whereas numbers immediately
followed by a ‘b’ (e.g. 010b) are binary values, and numbers immediately followed by an ‘h’ (e.g. A1h) are hexadecimal values.
RCLK circuits are mapped to input channels.
Reset
Upon application of power, the M21012V automatically generates a master reset. At any time, forcing xRST = L causes the
M21012V to enter the master reset state. A master reset can also be initiated through the registers in the serial interface control
mode by writing AAh to Mastreset. Once a master reset is initiated, all registers are returned to the default values, the internal
state machines cleared, and all RCLK reset to the out-of-lock condition. After a reset, the register Mastreset will automatically
return to the default value of 00h.
Each individual RCLK can be soft reset by setting RCLK_ctrlA_N[7] = 1b where N = 0 for RCLK#0, N = 1 for RCLK#1 and so
on. The bit should be returned to 0b for normal operation. In this case, the registers that determine the RCLK operation options
such as bit rate, window sizes, etc., remain unchanged and only the RCLK state-machine is reset, resulting in an out-of lock
condition.
Internal Voltage Regulator
The digital and analog core is designed to run at 1.2V, however, for operation from 1.8 to 3.3V, an internal linear regulator is
provided. xRegu_En = L enables the voltage regulator which uses AVDD_I/O and DVDD_I/O to generate the required 1.2V
for AVDD_Core and DVDD_Core. In this mode, the AVDD_Core and DVDD_Core pins should be connected to a floating DC
low inductance PCB plane and AC bypassed to Vss using standard decoupling techniques. If desired, AVDD_Core and
DVDD_Core can be separated into individual planes. If 1.2V is available, it can be connected directly to AVDD_Core and
DVDD_Core, to save power, by bypassing the internal linear regulator with xRegu_En = H. In this case, it is recommended
that the AVDD_Core and DVDD_Core pins be tied together to a common PCB plane, and bypassed to Vss with standard
decoupling techniques.
High-Speed I/O Pins
The high-speed input data interface can support PCML and LVPECL. The high-speed serial differential data enters the quad
RCLK via DinP/N[3:0]. Inputs 0 and 1 are internally terminated with 50Ω to VddT0/1 and inputs 2 and 3 are terminated with
50Ω to VddT2/3. For single-ended use, terminate the negative input pin to the common-mode voltage of the positive input. In
all cases, VddTx/y must be a low-impedance node, since it is shared between inputs, which requires either a low impedance
plane or bypass capacitors.
The M21012V supports two high-speed output modes. The I/O interface is set with Out_Mode[1:0] as shown in Table 17. In
the serial interface mode, the Out_ctrl_N[7:6] register is used to set the data level, and Out_Mode[1:0] is used to set the
interface type. In the serial mode, the data output can be enabled with Out_ctrl_N[2] = 1b (default) and the output data polarity
can be flipped by setting Out_ctrl_N[3] = 1b (default: no inversion). Output data polarity flip is an internal function that would
have the same effect as switching the P and N terminals. The serial data options are summarized in Table 17 and detailed
in Table 23 and Table 24. For the clock output in the serial interface control mode, the output interface and level is controlled
by the same register as the data while the clock output can be enabled with Out_ctrl_N[1] = 1b (default disabled) and the output
clock polarity can be flipped by setting Out_ctrl_N[0] = 1b (default: no inversion).
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M21012V
The recommended AVDD_I/O for the different outputs is also shown in Table 18. Non-standard lower swing modes for
LVPECL are provided for lower power dissipation, when desired.
Table 17: Output Interface and Level Mapping
Register
Out_ctrl_N[7:6]
PCML Mode
Out_Mode[1:0] = 00b
LVPECL Mode
Out_Mode[1:0] = 10b
00b
01b
10b
11b
Off
500 mV
900 mV
1200 mV
Off
900 mV
1200 mV
Standard: 1600 mV
Table 18: Output Interface and Recommended AVDD_I/O Range
Output Logic
AVDD_I/O Range (V)
Off
PCML @ 500 mV
PCML @ 900 mV
PCML @ 1200 mV
LVPECL
1.8 - 3.3
1.8 - 3.3
1.8 - 3.3
1.8 - 3.3
3.3
RCLK Reference Frequency
The RCLK frequency acquisition can be accomplished when an external reference is applied to RefClkP/N to enable the
frequency reference acquisition (FRA) mode in the RCLK. PCML, LVTTL, CMOS are examples of the wide variety of interfaces
supported for the reference clock. The inputs contain a DC-coupled 100Ω differential termination between RefClkP and
RefClkN along with a 100 KΩ pull down on each terminal to Vss. After this termination/pull-down block, the reference is ACcoupled internally. The common-mode and allowable voltage swings are specified in Table 13. In the FRA mode, the
RefClkP/N common-mode must be above 250 mV, which may require external pull-ups, in the case of external AC-coupling.
Multifunction Pins Overview
The M21012V is designed to be an extremely versatile device, with many user selectable options in the RCLK and I/O, to
optimize performance. All of these options can be accessed and controlled through the serial interface. The serial interface
supported by this device is a two-wire interface that is compatible with industry standard I2C, and shall be referred to as the
two-wire interface. The serial interface I/O pins and address pins are mapped to the multifunction pins (MF[11:0]). Another
feature of the multifunction pins is to support JTAG testing of this device during PCB manufacturing.
The various control and test modes of this device are selected with three pins: CTRL_Mode[1:0], and xJTAG_En. xJTAG_En
= L overrides CTRL_Mode[1:0], and puts the device in JTAG test mode, while xJTAG_En = H allows CTRL_Mode[1:0] to set
the M21012V in the serial interface control mode, as summarized in Table 19.
Table 19: Multifunction Pins Mode Select
Pin
JTAG Test Mode
2-Wire Serial
xJTAG_En
CTRL_Mode[1:0]
L
don’t care
H
01b
Multifunction pins: Two-Wire Serial Interface
The two-wire interface is compatible with the I2C standard. The M21012V supports the read/write slave-only mode; 7-bit device
address field width, and supports the standard data rate of 100 Kbps, fast mode of 400 Kbps, and high-speed mode of 3.4
Mbps. The 7-bit address for the device is determined with MF[6:0], which allows for a maximum of 128 unique addresses for
this device. SDA (MF11) and SCL (MF10) can drive a maximum of 500 pF each at the maximum bit rate. During the write mode
from the master to the M21012V, data is latched into the internal M21012V registers on the rising edge of SCL, during the
acknowledge phase (ACK) of communication. Table 20 summarizes the multifunction pins for the two-wire serial mode. For
information on timing, please refer to the I 2C bus specifications.
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M21012V
Table 20: Multifunction Pins for Two-Wire Interface
Pin
Function
MF0
MF1
MF2
MF3
MF4
MF5
MF6
MF10
MF11
Addr0
Addr1
Addr2
Addr3
Addr4
Addr5
Addr6
SCL
SDA
Description
7-bit address: Addr0 is LSB, Addr6 is MSB
Clock input (open drain)
Data input/output (open drain)
Multifunction pins: JTAG
The M21012V supports JTAG external boundary scan, which includes all of the high-speed I/O, as well as the traditional digital
I/O.
Table 21: Multifunction Pins for JTAG
Pin
Function
Description
MF8
MF9
MF10
MF11
TMS
TDI
TCK
TDO
Test select
Test data input
Test clock
Test data output
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M21012V
Feature Descriptions
General Objective
The objective of this section is to explain the various functions of the M21012V, as well as to provide a summary of the registers
associated with each of the functions. Please refer to Table 23 for a summary of the register bits and addresses, and
Table 24 for the detailed definition of each bit in the registers. If the text description differs from Table 23 or Table 24,
Table 24 takes precedence.
Input Deterministic Jitter Attenuators
Each of the four input channels contains an independent adaptive input equalizer (AIE) that automatically determines the best
input equalizer setting for minimum bit error rate (BER), over a given interconnect. For the AIE, the address N is mapped to
the input channel. Upon input of valid data, reset, or LOL=H, the AIE starts its optimization from the beginning.
The input equalization settings have been optimized for a variety of back-plane PCB applications, such as board traces and
cables. For a PCB, the input equalization settings have been specified to operate up to 60” at 2.97 Gbps on FR4, and up to
72” on FR4 at 1.485 Gbps. The equalizer has similar high performance on Nelco-13, Arlon 25, Rogers 3003, 4003C, 4340,
GeTek PCB materials, and Gore twinaxial cables. The input equalizer was designed to compensate for the effects of typical
backplane interconnects, which have bandwidths of hundreds of MHz to a few GHz, thus, the equalizers are not expected to
make a significant difference in performance with the bit rates in the lower end of the multi-rate range.
Another component of input deterministic jitter is ISI due to DC offsets. By default, a DC servo-like circuit is enabled to correct
for this type of deterministic jitter, and can be disabled by setting Ineq_ctrl_N[4] = 0b. The DC servo can also be used to track
changes in the common mode for single-ended operation.
Output Pre-Emphasis
Each of the four output channels contains an independent output pre-emphasis circuit that can be used to select the optimal
pre-emphasis level. The pre-emphasis settings have been optimized for a variety of backplane PCB applications. For the PCB,
the settings have been specified to operate up to 40” at 2.97 Gbps on FR4, and up to 60” on FR4 at 1.485 Gbps. Like the input
equalizer settings, the output pre-emphasis has similar high performance on Nelco-13, Arlon 25, Rogers 3003, 4003C, 4340,
GeTek PCB materials, and Gore twinaxial cables. The pre-emphasis level is selected, for each output channel, with
Preemp_ctrl_N[2:0], and the default value of 000b corresponds to pre-emphasis disabled. The pre-emphasis circuit tracks the
bit rate throughout the multi-rate range, however, like the input equalizer, it is designed to compensate for the bandwidth
limitations of the interconnect, and may not have the desired effects at the low end of the multi-rate range.
The output pre-emphasis is available for both data interface formats and levels. Selection of output level and format was
discussed previously in the Pin Descriptions: High-Speed I/O Pins section.
RCLK Overview
The M21012V contains 4 multi-rate RCLKs, that can each operate at independent bit rates. When the RCLK achieves phase
lock onto the incoming data stream, the RCLK removes the incoming random jitter above its loop bandwidth, as well as any
deterministic jitter remaining from the two input deterministic jitter attenuators (AIE & DC servo). The M21012V output data
has extremely low jitter, due to retiming with a very low jitter generation RCLK. The output pre-emphasis option allows for
compensation of interconnect deterministic jitter, generated up to the next downstream device. Clock outputs are also provided
and typically used to drive laser/modulator drivers with an external clock input, typically used for parallel optics module
applications.
Each RCLK is capable of multi-rate operation which is achieved by a combination of built in VCO frequency dividers (VCD),
Data Rate Dividers (DRD), and a wide VCO tuning range (Fmin = 2.0 GHz, Fmax = 3.0 GHz). As a result, the allowed input data
range is Fmin / DRDmax to Fmax / DRDmin. Although the ranges are not continuous, the ranges are deliberately chosen to cover
all typical video applications.
RCLK Features
All of the RCLKs are reset upon xRST = L, Mastreset = AAh, or upon power up. A soft reset through RCLK_ctrlA_N[7] = 1b
resets the individual RCLK state machine, and presets the RCLK to an out-of-lock condition, however, the register contents
that are related to RCLK setup are unchanged. It is required to force a soft reset if the bit rate is dynamically changed. The soft
reset register bit needs to be cleared for proper operation. A reset during operation will cause bit errors, until the RCLK achieves
phase lock.
By default, all of the RCLKs are active and powered up for normal operation. By setting RCLK_ctrlB_N[7:6] = 11b, a RCLK can
be bypassed and powered down, to allow for non-standard bit rates, or to save power when the RCLK is not required at lower
bit rates. When RCLK_ctrlB_N[7:6] = 01b, the RCLK is bypassed so the output data is not re-timed but active (VCO locked to
the input data). In the last mode with RCLK_ctrlB_N[7:6] = 10b, the RCLK is powered down, and all signals along the input and
output paths are also powered down, to save power. In this case, the input data does not reach the output.
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M21012V
To prevent the propagation of noise in the case where there is a LOL condition, the RCLK contains an auto-inhibit feature,
which is enabled by default. When LOL is active, the output of the RCLK is fixed at a logic high state (DoutP = H, DoutN = L).
This feature can be disabled by setting RCLK_ctrlA_N[3] = 0b, which allows RCLK_ctrlA_N[5] to either force an inhibit (1b) or
to never inhibit (0b).
In some back-plane applications, the optimal data sampling point is not in the middle of the data eye. By default, the RCLK
achieves phase lock very near the center of the eye. For optimal performance (jitter tolerance), the actual sampling point can
be adjusted with Phadj_ctrl_N[3:0]. The adjustment range is from –122.5 mUI to +122.5 mUI with 17.5 mUI steps.
Multi-Rate RCLK Bit Rate Selection
For multi-rate operation, the first step is to determine the desired bit rate range. The input data range must be bracketed by
DFmin = Fvco,min/DRD to DFmax = Fvco,max/DRD. DFmax/min are the maximum/minimum data input frequencies, DRD is the data
rate divider setting with RCLK_ctrlB_N[3:0], and Fvco,min/Fvco,max are the minimum/maximum VCO frequencies, which are 2.0
GHz and 3.0 GHz respectively. The valid data rates are shown in Table 22.
Table 22: Valid Input Data Ranges
Parameter
Data Rate Divider (DRD=1): RCLK_ctrlB_N[3:0] = 0000b
Data Rate Divider (DRD=2): RCLK_ctrlB_N[3:0] = 0001b
Data Rate Divider (DRD=4): RCLK_ctrlB_N[3:0] = 0010b
Data Rate Divider (DRD=8): RCLK_ctrlB_N[3:0] = 0011b
Data Rate Divider (DRD=12): RCLK_ctrlB_N[3:0] = 0100b
Data Rate Divider (DRD=16): RCLK_ctrlB_N[3:0] = 0101b
DFmin
DFmax
Units
2.0
1.0
500
250
167
125
3.0
1.5
750
375
250
188
GHz
GHz
MHz
MHz
MHz
MHz
It is important to note the difference between the VCO frequency (Fvco), and the data rate frequency (DF). Fvco is always
between 2 GHz to 3.0 GHz, while DF is the input data rate.
21012V-DSH-001-A, 7/11/03
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Page 18 of 29
M21012V
Serial Interface Register Details
Table 23: Register Table Summary
Addr
Register Name
d7: MSB
d6
d5
d4
d3
d2
d1
d0: LSB
MSPD Int
ref_divr[2]
rst
chipcode[3]
revcode[3]
LOL_3
MSPD Int
ref_divr[1]
rst
chipcode[2]
revcode[2]
LOL_2
reserved
ref_divr[0]
rst
chipcode[1]
revcode[1]
LOL_1
clear_alm
MSPD Int
rst
chipcode[0]
revcode[0]
LOL_0
MSPD Int
data_rate[2]
VCO_divr[2]
dataout_en
preemph[2]
MSPD Int]
phase_adj[2]
narwin_LOL[1]
MSPD Int
data_rate[1]
VCO_divr[1]
clkout_en
preemph[1]
MSPD Int
phase_adj[1]
narwin_LOL[0]
MSPD Int
data_rate[0]
VCO_divr[0]
clk_pol_flip
preemph[0]
MSPD Int
phase_adj[0]
widwin_LOL[0]
Common Registers
00h
04h
05h
06h
07h
30h
Globctrl
Refclk_ctrl
Mastreset
Chipcode
Revcode
Alarm_LOL
powerup
reserved
rst
chipcode[7]
revcode[7]
MSPD Int
MSPD Int
reserved
rst
chipcode[6]
revcode[6]
MSPD Int
MSPD Int
reserved
rst
chipcode[5]
revcode[5]
MSPD Int
M0h
M1h
M2h
M3h
M4h
M5h
M6h
M9h
RCLK_ctrlA_N
RCLK_ctrlB_N
RCLK_ctrlC_N
Out_ctrl_N
Preemp_ctrl_N
Ineq_ctrl_N
Phadj_ctrl_N
LOL_ctrl_N
softreset
RCLKmode[1]
VCO_divr[7]
outlvl[1]
reserved
reserved
i_trim[1]
tacq_LOL[2]
MSPD Int
RCLKmode[0]
VCO_divr[6]
outlvl[0]
MSPD Int
MSPD Int
i_trim[0]
tacq_LOL[1]
MSPD Int
reserved
rst
chipcode[4]
revcode[4]
MSPD Int
Per channel registers (N = RCLK#, M = N + 4)
inh_force
MSPD Int
VCO_divr[5]
reserved
MSPD Int
MSPD Int
r_sel[1]
tacq_LOL[0]
MSPD Int
reserved
VCO_divr[4]
reserved
MSPD Int
en_DCservo
r_sel[0]
narwin_LOL[3]
autoinh_en
data_rate[3]
VCO_divr[3]
data_pol_flip
MSPD Int
en_ad_eq
phase_adj[3]
narwin_LOL[2]
Notes:
1. N = 0h for RCLK 0, N = 1h for RCLK 1,..., N = 3h for RCLK 3.
2. M = 4h for RCLK 0, M = 5h for RCLK 1,..., M = 7h for RCLK 3. For example RCLK 0 starts at address 40h, RCLK 1 at 50h, RCLK 2 at 60h, RCLK 3 at 70h.
21012V-DSH-001-A, 7/11/03
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M21012V
Table 24: Register Table Details
Nomenclature:
1) Reserved bits: bits that exist and reserved for future use by Mindspeed.
2) Bits not defined and not reserved: bits that do not exist.
3) Do not write to reserved or undefined bits – operation not guaranteed.
4) MSPD Internal: defines an internal function. Must always write the default value to MSPD internal bits. When in doubt, read back
default value after reset.
General and Global Control Registers
00h: Global Control
Globctrl
[7] powerup
[6:2] MSPD Internal
[1] Reserved
[0] clear_alm
Powers up the IC by enabling the current references.
1b: Power up the IC [Default]
0b: Power down the IC
Default [00000b]
Reserved (Default = 0b)
Clears the Alarm_LOL alarm registers (write-only).
1b: Clear alarms
0b: Normal operation - latch alarm bits [Default]
Note: upon writing a 1b to this bit, it clears the registers, and user needs to write a 0b to
enable the normal state.
04h: External Reference Divider Control (RFD)
Refclk_ctrl
[7:4] Reserved
[3:1] ref_divr
[0] MSPD Internal
Reserved (Default = 0b)
Sets the divider ratio to scale down RefClkP/N.
000b: RefClkP/N by 1
001b: RefClkP/N by 2
010b: RefClkP/N by 4
011b: RefClkP/N by 8
100b: RefClkP/N by 12
101b: RefClkP/N by 16
110b: RefClkP/N by 32
Default = 0b
05h: Master Chip Reset
Mastreset
[7:0] rst
Same feature as hardware xRST. Resets entire IC (write-only).
AAh: Reset upon write to this register with AAh
00h: Normal operation [Default]
All other values are ignored.
06h: Chip Electronic ID
Chipcode
[7:0] chipcode
This read-only register determines the chipcode of this IC (12h: M21012V).
07h: Chip Revision Code
Revcode
21012V-DSH-001-A, 7/11/03
[7:0] revcode
This read-only register contains the revision of the device.
Format is A.B where A is the main revision and B is the sub revision.
Default value is 10h for revision 1.0.
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M21012V
30h: RCLK Loss of Lock Register Alarm Status
Alarm_LOL
[7:4] MSPD Internal
[3:0] LOL
Default = 0000b
Latched loss of lock alarm status (read-only).
1b = loss of RCLK lock, 0b = normal operation
[3]: RCLK 3
[2]: RCLK 2
[1]: RCLK 1
[0]: RCLK 0
After a clear (Globctrl[0]=1), the register is cleared and 1) will latch any new alarms that
make a L to H transition and 2) set any pre-existing alarm conditions to H.
Individual RCLK Control
Multiple Instance Conventions
Notes:
1. N = 0h for RCLK 0, N = 1h for RCLK 1,..., N = 3h for RCLK 3.
2. M = 4h for RCLK 0, M = 5h for RCLK 1,..., M = 7h for RCLK 3. For example RCLK 0 starts at address 40h, RCLK 1 at 50h, RCLK 2 at 60h, RCLK 3 at 70h.
M0h: RCLK N Control Register A
RCLK_ctrlA_N
[7] softreset
[6] MSPD Internal
[5] inh_force
[4] MSPD Internal
[3] autoinh_en
[2:0] MSPD Internal
21012V-DSH-001-A, 7/11/03
Resets individual RCLK N (setup registers remain unchanged; need to softreset after
rate change).
0b: Normal operation [Default]
1b: Reset single RCLK only
Default = 0b
Manual control of the output inhibit if RCLK_ctrlA_N[3] = 0b.
0b: Normal operation [Default]
1b: Forced inhibit
Default = 0b
Auto inhibit of the output (DoutP = H, DoutN = L) if RCLK N has a LOL condition.
0b: Auto inhibit disabled, RCLK_ctrlA_N[5] determines inhibit force state
1b: Auto inhibit enabled [Default]
Default = 101b
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M21012V
M1h: RCLK N Control Register B
RCLK_ctrlB_N
[7:6] RCLKmode
[5] MSPD Internal
[4] Reserved
[3:0] data_rate
Determines state of the PLL.
00b: RCLK powered up and active [Default]
01b: RCLK powered up and bypassed
10b: RCLK powered down (no signal through)
11b: RCLK powered down and bypassed
Default = 0b
Reserved (Default = 0b)
Data rate divider (DRD): this divides down the VCO frequency to match the input data
rate.
0000b: VCO/1 [Default]
0001b: VCO/2
0010b: VCO/4
0011b: VCO/8
0100b: VCO/12
0101b: VCO/16
Please consult Fvco,max and Fvco,min to determine frequency range of each DRD ratio.
M2h: RCLK N Control Register C
RCLK_ctrlC_N
21012V-DSH-001-A, 7/11/03
[7:0] VCO_divr
VCO comparison divider (VCD): this divider divides down the VCO, to compare it with
the divided down reference.
Binary value reflects the divider ratio.
1h: Minimum value (VCO /1)
FFh: Maximum value (VCO / 255)
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M21012V
M3h: Output Buffer Control for RCLK N
Out_ctrl_N
[7:6] outlvl
[5:4] Reserved
[3] data_pol_flip
[2] dataout_en
[1] clkout_en
[0] clk_pol_flip
Determines the output swing of a data and/or clock buffer for RCLK N.
In PCML mode:
00b: Power down
01b: 500 mV
10b: 900 mV [Default]
11b: 1200 mV
For LVPECL, the output swing is increased to:
00b: Power down
01b: 900 mV
10b: Standard (low specification side) 1200 mV [Default]
11b: Standard (Nominal) 1600 mV
Reserved (Default = 00b)
Flips the polarity of the output data.
0b: Normal [Default]
1b: Polarity flip
Enables the data output driver N.
1b: Data output enabled to level specified in Out_ctrl_N[7:6] [Default]
0b: Data output disabled and powered down
Enables the clock output driver N.
1b: Clock output enabled to level specified in Out_ctrl_N[7:6]
0b: Clock output disabled and powered down [Default]
Flips the polarity of the output clock.
0b: Normal [Default]
1b: Polarity flip
M4h: Output Buffer Pre-Emphasis Control for RCLK N
Preemp_ctrl_N
21012V-DSH-001-A, 7/11/03
[7] Reserved
[6:3] MSPD Internal
[2:0] preemph
Reserved (Default = 0b)
Default = 1000b
Selects the digital pre-emphasis level.
111b: 200%
110b: 150%
101b: 100%
100b: 75%
011b: 50%
010b: 37.5%
001b: 25%
000b: Pre-emphasis off [Default]
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M21012V
M5h: Input Buffer Equalization Control for RCLK N
Ineq_ctrl_N
[7] Reserved
[6:5] MSPD Internal
[4] en_DCservo
[3] en_ad_eq
[2:0] MSPD Internal
Reserved (Default = 0b)
Default = 00b
Enables DC servo in the input channel to remove offset based deterministic jitter.
0b: DC servo Dj attenuator off
1b: DC servo Dj attenuator on [Default]
Enables adaptive input equalization mode.
0b: Adaptive input equalization disabled
1b: Adaptive input equalization enabled [Default]
Default = 000b
M6h: RCLK N Static Phase Offset (Data Sampling Point) Adjust
Phadj_ctrl_N
[7:6] i_trim
[5:4] r_sel
[3:0] phase_adj
21012V-DSH-001-A, 7/11/03
Adjusts the charge-pump current.
00b: 0.65x
01b: 0.8x
10b: Nominal [Default]
11b: 1.15x
Adjusts the resistor of the RCLK loop filter.
00b: 0.8x
01b: Nominal [Default]
10b: 4x
Adjusts the static phase offset of the data.
1111b: -122.5 mUI
1110b: -105 mUI
1101b: -87.5 mUI
1100b: -70 mUI
1011b: -52.5 mUI
1010b: -35 mUI
1001b: -17.5 mUI
1000b: 0 mUI
0000b: 0 mUI [Default]
0001b: 17.5 mUI
0010b: 35 mUI
0011b: 52.5 mUI
0100b: 70 mUI
0101b: 87.5 mUI
0110b: 105 mUI
0111b: 122.5 mUI
Mindspeed Technologies™
Page 24 of 29
M21012V
M9h RCLK N FRA LOL Window Control
LOL_ctrl_N
[7:5] tacq_LOL
[4:1] narwin_LOL
[0] widwin_LOL
21012V-DSH-001-A, 7/11/03
Sets the value for the LOL reference window.
Code
Value
000b
128
001b
256
010b
512
011b
1024
100b
2048
101b
4096 [Default]
110b
8192
111b
16384
Sets the narrow LOL window for the LOL = H to LOL = L transition (transition to in lock
threshold).
Code
Value
0000b
2
0001b
3
0010b
4
0011b
6 [Default]
0100b
8
0101b
12
0110b
16
0111b
24
1000b
9
1001b
10
1010b
11
1011b
12
1100b
13
1101b
14
1110b
15
1111b
32
Sets the wide LOL window for the LOL = L to LOL = H transition (transition to out of lock
threshold).
Narrow
Wide
Wide
Code
Code 0b
Code 1b
0000b
3
8
0001b
4
12
0010b
6
16
0011b
8
24
0100b
12
32
0101b
16
32
0110b
24
32
0111b
32
32
1000b
12
32
1001b
12
32
1010b
12
32
1011b
16
32
1100b
16
32
1101b
16
32
1110b
16
32
1111b
32
32
0b: [Default]
Mindspeed Technologies™
Page 25 of 29
M21012V
10
2X
0.10
A
C
A
0.08
C
D
A
A1
D/2
A2
D1
A3
D1/2
2X
N
0.10
2
3
E/2
E1/2
E
E1
C
B
1
5
6
0.80 DIA.
0.10
C
B
2X
0
B
0.10
C
TOP VIEW
A
C
2X
SEATING
PLANE
SIDE VIEW
4
b
4X P
CL
0.10
C A B
M
SEE DETAIL "A"
FOR PIN #1 ID AND
TIE BAR MARK OPTION
D2
D2/2
PIN1 ID
0.20 R.
e
N
4X P
TERMINAL TIP
1
0.45
2
FOR ODD TERMINAL/SIDE
3
C
C
CL
E2
(Ne-1)Xe
REF.
e
E2/2
TERMINAL TIP
FOR EVEN TERMINAL/SIDE
0.25 MIN.
L
4
e
0.25 MIN
(Nd-1)Xe
REF.
SEATING
PLANE
b
A1
11
SECTION "C-C"
BOTTOM VIEW
SCALE: NONE
Figure 3. 68 Pin Package Drawing
Figure shows drawing for 68 pin package, see Figure 4 for 72 pin dimensions.
21012V-DSH-001-A, 7/11/03
Mindspeed Technologies™
Page 26 of 29
M21012V
STANDARD
DETAIL "A" - PIN #1 ID AND TIE BAR MARK OPTION
S
Y
M
B
O
L
e
N
Nd
Ne
L
b
Q
D2
E2
PITCH VARIATION D
N
O
NOM.
MIN.
0.30
0.18
0.00
T
MAX.
0.50 BSC
72
18
18
0.40
0.23
0.20
E
3
3
3
0.50
0.30
0.45
MIN
EXPOSED PAD
VARIATIONS
NOTES:
C
5.85
COMMON
DIMENSIONS
MIN.
NOM.
A
A1
A2
A3
0.00
-
0.85
0.01
0.65
0.20 REF.
N
O
MAX.
0.90
0.05
0.70
T
E
11
10.00 BSC
9.75 BSC
10.00 BSC
9.75 BSC
D
D1
E
E1
0
P
R
4
12
SEE EXPOSED PAD VARIATION:C
SEE EXPOSED PAD VARIATION:C
SYMBOLS
S
Y
M
B
O
L
0.24
0.13
0.42
0.17
D2
NOM
MAX
MIN
E2
NOM
MAX
6.00
6.15
5.85
6.00
6.15
12˚
0.60
0.23
12
NOTE
1. DIE THICKNESS ALLOWABLE IS 0.305mm MAXIMUM(.012 INCHES MAXIMUM)
2. DIMENSIONING & TOLERANCES CONFORM TO ASME Y14.5M. - 1994.
3.
N IS THE NUMBER OF TERMINALS.
Nd IS THE NUMBER OF TERMINALS IN X-DIRECTION &
4.
DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
Ne IS THE NUMBER OF TERMINALS IN Y-DIRECTION.
BETWEEN 0.20 AND 0.25mm FROM TERMINAL TIP.
5.
THE PIN #1 IDENTIFIER MUST BE EXISTED ON THE TOP SURFACE OF THE
PACKAGE BY USING INDENTATION MARK OR OTHER FEATURE OF PACKAGE BODY.
6.
EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
7.
ALL DIMENSIONS ARE IN MILLIMETERS.
8.
THE SHAPE SHOWN ON FOUR CORNERS ARE NOT ACTUAL I/O.
9.
PACKAGE WARPAGE MAX 0.08mm.
10.
APPLIED FOR EXPOSED PAD AND TERMINALS.
EXCLUDE EMBEDDING PART OF EXPOSED
PAD FROM MEASURING.
11.
APPLIED ONLY FOR TERMINALS.
12.
Q AND R APPLIES ONLY FOR STRAGHT TIEBAR SHAPES.
Figure 4. 72 Pin Package Dimensions
21012V-DSH-001-A, 7/11/03
Mindspeed Technologies™
Page 27 of 29
M21012V
Quad Multi-Rate Video Reclocker (SD-SDI, HD-SDI, 2x HD-SDI interim device)
© 2002, 2003 Mindspeed Technologies™, as a wholly owned subsidiary and the Internet infrastructure business of Conexant Systems,
Inc. All Rights are Reserved.
Information in this document is provided in connection with Mindspeed Technologies, Inc. "Mindspeed" products. These materials are
provided by Mindspeed as a service to its customers and may be used for informational purposes only. Mindspeed assumes no
responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and product descriptions at
any time, without notice. Mindspeed makes no commitment to update the information contained herein. Mindspeed shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as
provided in Mindspeed Terms and Conditions of Sale for such products, Mindspeed assumes no liability whatsoever.
THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING
TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL
PROPERTY RIGHT. Mindspeed further does not warrant the accuracy or completeness of the information, text, graphics or other items
contained within these materials. Mindspeed shall not be liable for any special, indirect, incidental, or consequential damages, including
without limitation, lost revenues or lost profits, which may result from the use of these materials.
Mindspeed products are not intended for use in medical, life saving or life sustaining applications. Mindspeed customers using or
selling Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages
resulting from such improper use or sale.
The following are trademarks of Mindspeed Technologies, Inc. the symbol M1, Mindspeed™, and "Build It First™" Product names or
services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and
names are the property of their respective owners.
For additional disclaimer information, please consult Mindspeed Technologies Legal Information posted at:
http://www.mindspeed.com/, which is incorporated by reference.
Reader Response: Mindspeed Technologies, Inc. strives to produce quality documentation and welcomes your feedback. Please send
comments and suggestions to mailto:[email protected] For technical questions, or to talk to a field applications engineer
contact your local Mindspeed™ sales office listed below. For literature send email request to [email protected]
21012V-DSH-001-A, 7/11/03
Mindspeed Technologies™
Preliminary Information
Page 28 of 29
Headquarters
Newport Beach
Mindspeed Technologies
4000 MacArthur Boulevard, East Tower
Newport Beach, CA 92660
Phone: (949) 579-3000
Fax: (949) 579-3200
www.mindspeed.com
21012V-DSH-001-A, 7/11/03
Mindspeed™ Technologies
Preliminary Information
Page 29 of 29