PCM1770, PCM1771 SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 LOW-VOLTAGE AND LOW-POWER STEREO AUDIO DIGITAL-TO-ANALOG CONVERTER WITH HEADPHONE AMPLIFIER FEATURES APPLICATIONS • • • • • • • • • • • • • • • Multilevel DAC Including Headphone Amplifier Analog Performance (VCC, VHP = 2.4 V): – Dynamic Range: 98 dB Typ – THD+N at 0 dB: 0.1% Typ – THD+N at –20 dB: 0.04% Typ – Output Power at RL = 16 Ω: 13 mW (Stereo), 26 mW (Monaural) 1.6-V to 3.6-V Single Power Supply Low Power Dissipation: 6.5 mW at VCC, VHP = 2.4 V System Clock: 128 fS, 192 fS, 256 fS, 384 fS Sampling Frequency: 5 kHz to 50 kHz Software Control (PCM1770): – 16-, 20-, 24-Bit Word Available – Left-, Right-Justified, and I2S – Slave/Master Selectable – Digital Attenuation: 0 dB to –62 dB, 1 dB/Step – 44.1-kHz Digital De-Emphasis – Zero Cross Attenuation – Digital Soft Mute – Monaural Analog-In With Mixing – Monaural Speaker Mode Hardware Control (PCM1771): – Left-Justified and I2S – 44.1-kHz Digital De-Emphasis – Monaural Analog-In With Mixing Pop-Noise-Free Circuit 3.3-V Tolerant Packages: TSSOP-16 and VQFN-20 Portable Audio Player Cellular Phone PDA Other Applications Requiring Low-Voltage Operation DESCRIPTION The PCM1770 and PCM1771 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, headphone circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages. The data converters use TI's enhanced multilevel ∆-Σ architecture, which employs noise shaping and multilevel amplitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1770 and PCM1771 devices accept several industry standard audio data formats with 16- to 24-bit data, left-justified, I2S, etc., providing easy interfacing to audio DSP and decoder devices. Sampling rates up to 50 kHz are supported. A full set of user-programmable functions is accessible through a 3-wire serial control port, which supports register write functions. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2007, Texas Instruments Incorporated PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) PCM1770 PCM1771 Supply voltage: VCC, VHP –0.3 V to 4 V Supply voltage differences: VCC, VHP ±0.1 V Ground voltage differences ±0.1 V Digital input voltage –0.3 V to 4 V Input current (any terminals except supplies) ±10 mA Operating temperature –40°C to 125°C Storage temperature –55°C to 150°C Junction temperature 150°C Lead temperature (soldering) 260°C, 5 s Package temperature (IR reflow, peak) (1) 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range Supply voltage: VCC, VHP MIN NOM MAX 1.6 2.4 3.6 V 0.64 19.2 MHz 5 50 kHz Digital input logic family Digital input clock frequency CMOS System clock Sampling clock Analog output load resistance Ω 16 Analog input level (VHP = 2.4 V) Operating free-air temperature, TA 2 UNIT –25 Submit Documentation Feedback 1.4 Vp-p 85 °C PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS all specifications at TA = 25°C, VCC = VHP = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 16 Ω, unless otherwise noted PARAMETER TEST CONDITIONS PCM1770PW, PCM1771PW, PCM1770RGA, PCM1771RGA MIN Resolution TYP UNIT MAX 24 Bits OPERATING FREQUENCY Sampling frequency (fS) 5 System clock frequency 50 kHz 128f S, 192 fS, 256 fS, 384 fS DIGITAL INPUT/OUTPUT (1) (2) Logic family VIH CMOS compatible 0.7 VCC Input logic level VIL IIH Input logic current IIL VOH Output logic level (3) VOL VDC 0.3 VCC VIN = VCC 10 VIN = 0 V –10 IOH = –2 mA 0.7 VCC VDC µA µA VDC IOL = 2 mA 0.3 VCC VDC DYNAMIC PERFORMANCE (HEADPHONE OUTPUT) THD+N Full-scale output voltage 0 dB Dynamic range EIAJ, A-weighted 90 98 dB Signal-to-noise ratio EIAJ, A-weighted 90 98 dB Total harmonic distortion + noise 0.55 VHP 0 dB (13 mW) Vp-p 0.1% –20 dB (0.1 mW) 0.04% 0.1% Stereo 10 13 mWrms Monaural 20 26 mWrms Channel separation 64 72 dB Load resistance 14 16 Ω Output power DC ACCURACY Gain error ±2 ±8 %FSR Gain mismatch, channel-to-channel ±2 ±8 %FSR ±30 ±75 mV 0.584 VHP Vp-p Bipolar zero error VOUT = 0.5 VCC at BPZ ANALOG LINE INPUT (MIXING CIRCUIT) Analog input voltage range Gain (analog input to headphone output) 0.67 Analog input impedance THD+N 10 Total harmonic distortion + noise AIN = 0.56 VHP (peak-to-peak) kΩ 0.1% DIGITAL FILTER PERFORMANCE Pass band 0.454 fS Stop band 0.546 fS Pass-band ripple ±0.04 Stop-band attenuation –50 dB dB Group delay 20/fS 44.1-kHz de-emphasis error ±0.1 dB ANALOG FILTER PERFORMANCE (1) (2) (3) Digital inputs and outputs are CMOS compatible. All logic inputs are 3.3-V tolerant and not terminated internally. LRCK and BCK terminals Submit Documentation Feedback 3 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) all specifications at TA = 25°C, VCC = VHP = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 16 Ω, unless otherwise noted PARAMETER TEST CONDITIONS PCM1770PW, PCM1771PW, PCM1770RGA, PCM1771RGA MIN Frequency response at 20 kHz TYP UNIT MAX ±0.2 dB POWER SUPPLY REQUIREMENTS Voltage range, VCC, VHP ICC IHP Supply current 1.6 2.4 3.6 BPZ input 1.5 2.5 BPZ input 1.2 2.5 5 15 µA BPZ input 6.5 12 mW Power down (4) 12 36 µW 85 °C Power down (4) ICC + IHP Power dissipation VDC mA TEMPERATURE RANGE Operation temperature θJA (4) 4 Thermal resistance –25 PCM1770PW, -71PW: 16-terminal TSSOP 150 PCM1770RGA, -71RGA: 20-terminal VQFN 130 All input signals are held static. Submit Documentation Feedback °C/W PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 PIN ASSIGNMENTS PCM1770 PW PACKAGE (TOP VIEW) LRCK DATA BCK PD AGND HGND VCOM HOUTR PCM1771 PW PACKAGE (TOP VIEW) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 SCKI MS MC MD VCC VHP AIN HOUTL LRCK DATA BCK PD AGND HGND VCOM HOUTR 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 SCKI FMT AMIX DEMP VCC VHP AIN HOUTL P0001-02 PCM1770 RGA PACKAGE (TOP VIEW) 2 14 3 13 4 12 5 7 8 11 9 10 VCOM HOUTR NC HOUTL 6 MS MC MD VCC VHP DATA BCK PD AGND HGND 1 20 19 18 17 16 15 2 14 AMIX 3 13 DEMP 4 12 VCC 11 9 10 VHP 5 6 7 8 NC − No internal connection FMT AIN 20 19 18 17 16 15 VCOM HOUT R NC HOUTL 1 AIN DATA BCK PD AGND HGND LRCK NC NC NC SCKI LRCK NC NC NC SCKI PCM1771 RGA PACKAGE (TOP VIEW) P0002-02 Submit Documentation Feedback 5 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 TERMINAL FUNCTIONS PCM1770PW TERMINAL NAME 6 NO. I/O DESCRIPTION AGND 5 – Analog ground. This is a return for VCC. AIN 10 I Monaural analog signal mixer input. The signal can be mixed with the outputs of the L- and R-channel DACs. BCK 3 I/O DATA 2 I Serial audio data input HGND 6 – Analog ground. This is a return for VHP. HOUTL 9 O L-channel analog signal output of the headphone amplifiers HOUTR 8 O R-channel analog signal output of the headphone amplifiers LRCK 1 I/O Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device. In the master interface mode, the PCM1770 device generates the LRCK output to an external device. MC 14 I Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD. MD 13 I Mode control port serial data input. Controls the operation mode on the PCM1770 device. MS 15 I Mode control port select. The control port is active when this terminal is low. PD 4 I Reset input. When low, the PCM1770 device is powered down, and all mode control registers are reset to default settings. SCKI 16 I System clock input VCC 12 – Power supply for all analog circuits except the headphone amplifier. VCOM 7 – Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is required for noise filtering. Voltage level of this terminal is 0.5 VHP nominal. VHP 11 – Analog power supply for the headphone amplifier circuits. The voltage level must be the same as VCC. Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input from an external device. In the master interface mode, the PCM1770 device generates the BCK output to an external device. Submit Documentation Feedback PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 TERMINAL FUNCTIONS (CONTINUED) PCM1770RGA TERMINAL NAME NO. I/O DESCRIPTION AGND 4 – Analog ground. This is a return for VCC. AIN 10 I Monaural analog signal mixer input. The signal can be mixed with the outputs of the L- and R-channel DACs. BCK 2 I/O DATA 1 I Serial audio data input HGND 5 – Analog ground. This is a return for VHP. HOUTL 9 O L-channel analog signal output of the headphone amplifiers HOUTR 7 O R-channel analog signal output of the headphone amplifiers LRCK 20 I/O Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device. In the master interface mode, the PCM1770 device generates the LRCK output to an external device. MC 14 I Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD. MD 13 I Mode control port serial data input. Controls the operation mode on the PCM1770 device. MS 15 I Mode control port select. The control port is active when this terminal is low. NC 8, 17, 18, 19 – No connect PD 3 I Reset input. When low, the PCM1770 device is powered down, and all mode control registers are reset to default settings. SCKI 16 I System clock input VCC 12 – Power supply for all analog circuits except the headphone amplifier. VCOM 6 – Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is required for noise filtering. Voltage level of this terminal is 0.5 VHP nominal. VHP 11 – Analog power supply for the headphone amplifier circuits. The voltage level must be the same as VCC. Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input from an external device. In the master interface mode, the PCM1770 device generates the BCK output to an external device. Submit Documentation Feedback 7 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 TERMINAL FUNCTIONS (CONTINUED) PCM1771PW TERMINAL NAME NO. I/O DESCRIPTION AGND 5 – Analog ground. This is a return for VCC. AIN 10 – Monaural analog signal mixer input. The signal can be mixed with the outputs of the L- and R-channel DACs. AMIX 14 I Analog mixing control BCK 3 I Serial bit clock. Clocks the individual bits of the audio data input, DATA. DATA 2 I Serial audio data input DEMP 13 I De-emphasis control FMT 15 I Data format select HGND 6 – Analog ground. This is a return for VHP. HOUTL 9 O L-channel analog signal output of the headphone amplifiers HOUTR 8 O R-channel analog signal output of the headphone amplifiers LRCK 1 I Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK must be the same as the audio sampling rate. PD 4 I Reset input. When low, the PCM1771 device is powered down, and all mode control registers are reset to default settings. SCKI 16 I System clock input VCC 12 – Power supply for all analog circuits except the headphone amplifier. VCOM 7 – Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is required for noise filtering. Voltage level of this terminal is 0.5 VHP nominal. VHP 11 – Analog power supply for the headphone amplifier circuits. The voltage level must be the same as VCC. PCM1771RGA TERMINAL NAME 8 NO. I/O DESCRIPTION AGND 4 – Analog ground. This is a return for VCC. AIN 10 – Monaural analog signal mixer input. The signal can be mixed with the outputs of the L- and R-channel DACs. AMIX 14 I Analog mixing control BCK 2 I Serial bit clock. Clocks the individual bits of the audio data input, DATA. DATA 1 I Serial audio data input DEMP 13 I De-emphasis control FMT 15 I Data format select HGND 5 – Analog ground. This is a return for VHP. HOUTL 9 O L-channel analog signal output of the headphone amplifiers HOUTR 7 O R-channel analog signal output of the headphone amplifiers LRCK 20 I Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK must be the same as the audio sampling rate. NC 8, 17, 18, 19 – No connect PD 3 I Reset input. When low, the PCM1771 device is powered down, and all mode control registers are reset to default settings. SCKI 16 I System clock input VCC 12 – Power supply for all analog circuits except the headphone amplifier VCOM 6 – Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is required for noise filtering. Voltage level of this terminal is 0.5 VHP nominal. VHP 11 – Analog power supply for the headphone amplifier circuits. The voltage level must be the same as VCC. Submit Documentation Feedback PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 FUNCTIONAL BLOCK DIAGRAM AIN Digital Attenuator LRCK ×8 Digital Filter Audio Interface DATA Headphone Amplifier ∆Σ DAC + HOUTR BCK VCOM (FMT) MS ×8 Digital Filter SPI Port (AMIX) MC ∆Σ DAC + VCOM HOUTL (DEMP) MD Clock Manager Power Supply SCKI PD ( ) : PCM1771 AGND HGND VCC VHP B0001-02 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = VHP 2.4 V, fS = 44.1 kHz, system clock = 256 fS, 24-bit data, and RL = 16 Ω, unless otherwise noted. Digital Filter Digital Filter (De-Emphasis Off) AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0.05 0.04 −20 0.03 0.02 Amplitude – dB Amplitude – dB −40 −60 −80 0.01 0.00 −0.01 −0.02 −100 −0.03 −120 −0.04 −140 0 1 2 f – Frequency [ fS] 3 −0.05 0.0 4 G001 Figure 1. 0.1 0.2 0.3 f – Frequency [ fS] 0.4 0.5 G002 Figure 2. Submit Documentation Feedback 9 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VHP 2.4 V, fS = 44.1 kHz, system clock = 256 fS, 24-bit data, and RL = 16 Ω, unless otherwise noted. De-Emphasis Curves DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 −1 0.4 −2 0.3 De-Emphasis Error – dB De-Emphasis Level – dB DE-EMPHASIS LEVEL vs FREQUENCY −3 −4 −5 −6 −7 0.1 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −10 0.0 −0.5 0.1 0.2 0.3 0.4 0.5 f – Frequency [ fS] 0.6 0 4 6 8 10 12 14 16 18 20 G003 G004 Figure 3. Figure 4. TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE DYNAMIC RANGE vs SUPPLY VOLTAGE 104 Dynamic Range – dB 102 0 dB 0.10 0.1 –20 dB 100 98 96 94 0.01 1.2 1.6 2.0 2.4 2.8 3.2 VCC – Supply Voltage – V 3.6 4.0 92 1.2 G005 Figure 5. 10 2 f – Frequency – kHz 1.00 1 THD+N – Total Harmonic Distortion + Noise – % 0.2 1.6 2.0 2.4 2.8 Figure 6. Submit Documentation Feedback 3.2 VCC – Supply Voltage – V 3.6 4.0 G006 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VHP 2.4 V, fS = 44.1 kHz, system clock = 256 fS, 24-bit data, and RL = 16 Ω, unless otherwise noted. CHANNEL SEPARATION vs SUPPLY VOLTAGE 104 78 102 76 Channel Separation – dB SNR – Signal-to-Noise Ratio − dB SIGNAL-TO-NOISE RATIO vs SUPPLY VOLTAGE 100 98 96 1.6 2.0 2.4 2.8 3.2 3.6 VCC – Supply Voltage – V 70 66 1.2 4.0 1.6 2.0 2.4 2.8 3.2 3.6 VCC – Supply Voltage – V G007 Figure 7. Figure 8. TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 1.00 1 4.0 G008 102 101 100 Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 72 68 94 92 1.2 74 0 dB 0.10 0.1 –20 dB 99 98 97 96 95 0.01 −40 −20 0 20 40 60 80 TA – Free-Air Temperature – °C 100 94 −40 G009 Figure 9. −20 0 20 40 60 TA – Free-Air Temperature – °C 80 100 G010 Figure 10. Submit Documentation Feedback 11 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VHP 2.4 V, fS = 44.1 kHz, system clock = 256 fS, 24-bit data, and RL = 16 Ω, unless otherwise noted. CHANNEL SEPARATION vs FREE-AIR TEMPERATURE 102 76 101 75 100 74 Channel Separation – dB 99 98 97 96 95 94 −40 72 71 70 69 −20 0 20 40 60 80 68 −40 100 TA – Free-Air Temperature – °C 0 20 40 60 80 100 TA – Free-Air Temperature – °C G011 Figure 12. SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs SAMPLING FREQUENCY G012 20 5.0 20 4.5 18 4.5 18 4.0 16 4.0 16 3.5 14 3.5 14 Operational 3.0 12 2.5 10 2.0 8 1.5 6 Power Down 1.0 4 0.5 2 2.0 2.4 2.8 3.2 VCC – Supply Current – V 3.6 3.0 12 Operational 2.5 10 2.0 8 Power Down 1.5 6 1.0 4 0.5 2 0.0 0 1.6 ICC – Supply Current, Operational – mA 5.0 0.0 1.2 0 0 4.0 G013 Figure 13. 12 −20 Figure 11. ICC – Supply Current, Power Down – µA ICC – Supply Current, Operational – mA 73 ICC – Supply Current, Power Down – µA SNR – Signal-to-Noise Ratio − dB SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE 10 20 30 fS – Sampling Frequency – kHz Figure 14. Submit Documentation Feedback 40 50 G014 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VHP 2.4 V, fS = 44.1 kHz, system clock = 256 fS, 24-bit data, and RL = 16 Ω, unless otherwise noted. DYNAMIC RANGE vs JITTER 100 Dynamic Range – dB 99 98 97 96 95 94 0 100 200 300 400 500 600 700 Jitter – ps G015 Figure 15. OUTPUT SPECTRUM (-60 dB, N = 8192) 0 0 −20 −20 −40 −40 Amplitude – dB Amplitude – dB OUTPUT SPECTRUM (-60 dB, N = 8192) −60 −80 −60 −80 −100 −100 −120 −120 −140 −140 0 5 10 15 20 0 f – Frequency – kHz 20 40 60 80 100 120 f – Frequency – kHz G016 Figure 16. G017 Figure 17. Submit Documentation Feedback 13 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 DETAILED DESCRIPTION System Clock, Reset, and Functions System Clock Input The PCM1770 and PCM1771 devices require a system clock for operating the digital interpolation filters and multilevel ∆-Σ modulators. The system clock is applied at terminal 16 (SCKI). Table 1 shows examples of system clock frequencies for common audio sampling rates. Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. Table 1. System Clock Frequency for Common Audio Sampling Frequencies SYSTEM CLOCK FREQUENCY, SCKI (MHz) SAMPLING FREQUENCY, LRCK 128 fS 192 fS 256 fS 384 fS 48 kHz 6.144 9.216 12.288 18.432 44.1 kHz 5.6448 8.4672 11.2896 16.9344 32 kHz 4.096 6.144 8.192 12.288 24 kHz 3.072 4.608 6.144 9.216 22.05 kHz 2.8224 4.2336 5.6448 8.4672 16 kHz 2.048 3.072 4.096 6.144 12 kHz 1.536 2.304 3.072 4.608 11.025 kHz 1.4112 2.1168 2.8224 4.2336 8 kHz 1.024 1.536 2.048 3.072 t(SCKH) 0.7 VCC SCKI 0.3 VCC t(SCKL) t(SCKY) T0005-02 MIN UNIT t(SCKH) System clock pulse duration, HIGH PARAMETER 7 ns t(SCKL) System clock pulse duration, LOW 7 ns t(SCKY) System clock pulse cycle time(1) 52 ns (1) 1/(128 fS), 1/(192 fS), 1/(256 fS) or 1/(384 fS) Figure 18. System Clock Timing 14 Submit Documentation Feedback PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 Power On/Off Reset The PCM1770/71 always must have the PD pin set from LOW to HIGH once after power-supply voltages VCC and VHP have reached the specified voltage range and stable clocks SCKI, BCK, and LRCK are being supplied for the power-on sequence. A minimum time of 1 ms after both the clock and power-supply requirements are met is required before the PD pin changes from LOW to HIGH, as shown in Figure 19. Subsequent to the PD LOW-to-HIGH transition, the internal logic state is held in reset for 1024 system clock cycles prior to the start of the power-on sequence. During the power-on sequence, HOUTL and HOUTR increase gradually from ground leved, reaching an output level that corresponds to the input data after a period of 9334/fS. When powering off, the PD pin is set from HIGH to LOW first. Then HOUTL and HOUTR decrease gradually to ground level over a period of 9334/fS, as shown in Figure 20, after which power can be removed without creating pop noise. When powering on or off, adhering to the timing requirements of Figure 19 and Figure 20 ensures that pop noise does not occur. If the timing requirements are not met, pop noise might occur. VCC, VHP 0V 1 ms (Min) 1024 Internal System Clocks LRCK, BCK, SCKI 1 ms (Min) PD Internal Reset 9334/fS HOUTL, HOUTR 0V T0006-02 Figure 19. Power-On Sequence VCC, VHP 0V LRCK, BCK, SCKI 9334/fS PD HOUTL, HOUTR 0V T0007-02 Figure 20. Power-Off Sequence Submit Documentation Feedback 15 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 Power-Up/-Down Sequence and Reset The PCM1770 device has two kinds of power-up/-down methods: the PD terminal through hardware control and PWRD (register 4, B0) through software control. The PCM1771 device has only the PD terminal through hardware control for the power-up/-down sequence. The power-up or power-down sequence operates the same as the power-on or power-off sequence. When powering up or down using the PD terminal, all digital circuits are reset. When powering up or down using PWRD, all digital circuits are reset except for maintaining the logic states of the registers. Figure 21 shows the power-up/power-down sequence. 2.4 V VCC, VHP 9334/fS 9334/fS LRCK, BCK, SCKI PD HOUTL, HOUTR 0V T0008-02 Figure 21. Power-Down and Power-Up Sequences 16 Submit Documentation Feedback PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 Audio Serial Interface The audio serial interface for the PCM1770 and PCM1771 devices consists of a 3-wire synchronous serial port. It includes terminals 1 (LRCK), 2 (DATA), and 3 (BCK). BCK is the serial audio bit clock, and it clocks the serial data present on DATA into the audio interface serial shift register. Serial data is clocked into the PCM1770 and PCM1771 devices on the rising edge of BCK. LRCK is the serial audio left/right word clock. It latches serial data into the serial audio interface internal registers. Both LRCK and BCK of the PCM1770 device support the slave and master modes, which are set by FMT (register 3). LRCK and BCK are outputs during the master mode and inputs during the slave mode. In slave mode, BCK and LRCK are synchronous to the audio system clock, SCKI. Ideally, it is recommended that LRCK and BCK be derived from SCKI. LRCK is operated at the sampling frequency, fS. BCK can be operated at 32, 48, or 64 times the sampling frequency. In master mode, BCK and LRCK are derived from the system clock and these terminals are outputs. BCK and LRCK are synchronous to SCKI. LRCK is operated at the sampling frequency, fS. BCK can be operated at 64 times the sampling frequency. The PCM1770 and PCM1771 devices operate under LRCK synchronized with the system clock. The PCM1770 and PCM1771 devices do not need a specific phase relationship between LRCK and the system clock, but do require the synchronization of LRCK and the system clock. If the relationship between the system clock and LRCK changes more than ±3 BCK during one sample period, internal operation of the PCM1770 and PCM1771 devices halts within 1/fS, and the analog output is kept in last data until resynchronization between system clock and LRCK is completed. Audio Data Formats and Timing The PCM1770 device supports industry-standard audio data formats, including standard, I2S, and left-justified. The PCM1771 device supports the I2S and left-justified data formats. Table 2 lists the main features of the audio data interface. Figure 22 shows the data formats. Data formats are selected using the format bits, FMT[2:0] of control register 3 in the case of the PCM1770 device, and are selected using the FMT terminal in the case of the PCM1771 device. The default data format is 24-bit, left-justified, slave mode. All formats require binary 2s complement, MSB-first audio data. Figure 23 shows a detailed timing diagram for the serial audio interface in slave mode. Figure 24 shows a detailed timing diagram for the serial audio interface in master mode. Table 2. Audio Data Interface AUDIO-DATA INTERFACE FEATURE Audio data interface format CHARACTERISTIC (PCM1770) Standard, I2S, left-justified (PCM1771) I2S, left-justified Audio data bit length 16-, 20-, 24-bit selectable Audio data format MSB-first, 2s-complement Submit Documentation Feedback 17 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 (1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW (Slave Mode) 1/fS LRCK R-Channel L-Channel BCK (= 32 fS, 48 fS or 64 fS) 16-Bit Right-Justified, BCK = 32 fS DATA 14 15 16 1 2 3 14 15 16 1 LSB MSB 2 3 14 15 16 LSB MSB 16-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 14 15 16 1 2 3 14 15 16 MSB 1 LSB 2 3 14 15 16 MSB LSB 20-Bit Right-Justified DATA 18 19 20 1 2 3 18 19 20 MSB 1 LSB 2 3 18 19 20 MSB LSB 24-Bit Right-Justified DATA 22 23 24 1 2 3 22 23 24 MSB 1 LSB 2 3 22 23 24 MSB LSB (2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH (Slave Mode) 1/fS LRCK R-Channel L-Channel BCK (= 32 fS, 48 fS or 64 fS) DATA 1 2 3 N−2 N−1 MSB N 1 LSB 2 3 N−2 N−1 MSB N 1 2 LSB (3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW (Slave Mode) 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS or 64 fS) DATA 1 2 3 MSB N−2 N−1 N 1 LSB 2 3 N−2 N−1 MSB N 1 2 N 1 2 LSB (4) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW (Master Mode) (The frequency of BCK is 64 fS and SCKI is 256 fS only) 1/fS LRCK L-Channel R-Channel BCK (= 64 fS) DATA 1 2 3 MSB N−2 N−1 LSB N 1 2 3 MSB N−2 N−1 LSB T0009-01 Figure 22. Audio Data Input Formats 18 Submit Documentation Feedback PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 50% of VCC LRCK (Input) t(BCL) t(BCH) t(LB) 50% of VCC BCK (Input) t(BCY) t(BL) 50% of VCC DATA t(DS) t(DH) PARAMETER T0010-02 MIN MAX UNIT )(1) t(BCY) BCK pulse cycle time 1/(64 fS t(BCH) BCK high-level time 35 ns t(BCL) BCK low-level time 35 ns t(BL) BCK rising edge to LRCK edge 10 ns t(LB) LRCK edge to BCK rising edge 10 ns t(DS) DATA set-up time 10 ns t(DH) DATA hold time 10 ns (1) fS is the sampling frequency. Figure 23. Audio Interface Timing (Slave Mode) Submit Documentation Feedback 19 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 t(SCY) 50% of VCC SCKI t(DL) 50% of VCC LRCK (Output) t(BCL) t(BCH) t(DB) t(DB) 50% of VCC BCK (Output) t(BCY) 50% of VCC DATA t(DS) t(DH) T0011-02 PARAMETER MIN MAX UNIT 0 40 ns 0 40 ns 1/(256 fS)(1) t(SCY) SCKI pulse cycle time t(DL) LRCK edge from SCKI rising edge t(DB) BCK edge from SCKI rising edge t(BCY) BCK pulse cycle time t(BCH) BCK high-level time 146 ns t(BCL) BCK low-level time 146 ns t(DS) DATA setup time 10 ns t(DH) DATA hold time 10 ns (1) 1/(64 fS)(1) fS is up to 48 kHz. fS is the sampling frequency. Figure 24. Audio Interface Timing (Master Mode) 20 Submit Documentation Feedback PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 Hardware Control (PCM1771) The digital functions of the PCM1771 device are capable of hardware control. Table 3 shows selectable formats, Table 4 shows de-emphasis control, and Table 5 shows analog mixing control. Table 3. Data Format Select FMT DATA FORMAT Low 16- to 24-bit, left-justified format High 16- to 24-bit, I2S format Table 4. De-Emphasis Control DEMP DE-EMPHASIS FUNCTION Low 44.1-kHz de-emphasis OFF High 44.1-kHz de-emphasis ON Table 5. Analog Mixing Control AMIX ANALOG MIXING Low Analog mixing OFF High Analog mixing ON Submit Documentation Feedback 21 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 Software Control (PCM1770) The PCM1770 device has many programmable functions that can be controlled in the software-control mode. The functions are controlled by programming the internal registers using MS, MC, and MD. The software-control interface is a 3-wire serial port that operates asynchronously to the serial audio interface. The serial control interface is used to program the on-chip mode registers. MD is the serial data input, used to program the mode registers. MC is the serial bit clock, used to shift data into the control port. MS is the mode control port select signal. Register Write Operation (PCM1770) All write operations for the serial control port use 16-bit data words. Figure 25 shows the control data word format. The most significant bit must be 0. There are seven bits, labeled IDX[6:0], that set the register index (or address) for the write operation. The eight least significant bits, D[7:0], contain the data to be written to the register specified by IDX[6:0]. Figure 26 shows the functional timing diagram for writing to the serial control port. To write data into the mode register, the data is clocked into an internal shift register on the rising edge of the MC clock. Serial data can change on the falling edge of the MC clock and must be stable on the rising edge of the MC clock. The MS signal must be low during the write mode and the rising edge of the MS signal must be aligned with the falling edge of the last MC clock pulse in the 16-bit frame. The MC clock can run continuously between transactions while the MS signal is low. LSB MSB 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 Register Index (or Address) D4 D3 D2 D1 D0 Register Data R0001-01 Figure 25. Control Data Word Format for MD (1) Single Write Operation 16 Bits MS MC MD MSB LSB MSB (2) Continuous Write Operation 16 Bits x N Frames MS MC MD MSB LSB MSB LSB MSB LSB N Frames T0012-01 Figure 26. Register Write Operation 22 Submit Documentation Feedback PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 Control Interface Timing Requirements (PCM1770) Figure 27 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for proper control port operation. t(MHH) MS 50% of VCC t(MLS) t(MCL) t(MCH) t(MLH) MC 50% of VCC t(MCY) LSB MD 50% of VCC t(MDS) t(MDH) T0013-02 PARAMETER SYMBOL MIN MC pulse cycle time t(MCY) 100(1) TYP MAX ns MC low-level time t(MCL) 50 ns MC high-level time t(MCH) 50 ns MS high-level time t(MHH) (2) ns MS falling edge to MC rising edge t(MLS) 20 ns MS hold time t(MLH) 20 ns MD hold time t(MDH) 15 ns MD setup time t(MDS) 20 ns (1) When MC runs continuously between transactions, MC pulse cycle time is specified as 3/(128 fS), where fS is sampling rate. (2) 3/(128 fS) s (min), where fS is sampling rate. UNIT Figure 27. Control Interface Timing Submit Documentation Feedback 23 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 Mode Control Registers (PCM1770) User-Programmable Mode Controls The PCM1770 device has a number of user-programmable functions that can be accessed via mode control registers. The registers are programmed using the serial control interface, as discussed in the Software Control (PCM1770) section. Table 6 lists the available mode control functions, along with their reset default conditions and associated register index. Register Map Table 7 shows the mode control register map. Each register includes an index (or address) indicated by the IDX[6:0] bits. Table 6. User-Programmable Mode Controls FUNCTION RESET DEFAULT Soft mute control, L/R independently BIT(S) Disabled 01 MUTL, MUTR 0 dB 01, 02 ATL[5:0], ATR[5:0] OVER Digital attenuation level setting, 0 dB to –63 dB in 1-dB steps, L/R independently Oversampling rate control (128 fS, 192 fS, 256 fS, 384 fS) REGISTER NO. 128 fS oversampling 03 Polarity control for analog output for R-channel DAC Not inverted 03 RINV Analog mixing control for analog in, AIN (terminal 14) Disabled 03 AMIX 44.1-kHz de-emphasis control Disabled 03 DEM 24-bit, left-justified format 03 FMT[2:0] Zero cross attenuation Disabled 04 ZCAT Power-down control Disabled 04 PWRD Audio data format select Table 7. Mode Control Register Map REGIS IDX [6:0] B15 TER (B14-B8) B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 01 01h 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MUTR MUTL ATL5 ATL4 ATL3 ATL2 ATL1 ATL0 02 02h 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 RINV AMIX DEM FMT2 FMT1 FMT0 ZCAT RSV RSV RSV PWR (1) (1) (1) 03 03h 0 RSV RSV (1) (1) IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER RSV (1) 04 (1) 24 04h 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV (1) (1) (1) RSV is reserved for test operation. It must be set to 0 during regular operation. Submit Documentation Feedback PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 Register Definitions Register 01 B15 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 MUTR B6 MUTL B5 ATL5 B4 ATL4 B3 ATL3 B2 ATL2 B1 ATL1 B0 ATL0 IDX[6:0]: 000 0001b MUTx: Soft Mute Control Where, x = L or R, corresponding to the headphone output HOUTL or HOUTR. Default value: 0 MUTL, MUTR = 0 Mute disabled (default) MUTL, MUTR = 1 Mute enabled The mute bits, MUTL and MUTR, enable or disable the soft mute function for the corresponding headphone outputs, HOUTL and HOUTR. The soft mute function is incorporated into the digital attenuators. When mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to the infinite attenuation, one attenuator step (1 dB) at a time. This provides pop-free muting of the headphone output. By setting MUTx = 0, the attenuator is increased one step at a time to the previously programmed attenuation level. ATL[5:0]: Digital Attenuation Level Setting for Headphone Output, HOUTL Default value: 11 1111b Headphone output HOUTL includes a digital attenuation function. The attenuation level can be set from 0 dB to –62 dB, in 1-dB steps. Changes in attenuator levels are made by incrementing or decrementing by one step (1 dB) for every 8/fS time internal until the programmed attenuator setting is reached. Alternatively, the attenuation level may be set to infinite attenuation (or mute). The following table shows the attenuation levels for various settings: ATL[5:0] ATTENUATION LEVEL SETTING 11 1111b 0 dB, no attenuation (default) 11 1110b –1 dB 11 1101b –2 dB : : 00 0010b –61 dB 00 0001b –62 dB 00 0000b Mute Register 02 B15 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 RSV B5 ATR5 B4 ATR4 B3 ATR3 B2 ATR2 B1 ATR1 B0 ATR0 IDX[6:0]: 000 0010b ATR[5:0]: Digital Attenuation Level Setting for Headphone Output, HOUTR Default value: 11 1111b Headphone output HOUTR includes a digital attenuation function. The attenuation level can be set from 0 dB to –62 dB, in 1-dB steps. Changes in attenuator levels are made by incrementing or decrementing by one step (1 dB) for every 8/fS time internal until the programmed attenuator setting in reached. Alternatively, the attenuation level can be set to infinite attenuation (or mute). To set the attenuation levels for ATR[5:0], see the table for ATL[5:0], register 01. Submit Documentation Feedback 25 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 Register 03 B15 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 OVER B6 RSV B5 RINV B4 AMIX B3 DEM B2 FMT2 B1 FMT1 B0 FMT0 IDX[6:0]: 000 0011b OVER: Oversampling Control Default value: 0 OVER = 0 128fS oversampling OVER = 1 192fS, 256fS, 384fS oversampling The OVER bit controls the oversampling rate of the ∆-Σ D/A converters. When it operates at a low sampling rate, less than 24 kHz, this function is recommended. RINV: Polarity Control for Headphone Output, HOUTR Default value: 0 RINV = 0 Not inverted RINV = 1 Inverted output The RINV bits allow the user to control the polarity of the headphone output, HOUTR. This function can be used to connect the monaural speaker using the BTL connection method. This bit is recommended to be 0 during the power-up/-down sequence for minimizing audible pop noise. AMIX: Analog Mixing Control for External Analog Signal, AIN Default value: 0 AMIX = 0 Disabled (not mixed) AMIX = 1 Enabled (mixing to the DAC output) The AMIX bit allows the user to mix analog input (AIN) with headphone outputs (HOUTL/HOUTR) internally. DEM: 44.1-kHz De-Emphasis Control Default value: 0 DEM = 0 Disabled DEM = 1 Enabled The DEM bit enables or disables the digital de-emphasis filter for the 44.1-kHz sampling rate. FMT[2:0]: Audio Interface Data Format Default value: 000 The FMT[2:0] bits select the data format for the serial audio interface. The following table shows the available format options. FMT[2:0] Audio Data Format Selection 000 16- to 24-bit, left-justified format (default) 001 16- to 24-bit, I2S format 010 24-bit right-justified data 011 20-bit right-justified data 100 16-bit right-justified data 101 16- to 24-bit, left-justified format, master mode 110 Reserved 111 Reserved 26 Submit Documentation Feedback PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 Register 04 B15 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 RSV B5 RSV B4 ZCAT B3 RSV B2 RSV B1 RSV B0 PWRD IDX[6:0]: 0000 0100b ZCAT: Zero Cross Attenuation Default value: 0 ZCAT = 0 Normal attenuation (default) ZCAT = 1 Zero cross attenuation This bit enables changing the signal level on zero crossing during attenuation control or muting. If the signal does not cross BPZ beyond 512/fS (11.6 ms at 44.1-kHz sampling rate), the signal level is changed similarly to normal attenuation control. This function is independently monitored for each channel; moreover, change of signal level is alternated between both channels. Figure 28 shows an example of zero cross attenuation. ATT CTRL START L-Channel (1.5 kHz) R-Channel (1 kHz) Level Change Point W0001-01 Figure 28. Example of Zero Cross Attenuation PWRD: Power Down Control Default value: 0 PWRD = 0 Normal operation (default) PWRD = 1 Power-down state This bit is used to enter into low-power mode. Note that PWRD has no reset function. When this bit is set to 1, the PCM1770 device enters low-power mode and all digital circuits are reset except the register states, which remain unchanged. Submit Documentation Feedback 27 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 Analog In/Out Headphone Output (Stereo) The PCM1770 and PCM1771 devices have two independent headphone amplifiers, and the amplifier outputs are provided at the HOUTL and HOUTR terminals. Because the capability of the headphone output is designed for driving a 16-Ω impedance headphone, less than a 16-Ω impedance headphone is not recommended. A resistor and a capacitor must be connected to HOUTL and HOUTR to ensure proper output loading. Monaural Output (BTL Mode/Monaural Speaker) The monaural output can be created by summing the left and right headphone outputs. When in the BTL mode, the user must set the headphone output levels to –3 dB using the ATL[5:0] bits in register 01 and the ATR[5:0] bits in register 02. Moreover, invert the polarity of the right headphone output by using the RINV bit on control register 03. The RINV bit is recommended to be 0 during the power-up/-down sequence for minimizing audible pop noise. Analog Input The PCM1770 and PCM1771 devices have an analog input, AIN (terminal 10). The AMIX bit (PCM1770) or the AMIX terminal (PCM1771) allows the user to mix AIN with the headphone outputs (HOUTL and HOUTR) internally. When in the mixing mode, an ac-coupling capacitor is needed for AIN. But if AIN is not used, AIN must be open and the AMIX bit (PCM1770) must be disabled or the AMIX terminal (PCM1771) must be low. Because AIN does not have an internal low-pass filter, it is recommended that the bandwidth of the input signal into AIN is limited to less than 100 kHz. The source of signals connected to AIN must be connected by low impedance. Although the maximum input voltage on AIN is designed to be as large as 0.584 VHP (peak-to-peak), the user must attenuate the input voltage on AIN and control the digital input data so that each line output (HOUTL and HOUTR) does not exceed 0.55 VHP (peak-to-peak) in the mixing mode. VCOM Output One unbuffered common-mode voltage output terminal, VCOM, is brought out for decoupling purposes. This terminal is nominally biased to a dc voltage level equal to 0.5 VHP and connected to a 10-µF capacitor. In the case of a capacitor smaller than 10 µF, pop noise can be generated during the power-on/-off or power-up/-down sequences. 28 Submit Documentation Feedback PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 APPLICATION INFORMATION Connection Diagrams Figure 29 shows the basic connection diagram with the necessary power supply bypassing and decoupling components. It is recommended that the component values shown in Figure 29 be used for all designs. The use of series resistors (22 Ω to 100 Ω) is recommended for the SCKI, LRCK, BCK, and DATA inputs. The series resistor combines with the stray PCB and device input capacitance to form a low-pass filter that reduces high-frequency noise emissions and helps to dampen glitches and ringing present on the clock and data lines. Power Supplies and Grounding The PCM1770 and PCM1771 devices require a 2.4-V typical analog supply for VCC and VHP. These 2.4-V supplies power the DAC, analog output filter, and other circuits. For best performance, these 2.4-V supplies must be derived from the analog supply using a linear regulator, as shown in Figure 29. Figure 29 shows the proper power supply bypassing. The 10-µF capacitors must be tantalum or aluminum electrolytic, while the 0.1-µF capacitors are ceramic (X7R type is recommended for surface-mount applications). Short-Circuit Protection Continuous shorting of HOUTL and HOUTR to GND, to a power supply, or to each other is not permitted, as protection circuitry for an output short is not implemented in the device. If the possibility of shorting cannot be eliminated in an application, an 8-Ω or higher series resistor must be added between the phase compensation circuits of the HOUTx pins and the application circuitry (headphone jack in Figure 29). Submit Documentation Feedback 29 PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 APPLICATION INFORMATION (continued) 1.6 V to 3.6 V Audio DSP Controller 10 µF 1 LRCK SCKI 16 2 DATA MS 15 3 BCK MC 14 4 PD MD 13 VCC 12 PCM1770 5 AGND 6 HGND VHP 11 7 VCOM AIN 10 8 HOUTR HOUTL 0.1 µF 10 µF 0.1 µF 10 µF Analog In 9 10 µF 220 µF 0.022 µF 16 Ω 220 µF Headphone RL = 16 Ω 0.022 µF 16 Ω S0008-01 Figure 29. Basic Connection Diagram 30 Submit Documentation Feedback PCM1770, PCM1771 www.ti.com SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from D Revision (April 2005) to E Revision .................................................................................................... Page • • Changed MCKI to SCKI...................................................................................................................................................... 29 Corrected errors, added recommended parts, and changed incorrect symbols ................................................................ 30 Changes from C Revision (May 2004) to D Revision ..................................................................................................... Page • • • • • • • • Changed data sheet to new format ...................................................................................................................................... 1 Changed value for power-supply voltage ............................................................................................................................. 2 Removed package/ordering information, reformatted, and appended at end of data sheet ................................................ 2 Added new Recommended Operating Conditions table to data sheet................................................................................. 2 Changed page layout for Terminal Function tables.............................................................................................................. 6 Changed page layout of Figure 13 and Figure 14.............................................................................................................. 12 In Figure 22, added arrows to all rising edges of BCK for data formats (2), (3), and (4) ................................................... 18 Added new subsection, Short-Circuit Protection, with information concerning protection of output pins........................... 29 Submit Documentation Feedback 31 PACKAGE OPTION ADDENDUM www.ti.com 22-Aug-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCM1770PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1770PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1770PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1770PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1770RGA ACTIVE QFN RGA 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1770RGAG4 ACTIVE QFN RGA 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1770RGAR ACTIVE QFN RGA 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1770RGARG4 ACTIVE QFN RGA 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1771PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1771PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1771PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1771PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1771RGA ACTIVE QFN RGA 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1771RGAG4 ACTIVE QFN RGA 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1771RGAR ACTIVE QFN RGA 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1771RGARG4 ACTIVE QFN RGA 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 22-Aug-2007 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCM1770RGAR RGA 20 SITE 49 330 13 4.4 4.4 1.3 8 12 Q1 PCM1771PWR PW 16 SITE 49 330 17 6.8 5.4 1.6 8 16 Q1 PCM1771RGAR RGA 20 SITE 49 330 13 4.4 4.4 1.3 8 12 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) PCM1770RGAR RGA 20 SITE 49 342.9 336.6 20.64 PCM1771PWR PW 16 SITE 49 342.9 336.6 28.58 PCM1771RGAR RGA 20 SITE 49 342.9 336.6 20.64 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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