MIC2782 - Micrel

MIC2782
Dual-Input Push Button Reset IC
with Immediate and Delayed Outputs
General Description
Features
The MIC2782 is a two input, two output push-button reset
IC. It will generate a reset pulse for a factory-programmed
reset timeout period after both manual reset inputs have
been held to a logic-low for the factory-programmed setup
period. The MIC2782 also has an ANDOUT logic output
which will activate if both inputs are held low for longer
than a debounce time (1.5ms), and deactivate if one or
both inputs are released for longer than a debounce time
(1.5ms). The RESET and ANDOUT outputs are active-low,
open-drain NMOS outputs.
The MIC2782 operates over the 1.5V to 5.5V supply
voltage range, consuming 2.2µA of supply current at 3.3V.
The device features 65kΩ internal pull-up resistors on both
of the inputs (/MR1 and /MR2). The device offers factory
programmed setup periods of 6s, 8s, 10s, or 12s and reset
timeout periods of 0.5s, 1s or 2s. It is available in a space
saving, 6-bump, 0.4mm pitch, 0.8mm × 1.2mm wafer level
chip scale package.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
•
•
•
•
•
•
•
•
•
•
1.5V to 5.5V operating supply voltage range
2.2µA supply current with /MR1, /MR2 not asserted
Factory-programmed setup periods of 6s, 8s, 10s or 12s
Factory-programmed reset timeout periods of 0.5s, 1s or
2s
Integrated 65kΩ /MR1 and /MR2 pull-up resistors
Supports single push-button reset with /MR1 tied to
/MR2
RESET asserts after /MR1 and /MR2 are asserted low
for a setup period
ANDOUT asserts after /MR1 and /MR2 are asserted low
for a debounce time (1.5ms)
Open-drain RESET and ANDOUT outputs
6-bump, 0.4mm pitch, 0.8mm × 1.2mm wafer level chip
scale package (WLCSP)
Applications
•
•
•
•
•
Smart phones
Tablets
eBooks
Portable games
Portable navigation device
____________________________________________________________________________________________________________________
Typical Application
VDD = 1.5V to 5.5V
100k
VDD
0.1uF
RESET
/MR1
100k
LOAD SWITCH
or PMIC
or µP
/RESET
MIC2782
PUSH-BUTTON
SWITCH
/MR1
PUSH-BUTTON
SWITCH
/MR2
/MR2
ANDOUT
LOAD SWITCH
or PMIC
or µP
/RESET
GND
.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
February 21, 2014
Revision 2.0
Micrel, Inc.
MIC2782
Ordering Information
Part Number
Setup Period
Reset Timeout Period
(tSETUP)
(tRESET)
(s)
(s)
UJA
6
0.5
6-bump, 0.4mm pitch, 0.8mm × 1.2mm WLCSP
-
6
1
6-bump, 0.4mm pitch, 0.8mm × 1.2mm WLCSP
Part Marking
MIC2782CLYCS
MIC2782CMYCS
(1)
Package
MIC2782CRYCS
UJC
6
2
6-bump, 0.4mm pitch, 0.8mm × 1.2mm WLCSP
MIC2782DLYCS
UKU
8
0.5
6-bump, 0.4mm pitch, 0.8mm × 1.2mm WLCSP
-
8
1
6-bump, 0.4mm pitch, 0.8mm × 1.2mm WLCSP
MIC2782DMYCS
(1)
MIC2782DRYCS
UJE
8
2
6-bump, 0.4mm pitch, 0.8mm × 1.2mm WLCSP
MIC2782ELYCS
UKW
10
0.5
6-bump, 0.4mm pitch, 0.8mm × 1.2mm WLCSP
UKX
10
1
6-bump, 0.4mm pitch, 0.8mm × 1.2mm WLCSP
-
10
2
6-bump, 0.4mm pitch, 0.8mm × 1.2mm WLCSP
MIC2782EMYCS
MIC2782ERYCS
(1)
MIC2782FLYCS
UJF
12
0.5
6-bump, 0.4mm pitch, 0.8mm × 1.2mm WLCSP
MIC2782FMYCS
-
12
1
6-bump, 0.4mm pitch, 0.8mm × 1.2mm WLCSP
MIC2782FRYCS
UKZ
12
2
6-bump, 0.4mm pitch, 0.8mm × 1.2mm WLCSP
(1)
Notes:
1.
Contact Factory for availability.
Ordering Guide
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Micrel, Inc.
MIC2782
Chip Scale Package (CS) Bump Configuration
Y = Year Code
WW = Week Code
TOP VIEW (BUMP SIDE DOWN)
TOP VIEW
BOTTOM VIEW (BUMP SIDE UP)
6-Bump, 0.4mm pitch, 0.8mm x 1.2mm WLCSP
Pin Description
Bump
Designation
Bump
Name
Pin Function
NMOS Open-Drain output, Active-Low. Asserts low 1.5ms after /MR1 and /MR2 are both asserted
low. Connect a resistor greater than 5kΩ from the ANDOUT pin to VDD in order to pull up the
ANDOUT output voltage when inactive. No ESD diode from ANDOUT to VDD. Please see the
Functional Description and Timing Diagram sections for further details of how the ANDOUT
output functions.
A1
ANDOUT
A2
/MR2
Manual Reset Input 2, Active-Low. Internal 65kΩ (typical) Pull-Up Resistor to VDD. Pulling both
manual reset inputs low for longer than the setup period causes one RESET output pulse for the
reset timeout delay period.
B1
RESET
NMOS Open-Drain output, Active-Low. Asserts low after /MR1 and /MR2 have both asserted low
for longer than setup period. Connect a resistor greater than 5kΩ from the RESET pin to VDD in
order to pull up the RESET output voltage when inactive. No ESD diode from RESET to VDD.
Please see the Functional Description and Timing Diagram sections for further details of how the
RESET output functions.
B2
/MR1
Manual Reset Input 1, Active-Low. Internal 65kΩ (typical) Pull-Up Resistor to VDD. Pulling both
manual reset inputs low for longer than the setup period causes one RESET output pulse for the
reset timeout delay period.
C1
VDD
Supply Voltage. Bypass to ground with minimum 0.1µF capacitor.
C2
GND
Supply Ground.
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MIC2782
Absolute Maximum Ratings (1)
Operating Ratings (2)
Supply Voltage (VDD) ......................................GND to +6.0V
Input Voltage (V/MR1, V/MR2)………GND - 0.3V to VDD + 0.3V
NMOS Output Voltage (VRESET, VANDOUT)…....GND - 0.3V to
+6.0V
Lead Temperature (soldering, 10sec.) ....................... 260°C
Storage Temperature (Ts).......................... -55°C to +150°C
(3)
ESD Rating (Human Body Model) .............................. 2kV
ESD Rating (Machine Model)…………………………...200V
Supply Voltage (VDD) .................................... +1.5V to +5.5V
Input Voltage (V/MR1, V/MR2)…………………...….…0V to VDD
NMOS Output Voltage (VRESET, VANDOUT)….……0V to +5.5V
Junction Temperature (TJ) .......................... –40°C to +85°C
Package Thermal Resistance
6-Bump, 0.4mm Pitch WLCSP (θJA) ................ 125°C/W
Electrical Characteristics (4)
For typical values, VDD = 3.3V, /MR1 = /MR2 = Open, TJ = 25°C, bold values indicate –40°C ≤ TJ ≤ +85°C; unless noted.
Parameter
Conditions
Min.
Typ.
Max.
Units
5.5
V
Power Supply Input
Supply Voltage (VDD)
Supply Current (IDD)
1.5
Reset Output Valid
VDD = 3.3V, /MR1 = /MR2 = VDD
2.2
4.0
VDD = 5.0V, /MR1 = /MR2 = VDD
3.2
5.0
VDD = 3.3V, /MR1 = /MR2 = GND
120
µA
Reset Time
Setup Period (tSETUP)
Reset Timeout Period (tRESET)
ANDOUT Debounce Time (tDB)
Output Low Voltage (VOL)
Open-Drain Leakage Current (ILEAKAGE)
Ordering Option: C
5.4
6
6.6
Ordering Option: D
7.2
8
8.8
Ordering Option: E
9.0
10
11
Ordering Option: F
10.8
12
13.2
Ordering Option: L
0.4
0.5
0.6
Ordering Option: M
0.9
1
1.1
s
Ordering Option: R
1.8
1
2
1.5
2.2
2
ms
V/MR1,2 < (VIL – 100mV)
VDD = 4.5V, ISINK = 1.6mA
0.3
VDD = 3.3V, ISINK = 1.2mA
0.3
VDD = 1.5V, ISINK = 0.5mA
0.3
RESET, ANDOUT Inactive
VRESET, VANDOUT = 5.5V
s
V
300
nA
0.4
V
75
kΩ
/MR1, /MR2 Input
1.2
Input High Voltage (VIH)
V
Input Low Voltage (VIL)
Internal Pull-Up Resistance (RPU)
55
For /MR1, /MR2
65
Notes:
1.
Exceeding the absolute maximum rating may damage the device.
2.
The device is not guaranteed to function outside its operating rating.
3.
Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
4.
Specification for packaged product only.
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MIC2782
Typical Characteristics
VDD Supply Current
vs. Supply Voltage
VDD Supply Current
vs. Temperature
4.4
3.0
2.6
2.2
1.8
1.4
TA = 25°C
/MR1 = NOT ASSERTED
/MR2 = NOT ASSERTED
3.6
2.8
2.0
1.2
-40
-15
10
35
60
2
1
4
5
6
-40
-15
SETUP PERIOD (s)
10.0
9.8
40
4
5
6
60
85
TA = 25°C
MIC2782ELYCS
10.2
100
35
11.0
10.4
160
10
Setup Period
vs. Supply Voltage
VDD = 3.3V
MIC2782ELYCS
220
3
119
TEMPERATURE (°C)
SETUP PERIOD (s)
SUPPLY CURRENT (µA)
3
10.6
TA = 25°C
/MR1 = /MR2 = GND
2
120
Setup Period
vs. Temperature
280
1
121
SUPPLY VOLTAGE (V)
Supply Current for /MR1 and
/MR2 Inputs Low
vs. Supply Voltage
0
VDD = 3.3V
/MR1 = /MR2 = GND
118
0
85
TEMPERATURE (°C)
10.5
10.0
9.5
9.0
-40
-15
SUPPLY VOLTAGE (V)
10
35
60
85
TEMPERATURE (°C)
0
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
Reset Timeout Period
vs. Supply Voltage
Reset Timeout Period
vs. Temperature
0.60
0.60
VDD = 3.3V
MIC2782ELYCS
RESET TIMEOUT PERIOD (s)
RESET TIMEOUT PERIOD (s)
122
SUPPLY CURRENT (µA)
VDD = 3.3V
/MR1 = NOT ASSERTED
/MR2 = NOT ASSERTED
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
3.4
Supply Current for /MR1 and
/MR2 Inputs Low
vs. Temperature
0.55
0.50
0.45
0.40
TA = 25°C
MIC2782ELYCS
0.55
0.50
0.45
0.40
-40
-15
10
35
TEMPERATURE (°C)
February 21, 2014
60
85
0
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
5
Revision 2.0
Micrel, Inc.
MIC2782
Timing Diagram
1.5V
VDD
1.5V
t > tDB
t = tDB
t = tDB
/MR1
/MR2
tRESET
tSETUP
RESET
UNDEFINED
STATE FOR
VDD < 1.5V
UNDEFINED
STATE FOR
VDD < 1.5V
ANDOUT
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MIC2782
Functional Diagram
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MIC2782
Functional Description
Design and Product Advantages
The MIC2782 is a dual push-button input reset IC with
extended setup delay times. It is used for generating a
hard reset for microcontrollers, PMICs or load
disconnect switches. The dual manual reset inputs and
long setup delay times help protect against accidental
system resets. The fixed Reset Timeout period allows for
more predictable phone or Tablet operation during
hardware resets. It is used in applications such as smart
phones, tablets, personal navigation devices, MP3
players and Set-Top Boxes (STB).
Keeping both manual reset inputs low for a longer time
does not generate additional RESET output pulses. Deasserting either manual reset input during the RESET
pulse duration, will not reset the Setup Timer. After the
RESET pin has de-asserted high, both the manual reset
inputs must be held high for more than a Debounce
Time to reset the Setup Timer.
ANDOUT Debounce Time is a de-glitch time, typically
1.5ms, that senses the asserting of both manual reset
inputs low together. A de-glitch time is needed if the
manual reset inputs come from noisy push-button
sources. If either manual reset inputs are asserted (or
de-asserted) for less than a Debounce Time, the
ANDOUT output will not respond.
General Functionality
As shown in Figure 1, if both /MR1 and /MR2 are
asserted low for longer than the Setup Period (tSETUP),
the RESET output will be asserted (logic-level low) for a
Reset Timeout Period (tRESET). During the Setup Period,
if either of the /MR1 or /MR2 inputs are de-asserted
high, then the Setup Period timer will be reset. To assert
the RESET output low again, both the /MR1 and /MR2
inputs will have to be asserted low together for the full
duration of the Setup period.
If both /MR1 and /MR2 are asserted low for longer than
the Debounce Time (tDB), then the ANDOUT output will
be asserted, (logic-level low). ANDOUT will remain
asserted low as long as both the /MR1 and /MR2 inputs
are asserted low. If either the /MR1 or /MR2 are deasserted for longer that the Debounce Time (tDB), then
the ANDOUT output will de-assert high.
Dual Manual Reset Inputs (/MR1, /MR2)
The /MR1, /MR2 are active-low manual inputs that have
integrated 65kΩ pull-up resistors to the VDD power
supply. If both inputs are asserted (logic-level low) for a
Setup Period (tSETUP), only one reset pulse, of width
tRESET, is generated. The behavior of the RESET and
ANDOUT outputs is independent of the order in which
the /MR1, /MR2 inputs are driven low. The MIC2782
consumes only 2µA when /MR1 and /MR2 manual inputs
are de-asserted (logic-level high) together. Current
consumption is typically 120µA when both manual inputs
are asserted low together and 55µA when only one of
the manual inputs is asserted low while the other manual
input is de-asserted high.
Outputs (RESET and ANDOUT)
The RESET and ANDOUT outputs are simple opendrain N-channel MOSFET structures that require a pullup resistor. For most applications, the pull-up voltage will
be the same as the power supply that supplies VDD to
the MIC2782. As shown in Figure 2, it is possible to tie
this resistor to some other voltage, other than VDD, thus
enabling level-shifting of the RESET or ANDOUT
outputs. The pull-up voltage must be limited to 5.5V to
avoid damaging the MIC2782. The pull-up resistor must
be small enough to supply current to the inputs and
leakage paths that are driven by the RESET or ANDOUT
outputs. A recommended value is 100kΩ.
Since the RESET and ANDOUT outputs are open-drain,
several reset sources can be wire-ORed, in parallel, to
allow resets from multiple sources.
Figure 1. Manual Reset Function
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Micrel, Inc.
MIC2782
+3.3V
VDD
RESET
+5V
100k
VCC
/RESET
MIC2782
µP
GND
GND
Figure 2. MIC2782 Used in Multiple Supply System
Bypass Capacitor from VDD to GND
A 0.1µF input bypass capacitor must be placed from
VDD (Pin C1) to GND (Pin C2).
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MIC2782
Typical Applications
VDD = 1.5V to 5.5V
0.1uF
100k
VDD
100k
/RESET
RESET
/MR1
LOAD SWITCH
or PMIC
or µP
MIC2782
/MR2
/MR
LOAD SWITCH
or PMIC
/RESET
or µP
ANDOUT
GND
PUSH-BUTTON
SWITCH
Figure 3. Single Button application for MIC2782 used for Microcontroller Reset
VDD = 1.5V to 5.5V
100k
VDD
0.1uF
LOAD SWITCH
or PMIC
or µP
/RESET
RESET
/MR1
100k
MIC2782
PUSH-BUTTON
SWITCH
/MR1
PUSH-BUTTON
SWITCH
/MR2
/MR2
LOAD SWITCH
or PMIC
/RESET
or µP
ANDOUT
GND
Figure 4. Dual Button application for MIC2782 used for Microcontroller Reset
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Micrel, Inc.
MIC2782
Evaluation Board Schematic
VDD
1.5V to 5.5V
U1
CBYP
0.1µF
VDD
VDD
RESET
B2
J7
SW1
J6
A2
/MR1
R2
100k
R1
100k
C1
J1
B1
J2
MIC2782
RESET
/MR1
/MR2
ANDOUT
A1
GND
PUSH-BUTTON
SWITCH
C2
SW2
J3
ANDOUT
J5
J4
/MR2
PUSH-BUTTON
SWITCH
Bill of Materials
Item
C1
Part Number
Manufacturer
(1)
GRM188R71C104KA01D
(2)
R1, R2
CRCW0603100KJNEA
U1
MIC2782ELYCS
(3)
Description
Qty.
Murata
0.1µF, 16V capacitor, X7R, 0603
Vishay
100k, 5% resistor, 0603
2
Dual-Input Push Button Reset IC
1
Micrel, Inc.
1
Notes:
1. Murata Tel: www.murata.com.
2. Vishay Tel: www.vishay.com.
3. Micrel, Inc.: www.micrel.com.
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MIC2782
PCB Layout Recommendations
Top Silkscreen
Copper Layer 1 (Top Layer)
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Micrel, Inc.
MIC2782
PCB Layout Recommendations (Continued)
Copper Layer 2 (Bottom Layer)
Bottom Silkscreen
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MIC2782
Package Information
6-Bump, 0.4mm Pitch 0.8mm × 1.2mm WLCSP (CS)
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Micrel, Inc.
MIC2782
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2012 Micrel, Incorporated.
February 21, 2014
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