Datasheet

MIC25400
2A Dual Output PWM Synchronous
Buck Regulator IC
General Description
Features
The MIC25400 is a synchronous PWM dual output step
down converter with internal 2A high-side switches. The
MIC25400 has an integrated low-side gate driver for
synchronous step-down conversion by connecting an
external N-channel MOSFET to achieve high efficiencies
in low duty-cycle applications. The IC’s switching
frequency is 1MHz. A patented control scheme allows the
use of a wide range of output capacitance from small
ceramic capacitors to large electrolytic types with only one
compensation component. A 2% output voltage tolerance
over the temperature range allows the maximum level of
system performance. The MIC25400 power good signal
allows full control for sequencing the output voltages with
minimum external components.
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An adjustable current limit allows the use of smaller
inductors in lower current applications.
The MIC25400 is available in the ePad 24-pin 4mm × 4mm
®
MLF package, and has an operating junction temperature
range of –40°C to +125°C.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
4.5V to 13.2V input voltage range
Adjustable output voltages down to 0.7V
2A per channel
180° out-of-phase operation
Low-side driver for synchronous operation
2% output voltage accuracy (over temperature)
1MHz switching frequency
Output voltage sequencing
Programmable maximum current-limit
Power good output
Ramp Control™ provides soft-start
Low-side current sensing allows very low duty-cycle
Works with ceramic output capacitors
24-pin 4mm × 4mm MLF package
Junction temperature range of –40°C to +125°C
Applications
• Multi-output power supplies with sequencing
• DSP, FPGA, CPU, and ASIC power supplies
• Telecom and networking equipment, servers
Typical Application
VIN
6.0V – 13.2V
22µF
VIN < 6.0V
10k
1.0µF
PVDD
PG1
PG1
10k
VIN
PG2
VIND1
VIND2
BST1
BST2
PG2
10µF
10µF
20
10nF
4.7µH
VOUT1
3.3V/2A
3.3nF
10nF
4.7µH
MIC25400
604
1.0k
20
22µF
SW1
SW2
CS1
CS2
LSD1
PGND1
FB1
VOUT2
1.2V/2A
604
22µF
LSD2
1.5nF
FB2
EN/DLY1 EN/DLY2
VEN1
1.0k
PGND2
VEN2
1.4k
274
10nF
68pF
COMP1
COMP2
AGND
47pF
10nF
MIC25400 Dual Output Buck Converter
Ramp Control is a trademark of Micrel, Inc.
MLF and MicroLead Frame are registered trademarks of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
July 11, 2013
Revision 1.4
Micrel, Inc.
MIC25400
Ordering Information
Part Number
MIC25400YML
Voltage
Switching Frequency
Temperature Range
Package
Lead Finish
Adjustable
1MHz
-40°C to +125°C
24-Pin 4mm × 4mm MLF
Pb-Free
Pin Configuration
24-Pin 4mm × 4mm MLF (ML)
(Top View)
Pin Description
Pin Number
Pin Name
Pin Description
1
BST1
Boost 1 (Input): Provides voltage for high-side internal MOSFET for channel 1. Connect a 0.01µF
capacitor from SW1 to BST1 pin and a diode-to-PVDD.
2
LSD1
Low-Side Drive 1 (Output): External low-side N-Channel MOSFET driver. Use 4.5V rated MOSFETs.
3
PGND1
4
CS1
Current Sense 1 (Input): Place a resistor from SW1 to this pin to program the current limit point from
0.5A to 2.7A.
5
PG1
Power Good 1 (Output): Open drain. Device is in the OFF state. i.e., high when output is within 90%
of regulation.
Power Ground 1 (Input).
Enable/Delay 1 (Input): This pin can be used to disable VOUT1. When used to disable VOUT1, this pin
must be pulled down to ground in less than 1µs for proper operation. It is also used for soft-start of
the output. Soft-start capacitor range is 4.7nF to 22nF (see the Functional Description section for
additional information).
6
EN/DLY1
7
COMP1
Compensation 1 (Input): Pin for external compensation, Channel 1.
8
FB1
Feedback 1 (Input): Input to Ch1 error amplifier. Regulates to 0.7V.
9
NC
No Connect.
10
AGND
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Analog Ground (Input): Control section ground. Connect to PGND.
2
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Micrel, Inc.
MIC25400
Pin Description (Continued)
Pin Number
Pin Name
11
FB2
12
COMP2
Pin Description
Feedback 2 (Input): Input to Channel 2 error amplifier. Regulates to 0.7V.
Compensation 2 (Input): Pin for external compensation, Channel 2.
Enable/Delay 2 (Input): This pin can be used to disable VOUT2. When used to disable VOUT2, this pin
must be pulled down to ground in less than 1µs for proper operation. It is also used for soft-start of
the output. Soft-start capacitor range is 4.7nF to 22nF (see the Functional Description section for
additional information).
13
EN/DLY2
14
PG2
Power Good 2 (Output) Open drain. Device is in the OFF state. i.e., high when output is within 90% of
regulation
15
CS2
Current Sense 2 (Input) Place a resistor from SW2 to this pin to program the current-limit point from
0.5A to 2.7A
16
PGND2
17
LSD2
Low-Side Drive 2 (Output): External low-side N-Channel MOSFET driver. Use 4.5V rated
MOSFETs.
18
BST2
Boost 2 (Input): Provides voltage for high-side internal MOSFET for Channel 2. Connect a 0.01µF
capacitor from SW2 to BST2 pin and a diode-to-PVDD.
19
SW2
Switch Node 2 (Output): Source of internal high-side power MOSFET.
20
VIND2
Supply voltage (Input): For the drain of internal high-side power MOSFET 4.5V to 13.2V.
21
PVDD
5V Internal Linear Regulator (Output): PVDD is the external MOSFET gate drive for LSD1 and LSD2
and an internal supply bus for the IC. Connect to an external 1µF bypass capacitor. When VIN is
<6V, this regulator operates in drop-out mode. Connect VDD to VIN when VIN <6V.
22
VIN
23
VIND1
24
SW1
Switch Node 1 (Output): Source of internal high-side power MOSFET.
EP
GND
Exposed thermal pad for package only. Connect to ground. Must make a full connection to the
ground plane to maximize thermal performance of the package.
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Power Ground 2 (Input)
Supply voltage (Input): For the internal 5V linear regulator. 4.5V to 13.2V.
Supply voltage (Input): For the drain of internal high-side power MOSFET 4.5V to 13.2V.
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Micrel, Inc.
MIC25400
Absolute Maximum Ratings(1)
Operating Ratings(2)
VIN to PGND .................................................... –0.3V to 16V
VIND1, VIND2 to PGND ........................................ –0.3V to 16V
VPVDD to PGND .................................................. –0.3V to 6V
VSW1, VSW2 to PGND ............................ –0.7V to (VIN + 0.3V)
VCS1, VCS2 to PGND ............................. –0.7V to (VIN + 0.3V)
VBST1 to VSW1, VBST2 to VSW2 ............................ –0.3V to 6.0V
VBST1, VBST2 to PGND ....................................... –0.3V to 22V
VEN/DLY1, VEN/DLY2 to PGND ............... –0.7V to (VPVDD + 0.3V)
VCOMP1, VCOMP2 to PGND .................. –0.7V to (VPVDD + 0.3V)
VFB1, VFB2 to PGND .......................... –0.7V to (VPVDD + 0.3V)
VPG1, VPG2 to PGND ......................... –0.7V to (VPVDD + 0.3V)
PGND1, PGND2 to AGND ........................... –0.3V to +0.3V
Junction Temperature ................................................ 150°C
Storage Temperature ............................... –65°C to +150°C
Lead Temperature (soldering,10s) ............................. 260°C
(3)
ESD Rating .................................................................. 2kV
Supply Voltage (VIN) ................................... +4.5V to +13.2V
Output Voltage Range (VOUT)…………….. .... 0.7V to 0.7*VIN
Maximum Output Current (IOUT)…………….. ................... 2A
Junction Temperature (TJ) ........................ –40°C to +125°C
Junction Thermal Resistance
4mm × 4mm MLF-24L (θJA) ............................... 35°C/W
Electrical Characteristics(4)
VIN = 12V; VEN = 5V; VOUT=1.8V; ILOAD=10mA; TA = 25°C, bold values indicate –40°C ≤ TJ ≤ +125°C, unless noted.
Parameter
Condition
Min.
Typ.
Max.
Units
13.2
V
Power Input Supply
Input Voltage Range (VIN)
4.5
Quiescent Supply Current
VFB = 0.8V, IOUT = 0A; Both outputs not switching
3.6
7
mA
Shutdown Current
VEN1 = VEN2 = 0V
360
425
µA
VIN UVLO Threshold
VIN Rising, PVDD open, for VIN≥6V
4.02
4.5
V
VIN UVLO Hysteresis
VIN ≥ 6V
VIN UVLO VIN <6V)
VIN Rising, PVDD connected to VIN, for VIN<6V
3.2
3.5
3.9
V
VFB = 0.8V, IPVDD = 75mA
4.7
5.1
5.4
V
Feedback Reference Voltage
±2% over temperature
686
700
714
mV
FB Bias Current
VFB = 0.7V
FB Line Regulation
3.6
150
mV
VDD Supply
Internal Bias Voltages PVDD
Reference (Each Channel)
5
nA
VIN = 6V to 13.2V, IOU T = 10mA
0.005
%/V
Output Voltage Line Regulation
VIN = 6V to 13.2V , VOUT = 1.8V, IOU T = 1A
0.005
%/V
Output Voltage Load Regulation
VOUT = 1.8V, IOU T = 0A to 2A
0.15
%
Output Voltage Total Regulation
VIN = 6V to 13.2V , IOU T = 0.25A to 2A, VOUT = 1.8V
0.1
%
Notes:
1. Exceeding the absolute maximum ratings may damage the device.
2. The device is not guaranteed to function outside its operating ratings.
3. Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5kΩ in series with 100pF.
4. Specification for packaged product only.
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Micrel, Inc.
MIC25400
Electrical Characteristics(4) (Continued)
VIN = 12V; VEN = 5V; VOUT=1.8V; ILOAD=10mA; TA = 25°C, bold values indicate –40°C ≤ TJ ≤ +125°C, unless noted.
Parameter
Condition
Min.
Typ.
Max.
Units
175
200
225
µA
External Current Sense, Adjustable
Current-Limit Trip Point Current
Sourcing current
Current-Limit Temperature
Coefficient
750
ppm/°C
−10
0
10
mV
0.8
1
1.2
MHz
70
75
%
15
ns
68
dB
150
mΩ
Pull Up, ISOURCE = 10mA
4
Ω
Pull Down; ISINK = 10mA
2.5
Ω
Into 1000pF
12
ns
Into 1000pF
9
ns
(Adaptive)
25
ns
Current-Limit Comparator Offset
Oscillator / PWM
Switching Frequency
Maximum Duty-cycle
Minimum On-Time
(5)
ILOAD > 200mA
Error Amplifier (each channel)
DC Gain
High-Side Internal MOSFET
On-Resistance RDS(ON)
IFET = 1A, VFB=0.8V
Low-Side MOSFET Driver
DH On-Resistance
DH Transition Time
Driver Non-Overlap Dead Time
EN/DLY and Soft-Start Control
EN/DLY Pull-Up Current
VEN/DLY=0V
5.0
6.5
8.0
µA
PVDD Threshold
PVDD turns on
0.3
0.4
0.6
V
Soft-Start Begins Threshold
Channel soft-start begins
1
1.35
1.8
V
Soft-Start Ends Threshold
Channel soft-start ends
2
2.4
2.8
V
PG Threshold Voltage
VOUT Rising (% of VOUT nominal)
86
90
94
%Nom
PG Output Low Voltage
VFB = 0V, IPG = 1mA
0.24
0.3
V
PG Leakage Current
VFB = 800mV, VPG = 5.5V
Power Good
5
nA
172
°C
22
°C
Thermal Protection
Overtemperature Shutdown
TJ Rising
Overtemperature Shutdown
Hysteresis
Note:
5. Minimum on-time before automatic cycle skipping begins (see Application Information).
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Micrel, Inc.
MIC25400
Typical Characteristics
IDD_ON vs.
Input Voltage
IDD_OFF vs.
Input Voltage
60
1.40
25°C
55
-40°C
ENABLE THRESHOLD (V)
6
50
5
25°C
IDD_ON (mA)
IDD_OFF (mA)
Enable Threshold
vs. Input Voltage
4
3
45
40
-40°C
35
85°C
30
85°C
1.38
25°C
1.36
1.34
85°C
1.32
-40°C
25
2
20
6
8
10
INPUT VOLTAGE (V)
12
1.30
10
8
INPUT VOLTAGE (V)
6
6
Output Voltage
vs. Input Voltage
Current Limit Threshold
vs. Input Voltage
3.33
25°C
3.05
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.10
3.30
85°C
3.25
-40°C
6
100.0
100.0
90.0
90.0
80.0
80.0
70.0
60.0
5Vo
40.0
1.8Vo
1.2Vo
0.7Vo
30.0
3.29
3.28
85°C
3.27
-40°C
3.26
3.25
VIN = 12V
VOUT = 3.3V
8
10
12
INPUT VOLTAGE (V)
0.0
0.5
1.0
1.5
OUTPUT CURRENT(A)
2.0
5VIN Efficiency
vs. Output Current (09)
EFFICIENCY (%)
EFFICIENCY (%)
12VIN Efficiency
vs. Output Current (09)
50.0
3.30
3.23
6
8
10
12
INPUT VOLTAGE (V)
3.31
3.24
3.20
3.00
25°C
3.32
25°C
3.15
8
10
12
INPUT VOLTAGE (V)
Load Regulation
3.35
3.20
CURRENT LIMIT THRESHOLD (A)
12
70.0
60.0
50.0
1.8Vo
1.2Vo
0.7Vo
40.0
30.0
20.0
20.0
0.0
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0.5
1.0
1.5
OUTPUT CURRENT (A)
2.0
0.0
0.5
1.0
1.5
OUTPUT CURRENT (A)
6
2.0
Revision 1.4
Micrel, Inc.
MIC25400
Functional Characteristics
July 11, 2013
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Micrel, Inc.
MIC25400
Functional Diagram
BST1,2
VIND1,2
PWM
Vref
ramp
FB1,2
Drive
SW1,2
clk
Ph1,2
COMP1,2
LSD1,2
AVDD
EN/DLY1,2
PGND1,2
Soft Start
AVDD
CS1,2
Logic
Enable
Current
Limit
UVLO
PG1,2
Vref-10%
Power Good
PWM Core
MIC25400 Block Diagram
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Micrel, Inc.
MIC25400
Functional Description
The MIC25400 is a dual output, synchronous buck
regulators. Output regulation is performed using a fixed
frequency, voltage mode control scheme. The fixed
frequency clock drives the two sections 180° out of
phase, which reduces input ripple current.
The dropout of the internal regulator causes VPVDD to drop
when VIN is below 6V. When operating below 6V, the
PVDD pin must be jumpered to VIN. This bypasses the
internal LDO and prevents VPVDD from dropping out.
A 1µF ceramic capacitor should be used to decouple
VPVDD-to-ground.
Oscillator
An internal oscillator provides a clock signal to each of
the two sides. The clock signals are 180° out of phase
with the other. Each phase is used to generate a ramp for
the PWM comparator and a clock pulse that terminates
the switching cycle. The MIC25400 oscillator frequency is
nominally 1MHz.
EN/DLY
The EN/DLY pins are used to turn on, turn off and softstart the outputs. The pins can be controlled with an open
collector or open drain device as shown in Figure 1. It
must not be actively driven high or damage will result.
When disabling the output with an external device, the
enable pin turn-off time must be less than 1µs.
UVLO
The UVLO monitors voltage on the VIN pin. The circuit
controls both regulators (side 1 and side 2). It disables
the output drivers and discharges the EN/DLY capacitor
when VIN is below the UVLO threshold. As VIN rises
above the threshold, the internal high-side FET drivers
and external low-side drives are enabled and the EN/DLY
pins are released.
A low impedance source should be used to supply input
voltage to the MIC25400. When VIN drops below the
UVLO threshold and the outputs turn off, the change in
input current will cause VIN to slight rise. The output
voltage will momentarily turn back on if the rise in VIN is
greater than the UVLO hysteresis.
Figure 1. Enable and Soft-Start Circuit
The preferred method is to use the EN/DLY pins, as
shown in Figure 1, for startup and shutdown of the
outputs. This avoids the possibility of glitching during
startup and shutdown. If an external control signal is not
available, the circuit in Figure 2 may be used to set a
higher turn-on and turn-off threshold than the internal
UVLO circuit. Moreover, the hysteresis is adjustable and
can accommodate a wider input source impedance
range. Refer to the MIC841 datasheet for additional
information on selecting the resistor values.
Supply Input
Voltage
MIC25400
MIC841LYC5
VDD
R1
75k
1μF
EN/DLY1,2
AVDD
Soft Start
logic
HTH
R2
2k
R3
20k
Regulator/Reference
The internal regulator generates a PVDD pin voltage that
powers the high-side MOSFET and low-side gate drive
circuits. It also generates an internal analog voltage,
AVDD, which is used by the low level analog and digital
sections. The AVDD voltage is also used by the bandgap
to generate a nominal 700mV for the error amplifier
reference. The output undervoltage and power good
circuits use the bandgap for their references.
July 11, 2013
VDD
OUT
LTH
BSS138
CSS
Internal
Discharge
GND
Figure 2. Adjustable UVLO Start-Up Circuit
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Micrel, Inc.
MIC25400
Minimum Output Load when Disabled
When one output is disabled and the other enabled, then
the disabled output requires a minimum output load to
prevent its output voltage from rising. Typically, a 2kΩ
load on the output will keep the output voltage below
100mV. The output setting voltage divider resistors may
be used for the 2kΩ load if the total resistance is set low
enough. A separate output resistor should be used for
lower output voltages since the voltage divider resistance
becomes impractically low.
The output voltage rise time can be calculated by
Equation 2:
tD =
Power Good
Power good is an open drain signal that asserts when
VOUT exceed the power good threshold. The circuit
monitors the FB pin. The internal FET is turned on while
the FB voltage is below the FB threshold. When voltage
on the FB in exceeds the FB threshold, the FET is turned
off. A pull-up resistor can be connected to PVDD or and
external source. The external source voltage must not
exceed the maximum rating of the pin. The PG pin can
be connected to another regulator’s EN/DLY pin for
sequencing of the outputs. A pull-up resistor is not used
when the power good pin is connected to another
regulators EN/DLY pin.
Output Sequencing
Sequencing of the outputs is shown in Figure 4. The
power good pin is used to disable VOUT2 until the VOUT1
reaches regulation. Sequencing waveforms are shown in
Figure 4.
A capacitor, CSS, is connected to the EN/DLY pin. The
CSS capacitor range is 4.7nF to 22nF. Releasing the pin
allows an internal current source to charge the capacitor.
The delay between the EN/DLY pin release and when
VOUT starts to rise can be calculated by Equation 1.
ISS
Eq. 2
• VThreshold_End is the EN/DLY pin voltage where the output
reaches regulation.
Figure 3. Soft-Start Timing Diagram
C SS × VThreshold_Start
ISS
where:
Soft-Start
Enable and soft-start waveforms are shown in Figure 3.
tD =
C SS × (VThreshold_End − VThreshold_Start )
Eq. 1
where:
• CSS is the soft-start capacitor.
• ISS is the internal soft-start current (200µA nominal).
• VThreshold_start is the EN/DLY pin voltage where the
output starts to rise (1.35V nominal).
The output voltage starts to rise when voltage on the
EN/DLY pin reaches the start threshold. The output
voltage reaches regulation when the EN/DLY pin voltage
reaches the end threshold.
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Figure 4. Output Sequencing
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Micrel, Inc.
MIC25400
Figure 5. Output Sequencing Waveforms
The MIC25400 must start up without a pre-biased output
voltage. During start up, the MIC25400 pulls the output to
ground if it is above 0V. This may cause the output to ring
below ground and excessive voltage on the VSW node. A
pre-bias condition can occur if the output is turned off
then immediately turned back on before the output
capacitor is discharged to ground. It is also possible that
the output of the MIC25400 could be pulled up or prebiased through parasitic conduction paths from one
supply rail to another in multiple voltage level ICs like a
FPGA.
Figure 6. High-Side Drive Circuitry
Low-Side Drive Output
The LSD pin is used to drive an external MOSFET. This
MOSFET is driven out of phase with the internal highside MOSFET to conduct inductor current during the
high-side MOSFETs off-time. Circuitry internal to the
regulator prevents short circuit “shoot-through” current
from flowing by preventing the high-side and low-side
MOSFETs from conducting at the same time.
High-Side Drive
The internal high-side drive circuit is designed to switch
the internal N-channel MOSFET. Figure 6 shows a
diagram of the high-side MOSFET, gate drive and
bootstrap circuit. D2 and CBST comprise the bootstrap
circuit, which supplies drive voltage to the high-side
MOSFET. Bootstrap capacitor CBST is charged through
diode D2 when the low-side MOSFET turns on and pulls
the SW pin voltage-to-ground. When the high-side
MOSFET driver is turned on, energy from CBST charges
the MOSFET gate, turning it on. Voltage on the SW pin
increases to approximately VIN. Diode D2 is reversed
biased and CBST flies high while maintaining gate voltage
on the high-side MOSFET.
The low-side MOSFET gate voltage is supplied from
VPVDD. Turn off of the MOSFET is accomplished by
discharging the gate through the LSD pin. The return
path is through the PGND pin and back to the MOSFET’s
source pin. These circuit paths must be kept short to
minimize noise. See the layout section of this datasheet
for additional information.
Driving the low-side MOSFET on and off dissipates
power in the MIC25400 regulator. The power can be
calculated by the equation below:
PDRIVER = Q G × VGS × f S
A resistor should be added in series with the BST1 and
BST2 pins. This will slow down the turn-on time of the
high-side MOSFET while leaving the turn-off time
unaffected. Slowing down the MOSFET rise time will
reduce the turn-on overshoot at the switch node, which is
important when operating with an input voltage close to
the maximum operating voltage.
where:
• PDRIVER is the power dissipated in the regulator by
switching the MOSFET on and off.
• QG is the total Gate charge of the MOSFET at VGS.
• VGS is the MOSFET’s Gate to Source voltage which is
equal to the voltage on PVDD.
• fS is the switching frequency of the regulator (1MHz
nominal).
The recommended capacitor for CBST is a 0.01µF
ceramic capacitor. The recommended value for RBST is
20Ω.
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Eq. 3
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Micrel, Inc.
MIC25400
dV/dT-Induced Turn-On of the Low-Side MOSFET
As the high-side MOSFET turns on, the rising dv/dt on
the switch-node forces current through CGD of the lowside MOSFET causing a glitch on its gate. Figure 7
demonstrates the basic mechanism causing this issue. If
the glitch on the gate is greater than the MOSFET’s turnon threshold, it may cause an unwanted turn-on of the
low-side MOSFET while the high-side MOSFET is on. A
short circuit between input and ground would
momentarily occur, which lowers efficiency and increases
power dissipation in both FETs. Additionally, turning on
the low-side FET during the off-time could interfere with
overcurrent sensing.
Current Limit
The MIC25400 uses the synchronous (low-side)
MOSFET’s RDSON to sense an over-current condition.
The low-side MOSFET is used because it displays lower
parasitic oscillations after switching than the upper
MOSFET. Additionally, it improves the accuracy and
reduces false tripping at lower voltage outputs and
narrow duty cycles since the off-time increases as dutycycle decreases. Figure 8 shows how over current
protection is performed using the low-side MOSFET.
Figure 8. Overcurrent Circuit
Inductor current, IL, flows from the lower MOSFET source
to the drain during the off-time, causing the drain voltage
to become negative with respect to ground. This negative
voltage is proportional to the instantaneous inductor
current times the MOSFET RDSON. The low-side
MOSFET voltage becomes even more negative as the
output current increases.
Figure 7. dv/dt-Induced Turn-On of the Low-Side MOSFET
The over-current circuit operates by passing a known
fixed current source through a resistor RCS. This sets up
an offset voltage (ICS x RCS) that is compared to the VDS of
the low-side FET. When ISD (source-to-drain current) x
RDSON is equal to this voltage the soft-start circuit is reset
and a hiccup current mode is initiated to protect the
power supply and load from excessive current during
short circuits.
The following steps can be taken to lower the gate drive
impedance, minimize the dv/dt-induced current and lower
the FET’s susceptibility to the induced glitch:
• Chose a low-side MOSFET with a high CGS/CGD ratio
and a low internal gate resistance
• Do not put a resistor between the LSD output and the
gate.
• Insure both the gate drive and return etch are short,
low inductance connections.
• Use a 4.5V VGS rated MOSFET. Its higher gate
threshold voltage is more immune to glitches than a
2.5V or 3.3V rated MOSFET. MOSFETs that are rated
for operation at less than 4.5 VGS should not be used.
• Add a resistor in series with the BST pin. This will slow
down the turn-on time of the high-side MOSFET while
leaving the turn-off time unaffected.
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Micrel, Inc.
MIC25400
Current-Limit Calculations and Maximum Peak Limit
The current limit method requires careful selection of the
inductor value and saturation current. If a short circuit
occurs during the off-time, the overcurrent circuit will take
up to a full cycle to detect the overcurrent once it exceeds
the overcurrent limit. The worst case occurs if the output
current is 0A and a hard short is applied to the output.
The short circuit causes the output voltage to fall, which
increases the pulse width of the regulator. It may take
three or four cycles for the current to build up in the
inductor before current limit forces the part into hiccup
mode. The wider pulse width generates a larger peak to
peak inductor current which can saturate the inductor.
The output voltage is determined by Equation 4.
R1 

VOUT = VREF × 1 +

R2


Eq. 4
where: VREF is 0.7V nominal.
If the voltage divider resistance is used to provide the
minimum load (see “EN/DLY” sub-section) then R1
should be low enough to provide the necessary
impedance.
For this reason, the minimum inductor value for the
MIC25400 is 4.7µH and the maximum peak current-limit
set point is 2.7A. The saturation current for each of these
inductors should be at least 1.5A higher than the
overcurrent limit setting.
Once R1 is selected, R2 can be calculated with the
following formula:
R2 =
Voltage Setting Components
The regulator requires two external resistors to set the
output voltage as shown in Figure 9.
VREF × R1
VOUT − VREF
Eq. 5
Minimum Pulse Width
Output voltage is regulated by adjusting the on-time pulse
width of the high-side FET. This is accomplished by
comparing the error amplifier output with a sawtooth
waveform (see Functional Diagram). The pulse width
output of the comparator becomes smaller as the error
amplifier voltage decreases. Due to propagation delay
and other circuit limitations, there is a minimum pulse
width at the output of the comparator. If the error amplifier
voltage drops any further, then the output of the
comparator will be low.
The PWM circuit will skip pulses if a smaller duty-cycle is
required to maintain output voltage regulation. This
effectively cuts the output frequency in half.
Figure 9. Setting the Output Voltage
Thermal Protection
The internal temperature of the regulator is monitored to
prevent damage to the device. Both outputs are inhibited
from switching if the over-temperature threshold is
exceeded. Hysteresis in the circuit allows the regulator to
cool before turning back on.
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MIC25400
Application Information
Component Selection
Inductor
The value of inductance is determined by the peak to
peak inductor current. Higher values of inductance
reduce the inductor current ripple at the expense of a
larger inductor. Smaller inductance values allow faster
response to output current transients but increase the
output ripple voltage and require more output
capacitance.
Maximizing efficiency requires the proper selection of
core material and minimizing the winding resistance. The
high-frequency operation of the MIC25400 requires the
use of ferrite materials. Lower cost iron powder cores
may be used but the increase in core loss will reduce the
efficiency of the power supply. This is especially
noticeable at low output power. The inductor winding
resistance decreases efficiency at the higher output
current levels. The winding resistance must be minimized
although this usually comes at the expense of a larger
inductor.
The inductor value and saturation current are also
controlled by the method of overcurrent limit used (see
explanation in the previous section). The minimum value
of inductance for the MIC25400 is 4.7µH.
The power dissipated in the inductor equals the sum of
the core and copper losses. Core loss information is
usually available from the magnetics vendor.
The peak-to-peak ripple current may be calculated using
the Equation 6:
IPP =
VOUT ⋅ (η ⋅ VIN(max) − VOUT )
η ⋅ VIN(max) ⋅ f S ⋅ L
Input Capacitor
A 10μF ceramic is suggested on each of the VIN pins for
bypassing. X5R or X7R dielectrics are recommended for
the input capacitor. Y5V dielectrics should not be used.
Besides losing most of their capacitance over
temperature, they also become resistive at high
frequencies, which reduce their ability to filter out high
frequency noise.
Eq. 6
where:
•
•
•
•
IPP is the peak to peak inductor ripple current
L is the value of inductance
fS is the switching frequency of the regulator
η is the efficiency of the power supply
Output Capacitor
The MIC25400 regulator is designed for ceramic output
capacitors although tantalum and Aluminum Electrolytic
may also be used.
Output ripple voltage is determined by the magnitude of
inductor current ripple, the output capacitor’s ESR and
the value of output capacitance. When using ceramic
output capacitors, the primary contributor to output ripple
is the value of capacitance. Output ripple using ceramic
capacitors may be calculated using Equation 9:
Efficiency values from the Functional Characteristics
section can be used for these calculations.
The peak inductor current in each channel is equal to the
average output current plus one half of the peak-to-peak
inductor ripple current:
IPK = IOUT + 0.5 × IPP
Eq. 7
C OUT ≥
IPP
8 ⋅ ΔVOUT ⋅ 2 ⋅ f S
Eq. 9
2
The RMS inductor current is used to calculate the I R
losses in the inductor:
IINDUCTORRMS = IOUT ⋅ 1 +
July 11, 2013
1  IPP 

3 I
 OUT 
where:
• ΔVOUT is the peak-to-peak output voltage ripple
• IPP is the peak-to-peak ripple current as see by the
capacitors
• fS is the switching frequency (1MHz nominal).
2
Eq. 8
14
Revision 1.4
Micrel, Inc.
MIC25400
Figure 10 shows the low-side MOSFET current
waveform. Peak current is measured after a small delay.
The equations used to calculate the current limit resistor
value are illustrated in Equation 13:
When using tantalum or aluminum electrolytic capacitors,
both the capacitance and ESR contribute to output ripple.
The total ripple is calculated as shown in Equation 10:
2


I PP
2
ΔVOUT = 
 + [I PP ⋅ R ESR ]
 8 ⋅ C OUT ⋅ 2 ⋅ f S 
Eq. 10
IPK = IOUT +
IPP
2
IOC = IPK −
VOUT ⋅ TDLY
L
R CS =
The output capacitor RMS current is calculated by
Equation 11:
IOC ⋅ RDS ON
ICS
Eq. 13
where:
ICOUTRMS =
IPP
•
•
•
•
IOC is the current-limit set point
L = inductor value
TDLY = Current-limit blanking time ~ 100ns
ICS is the overcurrent pin sense current (200µA
nominal)
• RDSON is the on resistance of the low-side MOSFET
Eq. 11
12
The power dissipated in the output capacitors can be
calculated by Equation 12:
(
PDISSCOUT = ICOUTRMS
)2 ⋅ R ESR
Snubber
A snubber is used to damp out high frequency ringing
caused by parasitic inductance and capacitance in the
buck converter circuit. Figure 11 shows a simplified
schematic of one of the buck converter phases. Stray
capacitance consists mostly of the two MOSFET’s output
capacitance (COSS). The stray inductances are mostly
package and etch inductance. The arrows show the
resonant current path when the high-side MOSFET turns
on. This ringing causes stress on the semiconductors in
the circuit as well as increased EMI.
Eq. 12
Current-Limit Resistor
The current-limit circuit responds to the peak inductor
current flowing through the low-side FET. Calculating the
current setting resistor RCS should take into account the
peak inductor current and the blanking delay of
approximately 100ns.
Figure 10. Overcurrent Waveform
Figure 11. Output Parasitics
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Micrel, Inc.
MIC25400
Step 1: First measure the ringing frequency on the switch
node voltage when the high-side MOSFET turns on. This
ringing is characterized by Equation 14:
One method of reducing the ringing is to use a resistor to
lower the Q of the resonant circuit. The circuit in Figure
12 shows an RC network connected between the switch
node and ground. Capacitor CS is used to block DC and
minimize the power dissipation in the resistor. This
capacitor value should be between five and ten times the
parasitic capacitance of the MOSFET COSS. A capacitor
that is too small will have high impedance and prevent
the resistor from damping the ringing. A capacitor that is
too large causes unnecessary power dissipation in the
resistor, which lowers efficiency.
f1 =
1
2π L P ⋅ C P
Eq. 14
where:
• CP and LP are the parasitic capacitance and inductance
The snubber components should be placed as close as
possible to the low-side MOSFET and/or external
Schottky diode since in contributes to most of the stray
capacitance. Placing the snubber too far from the FET or
using an etch that is too long or too thin adds inductance
to the snubber and diminishes its effectiveness.
Step 2: Add a capacitor, CS, in parallel with the
synchronous MOSFET, Q2. The capacitor value should
be approximately three times the COSS of Q2. Measure
the frequency of the switch node ringing, f2:
f2 =
1
2π LP ⋅ (CS + CP )
Eq. 15
Define f’ as:
f' =
f1
f2
Eq. 16
Combining the equations for f1, f2 and f’ to derive CP, the
parasitic capacitance:
CP =
Figure 12. Snubber Circuit
Proper snubber design requires the parasitic inductance
and capacitance be known. A method of determining
these values and calculating the damping resistor value
is outlined below.
Eq. 17
2 ⋅ (f ' ) 2 − 1
LP is solved by re-arranging the equation for f1:
LP =
1. Measure the ringing frequency at the switch node
which is determined by parasitic LP and CP. Define
this frequency as f1.
2. Add a capacitor CS (normally at least 3 times as big
as the COSS of the FET) from the switch node-toground and measure the new ringing frequency.
Define this new (lower) frequency as f2. LP and CP
can now be solved using the values of f1, f2 and CS.
1
(2π )
2
⋅ C P ⋅ (f1 ) 2
Eq. 18
Step 3: Calculate the damping resistor.
Critical damping occurs at Q = 1:
Q=
3. Add a resistor RS in series with CS to generate critical
damping.
July 11, 2013
CS
16
1
RS
LP
=1
CS + CP
Eq. 19
Revision 1.4
Micrel, Inc.
MIC25400
Solving for RS:
RS =
The average current required to drive the MOSFETs is:
IDD = Q G ⋅ f S
LP
CS + CP
Eq. 22
Eq. 20
where:
• QG is the gate charge for both of the external
MOSFETs. This information should be obtained from
the manufacturer’s data sheet.
Figure 12 shows the snubber in the circuit and the
damped switch node waveform.
The snubber capacitor, CS, is charged and discharged
each switching cycle. The energy stored in CS is
dissipated by the snubber resistor, RS, two times per
switching period. This power is calculated in Equation
21:
Psnubber = f S ⋅ C S ⋅ VIN
2
Since current from the gate drive is supplied by the input
voltage, power dissipated in the MIC25400 due to gate
drive is:
PGATE_DRIVE = Q G ⋅ f S ⋅ VIN
Eq. 21
Eq. 23
where:
Parameters that are important to MOSFET selection are:
• fS is the switching frequency for each phase
• VIN is the DC input voltage
• Voltage rating
• On resistance
• Total Gate Charge
Low-Side MOSFET Selection
An external N-channel logic level power MOSFET must
be used for the low-side switch. The MOSFET gate-tosource drive voltage of the MIC25400 is regulated by an
internal 5V regulator. Logic level MOSFETs, whose
operation is specified at VGS = 4.5V must be used. Use of
MOSFETs with a lower specified VGS (such as 3.3V or
2.5V) are not recommended since the low threshold can
cause them to turn on when the high-side FET is turning
on. When operating the regulator below a 6V input,
connect VDD to VIN to prevent the VDD regulator from
dropping out.
The MOSFET is subjected to a VDS equal to the input
voltage. A safety factor of 20% should be added to the
VDS(max) of the MOSFET to account for voltage spikes due
to circuit parasitics. Generally, 30V MOSFETs are
recommended for all applications since lower VDS rated
MOSFETs tend to have a VGS rating that is lower than the
recommended 4.5V.
RMS Current and MOSFET Power Dissipation
Calculation
Switching loss in the low-side MOSFET can be neglected
since it is turned on and off at a VDS of 0V. The power
dissipated in the MOSFET is mostly conduction loss
during the on-time (PCONDUCTION):
Total gate charge is the charge required to turn the
MOSFET on and off under specified operating conditions
(VDS and VGS). The gate charge is supplied by the
regulator’s gate drive circuit. Gate charge is a source of
power dissipation in the regulator due to the high
switching frequencies. At low output load this power
dissipation is noticeable as a reduction in efficiency.
2
PCONDUCTION = ISWITCH RMS ⋅ RDS ON
Eq. 24
where:
• RDSON is the on resistance of the MOSFET switch.
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Micrel, Inc.
MIC25400
The RMS value of the MOSFET current is:
Compensation is necessary to insure the control loop has
adequate bandwidth and phase margin to properly
respond to input voltage and output current transients.
High gain at DC and low frequencies is needed for
accurate output voltage regulation. Attenuation near the
switching frequency prevents switching frequency noise
from interfering with the control loop.
2
2
ISW_RMS = (1 − D) ⋅ (IOUT_MAX +
IPP
)
12
Eq. 25
The output filter contains a complex double pole formed
by the capacitor and inductor and a zero from the output
capacitor and it’s ESR. The transfer function of the filter
is:
where:
• D is the duty-cycle of the converter
IPP is the inductor ripple current:
1+
D=
VOUT
η ⋅ VIN
Gfilter(s) =
Eq. 26
where:
s
s
+
1+
ωo
Q ωo
2
Eq. 27
where:
• η is the efficiency of the converter.
External Schottky Diode
A freewheeling diode in parallel with the low-side FET is
needed to maintain continuous inductor current flow while
both MOSFETs are turned off (dead-time). Dead-time is
necessary to prevent current from flowing unimpeded
through both MOSFETs. An external Schottky diode is
used to bypass the low-side MOSFET’s parasitic body
diode. An external diode improves efficiency due to its
lower forward voltage drop as compared to the internal
parasitic diode in the FET. It may also decrease high
frequency noise because the Schottky diode junction
does not suffer from reverse recovery.
ωz =
1
C O ⋅ R ESR
ωo =
1
Q =R⋅
CO ⋅ L O
CO
L
The modulator gain is proportional to the input voltage
and inversely proportional to the internal ramp voltage
generated by the oscillator. The peak-peak ramp voltage
is 1V:
An external Schottky diode conducts at a lower forward
voltage preventing the body diode in the MOSFET from
turning on. The lower forward voltage drop dissipates
less power than the body diode. Depending on the circuit
components and operating conditions, an external
Schottky diode may give up to 1% improvement in
efficiency.
 VIN
Gmod = 
 VRAMP



Eq. 28
The output voltage divider attenuates VOUT and feeds it
back to the error amplifier. The divider gain is:
Compensation
The voltage regulation, filter and power stage section is
shown in Figure 13. The error amplifier regulates the
output voltage and compensates the voltage regulation
loop. It is a simplified type III compensator utilizing two
compensating zeros and two poles. Figure 12 also shows
the transfer function for each section.
July 11, 2013
s
ωz
H=
18
V
R4
= REF
R1 + R4 VOUT
Eq. 29
Revision 1.4
Micrel, Inc.
MIC25400
Figure 13. Voltage Loop and Transfer Functions
The modulator, filter and voltage divider gains can be
multiplied together to show the open loop gain of these
parts.
Gvd Transfer Function
50
90
40
60
30
Gain
20
Eq. 30
GAIN (dB)
Gvd(s) = Gfilter(s) ⋅ H ⋅ Gmod
This transfer function is plotted in Figure 14. At low
frequency, the transfer function gain equals the
modulator gain times the voltage divider gain. As the
frequency increases toward the LC filter resonant
frequency, the gain starts to peak. The increase in the
gain’s amplitude equals Q. Just above the resonant
frequency, the gain drops at a -40db/decade rate. The
phase quickly drops from 0° to almost 180° before the
phase boost of the zero brings it back up to -90°. Higher
values of Q will cause the phase to drop quickly. In a well
damped, low Q system the phase will change more
slowly.
Phase
0
-60
-90
-10
-20
-30
-40
0
-30
10
VIN = 12V
-120
VOUT = 1.8V
-150
COUT = 20µF
L = 4.7µH
-180
-50
10
100
PHASE (°)
30
1000
10000
-210
100000 1000000
FREQUENCY (Hz)
Figure 14. Gvd Transfer Function
If the output capacitance and/or ESR is high, the zero
moves lower in frequency and helps to boost the phase,
leading to a more stable system.
As the frequency approaches the zero frequency (fZ)
formed by CO and its ESR, then the slope of the gain
curve changes from -40db/dec. to -20db/dec and the
phase increases. The zero causes a 90° phase boost.
Ceramic capacitors, with their smaller values of
capacitance and ESR, push the zero and its phase boost
out to higher frequencies, which allow the phase lag from
the LC filter to drop closer to -180°. The system will be
close to being unstable if the overall open loop gain
crosses 0dB while the phase is close to −180°.
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Micrel, Inc.
MIC25400
Error Amplifier Poles and Zeros
The error amplifier has internal poles and zeros that can
be shifted in frequency with an external capacitor. The
general form of the error amplifier compensation is shown
in Equation 31:
Gea(s) = G DC
s 
s 

1 +
1 +

ωz1
ωz2



×

s 
s 

1 +
1 +
ωp1 
ωp2 

The general form of the feed-forward circuit is illustrated
in Equation 32.
s 

1 +

ωz3 
R2

×
H(s) =
R1 + R2 
s 

1 +
ωp3 

Eq. 31
Eq. 32
where:
1
2 × π × R1 × C1
1
fp3 =
 R1 × R2 
2 × π × C1 × 

 R1 + R2 
fz3 =
The GDC is the DC gain of the error amplifier. It is
internally set to 2500 (68dB).
As illustrated in Figure 13, there are two compensating
zeros. ωz1 is internally set with R3 and C3. The zero
frequency is fixed at a nominal 16kHz in the MIC25400.
The second zero, ωz2, is set by the external capacitor,
C2.
The total open loop transfer function is:
For the MIC25400:
R3 = 100k
C3 = 100pf
fz1 =
fz2 =
T(s) = Gea(s) × Gmod × Gfilter(s) × H(s)
1
= 16kHz
2 × π × R3 × C3
1
Table 1 list the recommended values of compensation
and filter components for different output voltages. The
output capacitors are ceramic.
2 × π × 21 ⋅ 10 3 × C2
Table 1. Recommended Compensation Values and Filter
Components for MIC25400
The two compensating pole frequencies are shown
below.
fp1 = 250Hz
fp2 =
1
2 × π × 12 ⋅ 10 3 × C2
fp2 and fz2 both depend on the value of C2 and are
proportionally spaced in frequency with the zero at a
lower frequency than the pole. This provides gain and
phase boost in the control loop.
VIN
VOUT
R1
R2
C2
C1
Lo
Co
12V
1.0V
1k
2.32k
47pF
1.5nF
4.7µH
22µF
12V
1.2V
1k
1.4k
47pF
1.5nF
4.7µH
22µF
12V
1.4V
1k
1k
47pF
1.5nF
4.7µH
22µF
12V
1.8V
1k
634
47pF
1.5nF
4.7µH
22µF
12V
2.5V
1k
383
47pF
3.3nF
4.7µH
22µF
12V
3.3V
1k
274
68pF
3.3nF
4.7µH
22µF
12V
5.0V
1k
162
68pF
3.3nF
4.7µH
22µF
Voltage Divider Feed-Forward Capacitor
The capacitor across the upper voltage divider resistor
boosts the gain and phase of the control loop by short
circuiting the high-side resistor at higher frequencies. The
capacitor and upper resistor form a zero at a lower
frequency. The capacitor and parallel combination of
upper and lower resistors form a pole at a higher
frequency. This phase boost circuit is most effective at
higher output voltages, where there is a larger
attenuation from the voltage divider resistors.
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Micrel, Inc.
MIC25400
PCB Layout Guidelines
Warning!!! To minimize EMI and output noise, follow
these layout recommendations.
• If a Tantalum input capacitor is placed in parallel with
the input capacitor, it must be recommended for
switching regulator applications and the operating
voltage must be derated by 50%.
• In “Hot-Plug” applications, a Tantalum or Electrolytic
bypass capacitor must be used to limit the over-voltage
spike seen on the input supply with power is suddenly
applied. The value must be sufficiently large to prevent
this voltage spike from exceeding the maximum
voltage rating of the MIC25400.
• An additional Tantalum or Electrolytic bypass input
capacitor of 22µF or higher is required at the input
power connection.
PCB Layout is critical to achieve reliable, stable and
efficient performance. A ground plane is required to
control EMI and minimize the inductance in power, signal
and return paths.
The following guidelines should be followed to insure
proper operation of the MIC25400 converter.
IC
• Place the IC and the external Low-side MOSFET close
to the point of load (POL).
• Use fat traces to route the input and output power
lines.
• The exposed pad (EP) on the bottom of the IC must be
connected to the ground.
• Use several vias to connect the EP to the ground plane
on layer 2.
• Signal and power grounds should be kept separate
and connected at only one location, the EP ground of
the package.
• The following signals and their components should be
decoupled or referenced to the power ground plane:
VIND1, VIND2, PVDD, PGND1, PGND2, LSD1, and
LSD2.
• These analog signals should be referenced or
decoupled to the analog ground plane: VIN, EN/DLY1,
EN/DLY2, COMP1, COMP2, FB1, and FB2.
• Place the overcurrent sense resistor close to the CS1
or CS2 pins. The trace coming from the switch node to
this resistor has high dv/dt and should be routed away
from other noise sensitive components and traces.
Avoid routing this trace under the inductor to prevent
noise from coupling into the signal.
Inductor
• Keep the inductor connection to the switch node (SW)
short.
• Do not route any digital or analog signal lines
underneath or close to the inductor.
• Keep the switch node (SW) away from the feedback
(FB) pin.
• To minimize noise, place a ground plane underneath
the inductor.
Output Capacitor
• Use a wide trace to connect the output capacitor
ground terminal to the input capacitor ground terminal.
• Phase margin will change as the output capacitor value
and ESR changes. Contact the factory if the output
capacitor is different from what is shown in the BOM.
• The feedback trace should be separate from the power
trace and connected as close as possible to the output
capacitor. Sensing a long high current load trace can
degrade the DC load regulation.
• If 0603 package ceramic output capacitors are used,
then make sure that it has enough capacitance at the
desired output voltage. Please refer to the capacitor
datasheet for more details.
Input Capacitor
• Place the input capacitor next. Ceramic capacitors
must be placed between VIND1 and PGND1 and
between VIND2 and PGND2.
• Place the input capacitors on the same side of the
board and as close to the IC and low-side MOSFET as
possible.
• Keep both the VIN and PGND connections short.
• Place several vias to the ground plane close to the
input capacitor ground terminal, but not between the
input capacitors and IC pins.
• Use either X7R or X5R dielectric input capacitors. Do
not use Y5V or Z5U type capacitors.
• Do not replace the ceramic input capacitor with any
other type of capacitor. Any type of capacitor can be
placed in parallel with the input capacitor.
July 11, 2013
Diode
• The external Schottky diode is placed next to the lowside MOSFET.
• The connection from the Schottky diode’s anode to the
input capacitors ground terminal must be as short as
possible.
• The diode’s cathode connection to the switch node
(SW) must be keep as short as possible.
21
Revision 1.4
Micrel, Inc.
MIC25400
PCB Layout Guidelines (Continued)
RC Snubber
• Place the RC snubber on the same side of the board
and as close as possible to the low-side MOSFET.
Low-Side MOSFET
• Low-side drive MOSFET traces (LSD pin-to- MOSFET
gate pin) must be short and routed over a ground
plane. The ground plane should be the connection
between the MOSFET source and PGND.
• Chose a low-side MOSFET with a high CGS/CGD ratio
and a low internal gate resistance to minimize the
effect of dv/dt-inducted turn-on.
• Do not put a resistor between the LSD output and the
gate.
• Use a 4.5V Vgs-rated MOSFET. Its higher gate
threshold voltage is more immune to glitches than a
2.5V or 3.3V rated MOSFET. MOSFETs that are rated
for operation at less than 4.5VGS should not be used.
High-Side MOSFET
• Add a 20Ω resistor in series with the boost pin. This
will slow down the turn-on time of the high-side
MOSFET while leaving the turn-off time unaffected.
July 11, 2013
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Revision 1.4
Micrel, Inc.
MIC25400
MIC25400 Evaluation Board Schematic
Bill of Materials
Item
Part Number
C1
12103D226MAT2A
C2, C13
12063D106MAT2A
C4, C10, C6,
C9
06033D103MAT2A
C5
08056D225MAT2A
C7
VJ0603Y680KXXMB
C8
VJ0603Y470KXXMB
C11, C14
Manufacturer
(6)
AVX
Description
Qty.
Ceramic Capacitor, 22µF, 25V, X5R
1
AVX
Ceramic Capacitor, 10µF, 25V, X5R
2
AVX
Ceramic Capacitor, 10nF, 25V
4
Ceramic Capacitor, 2.2µF, 6.3V
1
Ceramic Capacitor, 68pF, 50V, X7R
1
Vitramon
Ceramic Capacitor, 47pF, 50V, X7R
1
08056D226MAT2A
AVX
Ceramic Capacitor, 22µF, 6.3V, X5R
2
C12
06033D105MAT2A
AVX
Ceramic Capacitor, 1µF, 25V
1
C16
VJ0603Y332KXXMB
Vitramon
Ceramic Capacitor, 3.3nF, 50V, X7R
1
C17
VJ0603Y152KXXMB
Vitramon
Ceramic Capacitor, 1.5nF, 50V, X7R
1
C18, C19
VJ0603Y102KXXMB
Vitramon
Ceramic Capacitor, 1nF, 50V, X7R
2
AVX
Vitramon
(7)
Notes:
6. AVX: www.avx.com.
7. Vishay: www.vishay.com.
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Revision 1.4
Micrel, Inc.
MIC25400
Bill of Materials (Continued)
Item
D1, D2
D3, D4
L1, L2
Part Number
SD103BWS
B0530W
DR74-4R7-R
Manufacturer
(7)
Vishay
Diodes. Inc
Cooper
(8)
(9)
Qty.
Schottky Diode, 100mA, 30V
2
Schottky Diode, 30V, 0.5A
2
Inductor, 4.7µH, 4.3A
2
Resistor, 1k (0603 size), 1%
4
R1, R6
CRCW06031001FRT1
R2
CRCW06032740FRT1
Vishay Dale
Resistor, 274 (0603 size), 1%
1
R3, R8
CRCW06031002FRT1
Vishay Dale
Resistor, 10k (0603 size), 1%
4
R4, R5
CRCW06036040FRT1
Vishay Dale
Resistor, 604 (0603 size), 1%
2
R7
CRCW06031401FRT1
Vishay Dale
Resistor, 1.4k (0603 size), 1%
1
R9, R10
CRCW060320R0FRT1
Vishay Dale
Resistor, 20 (0603 size), 1%
2
R12, R13
CRCW06034992FRT1
Vishay Dale
Resistor, 49.9k (0603 size), 1%
2
R15, R16, R17
CRCW06030000FRT1
Vishay Dale
Resistor, 0Ω (0603 size)
3
R20, R21
CRCW08051R21FRT1
Vishay Dale
Resistor, 1.21Ω (0805 size), 1%
2
MOSFET
2
MOSFET
2
2A Dual Output PWM Synchronous Buck Regulator IC
1
Q1, Q2
FDN359AN
Q3, Q4
BSS138
U1
MIC25400YML
Vishay Dale
(7)
Description
Fairchild
(10)
Fairchild
(11)
Micrel, Inc.
Notes:
8. Diodes, Inc.: www.diodes.com.
9. Cooper Magnetics: www.cooperet.com.
10. Fairchild Semiconductor: www.fairchildsemi.com.
11. Micrel, Inc.: www.micrel.com.
July 11, 2013
24
Revision 1.4
Micrel, Inc.
MIC25400
PCB Layout Recommendations
Top Layer
Mid Layer 1
July 11, 2013
25
Revision 1.4
Micrel, Inc.
MIC25400
PCB Layout Recommendations (Continued)
Mid Layer 2
Bottom Layer
July 11, 2013
26
Revision 1.4
Micrel, Inc.
MIC25400
Package Information(12)
24-Pin 4mm × 4mm MLF (ML)
Note:
12. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
July 11, 2013
27
Revision 1.4
Micrel, Inc.
MIC25400
Recommended Landing Pattern
24-Pin 4mm × 4mm MLF (ML)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
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Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
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© 2009 Micrel, Incorporated.
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Revision 1.4