KSZ9031RNX Gigabit Ethernet Transceiver with RGMII Support Data Sheet Rev. 1.0 General Description Features The KSZ9031RNX is a completely integrated triple-speed (10Base-T/100Base-TX/1000Base-T) Ethernet physicallayer transceiver for transmission and reception of data on standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ9031RNX provides the Reduced Gigabit Media Independent Interface (RGMII) for direct connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at 10/100/1000Mbps. The KSZ9031RNX reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core. The KSZ9031RNX offers diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ9031 I/Os and the ® board. The LinkMD TDR-based cable diagnostic identifies faulty copper cabling. Remote and local loopback functions verify analog and digital data paths. The KSZ9031RNX is available in a 48-pin, lead-free QFN package (see “Ordering Information”). Data sheets and support documentation are available on Micrel’s web site at: www.micrel.com. • Single-chip 10/100/1000Mbps IEEE 802.3 compliant Ethernet transceiver • RGMII timing supports on-chip delay according to RGMII Version 2.0, with programming options for external delay and making adjustments and corrections to TX and RX timing paths • RGMII with 3.3V/2.5V/1.8V tolerant I/Os • Auto-negotiation to automatically select the highest linkup speed (10/100/1000Mbps) and duplex (half/full) • On-chip termination resistors for the differential pairs • On-chip LDO controller to support single 3.3V supply operation – requires only one external FET to generate 1.2V for the core • Jumbo frame support up to 16KB • 125MHz reference clock output • Energy detect power-down mode for reduced power consumption when the cable is not attached • Energy Efficient Ethernet (EEE) support with low-power idle (LPI) mode and clock stoppage for 100Base-TX/ 1000Base-T and transmit amplitude reduction with 10Base-Te option • Wake-on-LAN (WOL) support with robust custom-packet detection Functional Diagram LinkMD is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com October 2012 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Features (Continued) Applications • Programmable LED outputs for link, activity, and speed • Baseline wander correction • LinkMD TDR-based cable diagnostic to identify faulty copper cabling • Parametric NAND tree support to detect faults between chip I/Os and board • Loopback modes for diagnostics • Automatic MDI/MDI-X crossover to detect and correct pair swap at all speeds of operation • Automatic detection and correction of pair swaps, pair skew, and pair polarity • MDC/MDIO management interface for PHY register configuration • Interrupt pin option • Power-down and power-saving modes • Operating voltages – Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V (external FET or regulator) – VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V – Transceiver (AVDDH): 3.3V or 2.5V (commercial temp) • Available in a 48-pin QFN (7mm x 7mm) package • • • • • • • • • • • Laser/Network printer Network attached storage (NAS) Network server Gigabit LAN on motherboard (GLOM) Broadband gateway Gigabit SOHO/SMB router IPTV IP set-top box Game console Triple-play (data, voice, video) media center Media converter Ordering Information Temperature Range Package Lead Finish Wire Bonding 0°C to 70°C 48-Pin QFN Pb-Free Gold 0°C to 70°C 48-Pin QFN Pb-Free Copper (1) −40°C to 85°C 48-Pin QFN Pb-Free Gold (1) −40°C to 85°C 48-Pin QFN Pb-Free Copper 0°C to 70°C 48-Pin QFN Pb-Free Part Number KSZ9031RNXCA (1) KSZ9031RNXCC KSZ9031RNXIA KSZ9031RNXIC Description RGMII, Commercial Temperature, Gold Wire Bonding RGMII, Commercial Temperature, Copper Wire Bonding RGMII, Industrial Temperature, Gold Wire Bonding RGMII, Industrial Temperature, Copper Wire Bonding KSZ9031RNX Evaluation Board KSZ9031RNX-EVAL (Mounted with KSZ9031RNX device in commercial temperature) Note: 1. Contact factory for lead time. October 2012 2 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Revision History Revision Date Summary of Changes 1.0 10/31/12 Data sheet created October 2012 3 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Contents General Description ................................................................................................................................................................ 1 Features .................................................................................................................................................................................. 1 Functional Diagram ................................................................................................................................................................. 1 Features (Continued) .............................................................................................................................................................. 2 Applications ............................................................................................................................................................................. 2 Ordering Information ............................................................................................................................................................... 2 Revision History ...................................................................................................................................................................... 3 Contents .................................................................................................................................................................................. 4 List of Figures .......................................................................................................................................................................... 7 List of Tables ........................................................................................................................................................................... 8 Pin Configuration ..................................................................................................................................................................... 9 Pin Description ...................................................................................................................................................................... 10 Strapping Options ................................................................................................................................................................. 15 Functional Overview .............................................................................................................................................................. 16 Functional Description: 10Base-T/100Base-TX Transceiver ................................................................................................ 17 100Base-TX Transmit.......................................................................................................................................................................... 17 100Base-TX Receive........................................................................................................................................................................... 17 Scrambler/De-Scrambler (100Base-TX only) ...................................................................................................................................... 17 10Base-T Transmit .............................................................................................................................................................................. 17 10Base-T Receive ............................................................................................................................................................................... 17 Functional Description: 1000Base-T Transceiver ................................................................................................................. 18 Analog Echo-Cancellation Circuit ........................................................................................................................................................ 18 Automatic Gain Control (AGC) ............................................................................................................................................................ 18 Analog-to-Digital Converter (ADC) ...................................................................................................................................................... 19 Timing Recovery Circuit ...................................................................................................................................................................... 19 Adaptive Equalizer............................................................................................................................................................................... 19 Trellis Encoder and Decoder ............................................................................................................................................................... 19 Functional Description: 10/100/1000 Transceiver Features ................................................................................................. 19 Auto MDI/MDI-X .................................................................................................................................................................................. 19 Pair-Swap, Alignment, and Polarity Check .......................................................................................................................................... 20 Wave Shaping, Slew-Rate Control, and Partial Response .................................................................................................................. 20 PLL Clock Synthesizer ........................................................................................................................................................................ 20 Auto-Negotiation ................................................................................................................................................................... 20 RGMII Interface ..................................................................................................................................................................... 22 RGMII Signal Definition ....................................................................................................................................................................... 23 RGMII Signal Diagram ......................................................................................................................................................................... 23 RGMII Pad Skew Registers ................................................................................................................................................................. 23 RGMII In-Band Status ......................................................................................................................................................................... 27 MII Management (MIIM) Interface ......................................................................................................................................... 27 Interrupt (INT_N) ................................................................................................................................................................... 28 October 2012 4 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX LED Mode ............................................................................................................................................................................. 28 Single-LED Mode ................................................................................................................................................................................ 28 Tri-color Dual-LED Mode ..................................................................................................................................................................... 28 Loopback Mode ..................................................................................................................................................................... 29 Local (Digital) Loopback ...................................................................................................................................................................... 29 Remote (Analog) Loopback ................................................................................................................................................................. 30 ® LinkMD Cable Diagnostic .................................................................................................................................................... 31 NAND Tree Support .............................................................................................................................................................. 31 Power Management .............................................................................................................................................................. 32 Energy-Detect Power-Down Mode ...................................................................................................................................................... 32 Software Power-Down Mode ............................................................................................................................................................... 32 Chip Power-Down Mode ...................................................................................................................................................................... 32 Energy Efficient Ethernet (EEE) ............................................................................................................................................ 32 Transmit Direction Control (MAC-to-PHY) ........................................................................................................................................... 33 Receive Direction Control (PHY-to-MAC) ............................................................................................................................................ 34 Registers Associated with EEE ........................................................................................................................................................... 36 Wake-On-LAN ....................................................................................................................................................................... 36 Magic-Packet Detection....................................................................................................................................................................... 36 Customized-Packet Detection ............................................................................................................................................................. 36 Link Status Change Detection ............................................................................................................................................................. 37 Typical Current/Power Consumption .................................................................................................................................... 38 Transceiver (3.3V), Digital I/Os (3.3V) ................................................................................................................................................. 38 Transceiver (3.3V), Digital I/Os (1.8V) ................................................................................................................................................. 38 Transceiver (2.5V), Digital I/Os (2.5V) ................................................................................................................................................. 39 Transceiver (2.5V), Digital I/Os (1.8V) ................................................................................................................................................. 39 Register Map ......................................................................................................................................................................... 40 Standard Registers ............................................................................................................................................................... 42 IEEE Defined Registers – Descriptions ............................................................................................................................................... 42 Vendor-Specific Registers – Descriptions ........................................................................................................................................... 48 MMD Registers...................................................................................................................................................................... 52 MMD Registers – Descriptions ............................................................................................................................................................ 53 (1) Absolute Maximum Ratings ................................................................................................................................................ 62 Operating Ratings (2) .............................................................................................................................................................. 62 (3) Electrical Characteristics .................................................................................................................................................... 62 Timing Diagrams ................................................................................................................................................................... 65 RGMII Timing ...................................................................................................................................................................................... 65 Auto-Negotiation Timing ...................................................................................................................................................................... 66 MDC/MDIO Timing .............................................................................................................................................................................. 67 Power-Up/Power-Down/Reset Timing ................................................................................................................................................. 68 Reset Circuit .......................................................................................................................................................................... 69 Reference Circuits – LED Strap-In Pins ................................................................................................................................ 70 Reference Clock – Connection and Selection ...................................................................................................................... 71 Magnetic – Connection and Selection .................................................................................................................................. 72 October 2012 5 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Recommended Land Pattern ................................................................................................................................................ 74 Package Information ............................................................................................................................................................. 75 October 2012 6 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX List of Figures Figure 1. KSZ9031RNX Block Diagram ............................................................................................................................... 16 Figure 2. KSZ9031RNX 1000Base-T Transceiver Block Diagram – Single Channel.......................................................... 18 Figure 3. Auto-Negotiation Flow Chart ................................................................................................................................. 21 Figure 4. KSZ9031RNX RGMII Interface ............................................................................................................................. 23 Figure 5. Local (Digital) Loopback ....................................................................................................................................... 29 Figure 6. Remote (Analog) Loopback .................................................................................................................................. 30 Figure 7. LPI Mode (Refresh Transmissions and Quiet Periods) ........................................................................................ 33 Figure 8. LPI Transition – RGMII (1000Mbps) Transmit ...................................................................................................... 33 Figure 9. LPI Transition – RGMII (100Mbps) Transmit ........................................................................................................ 34 Figure 10. LPI Transition – RGMII (1000Mbps) Receive ..................................................................................................... 35 Figure 11. LPI Transition – RGMII (100Mbps) Receive ....................................................................................................... 35 Figure 12. RGMII v2.0 Specification (Figure 3 – Multiplexing and Timing Diagram) ........................................................... 65 Figure 13. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 66 Figure 14. MDC/MDIO Timing.............................................................................................................................................. 67 Figure 15. Power-Up/Power-Down/Reset Timing ................................................................................................................ 68 Figure 16. Recommended Reset Circuit .............................................................................................................................. 69 Figure 17. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ..................................................... 69 Figure 18. Reference Circuits for LED Strapping Pins......................................................................................................... 70 Figure 19. 25MHz Crystal/Oscillator Reference Clock Connection ..................................................................................... 71 Figure 20. Typical Gigabit Magnetic Interface Circuit .......................................................................................................... 72 Figure 21. Recommended Land Pattern, 48-Pin (7mm x 7mm) QFN ................................................................................. 74 October 2012 7 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX List of Tables Table 1. MDI/MDI-X Pin Mapping ........................................................................................................................................ 19 Table 2. Auto-Negotiation Timers ........................................................................................................................................ 22 Table 3. RGMII Signal Definition .......................................................................................................................................... 23 Table 4. RGMII Pad Skew Registers ................................................................................................................................... 24 Table 5. Absolute Delay for 5-bit Pad Skew Setting ............................................................................................................ 25 Table 6. Absolute Delay for 4-bit Pad Skew Setting ............................................................................................................ 26 Table 7. RGMII In-Band Status ............................................................................................................................................ 27 Table 8. MII Management Frame Format for the KSZ9031RNX ......................................................................................... 27 Table 9. Single-LED Mode – Pin Definition .......................................................................................................................... 28 Table 10. Tri-color Dual-LED Mode – Pin Definition ............................................................................................................ 28 Table 11. NAND Tree Test Pin Order for KSZ9031RNX ..................................................................................................... 31 Table 12. Typical Current/Power Consumption – Transceiver (3.3V), Digital I/Os (3.3V) ................................................... 38 Table 13. Typical Current/Power Consumption – Transceiver (3.3V), Digital I/Os (1.8V) ................................................... 38 Table 14. Typical Current/Power Consumption – Transceiver (2.5V), Digital I/Os (2.5V) ................................................... 39 Table 15. Typical Current/Power Consumption – Transceiver (2.5V), Digital I/Os (1.8V) ................................................... 39 Table 16. Standard Registers Supported by KSZ9031RNX ................................................................................................ 40 Table 17. MMD Registers Supported by KSZ9031RNX ...................................................................................................... 41 Table 18. Portal Registers (Access to Indirect MMD Registers) .......................................................................................... 52 Table 19. RGMII v2.0 Specification (Timing Specifics from Table 2) .................................................................................. 65 Table 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ............................................................................... 66 Table 21. MDC/MDIO Timing Parameters ........................................................................................................................... 67 Table 22. Power-Up/Power-Down/Reset Timing Parameters ............................................................................................. 68 Table 23. Reference Crystal/Clock Selection Criteria .......................................................................................................... 71 Table 24. Magnetics Selection Criteria ................................................................................................................................ 73 Table 25. Compatible Single-Port 10/100/1000 Magnetics ................................................................................................. 73 October 2012 8 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Pin Configuration 48-Pin QFN (Top View) October 2012 9 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Pin Description Pin Number Pin Name Type 1 AVDDH P 2 TXRXP_A I/O (1) Pin Function 3.3V/2.5V (commercial temp only) analog VDD Media Dependent Interface[0], positive signal of differential pair 1000Base-T mode: TXRXP_A corresponds to BI_DA+ for MDI configuration and BI_DB+ for MDI-X configuration, respectively. 10Base-T/100Base-TX mode: TXRXP_A is the positive transmit signal (TX+) for MDI configuration and the positive receive signal (RX+) for MDI-X configuration, respectively. 3 TXRXM_A I/O Media Dependent Interface[0], negative signal of differential pair 1000Base-T mode: TXRXM_A corresponds to BI_DA– for MDI configuration and BI_DB– for MDI-X configuration, respectively. 10Base-T/100Base-TX mode: TXRXM_A is the negative transmit signal (TX–) for MDI configuration and the negative receive signal (RX–) for MDI-X configuration, respectively. 4 AVDDL P 5 TXRXP_B I/O 1.2V analog VDD Media Dependent Interface[1], positive signal of differential pair 1000Base-T mode: TXRXP_B corresponds to BI_DB+ for MDI configuration and BI_DA+ for MDI-X configuration, respectively. 10Base-T/100Base-TX mode: TXRXP_B is the positive receive signal (RX+) for MDI configuration and the positive transmit signal (TX+) for MDI-X configuration, respectively. 6 TXRXM_B I/O Media Dependent Interface[1], negative signal of differential pair 1000Base-T mode: TXRXM_B corresponds to BI_DB– for MDI configuration and BI_DA– for MDI-X configuration, respectively. 10Base-T/100Base-TX mode: TXRXM_B is the negative receive signal (RX–) for MDI configuration and the negative transmit signal (TX–) for MDI-X configuration, respectively. 7 TXRXP_C I/O Media Dependent Interface[2], positive signal of differential pair 1000Base-T mode: TXRXP_C corresponds to BI_DC+ for MDI configuration and BI_DD+ for MDI-X configuration, respectively. 10Base-T/100Base-TX mode: TXRXP_C is not used. 8 TXRXM_C I/O Media Dependent Interface[2], negative signal of differential pair 1000Base-T mode: TXRXM_C corresponds to BI_DC– for MDI configuration and BI_DD– for MDI-X configuration, respectively. 10Base-T/100Base-TX mode: TXRXM_C is not used. 9 October 2012 AVDDL P 1.2V analog VDD 10 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Pin Number Pin Name Type 10 TXRXP_D I/O (1) Pin Function Media Dependent Interface[3], positive signal of differential pair 1000Base-T mode: TXRXP_D corresponds to BI_DD+ for MDI configuration and BI_DC+ for MDI-X configuration, respectively. 10Base-T/100Base-TX mode: TXRXP_D is not used. 11 TXRXM_D I/O Media Dependent Interface[3], negative signal of differential pair 1000Base-T mode: TXRXM_D corresponds to BI_DD– for MDI configuration and BI_DC– for MDI-X configuration, respectively. 10Base-T/100Base-TX mode: TXRXM_D is not used. 12 AVDDH P 3.3V/2.5V (commercial temp only) analog VDD 13 NC – No connect This pin is not bonded and can be connected to digital ground for footprint compatibility with the Micrel KSZ9021RN Gigabit PHY. 14 15 DVDDL P LED2/ I/O PHYAD1 1.2V digital VDD LED output: Programmable LED2 output Config mode: The pull-up/pull-down value is latched as PHYAD[1] during power-up/reset. See the “Strapping Options” section for details. The LED2 pin is programmed by the LED_MODE strapping option (pin 41), and is defined as follows: Single-LED Mode Link Pin State LED Definition Link off H OFF Link on (any speed) L ON Tri-Color Dual-LED Mode Pin State Link/Activity LED Definition LED2 LED1 LED2 LED1 Link off H H OFF OFF 1000 Link / No activity L H ON OFF 1000 Link / Activity (RX, TX) Toggle H Blinking OFF 100 Link / No activity H L OFF ON 100 Link / Activity (RX, TX) H Toggle OFF Blinking 10 Link / No activity L L ON ON 10 Link / Activity (RX, TX) Toggle Toggle Blinking Blinking For tri-color dual-LED mode, LED2 works in conjunction with LED1 (pin 17) to indicate 10Mbps link and activity. 16 October 2012 DVDDH P 3.3V, 2.5V, or 1.8V digital VDD_I/O 11 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Pin Number Pin Name 17 LED1/ Type (1) I/O Pin Function LED1 output: Programmable LED1 output PHYAD0/ Config mode: The voltage on this pin is sampled and latched during the powerup/reset process to determine the value of PHYAD[0]. See the “Strapping Options” section for details. PME_N1 PME_N output: Programmable PME_N output (pin option 1). This pin function requires an external pull-up resistor to DVDDH (digital VDD_I/O) in a range from 1.0kΩ to 4.7kΩ. When asserted low, this pin signals that a WOL event has occurred. The LED1 pin is programmed by the LED_MODE strapping option (pin 41), and is defined as follows. Single-LED Mode Activity Pin State LED Definition No activity H OFF Activity (RX, TX) Toggle Blinking Tri-Color Dual-LED Mode Pin State Link/Activity LED Definition LED2 LED1 LED2 LED1 Link off H H OFF OFF 1000 Link / No activity L H ON OFF 1000 Link / Activity (RX, TX) Toggle H Blinking OFF 100 Link / No activity H L OFF ON 100 Link / Activity (RX, TX) H Toggle OFF Blinking 10 Link / No activity L L ON ON 10 Link / Activity (RX, TX) Toggle Toggle Blinking Blinking For tri-color dual-LED mode, LED1 works in conjunction with LED2 (pin 15) to indicate 10Mbps link and activity. 18 DVDDL P 1.2V digital VDD 19 TXD0 I RGMII mode: RGMII TD0 (Transmit Data 0) input 20 TXD1 I RGMII mode: RGMII TD1 (Transmit Data 1) input\ 21 TXD2 I RGMII mode: RGMII TD2 (Transmit Data 2) input 22 TXD3 I RGMII mode: RGMII TD3 (Transmit Data 3) input 23 DVDDL P 1.2V digital VDD 24 GTX_CLK I RGMII mode: RGMII TXC (Transmit Reference Clock) input RGMII TX_CTL (Transmit Control) input 25 TX_EN I RGMII mode: 26 DVDDL P 1.2V digital VDD 27 RXD3/ I/O MODE3 28 RXD2/ I/O MODE2 29 VSS Gnd 30 DVDDL P October 2012 RGMII mode: RGMII RD3 (Receive Data 3) output Config mode: The pull-up/pull-down value is latched as MODE3 during power-up/reset. See the “Strapping Options” section for details. RGMII mode: RGMII RD2 (Receive Data 2) output Config mode: The pull-up/pull-down value is latched as MODE2 during power-up/reset. See the “Strapping Options” section for details. Digital ground 1.2V digital VDD 12 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Pin Number Pin Name 31 RXD1/ Type (1) I/O MODE1 32 RXD0/ I/O MODE0 33 RX_DV/ I/O CLK125_EN 34 DVDDH P 35 RX_CLK/ I/O PHYAD2 36 MDC Ipu Pin Function RGMII mode: RGMII RD1 (Receive Data 1) output Config mode: The pull-up/pull-down value is latched as MODE1 during power-up/reset. See the “Strapping Options” section for details. RGMII mode: RGMII RD0 (Receive Data 0) output Config mode: The pull-up/pull-down value is latched as MODE0 during power-up/reset. See the “Strapping Options” section for details. RGMII mode: RGMII RX_CTL (Receive Control) output Config mode: Latched as CLK125_NDO Output Enable during power-up/reset. See the “Strapping Options” section for details. 3.3V, 2.5V, or 1.8V digital VDD_I/O RGMII mode: RGMII RXC (Receive Reference Clock) output Config mode: The pull-up/pull-down value is latched as PHYAD[2] during power-up/reset. See the “Strapping Options” section for details. Management data clock input This pin is the input reference clock for MDIO (pin 37). 37 MDIO Ipu/O Management data input/output This pin is synchronous to MDC (pin 36) and requires an external pull-up resistor to DVDDH (digital VDD_I/O) in a range from 1.0kΩ to 4.7kΩ. 38 INT_N/ O PME_N2 Interrupt output: Programmable interrupt output, with register 1Bh as the Interrupt Control/Status register, for programming the interrupt conditions and reading the interrupt status. Register 1Fh, bit [14] sets the interrupt output to active low (default) or active high. PME_N output: Programmable PME_N output (pin option 2). When asserted low, this pin signals that a WOL event has occurred. For Interrupt (when active low) and PME functions, this pin requires an external pull-up resistor to DVDDH (digital VDD_I/O) in a range from 1.0kΩ to 4.7kΩ. 39 DVDDL P 1.2V digital VDD 40 DVDDH P 3.3V, 2.5V, or 1.8V digital VDD_I/O 41 CLK125_NDO/ I/O 125MHz clock output This pin provides a 125MHz reference clock output option for use by the MAC. LED_MODE 42 RESET_N Config mode: Ipu The pull-up/pull-down value is latched as LED_MODE during power-up/reset. See the “Strapping Options” section for details. Chip reset (active low) Hardware pin configurations are strapped-in at the de-assertion (rising edge) of RESET_N. See the “Strapping Options” section for more details. 43 LDO_O O On-chip 1.2V LDO controller output This pin drives the input gate of a P-channel MOSFET to generate 1.2V for the chip’s core voltages. If the system provides 1.2V and this pin is not used, it can be left floating. 44 AVDDL_PLL P 1.2V analog VDD for PLL 45 XO O 25MHz crystal feedback This pin is a no connect if an oscillator or external clock source is used. 46 XI I Crystal / Oscillator/ External Clock input 25MHz ±50ppm tolerance 47 NC – No connect This pin is not bonded and can be connected to AVDDH power for footprint compatibility with the Micrel KSZ9021RN Gigabit PHY. October 2012 13 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Pin Number Pin Name 48 ISET Type (1) I/O Pin Function Set the transmit output level Connect a 12.1kΩ 1% resistor to ground on this pin. PADDLE P_GND Gnd Exposed paddle on bottom of chip Connect P_GND to ground. Note: 1. P = Power supply. Gnd = Ground. I = Input. O = Output. I/O = Bi-directional. Ipu = Input with internal pull-up (see “Electrical Characteristics” for value). Ipu/O = Input with internal pull-up (see “Electrical Characteristics” for value)/Output. October 2012 14 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Strapping Options Pin Number Pin Name 35 PHYAD2 I/O 15 PHYAD1 I/O 17 PHYAD0 I/O Type (1) Pin Function The PHY address, PHYAD[2:0], is sampled and latched at power-up/reset and is configurable to any value from 0 to 7. Each PHY address bit is configured as follows: Pull-up = 1 Pull-down = 0 PHY address bits [4:3] are always set to ‘00’. 27 MODE3 I/O 28 MODE2 I/O 31 MODE1 I/O 32 MODE0 I/O 33 CLK125_EN I/O The MODE[3:0] strap-in pins are sampled and latched at power-up/reset as follows: MODE[3:0] Mode 0000 Reserved – not used 0001 Reserved – not used 0010 Reserved – not used 0011 Reserved – not used 0100 NAND tree mode 0101 Reserved – not used 0110 Reserved – not used 0111 Chip power-down mode 1000 Reserved – not used 1001 Reserved – not used 1010 Reserved – not used 1011 Reserved – not used 1100 RGMII mode – advertise 1000Base-T full-duplex only 1101 RGMII mode – advertise 1000Base-T full- and half-duplex only 1110 RGMII mode – advertise all capabilities (10/100/1000 speed half-/full-duplex), except 1000Base-T half-duplex 1111 RGMII mode – advertise all capabilities (10/100/1000 speed half-/full-duplex) CLK125_EN is sampled and latched at power-up/reset and is defined as follows: Pull-up = Enable 125MHz clock output Pull-down = Disable 125MHz clock output Pin 41 (CLK125_NDO) provides the 125MHz reference clock output option for use by the MAC. 41 LED_MODE I/O LED_MODE is latched at power-up/reset and is defined as follows: Pull-up = Single-LED mode Pull-down = Tri-color dual-LED mode Note: 1. I/O = Bi-directional. Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during power-up or reset, and consequently cause the PHY strap-in pins on the RGMII signals to be latched to an incorrect configuration. In this case, Micrel recommends adding external pull-ups/pull-downs on the PHY strap-in pins to ensure the PHY is configured to the correct pin strap-in mode. October 2012 15 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Functional Overview The KSZ9031RNX is a completely integrated triple-speed (10Base-T/100Base-TX/1000Base-T) Ethernet physical layer transceiver solution for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable. Its on-chip proprietary 1000Base-T transceiver and Manchester/MLT-3 signaling-based 10Base-T/100Base-TX transceivers are all IEEE 802.3 compliant. The KSZ9031RNX reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core. On the copper media interface, the KSZ9031RNX can automatically detect and correct for differential pair misplacements and polarity reversals, and correct propagation delays and re-sync timing between the four differential pairs, as specified in the IEEE 802.3 standard for 1000Base-T operation. The KSZ9031RNX provides the RGMII interface for direct and seamless connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at 10/100/1000Mbps. Figure 1 shows a high-level block diagram of the KSZ9031RNX. Figure 1. KSZ9031RNX Block Diagram October 2012 16 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Functional Description: 10Base-T/100Base-TX Transceiver 100Base-TX Transmit The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT-3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the RGMII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format then transmitted in MLT-3 current output. The output current is set by an external 12.1kΩ 1% resistor for the 1:1 transformer ratio. The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX transmitter. 100Base-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT-3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Because the amplitude loss and phase distortion are a function of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations. Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit converts the MLT-3 format back to NRZI. The slicing threshold is also adaptive. The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the RGMII format and provided as the input data to the MAC. Scrambler/De-Scrambler (100Base-TX only) The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and baseline wander. Transmitted data is scrambled using an 11-bit wide linear feedback shift register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence, then the receiver de-scrambles the incoming data stream using the same sequence as at the transmitter. 10Base-T Transmit The 10Base-T output drivers are incorporated into the 100Base-TX drivers to allow for transmission with the same magnetic. The drivers perform internal wave-shaping and pre-emphasis, and output signals with a typical amplitude of 2.5V peak for standard 10Base-T mode and 1.75V peak for energy-efficient 10Base-Te mode. The 10Base-T/10Base-Te signals have harmonic contents that are at least 31dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal. 10Base-T Receive On the receive side, input buffer and level-detecting squelch circuits are used. A differential input receiver circuit and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 300mV or with short pulse widths to prevent noises at the receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ9031RNX decodes a data frame. The receiver clock is maintained active during idle periods between receiving data frames. Auto-polarity correction is provided for the receive differential pair to automatically swap and fix the incorrect +/– polarity wiring in the cabling. October 2012 17 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Functional Description: 1000Base-T Transceiver The 1000Base-T transceiver is based-on a mixed-signal/digital-signal processing (DSP) architecture, which includes the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancellers, cross-talk cancellers, precision clock recovery scheme, and power-efficient line drivers. Figure 2 shows a high-level block diagram of a single channel of the 1000Base-T transceiver for one of the four differential pairs. Figure 2. KSZ9031RNX 1000Base-T Transceiver Block Diagram – Single Channel Analog Echo-Cancellation Circuit In 1000Base-T mode, the analog echo-cancellation circuit helps to reduce the near-end echo. This analog hybrid circuit relieves the burden of the ADC and the adaptive equalizer. This circuit is disabled in 10Base-T/100Base-TX mode. Automatic Gain Control (AGC) In 1000Base-T mode, the automatic gain control (AGC) circuit provides initial gain adjustment to boost up the signal level. This pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal. October 2012 18 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Analog-to-Digital Converter (ADC) In 1000Base-T mode, the analog-to-digital converter (ADC) digitizes the incoming signal. ADC performance is essential to the overall performance of the transceiver. This circuit is disabled in 10Base-T/100Base-TX mode. Timing Recovery Circuit In 1000Base-T mode, the mixed-signal clock recovery circuit together with the digital phase-locked loop is used to recover and track the incoming timing information from the received data. The digital phase-locked loop has very low long-term jitter to maximize the signal-to-noise ratio of the receive signal. The 1000Base-T slave PHY must transmit the exact receive clock frequency recovered from the received data back to the 1000Base-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission. This also helps to facilitate echo cancellation and NEXT removal. Adaptive Equalizer In 1000Base-T mode, the adaptive equalizer provides the following functions: • Detection for partial response signaling • Removal of NEXT and ECHO noise • Channel equalization Signal quality is degraded by residual echo that is not removed by the analog hybrid because of impedance mismatch. The KSZ9031RNX uses a digital echo canceller to further reduce echo components on the receive signal. In 1000Base-T mode, data transmission and reception occurs simultaneously on all four pairs of wires (four channels). This results in high-frequency cross-talk coming from adjacent wires. The KSZ9031RNX uses three NEXT cancellers on each receive channel to minimize the cross-talk induced by the other three channels. In 10Base-T/100Base-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and recover the channel loss from the incoming data. Trellis Encoder and Decoder In 1000Base-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5 symbols. The initial scrambler seed is determined by the specific PHY address to reduce EMI when more than one KSZ9031RNX is used on the same board. On the receiving side, the idle stream is examined first. The scrambler seed, pair skew, pair order, and polarity must be resolved through the logic. The incoming 4D-PAM5 data is then converted into 9-bit symbols and de-scrambled into 8-bit data. Functional Description: 10/100/1000 Transceiver Features Auto MDI/MDI-X The Automatic MDI/MDI-X feature eliminates the need to determine whether to use a straight cable or a crossover cable between the KSZ9031RNX and its link partner. This auto-sense function detects the MDI/MDI-X pair mapping from the link partner, and assigns the MDI/MDI-X pair mapping of the KSZ9031RNX accordingly. Table 1 shows the KSZ9031RNX 10/100/1000 pin configuration assignments for MDI/MDI-X pin mapping. Pin (RJ-45 pair) MDI MDI-X 1000Base-T 100Base-TX 10Base-T 1000Base-T 100Base-TX 10Base-T TXRXP/M_A (1,2) A+/– TX+/– TX+/– B+/– RX+/– RX+/– TXRXP/M_B (3,6) B+/– RX+/– RX+/– A+/– TX+/– TX+/– TXRXP/M_C (4,5) C+/– Not used Not used D+/– Not used Not used TXRXP/M_D (7,8) D+/– Not used Not used C+/– Not used Not used Table 1. MDI/MDI-X Pin Mapping October 2012 19 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to register 1Ch, bit [6]. MDI and MDI-X mode is set by register 1Ch, bit [7] if Auto MDI/MDI-X is disabled. An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X. Pair-Swap, Alignment, and Polarity Check In 1000Base-T mode, the KSZ9031RNX • Detects incorrect channel order and automatically restores the pair order for the A, B, C, D pairs (four channels) • Supports 50±10ns difference in propagation delay between pairs of channels in accordance with the IEEE 802.3 standard, and automatically corrects the data skew so the corrected four pairs of data symbols are synchronized Incorrect pair polarities of the differential signals are automatically corrected for all speeds. Wave Shaping, Slew-Rate Control, and Partial Response In communication systems, signal transmission encoding methods are used to provide the noise-shaping feature and to minimize distortion and error in the transmission channel. • For 1000Base-T, a special partial-response signaling method is used to provide the band-limiting feature for the transmission path. • For 100Base-TX, a simple slew-rate control method is used to minimize EMI. • For 10Base-T, pre-emphasis is used to extend the signal quality through the cable. PLL Clock Synthesizer The KSZ9031RNX generates 125MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from the external 25MHz crystal or reference clock. Auto-Negotiation The KSZ9031RNX conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification. Auto-negotiation allows UTP (unshielded twisted pair) link partners to select the highest common mode of operation. During auto-negotiation, link partners advertise capabilities across the UTP link to each other, and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the operating mode. The following list shows the speed and duplex operation mode from highest to lowest. • Priority 1: 1000Base-T, full-duplex • Priority 2: 1000Base-T, half-duplex • Priority 3: 100Base-TX, full-duplex • Priority 4: 100Base-TX, half-duplex • Priority 5: 10Base-T, full-duplex • Priority 6: 10Base-T, half-duplex If auto-negotiation is not supported or the KSZ9031RNX link partner is forced to bypass auto-negotiation for 10Base-T and 100Base-TX modes, the KSZ9031RNX sets its operating mode by observing the input signal at its receiver. This is known as parallel detection, and allows the KSZ9031RNX to establish a link by listening for a fixed signal protocol in the absence of the auto-negotiation advertisement protocol. The auto-negotiation link-up process is shown in Figure 3. October 2012 20 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Figure 3. Auto-Negotiation Flow Chart For 1000Base-T mode, auto-negotiation is always required to establish a link. During 1000Base-T auto-negotiation, the master and slave configuration is first resolved between link partners. Then the link is established with the highest common capabilities between link partners. Auto-negotiation is enabled by default after power-up or hardware reset. After that, auto-negotiation can be enabled or disabled through register 0h, bit [12]. If auto-negotiation is disabled, the speed is set by register 0h, bits [6, 13] and the duplex is set by register 0h, bit [8]. If the speed is changed on the fly, the link goes down and auto-negotiation and parallel detection initiate until a common speed between KSZ9031RNX and its link partner is re-established for a link. If the link is already established and there is no change of speed on the fly, the changes (for example, duplex and pause capabilities) will not take effect unless either auto-negotiation is restarted through register 0h, bit [9], or a link-down to linkup transition occurs (that is, disconnecting and reconnecting the cable). After auto-negotiation is completed, the link status is updated in register 1h, bit [2], and the link partner capabilities are updated in registers 5h, 6h, 8h, and Ah. The auto-negotiation finite state machines use interval timers to manage the auto-negotiation process. The duration of these timers under normal operating conditions is summarized in Table 2. October 2012 21 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Auto-Negotiation Interval Timers Time Duration Transmit burst interval 16 ms Transmit pulse interval 68 µs FLP detect minimum time 17.2 µs FLP detect maximum time 185 µs Receive minimum burst interval 6.8 ms Receive maximum burst interval 112 ms Data detect minimum interval 35.4 µs Data detect maximum interval 95 µs NLP test minimum interval 4.5 ms NLP test maximum interval 30 ms Link loss time 52 ms Break link time 1480 ms Parallel detection wait time 830 ms Link enable wait time 1000 ms Table 2. Auto-Negotiation Timers RGMII Interface The Reduced Gigabit Media Independent Interface (RGMII) supports on-chip data-to-clock delay timing according to the RGMII Version 2.0 Specification, with programming options for external delay timing and to adjust and correct TX and RX timing paths. RGMII provides a common interface between RGMII PHYs and MACs, and has the following key characteristics: • Pin count is reduced from 24 pins for the IEEE Gigabit Media Independent Interface (GMII) to 12 pins for RGMII. • All speeds (10Mbps, 100Mbps, and 1000Mbps) are supported at both half- and full-duplex. • Data transmission and reception are independent and belong to separate signal groups. • Transmit data and receive data are each four bits wide, a nibble. In RGMII operation, the RGMII pins function as follows: • The MAC sources the transmit reference clock, TXC, at 125MHz for 1000Mbps, 25MHz for 100Mbps, and 2.5MHz for 10Mbps. • The PHY recovers and sources the receive reference clock, RXC, at 125MHz for 1000Mbps, 25MHz for 100Mbps, and 2.5MHz for 10Mbps.. • For 1000Base-T, the transmit data, TXD[3:0], is presented on both edges of TXC, and the received data, RXD[3:0], is clocked out on both edges of the recovered 125MHz clock, RXC. • For 10Base-T/100Base-TX, the MAC holds TX_CTL low until both PHY and MAC operate at the same speed. During the speed transition, the receive clock is stretched on either a positive or negative pulse to ensure that no clock glitch is presented to the MAC. • TX_ER and RX_ER are combined with TX_EN and RX_DV, respectively, to form TX_CTL and RX_CTL. These two RGMII control signals are valid at the falling clock edge. After power-up or reset, the KSZ9031RNX is configured to RGMII mode if the MODE[3:0] strap-in pins are set to one of the RGMII mode capability options. See the “Strapping Options” section for available options. The KSZ9031RNX has the option to output a 125MHz reference clock on the CLK125_NDO pin. This clock provides a lower-cost reference clock alternative for RGMII MACs that require a 125MHz crystal or oscillator. The 125MHz clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high. October 2012 22 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX RGMII Signal Definition Table 3 describes the RGMII signals. Refer to the RGMII Version 2.0 Specification for more detailed information. RGMII Signal Name (per spec) RGMII Signal Name (per KSZ9031RNX) Pin Type (with respect to PHY) Pin Type (with respect to MAC) Description TXC GTX_CLK Input Output Transmit Reference Clock (125MHz for 1000Mbps, 25MHz for 100Mbps, 2.5MHz for 10Mbps) TX_CTL TX_EN Input Output Transmit Control TXD[3:0] TXD[3:0] Input Output Transmit Data[3:0] RXC RX_CLK Output Input Receive Reference Clock (125MHz for 1000Mbps, 25MHz for 100Mbps, 2.5MHz for 10Mbps) RX_CTL RX_DV Output Input Receive Control RXD[3:0] RXD[3:0] Output Input Receive Data[3:0] Table 3. RGMII Signal Definition RGMII Signal Diagram The KSZ9031RNX RGMII pin connections to the MAC are shown in Figure 4. Figure 4. KSZ9031RNX RGMII Interface RGMII Pad Skew Registers Pad skew registers are available for all RGMII pins (clocks, control signals, and data bits) to provide programming options to adjust or correct the timing relationship for each RGMII pin. Because RGMII is a source-synchronous bus interface, the timing relationship needs to be maintained only within the RGMII pin’s respective timing group. • RGMII transmit timing group pins: GTX_CLK, TX_EN, TXD[3:0] • RGMII receive timing group pins: RX_CLK, RX_DV, RXD[3:0] October 2012 23 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX The following four registers located at MMD Address 2h are provided for pad skew programming. Address Name Description Mode Default MMD Address 2h, Register 4h – RGMII Control Signal Pad Skew 2.4.15:8 Reserved Reserved RW 0000_0000 2.4.7:4 RX_DV Pad Skew RGMII RX_CTL output pad skew control (0.06ns/step) RW 0111 2.4.3:0 TX_EN Pad Skew RGMII TX_CTL input pad skew control (0.06ns/step) RW 0111 MMD Address 2h, Register 5h – RGMII RX Data Pad Skew 2.5.15:12 RXD3 Pad Skew RGMII RXD3 output pad skew control (0.06ns/step) RW 0111 2.5.11:8 RXD2 Pad Skew RGMII RXD2 output pad skew control (0.06ns/step) RW 0111 2.5.7:4 RXD1 Pad Skew RGMII RXD1 output pad skew control (0.06ns/step) RW 0111 2.5.3:0 RXD0 Pad Skew RGMII RXD0 output pad skew control (0.06ns/step) RW 0111 MMD Address 2h, Register 6h – RGMII TX Data Pad Skew 2.6.15:12 TXD3 Pad Skew RGMII TXD3 output pad skew control (0.06ns/step) RW 0111 2.6.11:8 TXD2 Pad Skew RGMII TXD2 output pad skew control (0.06ns/step) RW 0111 2.6.7:4 TXD1 Pad Skew RGMII TXD1 output pad skew control (0.06ns/step) RW 0111 2.6.3:0 TXD0 Pad Skew RGMII TXD0 output pad skew control (0.06ns/step) RW 0111 MMD Address 2h, Register 8h – RGMII Clock Pad Skew 2.8.15:10 Reserved Reserved RW 0000_00 2.8.9:5 GTX_CLK Pad Skew RGMII GTX_CLK input pad skew control (0.06ns/step) RW 01_111 2.8.4:0 RX_CLK Pad Skew RGMII RX_CLK output pad skew control (0.06ns/step) RW 0_1111 Table 4. RGMII Pad Skew Registers October 2012 24 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX The RGMII control signals and data bits have 4-bit skew settings, while the RGMII clocks have 5-bit skew settings. Each register bit is approximately a 0.06ns step change. A single-bit decrement decreases the delay by approximately 0.06ns, while a single-bit increment increases the delay by approximately 0.06ns. Table 5 and Table 6 list the approximate absolute delay for each pad skew (value) setting. Pad Skew (value) Delay (ns) 0_0000 –0.90 0_0001 –0.84 0_0010 –0.78 0_0011 –0.72 0_0100 –0.66 0_0101 –0.60 0_0110 –0.54 0_0111 –0.48 0_1000 –0.42 0_1001 –0.36 0_1010 –0.30 0_1011 –0.24 0_1100 –0.18 0_1101 –0.12 0_1110 –0.06 0_1111 No delay adjustment (default value) 1_0000 +0.06 1_0001 +0.12 1_0010 +0.18 1_0011 +0.24 1_0100 +0.30 1_0101 +0.36 1_0110 +0.42 1_0111 +0.48 1_1000 +0.54 1_1001 +0.60 1_1010 +0.66 1_1011 +0.72 1_1100 +0.78 1_1101 +0.84 1_1110 +0.90 1_1111 +0.96 Table 5. Absolute Delay for 5-bit Pad Skew Setting October 2012 25 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Pad Skew (value) Delay (ns) 0000 –0.42 0001 –0.36 0010 –0.30 0011 –0.24 0100 –0.18 0101 –0.12 0110 –0.06 0111 No delay adjustment (default value) 1000 +0.06 1001 +0.12 1010 +0.18 1011 +0.24 1100 +0.30 1101 +0.36 1110 +0.42 1111 +0.48 Table 6. Absolute Delay for 4-bit Pad Skew Setting When computing the RGMII timing relationships, delays along the entire data path must be aggregated to determine the total delay to be used for comparison between RGMII pins within their respective timing group. For the transmit data path, total delay includes MAC output delay, MAC-to-PHY PCB routing delay, and PHY (KSZ9031RNX) input delay and skew setting (if any). For the receive data path, the total delay includes PHY (KSZ9031RNX) output delay, PHY-to-MAC PCB routing delay, and MAC input delay and skew setting (if any). After power-up or reset, the KSZ9031RNX defaults to the following timings at its RGMII I/O pins to support on-chip datato-clock skew timing according to the RGMII Version 2.0 Specification: • Transmit Inputs: GTX_CLK clock is in sync within ±500ps of TX_EN and TXD[3:0] • Receive outputs: RX_CLK is delayed about 1.2ns with respect to RX_DV and RXD[3:0] The above default RGMII timings imply: • RX_CLK clock skew is set by the KSZ9031RNX default register settings. • GTX_CLK clock skew is provided by the MAC. • No PCB delay is required for GTX_CLK and RX_CLK clocks. The following examples show how to read/write to MMD Address 2h, Register 8h for the RGMII GTX_CLK and RX_CLK skew settings. MMD register access is through the direct portal registers Dh and Eh. For more programming details, refer to the “MMD Registers – Descriptions” section. • Read back value of MMD Address 2h, Register 8h. - Write register 0xD = 0x0002 // Select MMD Device Address 2h - Write register 0xE = 0x0008 // Select register 8h of MMD Device Address 2h - Write register 0xD = 0x4002 // Select register data for MMD Device Address 2h, register 8h - Read register 0xE // Read value of MMD Device Address 2h, Register 8h October 2012 26 M9999-103112-1.0 Micrel, Inc. • KSZ9031RNX Write value 0x03FF (delay GTX_CLK and RX_CLK pad skews to their maximum values) to MMD Address 2h, register 8h - Write register 0xD = 0x0002 // Select MMD Device Address 2h - Write register 0xE = 0x0008 // Select register 8h of MMD Device Address 2h - Write register 0xD = 0x4002 // Select register data for MMD Device Address 2h, register 8h - Write register 0xE = 0x03FF // Write value 0x03FF to MMD Device Address 2h, register 8h RGMII In-Band Status The KSZ9031RNX provides in-band status to the MAC during the inter-frame gap when RX_DV is de-asserted. RGMII inband status is always enabled after power-up. The in-band status is sent to the MAC using the RXD[3:0] data pins, and is described in Table 7. RX_DV RXD3 RXD[2:1] RXD0 0 Duplex Status RX_CLK clock speed Link Status (valid only when RX_DV is low) 0 = Half-duplex 00 = 2.5MHz (10Mbps) 0 = Link down 01 = 25MHz (100Mbps) 1 = Link up 1 = Full-duplex 10 = 125MHz (1000Mbps) 11 = Reserved Table 7. RGMII In-Band Status MII Management (MIIM) Interface The KSZ9031RNX supports the IEEE 802.3 MII Management interface, also known as the Management Data Input/ Output (MDIO) interface. This interface allows upper-layer devices to monitor and control the state of the KSZ9031RNX. An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification. The MIIM interface consists of the following: • A physical connection that incorporates the clock line (MDC) and the data line (MDIO). • A specific protocol that operates across the physical connection mentioned earlier, which allows an external controller to communicate with one or more KSZ9031RNX devices. Each KSZ9031RNX device is assigned a unique PHY address between 0h and 7h by the PHYAD[2:0] strapping pins. • A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for indirect access to MMD addresses and registers. See the “Register Map” section. PHY address 0h is supported as the unique PHY address only; it is not supported as the broadcast PHY address, which allows for a single write command to simultaneously program an identical PHY register for two or more PHY devices (for example, using PHY address 0h to set register 0h to a value of 0x1940 to set bit [11] to a value of one to enable software power-down). Instead, separate write commands are used to program each PHY device. Table 8 shows the MII Management frame format for the KSZ9031RNX. Preamble Start of Frame Read/Write OP Code PHY Address Bits [4:0] REG Address Bits [4:0] TA Data Bits [15:0] Idle Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z Table 8. MII Management Frame Format for the KSZ9031RNX October 2012 27 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Interrupt (INT_N) The INT_N pin is an optional interrupt signal that is used to inform the external controller that there has been a status update in the KSZ9031RNX PHY register. Bits [15:8] of register 1Bh are the interrupt control bits that enable and disable the conditions for asserting the INT_N signal. Bits [7:0] of register 1Bh are the interrupt status bits that indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 1Bh. Bit [14] of register 1Fh sets the interrupt level to active high or active low. The default is active low. The MII Management bus option gives the MAC processor complete access to the KSZ9031RNX control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change. LED Mode The KSZ9031RNX provides two programmable LED output pins, LED2 and LED1, which are configurable to support two LED modes. The LED mode is configured by the LED_MODE strap-in (pin 41). It is latched at power-up/reset and is defined as follows: • Pull-up: • Pull-down: Tri-color dual-LED mode Single-LED mode Single-LED Mode In single-LED mode, the LED2 pin indicates the link status while the LED1 pin indicates the activity status, as shown in Table 9. LED Pin LED2 LED1 Pin State LED Definition Link/Activity H OFF Link off L ON Link on (any speed) H OFF No activity Toggle Blinking Activity (RX, TX) Table 9. Single-LED Mode – Pin Definition Tri-color Dual-LED Mode In tri-color dual-LED mode, the link and activity status are indicated by the LED2 pin for 1000Base-T; by the LED1 pin for 100Base-TX; and by both LED2 and LED1 pins, working in conjunction, for 10Base-T. This is summarized in Table 10. LED Pin (State) LED Pin (Definition) Link/Activity LED2 LED1 LED2 LED1 H H OFF OFF Link off L H ON OFF 1000 Link / No activity Toggle H Blinking OFF 1000 Link / Activity (RX, TX) H L OFF ON 100 Link / No activity H Toggle OFF Blinking 100 Link / Activity (RX, TX) L L ON ON 10 Link / No activity Toggle Toggle Blinking Blinking 10 Link / Activity (RX, TX) Table 10. Tri-color Dual-LED Mode – Pin Definition Each LED output pin can directly drive an LED with a series resistor (typically 220Ω to 470Ω). October 2012 28 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Loopback Mode The KSZ9031RNX supports the following loopback operations to verify analog and/or digital data paths. • Local (digital) loopback • Remote (analog) loopback Local (Digital) Loopback This loopback mode checks the RGMII transmit and receive data paths between KSZ9031RNX and external MAC, and is supported for all three speeds (10/100/1000Mbps) at full-duplex. The loopback data path is shown in Figure 5. 1. RGMII MAC transmits frames to KSZ9031RNX. 2. Frames are wrapped around inside KSZ9031RNX. 3. KSZ9031RNX transmits frames back to RGMII MAC. Figure 5. Local (Digital) Loopback The following programming steps and register settings are used for local loopback mode. For 1000Mbps loopback, 1. Set register 0h, • Bit [14] = 1 // Enable local loopback mode • Bits [6, 13] = 10 // Select 1000Mbps speed • Bit [12] = 0 // Disable auto-negotiation • Bit [8] = 1 // Select full-duplex mode 2. Set register 9h, • Bit [12] = 1 // Enable master-slave manual configuration • Bit [11] = 0 // Select slave configuration (required for loopback mode) For 10/100Mbps loopback, 1. Set register 0h, • Bit [14] = 1 // Enable local loopback mode • Bits [6, 13] = 00 / 01 // Select 10Mbps/100Mbps speed • Bit [12] = 0 // Disable auto-negotiation • Bit [8] = 1 // Select full-duplex mode October 2012 29 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Remote (Analog) Loopback This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and receive data paths between KSZ9031RNX and its link partner, and is supported for 1000Base-T full-duplex mode only. The loopback data path is shown in Figure 6. 1. The Gigabit PHY link partner transmits frames to KSZ9031RNX. 2. Frames are wrapped around inside KSZ9031RNX. 3. KSZ9031RNX transmits frames back to the Gigabit PHY link partner. Figure 6. Remote (Analog) Loopback The following programming steps and register settings are used for remote loopback mode. 1. Set register 0h, • Bits [6, 13] = 10 // Select 1000Mbps speed • Bit [12] = 0 // Disable auto-negotiation • Bit [8] = 1 // Select full-duplex mode Or just auto-negotiate and link up at 1000Base-T full-duplex mode with link partner. 2. Set Register 11h, • October 2012 Bit [8] = 1 // Enable remote loopback mode 30 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX LinkMD® Cable Diagnostic The LinkMD function uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems, such as open circuits, short circuits, and impedance mismatches. LinkMD operates by sending a pulse of known amplitude and duration down the selected differential pair, then analyzing the polarity and shape of the reflected signal to determine the type of fault: open circuit for a positive/non-inverted amplitude reflection and short circuit for a negative/inverted amplitude reflection. The time duration for the reflected signal to return provides the approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a numerical value that can be translated to a cable distance. LinkMD is initiated by accessing register 12h, the LinkMD – Cable Diagnostic register, in conjunction with register 1Ch, the Auto MDI/MDI-X register. The latter register is needed to disable the Auto MDI/MDI-X function before running the LinkMD test. Additionally, a software reset (Reg. 0h, bit [15] = 1) should be performed before and after running the LinkMD test. The reset helps to ensure the KSZ9031RNX is in the normal operating state before and after the test. NAND Tree Support The KSZ9031RNX provides parametric NAND tree support for fault detection between chip I/Os and board. NAND tree mode is enabled at power-up/reset with the MODE[3:0] strap-in pins set to ‘0100’. Table 11 lists the NAND tree pin order. Pin Description LED2 Input LED1/PME_N1 Input TXD0 Input TXD1 Input TXD2 Input TXD3 Input GTX_CLK Input TX_EN Input RX_DV Input RX_CLK Input INT_N/PME_N2 Input MDC Input MDIO Input CLK125_NDO Output Table 11. NAND Tree Test Pin Order for KSZ9031RNX October 2012 31 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Power Management The KSZ9031RNX incorporates a number of power-management modes and features that provide methods to consume less energy. These are discussed in the following sections. Energy-Detect Power-Down Mode Energy-detect power-down (EDPD) mode is used to further reduce the transceiver power consumption when the cable is unplugged. It is enabled by writing a one to MMD address 1Ch, register 23h, bit [0], and is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link). In EDPD Mode, the KSZ9031RNX shuts down all transceiver blocks, except for the transmitter and energy detect circuits. Power can be reduced further by extending the time interval between the transmissions of link pulses to check for the presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ9031RNX and its link partner, when operating in the same low-power state and with Auto MDI/MDI-X disabled, can wake up when the cable is connected between them. By default, EDPD mode is disabled after power-up. Software Power-Down Mode This mode is used to power down the KSZ9031RNX device when it is not in use after power-up. Software power-down (SPD) mode is enabled by writing a one to register 0h, bit [11]. In the SPD state, the KSZ9031RNX disables all internal functions, except for the MII management interface. The KSZ9031RNX exits the SPD state after a zero is written to register 0h, bit [11]. Chip Power-Down Mode This mode provides the lowest power state for the KSZ9031RNX device when it is mounted on the board but not in use. Chip power-down (CPD) mode is enabled after power-up/reset with the MODE[3:0] strap-in pins set to ‘0111’. The KSZ9031RNX exits CPD mode after a hardware reset is applied to the RESET_N pin (pin 42) with the MODE[3:0] strap-in pins set to an operating mode other than CPD. Energy Efficient Ethernet (EEE) The KSZ9031RNX implements Energy Efficient Ethernet (EEE) as described in IEEE Standard 802.3az for line signaling by the four differential pairs (analog side) and according to the multisource agreement (MSA) of collaborating Gigabit Ethernet chip vendors for the RGMII (digital side). This agreement is based on the IEEE Standard’s EEE implementation for GMII (1000Mbps) and MII (100Mbps). The specification is defined around an EEE-compliant MAC on the host side and an EEE-compliant link partner on the line side that support the special signaling associated with EEE. EEE saves power by keeping the AC signal on the copper Ethernet cable at approximately 0V peak-to-peak as often as possible during periods of no traffic activity, while maintaining the link-up status. This is referred to as low-power idle (LPI) mode or state. During LPI mode, the copper link responds automatically when it receives traffic and resumes normal PHY operation immediately, without blockage of traffic or loss of packet. This involves exiting LPI mode and returning to normal 100/1000Mbps operating mode. Wake-up times are <16µs for 1000Base-T and <30µs for 100Base-TX. The LPI state is controlled independently for transmit and receive paths, allowing the LPI state to be active (enabled) for: • Transmit cable path only • Receive cable path only • Both transmit and receive cable paths The KSZ9031RNX has the EEE function disabled as the power-up default setting. The EEE function is enabled by setting the following EEE advertisement bits at MMD address 7h, register 3Ch, followed by restarting auto-negotiation (writing a ‘1’ to register 0h, bit [9]): • Bit [2] = 1 // Enable 1000Mbps EEE mode • Bit [1] = 1 // Enable 100Mbps EEE mode For standard (non-EEE) 10Base-T mode, normal link pulses (NLPs) with long periods of no AC signal transmission are used to maintain the link during the idle period when there is no traffic activity. To save more power, the KSZ9031RNX provides the option to enable 10Base-Te mode, which saves additional power by reducing the transmitted signal amplitude from 2.5V to 1.75V. To enable 10Base-Te mode, write a ‘1’ to MMD address 1Ch, register 4h, bit [10]. October 2012 32 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX During LPI mode, refresh transmissions are used to maintain the link; power savings occur in quiet periods. Approximately every 20 to 22 milliseconds, a refresh transmission of 200 to 220 microseconds is sent to the link partner. The refresh transmissions and quiet periods are shown in Figure 7. Figure 7. LPI Mode (Refresh Transmissions and Quiet Periods) Transmit Direction Control (MAC-to-PHY) RGMII 1000Mbps transmission from MAC-to-PHY uses both rising and falling edges of the GTX_CLK clock. The KSZ9031RNX uses the TX_EN pin as the RGMII transmit control signal (TX_CTL) to clock in the TX_EN signal on the rising edge and the TX_ER signal on the falling edge. It also uses the TXD[3:0] pins to clock in the TX data low nibble bits [3:0] on the rising edge and the TX data high nibble bits [7:4] on the falling edge. The KSZ9031RNX enters LPI mode for the transmit direction when its attached EEE-compliant MAC de-asserts the TX_EN signal (the TX_CTL pin outputs low on the rising edge), asserts the TX_ER signal (the TX_CTL pin outputs high on the falling edge), and sets TX data bits [7:0] to 0000_0001 (TXD[3:0] pins output 0001 on the rising edge and 0000 on the falling edge). The KSZ9031RNX remains in the 1000Mbps transmit LPI state while the MAC maintains the states of these signals. When the MAC changes any of the TX_EN, TX_ER, or TX data signals from their LPI state values, the KSZ9031RNX exits the LPI transmit state. To save more power, the MAC can stop the GTX_CLK clock after the RGMII signals for the LPI state have been asserted for 10 or more GTX_CLK clock cycles. Figure 8 shows the LPI transition for RGMII transmit in 1000Mbps mode. Figure 8. LPI Transition – RGMII (1000Mbps) Transmit October 2012 33 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX RGMII 100Mbps transmission from MAC-to-PHY uses both rising and falling edges of the GTX_CLK clock. The KSZ9031RNX uses the TX_EN pin as the RGMII transmit control signal (TX_CTL) to clock in the TX_EN signal on the rising edge and the TX_ER signal on the falling edge. It also uses the TXD[3:0] pins to clock in the TX data bits [3:0] on the rising edge. The KSZ9031RNX enters LPI mode for the transmit direction when its attached EEE-compliant MAC de-asserts the TX_EN signal (the TX_CTL pin outputs low on the rising edge), asserts the TX_ER signal (the TX_CTL pin outputs high on the falling edge), and sets TX data bits [3:0] to 0001 (the TXD[3:0] pins output 0001). The KSZ9031RNX remains in the 100Mbps transmit LPI state while the MAC maintains the states of these signals. When the MAC changes any of the TX_EN, TX_ER, or TX data signals from their LPI state values, the KSZ9031RNX exits the LPI transmit state. To save more power, the MAC can stop the GTX_CLK clock after the RGMII signals for the LPI state have been asserted for 10 or more GTX_CLK clock cycles. Figure 9 shows the LPI transition for RGMII transmit in 100Mbps mode. Figure 9. LPI Transition – RGMII (100Mbps) Transmit Receive Direction Control (PHY-to-MAC) RGMII 1000Mbps transmission from PHY-to-MAC uses both rising and falling edges of the RX_CLK clock. The KSZ9031RNX uses the RX_DV pin as the RGMII receive control signal (RX_CTL) to clock out the RX_DV signal on the rising edge and the RX_ER signal on the falling edge It also uses the RXD[3:0] pins to clock out the RX data low nibble bits [3:0] on the rising edge and the RX data high nibble bits [7:4] on the falling edge. The KSZ9031RNX enters LPI mode for the receive direction when it receives the /P/ code bit pattern (sleep/refresh) from its EEE-compliant link partner. It then drives the RX_DV pin low on the rising clock edge and high on the falling clock edge to de-assert the RX_DV signal and assert the RX_ER signal, respectively, to the MAC. Also, the RXD[3:0] pins are driven to 0001 on the rising clock edge and 0000 on the falling clock edge to set the RX data bits [7:0] to 0000_0001. The KSZ9031RNX remains in the 1000Mbps receive LPI state while it continues to receive the refresh from its link partner, so it will continue to maintain and drive the LPI output states for the RGMII receive output pins to inform the attached EEEcompliant MAC that it is in the receive LPI state. When the KSZ9031RNX receives a non /P/ code bit pattern (non Refresh), it exits the receive LPI state and sets the RX_DV and RXD[3:0] output pins accordingly for a normal frame or normal idle. To save more power, the KSZ9031RNX stops the RX_CLK clock output to the MAC after 10 or more RX_CLK clock cycles have occurred in the receive LPI state. Figure 10 shows the LPI transition for RGMII receive in 1000Mbps mode. October 2012 34 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Figure 10. LPI Transition – RGMII (1000Mbps) Receive RGMII 100Mbps transmission from PHY-to-MAC uses both rising and falling edges of the RX_CLK clock. The KSZ9031RNX uses the RX_DV pin as the RGMII receive control signal (RX_CTL) to clock out the RX_DV signal on the rising edge and the RX_ER signal on the falling edge. It also uses the RXD[3:0] pins to clock out the RX data bits [3:0] on the rising edge. The KSZ9031RNX enters LPI mode for the receive direction when it receives the /P/ code bit pattern (sleep/refresh) from its EEE-compliant link partner. It then drives the RX_DV pin low on the rising clock edge and high on the falling clock edge to de-assert the RX_DV signal and assert the RX_ER signal, respectively, to the MAC. Also, the RXD[3:0] pins are driven to 0001. The KSZ9031RNX remains in the 100Mbps receive LPI state while it continues to receive the refresh from its link partner, so it will continue to maintain and drive the LPI output states for the RGMII receive output pins to inform the attached EEE-compliant MAC that it is in the receive LPI state. When the KSZ9031RNX receives a non /P/ code bit pattern (non-refresh), it exits the receive LPI state and sets the RX_DV and RXD[3:0] output pins accordingly for a normal frame or normal idle. The KSZ9031RNX stops the RX_CLK clock output to the MAC after 10 or more RX_CLK clock cycles have occurred in the receive LPI state to save more power. Figure 11 shows the LPI transition for RGMII receive in 100Mbps mode. Figure 11. LPI Transition – RGMII (100Mbps) Receive October 2012 35 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Registers Associated with EEE The following MMD registers are provided for EEE configuration and management: • MMD address 3h, register 0h - PCS EEE – Control register • MMD address 3h, register 1h - PCS EEE – Status register • MMD address 7h, register 3Ch - EEE Advertisement register • MMD address 7h, register 3Dh - EEE Link Partner Advertisement register Wake-On-LAN Wake-On-LAN (WOL) is normally a MAC-based function to wake up a host system (for example, an Ethernet end device, such as a PC) that is in standby power mode. Wake-up is triggered by receiving and detecting a special packet (commonly referred to as the “magic packet”) that is sent by the remote link partner. The KSZ9031RNX can perform the same WOL function if the MAC address of its associated MAC device is entered into the KSZ9031RNX PHY registers for magic-packet detection. When the KSZ9031RNX detects the magic packet, it wakes up the host by driving its power management event (PME) output pin low. By default, the WOL function is disabled. It is enabled by setting the enabling bit and configuring the associated registers for the selected PME wake-up detection method. The KSZ9031RNX provides three methods to trigger a PME wake-up: • Magic-packet detection • Customized-packet detection • Link status change detection Magic-Packet Detection The magic packet’s frame format starts with 6 bytes of 0xFFh and is followed by 16 repetitions of the MAC address of its associated MAC device (local MAC device). When the magic packet is detected from its link partner, the KSZ9031RNX asserts its PME output pin low. The following MMD address 2h registers are provided for magic-packet detection: • Magic-packet detection is enabled by writing a ‘1’ to MMD address 2h, register 10h, bit [6] • The MAC address (for the local MAC device) is written to and stored in MMD address 2h, registers 11h – 13h The KSZ9031RNX does not generate the magic packet. The magic packet must be provided by the external system. Customized-Packet Detection The customized packet has associated register/bit masks to select which byte, or bytes, of the first 64 bytes of the packet to use in the CRC calculation. After the KSZ9031RNX receives the packet from its link partner, the selected bytes for the received packet are used to calculate the CRC. The calculated CRC is compared to the expected CRC value that was previously written to and stored in the KSZ9031RNX PHY registers. If there is a match, the KSZ9031RNX asserts its PME output pin low. Four customized packets are provided to support four types of wake-up scenarios. A dedicated set of registers is used to configure and enable each customized packet. The following MMD registers are provided for customized-packet detection: • Each of the four customized packets is enabled via MMD address 2h, register 10h, - Bit [2] // For customized packets, type 0 - Bit [3] // For customized packets, type 1 - Bit [4] // For customized packets, type 2 - Bit [5] // For customized packets, type 3 October 2012 36 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX • 32-bit expected CRCs are written to and stored in: - MMD address 2h, registers 14h – 15h // For customized packets, type 0 - MMD address 2h, registers 16h – 17h // For customized packets, type 1 - MMD address 2h, registers 18h – 19h // For customized packets, type 2 - MMD address 2h, registers 1Ah – 1Bh // For customized packets, type 3 • Masks to indicate which of the first 64-bytes to use in the CRC calculation are set in: - MMD address 2h, registers 1Ch – 1Fh // For customized packets, type 0 - MMD address 2h, registers 20h – 23h // For customized packets, type 1 - MMD address 2h, registers 24h – 27h // For customized packets, type 2 - MMD address 2h, registers 28h – 2Bh // For customized packets, type 3 • 32-bit calculated CRCs (of receive packet) are stored in: - MMD address 2h, registers 30h – 31h // For customized packets, type 0 - MMD address 2h, registers 32h – 33h // For customized packets, type 1 - MMD address 2h, registers 34h – 35h // For customized packets, type 2 - MMD address 2h, registers 36h – 37h // For customized packets, type 3 Link Status Change Detection If link status change detection is enabled, the KSZ9031RNX asserts its PME output pin low whenever there is a link status change, using the following MMD address 2h register bits and their enabled (1) or disabled (0) settings: • MMD address 2h, register 10h, bit [0] // For link-up detection • MMD address 2h, register 10h, bit [1] // For link-down detection The PME output signal is available on either LED1/PME_N1 (pin 17) or INT_N/PME_N2 (pin 38), and is selected and enabled using MMD address 2h, register 2h, bits [8] and [10], respectively. Additionally, MMD address 2h, register 10h, bits [15:14] defines the output functions for pins 17 and 38. The PME output is active low and requires a 1kΩ pull-up to the VDDIO supply. When asserted, the PME output is cleared by disabling the register bit that enabled the PME trigger source (magic packet, customized packet, link status change). October 2012 37 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Typical Current/Power Consumption Table 12 through Table 15 show the typical current consumption by the core (DVDDL, AVDDL, AVDDL_PLL), transceiver (AVDDH) and digital I/O (DVDDH) supply pins, and the total typical power for the entire KSZ9031RNX device for various nominal operating voltage combinations. Transceiver (3.3V), Digital I/Os (3.3V) 1.2V Core (DVDDL, AVDDL, AVDDL_PLL) 3.3V Transceiver (AVDDH) 3.3V Digital I/Os (DVDDH) Total Chip Power mA mA mA mW 1000Base-T link-up (no traffic) 210 67.4 19.5 538 1000Base-T full-duplex @ 100% utilization 221 66.3 41.5 621 100Base-TX link-up (no traffic) 63.6 28.7 13.9 217 100Base-TX full-duplex @ 100% utilization 63.8 28.6 17.2 228 10Base-T link-up (no traffic) 7.1 15.9 11.5 99 10Base-T full-duplex @ 100% utilization 7.7 28.6 13.7 149 EEE Mode – 1000Mbps 43.5 5.7 30.6 172 EEE Mode – 100Mbps (TX and RX in LPI) 25.6 5.3 18.1 108 Software power-down mode (Reg. 0h.11 = 1) 1.0 4.2 9.3 46 Condition Table 12. Typical Current/Power Consumption – Transceiver (3.3V), Digital I/Os (3.3V) Transceiver (3.3V), Digital I/Os (1.8V) 1.2V Core (DVDDL, AVDDL, AVDDL_PLL) 3.3V Transceiver (AVDDH) 1.8V Digital I/Os (DVDDH) Total Chip Power mA mA mA mW 1000Base-T link-up (no traffic) 210 67.4 11.2 494 1000Base-T full-duplex @ 100% utilization 221 66.3 23.6 526 100Base-TX link-up (no traffic) 63.6 28.7 8.4 186 100Base-TX full-duplex @ 100% utilization 63.8 28.6 9.8 189 10Base-T link-up (no traffic) 7.1 15.9 3.6 67 10Base-T full-duplex @ 100% utilization 7.7 28.6 5.6 114 EEE Mode – 1000Mbps 43.5 5.7 15.9 100 EEE Mode – 100Mbps (TX and RX in LPI) 25.6 5.3 9.1 65 Software power-down mode (Reg. 0h.11 = 1) 1.0 4.2 5.5 25 Condition Table 13. Typical Current/Power Consumption – Transceiver (3.3V), Digital I/Os (1.8V) October 2012 38 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Transceiver (2.5V), Digital I/Os (2.5V) (1) 1.2V Core (DVDDL, AVDDL, AVDDL_PLL) 2.5V Transceiver (AVDDH – commercial temp only) 2.5V Digital I/Os (DVDDH) Total Chip Power mA mA mA mW 1000Base-T link-up (no traffic) 210 58.8 14.7 435 1000Base-T full-duplex @ 100% utilization 221 57.9 31.5 488 100Base-TX link-up (no traffic) 63.6 24.9 10.5 165 100Base-TX full-duplex @ 100% utilization 63.8 24.9 13.0 171 10Base-T link-up (no traffic) 7.1 11.5 6.3 53 10Base-T full-duplex @ 100% utilization 7.7 25.3 9.0 95 Condition EEE Mode – 1000Mbps 43.5 4.5 23.6 122 EEE Mode – 100Mbps (TX and RX in LPI) 25.6 4.1 13.8 75 Software power-down mode (Reg. 0h.11 = 1) 1.0 3.1 6.7 26 Table 14. Typical Current/Power Consumption – Transceiver (2.5V), Digital I/Os (2.5V) Transceiver (2.5V), Digital I/Os (1.8V) (1) Condition 1000Base-T link-up (no traffic) 1.2V Core (DVDDL, AVDDL, AVDDL_PLL) 2.5V Transceiver (AVDDH – commercial temp only) 1.8V Digital I/Os (DVDDH) Total Chip Power mA mA mA mW 210 58.8 11.2 419 1000Base-T full-duplex @ 100% utilization 221 57.9 23.6 452 100Base-TX link-up (no traffic) 63.6 24.9 8.4 154 100Base-TX full-duplex @ 100% utilization 63.8 24.9 9.8 156 10Base-T link-up (no traffic) 7.1 11.5 3.6 44 10Base-T full-duplex @ 100% utilization 7.7 25.3 5.6 83 EEE Mode – 1000Mbps 43.5 4.5 15.9 92 EEE Mode – 100Mbps (TX and RX in LPI) 25.6 4.1 9.1 57 Software power-down mode (Reg. 0h.11 = 1) 1.0 3.1 5.5 19 Table 15. Typical Current/Power Consumption – Transceiver (2.5V), Digital I/Os (1.8V) Note: 1. 2.5V AVDDH is recommended for commercial temperature range (0°C to +70°C) operation only. October 2012 39 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Register Map The register space within the KSZ9031RNX consists of two distinct areas. • Standard registers // Direct register access • MDIO manageable device (MMD) registers // Indirect register access The KSZ9031RNX supports the following standard registers. Register Number (Hex) Description IEEE-Defined Registers 0h Basic Control 1h Basic Status 2h PHY Identifier 1 3h PHY Identifier 2 4h Auto-Negotiation Advertisement 5h Auto-Negotiation Link Partner Ability 6h Auto-Negotiation Expansion 7h Auto-Negotiation Next Page 8h Auto-Negotiation Link Partner Next Page Ability 9h 1000Base-T Control Ah 1000Base-T Status Bh – Ch Reserved Dh MMD Access – Control Eh MMD Access – Register/Data Fh Extended Status Vendor-Specific Registers 10h Reserved 11h Remote Loopback 12h LinkMD Cable Diagnostic 13h Digital PMA/PCS Status 14h Reserved 15h RXER Counter 16h – 1Ah Reserved 1Bh Interrupt Control/Status 1Ch Auto MDI/MDI-X 1Dh – 1Eh 1Fh Reserved PHY Control Table 16. Standard Registers Supported by KSZ9031RNX The KSZ9031RNX supports the following MMD device addresses and their associated register addresses, which make up the indirect MMD registers. October 2012 40 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Device Address (Hex) Register Address (Hex) 1h 5Ah 2h Description 1000Base-T Link-Up Time Control 0h Common Control 1h Strap Status 2h Operation Mode Strap Override 3h Operation Mode Strap Status 4h RGMII Control Signal Pad Skew 5h RGMII RX Data Pad Skew 6h RGMII TX Data Pad Skew 8h RGMII Clock Pad Skew 10h Wake-On-LAN – Control 11h Wake-On-LAN – Magic Packet, MAC-DA-0 12h Wake-On-LAN – Magic Packet, MAC-DA-1 13h Wake-On-LAN – Magic Packet, MAC-DA-2 14h Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0 15h Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1 16h Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0 17h Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1 18h Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0 19h Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1 1Ah Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0 1Bh Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1 1Ch Wake-On-LAN – Customized Packet, Type 0, Mask 0 1Dh Wake-On-LAN – Customized Packet, Type 0, Mask 1 1Eh Wake-On-LAN – Customized Packet, Type 0, Mask 2 1Fh Wake-On-LAN – Customized Packet, Type 0, Mask 3 20h Wake-On-LAN – Customized Packet, Type 1, Mask 0 21h Wake-On-LAN – Customized Packet, Type 1, Mask 1 22h Wake-On-LAN – Customized Packet, Type 1, Mask 2 23h Wake-On-LAN – Customized Packet, Type 1, Mask 3 24h Wake-On-LAN – Customized Packet, Type 2, Mask 0 25h Wake-On-LAN – Customized Packet, Type 2, Mask 1 26h Wake-On-LAN – Customized Packet, Type 2, Mask 2 27h Wake-On-LAN – Customized Packet, Type 2, Mask 3 28h Wake-On-LAN – Customized Packet, Type 3, Mask 0 29h Wake-On-LAN – Customized Packet, Type 3, Mask 1 2Ah Wake-On-LAN – Customized Packet, Type 3, Mask 2 2Bh Wake-On-LAN – Customized Packet, Type 3, Mask 3 3h 0h 1h PCS EEE – Status 7h 3Ch EEE Advertisement 3Dh EEE Link Partner Advertisement 1Ch PCS EEE – Control 4h Analog Control 4 23h EDPD Control Table 17. MMD Registers Supported by KSZ9031RNX October 2012 41 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Standard Registers Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE 802.3 Specification. Within this address space, the first 16 registers (registers 0h to Fh) are defined according to the IEEE specification, while the remaining 16 registers (registers 10h to 1Fh) are defined specific to the PHY vendor. IEEE Defined Registers – Descriptions Address Name (1) Description Mode 1 = Software PHY reset RW/SC 0 RW 0 RW 0 RW 1 RW 0 RW 0 RW/SC 0 RW 1 Default Register 0h – Basic Control 0.15 Reset 0 = Normal operation This bit is self-cleared after a ‘1’ is written to it. 0.14 Loopback 1 = Loopback mode 0 = Normal operation 0.13 Speed Select (LSB) [0.6, 0.13] [1,1] = Reserved [1,0] = 1000Mbps [0,1] = 100Mbps [0,0] = 10Mbps This bit is ignored if auto-negotiation is enabled (Reg. 0.12 = 1). 0.12 0.11 AutoNegotiation Enable Power-Down 1 = Enable auto-negotiation process 0 = Disable auto-negotiation process If enabled, auto-negotiation result overrides settings in Reg. 0.13, 0.8 and 0.6. 1 = Power-down mode 0 = Normal operation 0.10 Isolate 1 = Electrical isolation of PHY from RGMII 0 = Normal operation 0.9 Restart AutoNegotiation 1 = Restart auto-negotiation process 0 = Normal operation This bit is self-cleared after a ‘1’ is written to it. 0.8 Duplex Mode 1 = Full-duplex 0.7 Reserved Reserved RW 0 0.6 Speed Select (MSB) [0.6, 0.13] RW Set by MODE[3:0] strapping pins. 0 = Half-duplex [1,1] = Reserved See the “Strapping Options” section for details. [1,0] = 1000Mbps [0,1] = 100Mbps [0,0] = 10Mbps This bit is ignored if auto-negotiation is enabled (Reg. 0.12 = 1). 0.5:0 October 2012 Reserved Reserved RO 42 00_0000 M9999-103112-1.0 Micrel, Inc. Address KSZ9031RNX Name (1) Description Mode 1 = T4 capable RO 0 RO 1 RO 1 RO 1 RO 1 Default Register 1h – Basic Status 1.15 100Base-T4 0 = Not T4 capable 1.14 1.13 100Base-TX Full-Duplex 1 = Capable of 100Mbps full-duplex 0 = Not capable of 100Mbps full-duplex 100Base-TX Half-Duplex 1 = Capable of 100Mbps half-duplex 1.12 10Base-T Full-Duplex 1 = Capable of 10Mbps full-duplex 1.11 10Base-T Half-Duplex 1 = Capable of 10Mbps half-duplex 0 = Not capable of 100Mbps half-duplex 0 = Not capable of 10Mbps full-duplex 0 = Not capable of 10Mbps half-duplex 1.10:9 Reserved Reserved RO 00 1.8 Extended Status 1 = Extended status info in Reg. 15h. RO 1 1.7 Reserved Reserved RO 0 1.6 No Preamble 1 = Preamble suppression RO 1 RO 0 RO/LH 0 RO 1 RO/LL 0 RO/LH 0 1 = Supports extended capability registers RO 1 Assigned to bits [3:18] of the organizationally unique identifier (OUI). KENDIN Communication’s OUI is 0010A1h. RO 0022h 0 = No extended status info in Reg. 15h. 0 = Normal preamble 1.5 1.4 AutoNegotiation Complete 0 = Auto-negotiation process not completed 1 = Auto-negotiation process completed Remote Fault 1 = Remote fault 0 = No remote fault 1.3 1.2 AutoNegotiation Ability 1 = Can perform auto-negotiation Link Status 1 = Link is up 0 = Cannot perform auto-negotiation 0 = Link is down 1.1 Jabber Detect 1.0 Extended Capability 1 = Jabber detected 0 = Jabber not detected (default is low) Register 2h – PHY Identifier 1 2.15:0 PHY ID Number Register 3h – PHY Identifier 2 3.15:10 PHY ID Number Assigned to bits [19:24] of the organizationally unique identifier (OUI). KENDIN Communication’s OUI is 0010A1h. RO 0001_01 3.9:4 Model Number Six-bit manufacturer’s model number RO 10_0010 3.3:0 Revision Number Four-bit manufacturer’s revision number RO Indicates silicon revision RW 0 Register 4h – Auto-Negotiation Advertisement 4.15 Next Page 1 = Next page capable 0 = No next page capability October 2012 43 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Address Name 4.14 4.13 (1) Description Mode Reserved Reserved RO 0 Remote Fault 1 = Remote fault supported RW 0 Default 0 = No remote fault 4.12 Reserved Reserved RO 0 4.11:10 Pause [4.11, 4.10] RW 00 RO 0 RW 1 RW 1 RW 1 RW 1 RW 0_0001 RO 0 RO 0 RO 0 [0,0] = No pause [1,0] = Asymmetric pause (link partner) [0,1] = Symmetric pause [1,1] = Symmetric and asymmetric pause (local device) 4.9 100Base-T4 1 = T4 capable 0 = No T4 capability 4.8 100Base-TX Full-Duplex 4.7 100Base-TX Half-Duplex 1 = 100Mbps half-duplex capable 10Base-T Full-Duplex 1 = 10Mbps full-duplex capable 4.5 10Base-T Half-Duplex 1 = 10Mbps half-duplex capable 4.4:0 Selector Field [00001] = IEEE 802.3 4.6 1 = 100Mbps full-duplex capable 0 = No 100Mbps full-duplex capability 0 = No 100Mbps half-duplex capability 0 = No 10Mbps full-duplex capability 0 = No 10Mbps half-duplex capability Register 5h – Auto-Negotiation Link Partner Ability 5.15 Next Page 1 = Next page capable 0 = No next page capability 5.14 Acknowledge 5.13 Remote Fault 1 = Link code word received from partner 0 = Link code word not yet received 1 = Remote fault detected 0 = No remote fault 5.12 Reserved Reserved RO 0 5.11:10 Pause [5.11, 5.10] RW 00 RO 0 RO 0 RO 0 RO 0 [0,0] = No pause [1,0] = Asymmetric pause (link partner) [0,1] = Symmetric pause [1,1] = Symmetric and asymmetric pause (local device) 5.9 100Base-T4 5.8 100Base-TX Full-Duplex 1 = T4 capable 0 = No T4 capability 5.7 5.6 October 2012 1 = 100Mbps full-duplex capable 0 = No 100Mbps full-duplex capability 100Base-TX Half-Duplex 1 = 100Mbps half-duplex capable 10Base-T Full-Duplex 1 = 10Mbps full-duplex capable 0 = No 100Mbps half-duplex capability 0 = No 10Mbps full-duplex capability 44 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX (1) Address Name Description Mode 5.5 10Base-T Half-Duplex 1 = 10Mbps half-duplex capable RO 0 Selector Field [00001] = IEEE 802.3 RO 0_0000 5.4:0 Default 0 = No 10Mbps half-duplex capability Register 6h – Auto-Negotiation Expansion 6.15:5 Reserved Reserved RO 0000_0000_000 6.4 Parallel Detection Fault 1 = Fault detected by parallel detection RO/LH 0 6.3 Link Partner Next Page Able 1 = Link partner has next page capability RO 0 Next Page Able 1 = Local device has next page capability RO 1 6.1 Page Received 1 = New page received RO/LH 0 6.0 Link Partner AutoNegotiation Able RO 0 RW 0 6.2 0 = No fault detected by parallel detection 0 = Link partner does not have next page capability 0 = Local device does not have next page capability 0 = New page not received 1 = Link partner has auto-negotiation capability 0 = Link partner does not have auto-negotiation capability Register 7h – Auto-Negotiation Next Page 7.15 Next Page 1 = Additional next pages will follow 0 = Last page 7.14 Reserved Reserved RO 0 7.13 Message Page 1 = Message page RW 1 RW 0 RO 0 RW 000_0000_0001 RO 0 RO 0 RO 0 RO 0 RO 0 RO 000_0000_0000 0 = Unformatted page 7.12 Acknowledge2 1 = Will comply with message 0 = Cannot comply with message 7.11 Toggle 1 = Previous value of the transmitted link code word equaled logic one 0 = Logic zero 7.10:0 Message Field 11-bit wide field to encode 2048 messages Register 8h – Auto-Negotiation Link Partner Next Page Ability 8.15 Next Page 1 = Additional next pages will follow 0 = Last page 8.14 Acknowledge 1 = Successful receipt of link word 0 = No successful receipt of link word 8.13 Message Page 8.12 Acknowledge2 1 = Message page 0 = Unformatted page 1 = Able to act on the information 0 = Not able to act on the information 8.11 Toggle 1 = Previous value of transmitted link code word equal to logic zero 0 = Previous value of transmitted link code word equal to logic one 8.10:0 October 2012 Message Field 45 M9999-103112-1.0 Micrel, Inc. Address KSZ9031RNX Name Description Mode (1) Default Register 9h – 1000Base-T Control 9.15:13 Test Mode Bits Transmitter test mode operations [9.15:13] 9.12 9.11 RW 000 RW 0 RW 0 RW 0 RW 1 RW Set by MODE[3:0] strapping pins. Mode [000] Normal operation [001] Test mode 1 –Transmit waveform test [010] Test mode 2 –Transmit jitter test in master mode [011] Test mode 3 –Transmit jitter test in slave mode [100] Test mode 4 –Transmitter distortion test [101] Reserved, operations not identified [110] Reserved, operations not identified [111] Reserved, operations not identified Master-Slave Manual Configuration Enable 1 = Enable master-slave manual configuration value Master-Slave Manual Configuration Value 1 = Configure PHY as master during masterslave negotiation 0 = Disable master-slave manual configuration value 0 = Configure PHY as slave during masterslave negotiation This bit is ignored if master-slave manual configuration is disabled (Reg. 9.12 = 0). 9.10 Port Type 1 = Indicate the preference to operate as multiport device (master) 0 = Indicate the preference to operate as singleport device (slave) This bit is valid only if master-slave manual configuration is disabled (Reg. 9.12 = 0). 9.9 1000Base-T Full-Duplex 1 = Advertise PHY is 1000Base-T full-duplex capable 0 = Advertise PHY is not 1000Base-T fullduplex capable 9.8 1000Base-T Half-Duplex 1 = Advertise PHY is 1000Base-T half-duplex capable 0 = Advertise PHY is not 1000Base-T halfduplex capable 9.7:0 Reserved Write as 0, ignore on read See the “Strapping Options” section for details. RO – RO/LH/SC 0 Register Ah – 1000Base-T Status A.15 October 2012 Master-Slave Configuration Fault 1 = Master-slave configuration fault detected 0 = No master-slave configuration fault detected 46 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX (1) Address Name Description Mode A.14 Master-Slave Configuration Resolution 1 = Local PHY configuration resolved to master RO 0 A.13 Local Receiver Status 1 = Local receiver OK (loc_rcvr_status = 1) RO 0 A.12 Remote Receiver Status 1 = Remote receiver OK (rem_rcvr_status = 1) RO 0 Link Partner 1000Base-T Full-Duplex Capability 1 = Link partner is capable of 1000Base-T fullduplex RO 0 RO 0 A.11 A.10 Default 0 = Local PHY configuration resolved to slave 0 = Local receiver not OK (loc_rcvr_status = 0) 0 = Remote receiver not OK (rem_rcvr_status = 0) 0 = Link partner is not capable of 1000Base-T full-duplex Link Partner 1000Base-T Half-Duplex Capability 0 = Link Partner is not capable of 1000Base-T half-duplex A.9:8 Reserved Reserved RO 00 A.7:0 Idle Error Count Cumulative count of errors detected when receiver is receiving idles and PMA_TXMODE.indicate = SEND_N. RO/SC 0000_0000 RW 00 1 = Link partner is capable of 1000Base-T halfduplex The counter is incremented every symbol period that rxerror_status = ERROR. Register Dh – MMD Access – Control D.15:14 MMD – Operation Mode For the selected MMD device address (bits [4:0] of this register), these two bits select one of the following register or data operations and the usage for MMD Access – Register/Data (Reg. Eh). 00 = Register 01 = Data, no post increment 10 = Data, post increment on reads and writes 11 = Data, post increment on writes only D.13:5 Reserved Reserved RW 00_0000_000 D.4:0 MMD – Device Address These five bits set the MMD device address. RW 0_0000 RW 0000_0000_0000_0000 Register Eh – MMD Access – Register/Data E.15:0 MMD – Register/Data For the selected MMD device address (Reg. Dh, bits [4:0]), When Reg. Dh, bits [15:14] = 00, this register contains the read/write register address for the MMD device address. Otherwise, this register contains the read/write data value for the MMD device address and its selected register address. See also Reg. Dh, bits [15:14], for descriptions of post increment reads and writes of this register for data operation. October 2012 47 M9999-103112-1.0 Micrel, Inc. Address KSZ9031RNX Name (1) Description Mode 1 = PHY can perform 1000Base-X full-duplex RO 0 RO 0 RO 1 RO 1 RO – Default Register Fh – Extended Status F.15 1000Base-X Full-Duplex 0 = PHY cannot perform 1000Base-X fullduplex F.14 1000Base-X Half-Duplex 1 = PHY can perform 1000Base-X half-duplex 0 = PHY cannot perform 1000Base-X half-duplex F.13 1000Base-T Full-Duplex 1 = PHY can perform 1000Base-T full-duplex 0 = PHY cannot perform 1000Base-T full-duplex F.12 F.11:0 1000Base-T Half-Duplex 1 = PHY can perform 1000Base-T half-duplex Reserved Ignore when read 0 = PHY cannot perform 1000Base-T half-duplex Note: 1. RW = Read/Write. RO = Read only. SC = Self-cleared. LH = Latch high. LL = Latch low. Vendor-Specific Registers – Descriptions Address Name Description Mode (1) Default Register 11h – Remote Loopback 11.15:9 Reserved Reserved RW 0000_000 11.8 Remote Loopback 1 = Enable remote loopback RW 0 11.7:1 Reserved Reserved RW 1111_010 11.0 Reserved Reserved RO 0 RW/SC 0 RW 0 0 = Disable remote loopback Register 12h – LinkMD – Cable Diagnostic 12.15 Cable Diagnostic Test Enable Write value: 1 = Enable cable diagnostic test. After test has completed, this bit is self-cleared. 0 = Disable cable diagnostic test. Read value: 1 = Cable diagnostic test is in progress. 0 = Indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. 12.14 October 2012 Reserved This bit should always be set to ‘0’. 48 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX (1) Address Name Description Mode 12.13:12 Cable Diagnostic Test Pair These two bits select the differential pair for testing: RW 00 Default 00 = Differential pair A (pins 2, 3) 01 = Differential pair B (pins 5, 6) 10 = Differential pair C (pins 7, 8) 11 = Differential pair D (pins 10, 11) 12.11:10 Reserved These two bits should always be set to ‘00’. RW 00 12.9:8 Cable Diagnostic Status These two bits represent the test result for the selected differential pair in bits [13:12] of this register. RO 00 RO 0000_0000 00 = Normal cable condition (no fault detected) 01 = Open cable fault detected 10 = Short cable fault detected 11 = Reserved 12.7:0 Cable Diagnostic Fault Data For the open or short cable fault detected in bits [9:8] of this register, this 8-bit value represents the distance to the cable fault. Register 13h – Digital PMA/PCS Status 13.15:3 Reserved Reserved RO/LH 0000_0000_0000_0 13.2 1000Base-T Link Status 1000Base-T link status RO 0 RO 0 Reserved RO 0 Receive error counter for symbol error frames RO/RC 0000_0000_0000_0000 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 1 = Link status is OK 0 = Link status is not OK 13.1 100Base-TX Link Status 100Base-TX link status 1 = Link status is OK 0 = Link status is not OK 13.0 Reserved Register 15h – RXER Counter 15.15:0 RXER Counter Register 1Bh – Interrupt Control/Status 1B.15 1B.14 1B.13 1B.12 1B.11 1B.10 October 2012 Jabber Interrupt Enable 1 = Enable jabber interrupt Receive Error Interrupt Enable 1 = Enable receive error interrupt Page Received Interrupt Enable Parallel Detect Fault Interrupt Enable Link Partner Acknowledge Interrupt Enable Link-Down Interrupt Enable 0 = Disable jabber interrupt 0 = Disable receive error interrupt 1 = Enable page received interrupt 0 = Disable page received interrupt 1 = Enable parallel detect fault interrupt 0 = Disable parallel detect fault interrupt 1 = Enable link partner acknowledge interrupt 0 = Disable link partner acknowledge interrupt 1 = Enable link-down interrupt 0 = Disable link-down interrupt 49 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX (1) Address Name Description Mode 1B.9 Remote Fault Interrupt Enable 1 = Enable remote fault interrupt RW 0 Link-Up Interrupt Enable 1 = Enable link-up interrupt RW 0 Jabber Interrupt 1 = Jabber occurred RO/RC 0 1B.6 Receive Error Interrupt 1 = Receive error occurred RO/RC 0 1B.5 Page Receive Interrupt 1 = Page receive occurred RO/RC 0 0 = Page receive did not occur Parallel Detect Fault Interrupt RO/RC 0 0 = Parallel detect fault did not occur RO/RC 0 RO/RC 0 RO/RC 0 RO/RC 0 1B.8 1B.7 1B.4 1B.3 0 = Disable remote fault interrupt 0 = Disable link-up interrupt 0 = Jabber did not occur 0 = Receive error did not occur 1 = Parallel detect fault occurred Link Partner Acknowledge Interrupt 1 = Link partner acknowledge occurred Link-Down Interrupt 1 = Link-down occurred 1B.1 Remote Fault Interrupt 1 = Remote fault occurred 1B.0 Link-Up Interrupt 1B.2 Default 0 = Link partner acknowledge did not occur 0 = Link-down did not occur 0 = Remote fault did not occur 1 = Link-up occurred 0 = Link-up did not occur Register 1Ch – Auto MDI/MDI-X 1C.15:8 Reserved Reserved RW 0000_0000 1C.7 MDI Set When Swap-Off (bit [6] of this register) is asserted (1), RW 0 RW 0 Reserved RW 00_0000 1 = PHY is set to operate as MDI mode 0 = PHY is set to operate as MDI-X mode This bit has no function when Swap-Off is deasserted (0). 1C.6 Swap-Off 1 = Disable Auto MDI/MDI-X function 0 = Enable Auto MDI/MDI-X function 1C.5:0 Reserved Register 1Fh – PHY Control 1F.15 Reserved Reserved RW 0 1F.14 Interrupt Level 1 = Interrupt pin active high RW 0 0 = Interrupt pin active low 1F.13:12 Reserved Reserved RW 00 1F.11:10 Reserved Reserved RO/LH/RC 00 1F.9 Enable Jabber 1 = Enable jabber counter RW 1 1F.8:7 Reserved Reserved RW 00 1F.6 Speed Status 1000Base-T 1 = Indicate chip final speed status at 1000Base-T RO 0 0 = Disable jabber counter October 2012 50 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX (1) Address Name Description Mode 1F.5 Speed Status 100Base-TX 1 = Indicate chip final speed status at 100Base-TX RO 0 1F.4 Speed Status 10Base-T 1 = Indicate chip final speed status at 10Base-T RO 0 1F.3 Duplex Status Indicate chip duplex status RO 0 RO 0 Default 1 = Full-duplex 0 = Half-duplex 1F.2 1000Base-T Master/Slave Status Indicate chip master/slave status 1 = 1000Base-T master mode 0 = 1000Base-T slave mode 1F.1 Reserved Reserved RW 0 1F.0 Link Status Check Fail 1 = Fail RO 0 0 = Not failing Note: 1. RW = Read/Write. RC = Read-cleared RO = Read only. SC = Self-cleared. LH = Latch high. October 2012 51 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX MMD Registers MMD registers provide indirect read/write access to up to 32 MMD Device Addresses with each device supporting up to 65,536 16-bit registers, as defined in Clause 22 of the IEEE 802.3 Specification. The KSZ9031RNX, however, uses only a small fraction of the available registers. See the “Register Map” section for a list of supported MMD device addresses and their associated register addresses. The following two standard registers serve as the portal registers to access the indirect MMD registers. • Standard register Dh – MMD Access – Control • Standard register Eh – MMD Access – Register/Data Address Name Description Mode Default RW 00 Register Dh – MMD Access – Control D.15:14 MMD – Operation Mode For the selected MMD device address (bits [4:0] of this register), these two bits select one of the following register or data operations and the usage for MMD Access – Register/Data (Reg. Eh). 00 = Register 01 = Data, no post increment 10 = Data, post increment on reads and writes 11 = Data, post increment on writes only D.13:5 Reserved Reserved RW 00_0000_000 D.4:0 MMD – Device Address These five bits set the MMD device address. RW 0_0000 RW 0000_0000_0000_0000 Register Eh – MMD Access – Register/Data E.15:0 MMD – Register/Data For the selected MMD device address (Reg. Dh, bits [4:0]), When Reg. Dh, bits [15:14] = 00, this register contains the read/write register address for the MMD device address. Otherwise, this register contains the read/write data value for the MMD device address and its selected register address. See also Register Dh, bits [15:14] descriptions for post increment reads and writes of this register for data operation. Table 18. Portal Registers (Access to Indirect MMD Registers) Examples: • MMD Register Write Write MMD – Device Address 2h, Register 10h = 0001h to enable link-up detection to trigger PME for WOL. 1. Write register Dh with 0002h // Set up register address for MMD – Device Address 2h. 2. Write register Eh with 0010h // Select register 10h of MMD – Device Address 2h. 3. Write register Dh with 4002h // Select register data for MMD – Device Address 2h, Register 10h. 4. Write register Eh with 0001h // Write value 0001h to MMD – Device Address 2h, Register 10h. October 2012 52 M9999-103112-1.0 Micrel, Inc. • KSZ9031RNX MMD Register Read Read MMD – Device Address 2h, Register 11h – 13h for the magic packet’s MAC address 1. Write register Dh with 0002h // Set up register address for MMD – Device Address 2h. 2. Write register Eh with 0011h // Select register 11h of MMD – Device Address 2h. 3. Write register Dh with 8002h // Select register data for MMD – Device Address 2h, Register 11h. 4. Read register Eh // Read data in MMD – Device Address 2h, Register 11h. 5. Read register Eh // Read data in MMD – Device Address 2h, Register 12h. 6. Read register Eh // Read data in MMD – Device Address 2h, Register 13h. MMD Registers – Descriptions Address Name Description Mode (1) Default MMD Address 1h, Register 5Ah – 1000Base-T Link-Up Time Control 1.5A.15:9 Reserved Reserved RO 0000_000 1.5A.8:4 Reserved Reserved RW 1_0000 1.5A.3:1 1000Base-T Link-Up Time When the link partner is another KSZ9031 device, the 1000Base-T link-up time can be long. These three bits provide an optional setting to reduce the 1000Base-T link-up time. RW 100 RW 0 100 = Default power-up setting 011 = Optional setting to reduce link-up time when the link partner is a KSZ9031 device. All other settings are reserved and should not be used. The optional setting is safe to use with any link partner. Note: Read/Write access to this register bit is available only when Reg. 0h is set to 0x2100 to disable auto-negotiation and force 100Base-TX mode. 1.5A.0 Reserved Reserved MMD Address 2h, Register 0h – Common Control 2.0.15:4 Reserved Reserved RW 0000_0000_0000 2.0.3 LED Mode Override strap-in for LED_MODE RW Set by LED_MODE strapping pin. 1 = Single-LED mode See the “Strapping Options” section for details. 0 = Bi-color dual-LED mode 2.0.2 Reserved Reserved RW 0 2.0.1 CLK125_EN Status Override strap-in for CLK125_EN RW Set by CLK125_EN strapping pin. 1 = CLK125_EN strap-in is enabled See the “Strapping Options” section for details. 0 = CLK125_EN strap-in is disabled 2.0.0 Reserved Reserved RW 0 RO 0000_0000 MMD Address 2h, Register 1h – Strap Status 2.1.15:8 October 2012 Reserved Reserved 53 M9999-103112-1.0 Micrel, Inc. Address 2.1.7 KSZ9031RNX Name LED_MODE Strap-In Status Description Mode Strap to RO 1 = Single-LED mode (1) Default Set by LED_MODE strapping pin. See the “Strapping Options” section for details. 0 = Bi-color dual-LED mode 2.1.6 Reserved Reserved RO 0 2.1.5 CLK125_EN Strap-In Status Strap to RO Set by CLK125_EN strapping pin. 1 = CLK125_EN strap-in is enabled See the “Strapping Options” section for details. 0 = CLK125_EN strap-in is disabled 2.1.4:3 Reserved Reserved RO 00 2.1.2:0 PHYAD[2:0] Strap-In Value Strap-in value for PHY address RO Set by PHYAD[2:0] strapping pin. Bits [4:3] of PHY address are always set to ‘00’. See the “Strapping Options” section for details. MMD Address 2h, Register 2h – Operation Mode Strap Override 2.2.15 RGMII All Capabilities Override 1 = Override strap-in for RGMII to advertise all capabilities RW Set by MODE[3:0] strapping pin. 2.2.14 RGMII No 1000BT_HD Override 1 = Override strap-in for RGMII to advertise all capabilities except 1000Base-T half-duplex RW 2.2.13 RGMII 1000BT_H/FD Only Override 1 = Override strap-in for RGMII to advertise 1000Base-T full- and half-duplex only RW 2.2.12 RGMII 1000BT_FD Only Override 1 = Override strap-in for RGMII to advertise 1000Base-T full-duplex only RW 2.2.11 Reserved Reserved RW 0 2.2.10 PME_N2 Output Enable For INT_N/PME_N2 (pin 38), RW 0 See the “Strapping Options” section for details. 1 = Enable PME output 0 = Disable PME output This bit works in conjunction with MMD Address 2h, Reg. 10h, Bits [15:14] to define the output for pin 38. 2.2.9 Reserved Reserved RW 0 2.2.8 PME_N1 Output Enable For LED1/PME_N1 (pin 17), RW 0 RW Set by MODE[3:0] strapping pin. 1 = Enable PME output 0 = Disable PME output This bit works in conjunction with MMD Address 2h, Reg. 10h, Bits [15:14] to define the output for pin 17. 2.2.7 Chip PowerDown Override 1 = Override strap-in for chip power-down mode See the “Strapping Options” section for details. 2.2.6:5 Reserved Reserved RW 00 2.2.4 NAND Tree Override 1 = Override strap-in for NAND Tree mode RW Set by MODE[3:0] strapping pin. Reserved Reserved 2.2.3:0 October 2012 See the “Strapping Options” section for details. RW 54 0000 M9999-103112-1.0 Micrel, Inc. Address KSZ9031RNX Name Description Mode (1) Default MMD Address 2h, Register 3h – Operation Mode Strap Status 2.3.15 RGMII All Capabilities Strap-In Status 1 = Strap to RGMII to advertise all capabilities 2.3.14 RGMII No 1000BT_HD Strap-In Status 1 = Strap to RGMII to advertise all capabilities except 1000Base-T half-duplex RO 2.3.13 RGMII Only 1000BT_H/FD Strap-In Status 1 = Strap to RGMII to advertise 1000Base-T full-and half-duplex only RO 2.3.12 RGMII Only 1000BT_FD Strap-In Status 1 = Strap to RGMII to advertise 1000Base-T full-duplex only RO 2.3.11:8 Reserved Reserved RO 0000 2.3.7 Chip PowerDown Strap-In Status 1 = Strap to chip power-down mode RO Set by MODE[3:0] strapping pin. 2.3.6:5 Reserved Reserved RO 00 2.3.4 NAND Tree Strap-In Status 1 = Strap to NAND Tree mode RO Set by MODE[3:0] strapping pin. Reserved Reserved 2.3.3:0 RO Set by MODE[3:0] strapping pin. See the “Strapping Options” section for details. See the “Strapping Options” section for details. See the “Strapping Options” section for details. RO 0000 MMD Address 2h, Register 4h – RGMII Control Signal Pad Skew 2.4.15:8 Reserved Reserved RW 0000_0000 2.4.7:4 RX_DV Pad Skew RGMII RX_CTL output pad skew control (0.06ns/step) RW 0111 2.4.3:0 TX_EN Pad Skew RGMII TX_CTL input pad skew control (0.06ns/step) RW 0111 MMD Address 2h, Register 5h – RGMII RX Data Pad Skew 2.5.15:12 RXD3 Pad Skew RGMII RXD3 output pad skew control (0.06ns/step) RW 0111 2.5.11:8 RXD2 Pad Skew RGMII RXD2 output pad skew control (0.06ns/step) RW 0111 2.5.7:4 RXD1 Pad Skew RGMII RXD1 output pad skew control (0.06ns/step) RW 0111 2.5.3:0 RXD0 Pad Skew RGMII RXD0 output pad skew control (0.06ns/step) RW 0111 MMD Address 2h, Register 6h – RGMII TX Data Pad Skew 2.6.15:12 TXD3 Pad Skew RGMII TXD3 output pad skew control (0.06ns/step) RW 0111 2.6.11:8 TXD2 Pad Skew RGMII TXD2 output pad skew control (0.06ns/step) RW 0111 2.6.7:4 TXD1 Pad Skew RGMII TXD1 output pad skew control (0.06ns/step) RW 0111 2.6.3:0 TXD0 Pad Skew RGMII TXD0 output pad skew control (0.06ns/step) RW 0111 October 2012 55 M9999-103112-1.0 Micrel, Inc. Address KSZ9031RNX Name Description Mode (1) Default MMD Address 2h, Register 8h – RGMII Clock Pad Skew 2.8.15:10 Reserved Reserved RW 0000_00 2.8.9:5 GTX_CLK Pad Skew RGMII GTX_CLK input pad skew control (0.06ns/step) RW 01_111 2.8.4:0 RX_CLK Pad Skew RGMII RX_CLK output pad skew control (0.06ns/step) RW 0_1111 RW 00 MMD Address 2h, Register 10h – Wake-On-LAN – Control 2.10.15:14 PME Output Select These two bits work in conjunction with MMD Address 2h, Reg. 2h, Bits [8] and [10] for PME_N1 and PME_N2 enable, to define the output for pins 17 and 38, respectively. LED1/PME_N1 (pin 17) 00 = PME_N1 output only 01 = LED1 output only 10 = LED1 and PME_N1 output 11 = Reserved INT_N/PME_N2 (pin 38) 00 = PME_N2 output only 01 = INT_N output only 10 = INT_N and PME_N2 output 11 = Reserved 2.10.13:7 Reserved Reserved RW 00_0000_0 2.10.6 Magic Packet Detect Enable 1 = Enable magic-packet detection RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 2.10.5 2.10.4 2.10.3 2.10.2 0 = Disable magic-packet detection CustomPacket Type 3 Detect Enable 0 = Disable custom-packet, Type 3 detection CustomPacket Type 2 Detect Enable 0 = Disable custom-packet, Type 2 detection CustomPacket Type 1 Detect Enable CustomPacket Type 0 Detect Enable 1 = Enable custom-packet, Type 3 detection 1 = Enable custom-packet, Type 2 detection 1 = Enable custom-packet, Type 1 detection 0 = Disable custom-packet, Type 1 detection 1 = Enable custom-packet, Type 0 detection 0 = Disable custom-packet, Type 0 detection 2.10.1 Link-Down Detect Enable 1 = Enable link-down detection 2.10.0 Link-Up Detect Enable 1 = Enable link-up detection October 2012 0 = Disable link-down detection 0 = Disable link-up detection 56 M9999-103112-1.0 Micrel, Inc. Address KSZ9031RNX Name Description Mode (1) Default MMD Address 2h, Register 11h – Wake-On-LAN – Magic Packet, MAC-DA-0 2.11.15:0 Magic Packet MAC-DA-0 This register stores the lower two bytes of the destination MAC address for the magic packet. RW 0000_0000_0000_0000 RW 0000_0000_0000_0000 RW 0000_0000_0000_0000 Bit [15:8] = Byte 2 (MAC Address [15:8]) Bit [7:0] = Byte 1 (MAC Address [7:0]) The upper four bytes of the destination MAC address are stored in the following two registers. MMD Address 2h, Register 12h – Wake-On-LAN – Magic Packet, MAC-DA-1 2.12.15:0 Magic Packet MAC-DA-1 This register stores the middle two bytes of the destination MAC address for the magic packet. Bit [15:8] = Byte 4 (MAC Address [31:24]) Bit [7:0] = Byte 3 (MAC Address [23:16]) The lower two bytes and upper two bytes of the destination MAC address are stored in the previous and following registers, respectively. MMD Address 2h, Register 13h – Wake-On-LAN – Magic Packet, MAC-DA-2 2.13.15:0 Magic Packet MAC-DA-2 This register stores the upper two bytes of the destination MAC address for the magic packet. Bit [15:8] = Byte 6 (MAC Address [47:40]) Bit [7:0] = Byte 5 (MAC Address [39:32]) The lower four bytes of the destination MAC address are stored in the previous two registers. MMD Address 2h, Register 14h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0 MMD Address 2h, Register 16h – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0 MMD Address 2h, Register 18h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0 MMD Address 2h, Register 1Ah – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0 2.14.15:0 2.16.15:0 2.18.15:0 Custom Packet Type X CRC 0 This register stores the lower two bytes for the expected CRC. 0000_0000_0000_0000 Bit [15:8] = Byte 2 (CRC [15:8]) Bit [7:0] 2.1A.15:0 RW = Byte 1 (CRC [7:0]) The upper two bytes for the expected CRC are stored in the following register. MMD Address 2h, Register 15h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1 MMD Address 2h, Register 17h – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1 MMD Address 2h, Register 19h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1 MMD Address 2h, Register 1Bh – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1 2.15.15:0 2.17.15:0 2.19.15:0 2.1B.15:0 Custom Packet Type X CRC 1 This register stores the upper two bytes for the expected CRC. RW 0000_0000_0000_0000 Bit [15:8] = Byte 4 (CRC [31:24]) Bit [7:0] = Byte 3 (CRC [23:16]) The lower two bytes for the expected CRC are stored in the previous register. October 2012 57 M9999-103112-1.0 Micrel, Inc. Address KSZ9031RNX Name Description Mode (1) Default MMD Address 2h, Register 1Ch – Wake-On-LAN – Customized Packet, Type 0, Mask 0 MMD Address 2h, Register 20h – Wake-On-LAN – Customized Packet, Type 1, Mask 0 MMD Address 2h, Register 24h – Wake-On-LAN – Customized Packet, Type 2, Mask 0 MMD Address 2h, Register 28h – Wake-On-LAN – Customized Packet, Type 3, Mask 0 2.1C.15:0 2.20.15:0 2.24.15:0 Custom Packet Type X Mask 0 This register selects the bytes in the first 16 bytes of the packet (bytes 1 thru 16) that will be used for CRC calculation. RW 0000_0000_0000_0000 For each bit in this register, 2.28.15:0 1 = Byte is selected for CRC calculation 0 = Byte is not selected for CRC calculation The register-bit to packet-byte mapping is as follows: Bit [15] : Byte 16 … : … Bit [2] : Byte 2 Bit [0] : Byte 1 MMD Address 2h, Register 1Dh – Wake-On-LAN – Customized Packet, Type 0, Mask 1 MMD Address 2h, Register 21h – Wake-On-LAN – Customized Packet, Type 1, Mask 1 MMD Address 2h, Register 25h – Wake-On-LAN – Customized Packet, Type 2, Mask 1 MMD Address 2h, Register 29h – Wake-On-LAN – Customized Packet, Type 3, Mask 1 2.1D.15:0 2.21.15:0 2.25.15:0 2.29.15:0 Custom Packet Type X Mask 1 This register selects the bytes in the second 16 bytes of the packet (bytes 17 thru 32) that will be used for CRC calculation. RW 0000_0000_0000_0000 For each bit in this register, 1 = Byte is selected for CRC calculation 0 = Byte is not selected for CRC calculation The register-bit to packet-byte mapping is as follows: October 2012 Bit [15] : Byte 32 … : … Bit [2] : Byte 18 Bit [0] : Byte 17 58 M9999-103112-1.0 Micrel, Inc. Address KSZ9031RNX Name Description Mode (1) Default MMD Address 2h, Register 1Eh – Wake-On-LAN – Customized Packet, Type 0, Mask 2 MMD Address 2h, Register 22h – Wake-On-LAN – Customized Packet, Type 1, Mask 2 MMD Address 2h, Register 26h – Wake-On-LAN – Customized Packet, Type 2, Mask 2 MMD Address 2h, Register 2Ah – Wake-On-LAN – Customized Packet, Type 3, Mask 2 2.1E.15:0 2.22.15:0 2.26.15:0 Custom Packet Type X Mask 2 This register selects the bytes in the third 16 bytes of the packet (bytes 33 thru 48) that will be used for CRC calculation. RW 0000_0000_0000_0000 For each bit in this register, 2.2A.15:0 1 = Byte is selected for CRC calculation 0 = Byte is not selected for CRC calculation The register-bit to packet-byte mapping is as follows: Bit [15] : Byte 48 … : … Bit [2] : Byte 34 Bit [0] : Byte 33 MMD Address 2h, Register 1Fh – Wake-On-LAN – Customized Packet, Type 0, Mask 3 MMD Address 2h, Register 23h – Wake-On-LAN – Customized Packet, Type 1, Mask 3 MMD Address 2h, Register 27h – Wake-On-LAN – Customized Packet, Type 2, Mask 3 MMD Address 2h, Register 2Bh – Wake-On-LAN – Customized Packet, Type 3, Mask 3 2.1F.15:0 2.23.15:0 2.27.15:0 Custom Packet Type X Mask 3 This register selects the bytes in the fourth 16 bytes of the packet (bytes 49 thru 64) that will be used for CRC calculation. RW 0000_0000_0000_0000 For each bit in this register, 2.2B.15:0 1 = Byte is selected for CRC calculation 0 = Byte is not selected for CRC calculation The register-bit to packet-byte mapping is as follows: Bit [15] : Byte 64 … : … Bit [2] : Byte 50 Bit [0] : Byte 49 MMD Address 3h, Register 0h – PCS EEE – Control 3.0.15:12 Reserved Reserved RW 0000 3.0.11 1000Base-T Force LPI 1 = Force 1000Base-T low-power idle transmission RW 0 RW 0 RW 00_0000_0000 0 = Normal operation 3.0.10 3.0.9:0 October 2012 100Base-TX RX_CLK Stoppable During receive lower-power idle mode, 1 = RX_CLK stoppable for 100Base-TX Reserved Reserved 0 = RX_CLK not stoppable for 100Base-TX 59 M9999-103112-1.0 Micrel, Inc. Address KSZ9031RNX Name Description Mode (1) Default MMD Address 3h, Register 1h – PCS EEE – Status 3.1.15:12 Reserved Reserved RO 0000 3.1.11 Transmit LowPower Idle Received 1 = Transmit PCS has received low-power idle RO/LH 0 Receive LowPower Idle Received 1 = Receive PCS has received low-power idle RO/LH 0 Transmit LowPower Idle Indication 1 = Transmit PCS is currently receiving lowpower idle 3.1.10 3.1.9 3.1.8 3.1.7:0 Receive LowPower Idle Indication Reserved 0 = Low-power idle not received 0 = Low-power idle not received RO 0 = Transmit PCS is not currently receiving lowpower idle 1 = Receive PCS is currently receiving lowpower idle RO 0 = Receive PCS is not currently receiving lowpower idle Reserved RO 0000_0000 MMD Address 7h, Register 3Ch – EEE Advertisement 7.3C.15:3 Reserved Reserved RW 0000_0000_0000_0 7.3C.2 1000Base-T EEE 1 = 1000Mbps EEE capable RW 0 RW 0 RW 0 0 = No 1000Mbps EEE capability This bit is set to ‘0’ as the default after power-up or reset. Set this bit to ‘1’ to enable 1000Mbps EEE mode. 7.3C.1 100Base-TX EEE 1 = 100Mbps EEE capable 0 = No 100Mbps EEE capability This bit is set to ‘0’ as the default after power-up or reset. Set this bit to ‘1’ to enable 100Mbps EEE mode. 7.3C.0 Reserved Reserved MMD Address 7h, Register 3Dh – EEE Link Partner Advertisement 7.3D.15:3 Reserved Reserved RO 0000_0000_0000_0 7.3D.2 1000Base-T EEE 1 = 1000Mbps EEE capable RO 0 7.3D.1 100Base-TX EEE 1 = 100Mbps EEE capable RO 0 Reserved Reserved RO 0 7.3D.0 0 = No 1000Mbps EEE capability 0 = No 100Mbps EEE capability MMD Address 1Ch, Register 4h – Analog Control 4 1C.4.15:11 Reserved Reserved RW 0000_0 1C.4.10 10Base-Te Mode 1 = EEE 10Base-Te (1.75V TX amplitude) RW 0 Reserved Reserved RW 00_1111_1111 1C.4.9:0 October 2012 0 = Standard 10Base-T (2.5V TX amplitude) 60 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Address Name Description Mode (1) Default MMD Address 1Ch, Register 23h – EDPD Control 1C.23.15:1 Reserved Reserved RW 0000_0000_0000_000 1C.23.0 EDPD Mode Enable Energy-detect power-down mode RW 0 1 = Enable 0 = Disable Note: 1. RW = Read/Write. RO = Read only. LH = Latch high. October 2012 61 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VIN) (DVDDL, AVDDL, AVDDL_PLL) ............. –0.5V to +1.8V (AVDDH) ................................................. –0.5V to +5.0V (DVDDH) ................................................. –0.5V to +5.0V Input Voltage (all inputs) .............................. –0.5V to +5.0V Output Voltage (all outputs) ......................... –0.5V to +5.0V Lead Temperature (soldering, 10sec.) ....................... 260°C Storage Temperature (Ts) ......................... –55°C to +150°C Supply Voltage (DVDDL, AVDDL, AVDDL_PLL) ..... +1.140V to +1.260V (AVDDH @ 3.3V) ............................ +3.135V to +3.465V (AVDDH @ 2.5V, C-temp only) ....... +2.375V to +2.625V (DVDDH @ 3.3V) ............................ +3.135V to +3.465V (DVDDH @ 2.5V) ............................ +2.375V to +2.625V (DVDDH @ 1.8V) ............................ +1.710V to +1.890V Ambient Temperature (TA Commercial: KSZ9031RNXC).............. 0°C to +70°C (TA Industrial: KSZ9031RNXI) ................ −40°C to +85°C Maximum Junction Temperature (TJ Max) ................. 125°C Thermal Resistance (θJA) .................................... 36.34°C/W Thermal Resistance (θJC) ...................................... 9.47°C/W Electrical Characteristics(3) Symbol Parameter Condition Min. Typ. Max. Units Supply Current – Core / Digital I/Os 1.2V Total of: DVDDL (digital core) + ICORE AVDDL (analog core) + AVDDL_PLL (PLL) IDVDDH_1.8 1.8V for Digital I/Os (RGMII operating @ 1.8V) 1000Base-T link-up (no traffic) 210 mA 1000Base-T full-duplex @ 100% utilization 221 mA 100Base-TX link-up (no traffic) 63.6 mA 100Base-TX full-duplex @ 100% utilization 63.8 mA 10Base-T link-up (no traffic) 7.1 mA 10Base-T full-duplex @ 100% utilization 7.7 mA Software power-down mode (Reg. 0.11 = 1) 1.0 mA Chip power-down mode (strap-in pins MODE[3:0] = 0111) 0.7 mA 1000Base-T link-up (no traffic) 11.2 mA 1000Base-T full-duplex @ 100% utilization 23.6 mA 100Base-TX link-up (no traffic) 8.4 mA 100Base-TX full-duplex @ 100% utilization 9.8 mA 10Base-T link-up (no traffic) 3.6 mA 10Base-T full-duplex @ 100% utilization 5.6 mA Software power-down mode (Reg. 0.11 = 1) 5.5 mA Chip power-down mode (strap-in pins MODE[3:0] = 0111) 0.3 mA Notes: 1. Exceeding the absolute maximum rating can damage the device. Stresses greater than the absolute maximum rating can cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. 2. The device is not guaranteed to function outside its operating rating. 3. TA = 25°C. Specification is for packaged product only. October 2012 62 M9999-103112-1.0 Micrel, Inc. Symbol IDVDDH_2.5 IDVDDH_3.3 KSZ9031RNX Parameter 2.5V for Digital I/Os (RGMII operating @ 2.5V) 3.3V for Digital I/Os (RGMII operating @ 3.3V) Condition Min. Typ. Max. Units 1000Base-T link-up (no traffic) 14.7 mA 1000Base-T full-duplex @ 100% utilization 31.5 mA 100Base-TX link-up (no traffic) 10.5 mA 100Base-TX full-duplex @ 100% utilization 13.0 mA 10Base-T link-up (no traffic) 6.3 mA 10Base-T full-duplex @ 100% utilization 9.0 mA Software power-down mode (Reg. 0.11 = 1) 6.7 mA Chip power-down mode (strap-in pins MODE[3:0] = 0111) 0.7 mA 1000Base-T link-up (no traffic) 19.5 mA 1000Base-T full-duplex @ 100% utilization 41.5 mA 100Base-TX link-up (no traffic) 13.9 mA 100Base-TX full-duplex @ 100% utilization 17.2 mA 10Base-T link-up (no traffic) 11.5 mA 10Base-T full-duplex @ 100% utilization 13.7 mA Software power-down mode (Reg. 0.11 = 1) 9.3 mA Chip power-down mode (strap-in pins MODE[3:0] = 0111) 2.2 mA Supply Current – Transceiver (equivalent to current draw through external transformer center taps for PHY transceivers with current-mode transmit drivers) IAVDDH_2.5 IAVDDH_3.3 1000Base-T link-up (no traffic) 58.8 mA 1000Base-T full-duplex @ 100% utilization 57.9 mA 100Base-TX link-up (no traffic) 24.9 mA 2.5V for Transceiver 100Base-TX full-duplex @ 100% utilization 24.9 mA (Recommended for commercial temperature range operation only) 10Base-T link-up (no traffic) 11.5 mA 10Base-T full-duplex @ 100% utilization 25.3 mA Software power-down mode (Reg. 0h, bit 11 = 1) 3.1 Chip power-down mode (strap-in pins MODE[3:0] = 0111) 0.02 1000Base-T link-up (no traffic) 67.4 mA 1000Base-T full-duplex @ 100% utilization 66.3 mA 100Base-TX link-up (no traffic) 28.7 mA 100Base-TX full-duplex @ 100% utilization 28.6 mA 10Base-T link-up (no traffic) 15.9 mA 10Base-T full-duplex @ 100% utilization 28.6 mA Software power-down mode (Reg. 0h, bit 11 = 1) 4.2 Chip power-down mode (strap-in pins MODE[3:0] = 0111) 0.02 3.3V for Transceiver mA mA mA mA CMOS Inputs VIH Input High Voltage October 2012 DVDDH (digital I/Os) = 3.3V 2.0 V DVDDH (digital I/Os) = 2.5V 1.5 V DVDDH (digital I/Os) = 1.8V 1.1 V 63 M9999-103112-1.0 Micrel, Inc. Symbol KSZ9031RNX Parameter Condition Min. Typ. Max. Units DVDDH (digital I/Os) = 3.3V 1.3 V V VIL Input Low Voltage DVDDH (digital I/Os) = 2.5V 1.0 DVDDH (digital I/Os) = 1.8V 0.7 V |IIN| Input Current VIN = GND ~ VDDIO 10 µA CMOS Outputs VOH VOL |Ioz| Output High Voltage Output Low Voltage DVDDH (digital I/Os) = 3.3V 2.7 V DVDDH (digital I/Os) = 2.5V 2.0 V DVDDH (digital I/Os) = 1.8V 1.5 V DVDDH (digital I/Os) = 3.3V 0.3 V DVDDH (digital I/Os) = 2.5V 0.3 V DVDDH (digital I/Os) = 1.8V 0.3 V 10 µA Output Tri-State Leakage LED Outputs ILED Output Drive Current Each LED pin (LED1, LED2) 8 mA Pull-Up Pins pu Internal Pull-Up Resistance (MDC, MDIO, RESET_N pins) DVDDH (digital I/Os) = 3.3V 13 22 31 kΩ DVDDH (digital I/Os) = 2.5V 16 28 39 kΩ DVDDH (digital I/Os) = 1.8V 26 44 62 kΩ 100Base-TX Transmit (measured differentially after 1:1 transformer) VO Peak Differential Output Voltage 100Ω termination across differential output VIMB Output Voltage Imbalance 100Ω termination across differential output tr , tf Rise/Fall Time Rise/Fall Time Imbalance 0.95 1.05 V 2 % 3 5 ns 0 0.5 ns ±0.25 ns 5 % Duty Cycle Distortion Overshoot Output Jitter Peak-to-peak 0.7 ns 10Base-T Transmit (measured differentially after 1:1 transformer) VP Peak Differential Output Voltage 100Ω termination across differential output Jitter Added Peak-to-peak Harmonic Rejection Transmit all-one signal sequence 2.2 2.8 V 3.5 ns –31 dB 400 mV 1.2 V 10Base-T Receive VSQ Squelch Threshold 5MHz square wave 300 Transmitter – Drive Setting VSET Reference Voltage of ISET R(ISET) = 12.1kΩ LDO Controller – Drive Range VLDO_O Output Drive Range for LDO_O (pin 43) to Gate Input of P-Channel MOSFET October 2012 AVDDH = 3.3V for MOSFET source voltage 0.85 2.8 V AVDDH = 2.5V for MOSFET source voltage (recommended for commercial temperature range operation only) 0.85 2.0 V 64 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Timing Diagrams RGMII Timing The KSZ9031RNX RGMII timing conforms to the timing requirements in the RGMII Version 2.0 Specification. Figure 12. RGMII v2.0 Specification (Figure 3 – Multiplexing and Timing Diagram) Timing Parameter Description Min. Max. Unit TskewT Data to clock output skew (at transmitter) –500 Typ. 500 ps TskewR Data to clock input skew (at receiver) 1.0 2.6 ns Tcyc (1000Base-T) Clock cycle duration for 1000Base-T 7.2 8.8 ns Tcyc (100Base-TX) Clock cycle duration for 100Base-TX 36 40 44 ns Tcyc (10Base-T) Clock cycle duration for 10Base-T 360 400 440 ns 8 Table 19. RGMII v2.0 Specification (Timing Specifics from Table 2) October 2012 65 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Auto-Negotiation Timing Figure 13. Auto-Negotiation Fast Link Pulse (FLP) Timing Timing Parameter Description tBTB FLP burst to FLP burst Min. Typ. Max. Units 8 16 24 ms tFLPW FLP burst width tPW Clock/Data pulse width tCTD Clock pulse to data pulse 55.5 64 69.5 µs tCTC Clock pulse to clock pulse 111 128 139 µs Number of clock/data pulses per FLP burst 17 2 ms 100 ns 33 Table 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters October 2012 66 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX MDC/MDIO Timing Figure 14. MDC/MDIO Timing Timing Parameter Description Min. Typ. tP MDC period t1MD1 MDIO (PHY input) setup to rising edge of MDC 10 ns tMD2 MDIO (PHY input) hold from rising edge of MDC 10 ns tMD3 MDIO (PHY output) delay from rising edge of MDC 0 ns 400 Max. Unit ns Table 21. MDC/MDIO Timing Parameters October 2012 67 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Power-Up/Power-Down/Reset Timing Figure 15. Power-Up/Power-Down/Reset Timing Parameter Description Min Max Units tVR Supply voltages rise time (must be monotonic) 200 µs tSR Stable supply voltages to de-assertion of reset 10 ms tCS Strap-in pin configuration setup time 5 ns tCH Strap-in pin configuration hold time 5 ns tRC De-assertion of reset to strap-in pin output 6 ns tPC Supply voltages cycle off-to-on time 150 ms Table 22. Power-Up/Power-Down/Reset Timing Parameters NOTE 1: The recommended power-up sequence is to have the transceiver (AVDDH) and digital I/O (DVDDH) voltages power up before the 1.2V core (DVDDL, AVDDL, AVDDL_PLL) voltage. If the 1.2V core must power up first, the maximum lead time for the 1.2V core voltage with respect to the transceiver and digital I/O voltages should be 200µs. There is no power sequence requirement between transceiver (AVDDH) and digital I/O (DVDDH) power rails. The power-up waveforms should be monotonic for all supply voltages to the KSZ9031RNX. NOTE 2: After the de-assertion of reset, wait a minimum of 100µs before starting programming on the MIIM (MDC/MDIO) interface. NOTE 3: The recommended power-down sequence is to have the 1.2V core voltage power down before powering down the transceiver and digital I/O voltages. Before the next power-up cycle, all supply voltages to the KSZ9031RNX should reach 0V and there should be a minimum wait time of 150ms from power-off to power-on. October 2012 68 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Reset Circuit The following reset circuit is recommended for powering up the KSZ9031RNX if reset is triggered by the power supply. Figure 16. Recommended Reset Circuit The following reset circuit is recommended for applications where reset is driven by another device (for example, the CPU or an FPGA). At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the KSZ9031RNX device. The RST_OUT_N from the CPU/FPGA provides the warm reset after power-up. Figure 17. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output October 2012 69 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Reference Circuits – LED Strap-In Pins The pull-up and pull-down reference circuits for the LED2/PHYAD1 and LED1/PHYAD0 strapping pins are shown in Figure 18 for 3.3V and 2.5V DVDDH. Figure 18. Reference Circuits for LED Strapping Pins For 1.8V DVDDH, LED indication support is not recommended due to the low voltage. Without the LED indicator, the PHYAD1 and PHYAD0 strapping pins are functional with 10kΩ pull-up to 1.8V DVDDH for a value of 1, and with 1.0kΩ pull-down to ground for a value of 0. October 2012 70 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Reference Clock – Connection and Selection A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ9031RNX. The reference clock is 25MHz for all operating modes of the KSZ9031RNX. Figure 19 and Table 23 shows the reference clock connection to XI and XO of the KSZ9031RNX, and the reference clock selection criteria. Figure 19. 25MHz Crystal/Oscillator Reference Clock Connection Characteristics Value Units Frequency 25 MHz Frequency tolerance (max) ±50 ppm Table 23. Reference Crystal/Clock Selection Criteria October 2012 71 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Magnetic – Connection and Selection A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs exceeding FCC requirements. An optional auto-transformer stage following the chokes provides additional common-mode noise and signal attenuation. The KSZ9031RNX design incorporates voltage-mode transmit drivers and on-chip terminations. With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the four differential pairs. Therefore, the four transformer center tap pins on the KSZ9031RNX side should not be connected to any power supply source on the board; rather, the center tap pins should be separated from one another and connected through separate 0.1µF common-mode capacitors to ground. Separation is required because the common-mode voltage could be different between the four differential pairs, depending on the connected speed mode. Figure 20 shows the typical gigabit magnetic interface circuit for the KSZ9031RNX. Figure 20. Typical Gigabit Magnetic Interface Circuit October 2012 72 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Table 24 lists recommended magnetic characteristics. Parameter Value Test Condition Turns ratio 1 CT : 1 CT Open-circuit inductance (min.) 350µH 100mV, 100kHz, 8mA Insertion loss (max.) 1.0dB 0MHz to 100MHz HIPOT (min.) 1500Vrms Table 24. Magnetics Selection Criteria Table 25 is a list of compatible single-port magnetics with separated transformer center tap pins on the G-PHY chip side that can be used with the KSZ9031RNX. Manufacturer Part Number AutoTransformer Temperature Range Magnetic + RJ-45 Bel Fuse 0826-1G1T-23-F Yes 0°C to 70°C Yes HALO TG1G-E001NZRL No –40°C to 85°C No HALO TG1G-S001NZRL No 0°C to 70°C No HALO TG1G-S002NZRL Yes 0°C to 70°C No Pulse H5007NL Yes 0°C to 70°C No Pulse H5062NL Yes 0°C to 70°C No Pulse HX5008NL Yes –40°C to 85°C No Pulse JK0654219NL Yes 0°C to 70°C Yes Pulse JK0-0136NL No 0°C to 70°C Yes TDK TLA-7T101LF No 0°C to 70°C No Wurth/Midcom 000-7093-37R-LF1 Yes 0°C to 70°C No Table 25. Compatible Single-Port 10/100/1000 Magnetics October 2012 73 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Recommended Land Pattern Figure 21. Recommended Land Pattern, 48-Pin (7mm x 7mm) QFN Red circles indicate thermal vias. They should be 0.350mm in diameter and be connected to the GND plane for maximum thermal performance. Green rectangles (with shaded area) indicate solder stencil openings on the exposed pad area. They should be 0.93x0.93mm in size, 1.13mm pitch. October 2012 74 M9999-103112-1.0 Micrel, Inc. KSZ9031RNX Package Information 48-Pin (7mm x 7mm) QFN MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2012 Micrel, Incorporated. October 2012 75 M9999-103112-1.0