Low-Jitter Configurable HCSL-LVDS Oscillator

DSC2043
Low-Jitter Configurable HCSL-LVDS Oscillator
General Description
The DSC2043 series of high performance
dual output oscillators utilize a proven silicon
MEMS technology to provide excellent jitter
and stability while incorporating additional
device functionality. The two outputs are
controlled by separate supply voltages to
allow for high output isolation. The
frequencies of the outputs can be identical or
independently derived from a common PLL
frequency source.
The DSC2043 has
provision for up to eight user-defined preprogrammed, pin selectable output frequency
combinations.
DSC2043 is packaged in a 14-pin 3.2x2.5
mm
QFN
package
and
available
in
temperature grades from Ext. Commercial to
Industrial.
Features
 Low RMS Phase Jitter: <1 ps (typ)
 High Stability: ±10, ±25, ±50 ppm
 Wide Temperature Range
o Industrial: -40° to 85° C
o Ext. commercial: -20° to 70° C
 High Supply Noise Rejection: -50 dBc
 Two Independent Outputs
o LVDS & HCSL
 Pin-Selectable Configurations
o 3-bit Output Frequency Combinations
 Wide Freq. Range:
o HCSL output: 2.3 – 460 MHz
o LVDS output: 2.3 – 460 MHz
 Miniature Footprint of 3.2x2.5mm
 Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
 High Reliability
o 20x better MTF than quartz oscillators
Block Diagram
 Supply Range of 2.25 to 3.6 V
 Lead Free & RoHS Compliant
Applications
 Storage Area Networks
o SATA, SAS, Fibre Channel
 Passive Optical Networks
o EPON, 10G-EPON, GPON, 10G-PON
 Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FCoE
 HD/SD/SDI Video & Surveillance
 PCI Express
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DSC2043
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MK-Q-B-P-D-12042613-2
DSC2043
Low-Jitter Configurable HCSL-LVDS Oscillator
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
NC
GND
FS0
FS1
FS2
Output1+
Output1Output 2Output 2+
VDD2
VDD
NC
Pin Type
I
NA
NA
Power
I
I
I
O
O
O
O
Power
Power
NA
Description
Enables outputs when high and disables when low
Leave unconnected or grounded
Leave unconnected or grounded
Ground
Least significant bit for frequency selection
Middle bit for frequency selection
Most significant bit for frequency selection
Positive HCSL Output 1
Negative HCSL Output 1
Negative LVDS Output 2
Positive LVDS Output 2
Power Supply 2 for LVDS Output 2
Power Supply
Leave unconnected or grounded
Operational Description
The DSC2043 is a dual oscillator with an LVDS
output and an HCSL output.
The device
consists of a MEMS resonator and a support
PLL IC.
The two outputs are generated
through independent 8-bit programmable
dividers from the output of the internal PLL.
Two constraints are imposed on the output
frequencies: 1) f2=M x f1/N, where M and N
are even integers between 4 and 254, 2)
1.2GHz < N x f2 < 1.7GHz.
The actual frequencies output by the DSC2043
are controlled by an internal pre-programmed
memory (OTP).
This memory stores all
coefficients required by the PLL for up to eight
different frequency combinations.
Three
control pins (FS0 – FS2) select the output
frequency combination.
Discera supports
customer defined versions of the DSC2043.
Standard frequency options are described in in
the following sections.
When Enable (pin 1) is floated or connected to
VDD, the DSC2043 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
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DSC2043
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MK-Q-B-P-D-12042613-2
DSC2043
Low-Jitter Configurable HCSL-LVDS Oscillator
Output Clock Frequencies
Table 1 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code. Customer defined combinations are available.
Table 1. Pre-programmed pin-selectable output frequency combinations
Ordering
Info
N0001
NXXXXX
Freq
(MHz)
Freq Select Bits [FS2, FS1, FS0] – Default is [111]
000
001
010
011
100
101
110
111
fOUT1
fOUT2
fOUT1
Contact factory for additional configurations.
fOUT2
Frequency select bit are weakly tied high so if left unconnected the default setting will be [111] and
the device will output the associated frequency highlighted in Bold.
Absolute Maximum Ratings
Item
Min
Max
Unit
Supply Voltage
-0.3
+4.0
V
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
-0.3
-55
-
VDD+0.3
+150
+150
+260
V
°C
°C
°C
V
4000
400
1500
Ordering Code
Condition
Temp Range
E: -20 to 70
I: -40 to 85
DSC2043
F I 2
-
xxxxx
Packing
T: Tape & Reel
: Tube
T
40sec max.
Package
F: 3.2x2.5mm
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Freq (MHz)
See Freq. table
Note: 1000+ years of data retention on internal memory
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DSC2043
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MK-Q-B-P-D-12042613-2
DSC2043
Low-Jitter Configurable HCSL-LVDS Oscillator
Specifications
(Unless specified otherwise: T=25° C)
Parameter
Supply Voltage
Condition
1
VDD
Min.
Typ.
2.25
Supply Current
IDD
EN pin low – outputs are disabled
21
Supply Current2
IDD
EN pin high – outputs are enabled
RL=50Ω, FO1= FO2=156.25 MHz
76
Frequency Stability
Δf
Aging
Startup Time3
Input Logic Levels
Input logic high
Input logic low
Δf
tSU
VIH
VIL
Output Disable Time4
Output Enable Time
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
Max.
3.6
V
23
mA
mA
±10
±25
±50
±5
5
ppm
ppm
ms
0.25xVDD
V
tDA
5
ns
tEN
20
ns
2
Pull-Up Resistor
0.75xVDD
-
Unit
Pull-up exists on all digital IO
40
kΩ
HCSL Outputs
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
Pk to Pk Output Swing
Output Transition time
Rise Time
Fall Time
Frequency
RL=50Ω
0.725
-
Single-Ended
4
tR
tF
f0
0.1
750
V
mV
20% to 80%
RL=50Ω, CL= 2pF
200
400
ps
Single Frequency
2.3
460
MHz
48
52
%
Output Duty Cycle
SYM
Differential
Period Jitter5
JPER
FO1=FO2=156.25 MHz
2.8
Integrated Phase Noise
JPH
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.25
0.37
1.7
psRMS
2
psRMS
LVDS Outputs
Output Offset Voltage
R=100Ω Differential
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition time4
Rise Time
Fall Time
tR
tF
Frequency
f0
Single-Ended
350
20% to 80%
RL=100Ω, CL= 2pF
200
Single Frequency
2.3
48
Output Duty Cycle
SYM
Differential
Period Jitter5
JPER
Integrated Phase Noise
JCC
FO1=125 MHz
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
Notes:
1.
2.
3.
4.
5.
1.125
1.4
V
50
mV
mV
350
ps
460
MHz
52
2.5
0.25
0.38
1.7
%
psRMS
2
psRMS
Pin 4 VDD should be filtered with 0.01uf capacitor.
Output is enabled if Enable pad is floated or not connected.
tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
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DSC2043
Low-Jitter Configurable HCSL-LVDS Oscillator
Nominal Performance Parameters (Unless specified otherwise: T=25° C, VDD=3.3 V)
2.5
2.5
156MHz-LVDS
106MHz-HCSL
2.0
Phase Jitter (ps RMS)
Phase Jitter (ps RMS)
50MHz-HCSL
156MHz-HCSL
1.5
212MHz-HCSL
1.0
0.5
212MHz-LVDS
2.0
320MHz-LVDS
1.5
410MHz-LVDS
1.0
0.5
0.0
0.0
0
200
400
600
800
1000
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
Low-end of integration BW: x kHz to 20 MHz
HCSL Phase jitter (integrated phase noise)
LVDS Phase jitter (integrated phase noise)
Output Waveform: HCSL
tR
Output
tF
80%
675mv
mV
830
50%
Output
20%
tEN
1/f o
tDA
VIH
Enable
VIL
Output Waveform: LVDS
tR
Output
tF
80%
350mv
mV
830
50%
Output
20%
tEN
1/f o
tDA
VIH
Enable
VIL
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DSC2043
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MK-Q-B-P-D-12042613-2
DSC2043
Low-Jitter Configurable HCSL-LVDS Oscillator
Solder Reflow Profile
20-40
Sec
Se
3C
/
217°C
200°C
60-150
Sec
.
ax
cM
Se
3C
/
25°C
a x.
Reflow
60-180
Sec
cM
150°C
Se
6C/
Temperature (°C)
cM
ax
.
260°C
Cool
Pre heat
Time
8 min max
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max.
Preheat Time 150°C to 200°C
60-180 Sec
Time maintained above 217°C
60-150 Sec
255-260°C
Peak Temperature
Time within 5°C of actual Peak
20-40 Sec
6°C/Sec Max.
Ramp-Down Rate
Time 25°C to Peak Temperature
8 min Max.
Package Dimensions
3.2 x 2.5 mm 14 Lead Plastic Package
Disclaimer:
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information
is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and
descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted
by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims
any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose,
merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the
body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or
sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any
damages resulting from such use or sale.
MICREL, Inc.
Phone: +1 (408) 944-0800
●
●
2180 Fortune Drive,
Fax: +1 (408) 474-1000
San Jose, California
95131
● Email: [email protected]
●
●
USA
www.micrel.com
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