KSZ8851SNL(I)

KSZ8851SNL/SNLI
Single-Port Ethernet Controller
with SPI Interface
Rev. 2.0
General Description
The KSZ8851SNL is a single-chip Fast Ethernet controller
consisting of a 10/100 physical layer transceiver (PHY), a
MAC, and a Serial Peripheral Interface (SPI). The
KSZ8851SNL is designed to enable an Ethernet network
connectivity with any host micro-controller equipped with
SPI interface. The KSZ8851SNL offers the most costeffective solution for adding high-throughput Ethernet link
to traditional embedded systems with SPI interface.
The KSZ8851SNL is a single chip, mixed analog/digital
device offering Wake-on-LAN technology for effectively
addressing Fast Ethernet applications. It consists of a Fast
Ethernet MAC controller, SPI interface and incorporates a
unique dynamic memory pointer with 4-byte buffer
boundary and a fully utilizable 18KB for both TX (allocated
6KB) and RX (allocated 12KB) directions in host buffer
interface.
The KSZ8851SNL is designed to be fully compliant with
the appropriate IEEE 802.3 standards. An industrial
temperature-grade version of the KSZ8851SNL, the
KSZ8851SNLI is also available (see “Ordering Information”
section).
®
LinkMD
Physical signal transmission and reception are enhanced
through the use of analog circuitry, making the design
more efficient and allowing for lower-power consumption.
The KSZ8851SNL is designed using a low-power CMOS
process that features a single 3.3V power supply with
options for 1.8V, 2.5V or 3.3V VDD I/O. The device
includes an extensive feature set that offers management
information base (MIB) counters and a fast SPI interface
with clock speed up to 40MHz.
The KSZ8851SNL includes unique cable diagnostics
®
feature called LinkMD . This feature determines the length
of the cabling plant and also ascertains if there is an open
or short condition in the cable. Accompanying software
enables the cable length and cable conditions to be
conveniently displayed. In addition, the KSZ8851SNL
supports Hewlett Packard (HP) Auto-MDIX thereby
eliminating the need to differentiate between straight or
crossover cables in applications.
Functional Diagram
Figure 1. KSZ8851SNL/SNLI Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Magic Packet is a trademark of Advanced Micro Devices, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc.
Product names used in this datasheet are for identification purposes
only and may be trademarks of their respective companies.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2009
M9999-083109-2.0
Micrel, Inc.
KSZ8851SNL/SNLI
Features
Additional Features
• Integrated MAC and PHY Ethernet Controller fully
compliant with IEEE 802.3/802.3u standards
• SPI Interface with clock speeds up to 40MHz for high
throughput applications
• Supports 10BASE-T/100BASE-TX
• Supports IEEE 802.3x full-duplex flow control and halfduplex backpressure collision flow control
• Supports RXQ and TXQ FIFO DMA for fast data read
and write transfers
• Supports IP Header (IPv4)/TCP/UDP/ICMP checksum
generation and checking
• Supports IPv6 TCP/UDP/ICMP checksum generation
and checking
• Automatic 32-bit CRC generation and checking
• Supports simple command and data phases in SPI
cycle for RXQ/TXQ FIFO and registers read/write
• Supports multiple data frames for TXQ FIFO and RXQ
FIFO without additional command phase
• Supports flexible Byte (8-bit), Word (16-bit) and Double
word (32-bit) read/write access to internal registers
• Larger internal memory with 12K Bytes for RX FIFO and
6K Bytes for TX FIFO. Programmable low, high and
overrun watermark for flow control in RX FIFO
• Efficient architecture design with configurable host
interrupt schemes to minimize host CPU overhead and
utilization
• Powerful and flexible address filtering scheme
• Optional to use external serial EEPROM configuration
for MAC address
• Single 25MHz reference clock for both PHY and MAC
• HBM ESD Rating 6kV
In addition to offering all of the features of a Layer 2
controller, the KSZ8851SNL offers:
• Supports to add two-byte before frame header in order
for IP frame content with double word boundary
®
• Micrel LinkMD cable diagnostic capabilities to
determine cable length, diagnose faulty cables, and
determine distance to fault
• Wake-on-LAN functionality
– Incorporates Magic Packet™, wake-up frame, network
link state, and detection of energy signal technology
• HP Auto MDI-X™ crossover with disable/enable option
• Ability to transmit and receive frames up to 2000 bytes
Power Modes, Power Supplies, and Packaging
• Single 3.3V power supply with options for 1.8V, 2.5V
and 3.3V VDD I/O
• Built-in integrated 3.3V or 2.5V to 1.8V low noise
regulator (LDO) for core and analog blocks
• Enhanced power management feature with energy
detect mode and soft power-down mode to ensure lowpower dissipation during device idle periods
• Comprehensive LED indicator support for link, activity
and 10/100 speed (2 LEDs)
– User programmable
• Low-power CMOS design
o
o
• Commercial Temperature Range: 0 C to +70 C
o
o
• Industrial Temperature Range: –40 C to +85 C
®
• Available in 32-pin (5mm x 5mm) MLF package
August 2009
Network Features
•
•
•
•
10BASE-T and 100BASE-TX physical layer support
Auto-negotiation: 10/100 Mbps full and half duplex
Adaptive equalizer
Baseline wander correction
Applications
• Video/Audio Distribution Systems
• Voice over IP (VoIP) and Analog Telephone Adapters
(ATA)
• Building Automation
• Home Base Control with Ethernet Connection
• Industrial Control Sensor Devices (Temperature,
Pressure, Levels, and Valves)
• Security, Motion Control and Surveillance Cameras
Markets
•
•
•
•
2
Fast Ethernet
Embedded Ethernet
Industrial Ethernet
Embedded Systems
M9999-083109-2.0
Micrel, Inc.
KSZ8851SNL/SNLI
Ordering Information
Part Number
Temperature Range
o
o
0 C to 70 C
KSZ8851SNL TR
o
KSZ8851SNLI TR
o
–40 C to +85 C
KSZ8851SNL-Eval
Package
Lead Finish
®
Pb-Free
®
Pb-Free
32-Pin MLF (QFN per JDEC)
32-Pin MLF (QFN per JDEC)
Evaluation Board for the KSZ8851SNL
Revision History
Revision
Date
Summary of Changes
1.0
06/30/2008
First released Information.
1.1
2/13/2009
Improved EDS Rating up to 6KV, revised Ordering Information and updated Table content
and description.
2.0
8/31/2009
To tri-state the SO output when CSN is de-asserted. To use falling edge of SCLK to send
data out (SO) and to support 40MHz SPI clock rate. Change revision ID from “0” to “1” in
CIDER (0xc0) register. To enable software read or write external EEPROM. Update pins
5, 9, 23 description for 1.8V VDD_IO supply.
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Contents
Pin Configuration ................................................................................................................................................................ 10
Pin Description .................................................................................................................................................................... 11
Strapping Options ............................................................................................................................................................... 12
Functional Description ....................................................................................................................................................... 13
Functional Overview ........................................................................................................................................................... 13
Power Management........................................................................................................................................................ 13
Normal Operation Mode........................................................................................................................................... 13
Energy Detect Mode ................................................................................................................................................ 13
Soft Power Down Mode ........................................................................................................................................... 14
Power Saving Mode ................................................................................................................................................. 14
Wake-on-LAN ................................................................................................................................................................. 14
Detection of Energy.................................................................................................................................................. 14
Detection of Linkup .................................................................................................................................................. 14
Wake-up Packet....................................................................................................................................................... 15
Magic Packet............................................................................................................................................................ 15
Physical Layer Transceiver (PHY).................................................................................................................................. 16
100BASE-TX Transmit .............................................................................................................................................. 16
100BASE-TX Receive ............................................................................................................................................... 16
PLL Clock Synthesizer (Recovery)............................................................................................................................. 16
Scrambler/De-scrambler (100BASE-TX only) ............................................................................................................ 16
10BASE-T Transmit .................................................................................................................................................. 16
10BASE-T Receive ................................................................................................................................................... 16
MDI/MDI-X Auto Crossover...................................................................................................................................... 17
Straight Cable .................................................................................................................................................... 17
Crossover Cable ................................................................................................................................................ 17
Auto Negotiation....................................................................................................................................................... 18
®
LinkMD Cable Diagnostics ..................................................................................................................................... 19
Access ............................................................................................................................................................... 19
Usage ................................................................................................................................................................ 20
Media Access Control (MAC) Operation ........................................................................................................................ 20
Inter Packet Gap (IPG)............................................................................................................................................. 20
Back-Off Algorithm ................................................................................................................................................... 20
Late Collision............................................................................................................................................................ 20
Flow Control ............................................................................................................................................................. 20
Half-Duplex Backpressure ....................................................................................................................................... 21
Address Filtering Function ....................................................................................................................................... 21
Clock Generator ....................................................................................................................................................... 22
Serial Peripheral Interface (SPI) ..................................................................................................................................... 22
SPI Internal I/O Registers Access Operation Timing............................................................................................... 23
SPI TXQ/RXQ FIFOs Access Operation Timing...................................................................................................... 23
Queue Management Unit (QMU).................................................................................................................................... 24
Transmit Queue (TXQ) Frame Format..................................................................................................................... 24
Frame Transmitting Path Operation in TXQ ............................................................................................................ 25
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Driver Routine for Transmit Packet from Host Processor to KSZ8851SNL............................................................. 26
Receive Queue (RXQ) Frame Format ..................................................................................................................... 29
Frame Receiving Path Operation in RXQ ................................................................................................................ 29
Driver Routine for Receive Packet from KSZ8851SNL to Host Processor.............................................................. 30
EEPROM Interface ......................................................................................................................................................... 31
Loopback Support........................................................................................................................................................... 32
Near-end (Remote) Loopback.................................................................................................................................. 32
Far-end (Local) Loopback ........................................................................................................................................ 32
SPI Interface to I/O Registers............................................................................................................................................. 33
I/O Registers................................................................................................................................................................... 33
Internal I/O Registers Space Mapping............................................................................................................................ 34
Register Map: MAC, PHY and QMU................................................................................................................................... 40
Bit Type Definition........................................................................................................................................................... 40
0x00 – 0x07: Reserved................................................................................................................................................... 40
Chip Configuration Register (0x08 – 0x09): CCR .......................................................................................................... 40
0x0A – 0x0F: Reserved .................................................................................................................................................. 40
Host MAC Address Registers: MARL, MARM and MARH ............................................................................................. 40
Host MAC Address Register Low (0x10 – 0x11): MARL................................................................................................ 41
Host MAC Address Register Middle (0x12 – 0x13): MARM........................................................................................... 41
Host MAC Address Register High (0x14 – 0x15): MARH .............................................................................................. 41
0x16 – 0x1F: Reserved .................................................................................................................................................. 41
On-Chip Bus Control Register (0x20 – 0x21): OBCR .................................................................................................... 41
EEPROM Control Register (0x22 – 0x23): EEPCR ....................................................................................................... 42
Memory BIST Info Register (0x24 – 0x25): MBIR .......................................................................................................... 42
Global Reset Register (0x26 – 0x27): GRR ................................................................................................................... 43
0x28 – 0x29: Reserved................................................................................................................................................... 43
Wakeup Frame Control Register (0x2A – 0x2B): WFCR ............................................................................................... 43
0x2C – 0x2F: Reserved .................................................................................................................................................. 43
Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 ........................................................................................ 43
Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 ........................................................................................ 44
Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 ................................................................................ 44
Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 ................................................................................ 44
Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 ................................................................................ 44
Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3................................................................................ 44
0x3C – 0x3F: Reserved .................................................................................................................................................. 45
Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0 ........................................................................................ 45
Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1 ........................................................................................ 45
Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 ................................................................................ 45
Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 ................................................................................ 45
Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 ................................................................................ 45
Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3................................................................................ 45
0x4C – 0x4F: Reserved .................................................................................................................................................. 46
Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 ........................................................................................ 46
Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 ........................................................................................ 46
Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 ................................................................................ 46
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KSZ8851SNL/SNLI
Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1 ................................................................................ 46
Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2 ................................................................................ 46
Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3................................................................................ 47
0x5C – 0x5F: Reserved .................................................................................................................................................. 47
Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0 ........................................................................................ 47
Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1 ........................................................................................ 47
Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 ................................................................................ 47
Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 ................................................................................ 47
Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 ................................................................................ 47
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3................................................................................ 48
0x6C – 0x6F: Reserved .................................................................................................................................................. 48
Transmit Control Register (0x70 – 0x71): TXCR............................................................................................................ 48
Transmit Status Register (0x72 – 0x73): TXSR ............................................................................................................. 48
Receive Control Register 1 (0x74 – 0x75): RXCR1 ....................................................................................................... 49
Receive Control Register 2 (0x76 – 0x77): RXCR2 ....................................................................................................... 50
TXQ Memory Information Register (0x78 – 0x79): TXMIR ............................................................................................ 51
0x7A – 0x7B: Reserved .................................................................................................................................................. 51
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR ............................................................................... 51
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR...................................................................... 52
TXQ Command Register (0x80 – 0x81): TXQCR .......................................................................................................... 52
RXQ Command Register (0x82 – 0x83): RXQCR.......................................................................................................... 53
TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR............................................................................................. 54
RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR............................................................................................ 54
0x88 – 0x8B: Reserved .................................................................................................................................................. 55
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR ................................................................................. 55
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR ............................................................................ 55
Interrupt Enable Register (0x90 – 0x91): IER ................................................................................................................ 55
Interrupt Status Register (0x92 – 0x93): ISR ................................................................................................................. 56
0x94 – 0x9B: Reserved .................................................................................................................................................. 57
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR................................................................................. 57
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR ................................................................................... 57
MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0.................................................................................... 58
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1.................................................................................... 58
MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2.................................................................................... 58
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3.................................................................................... 58
0xA8 – 0xAF: Reserved.................................................................................................................................................. 58
Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR.................................................................................... 58
Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR................................................................................... 59
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR............................................................................. 59
0xB6 – 0xBF: Reserved.................................................................................................................................................. 59
Chip ID and Enable Register (0xC0 – 0xC1): CIDER .................................................................................................... 59
0xC2 – 0xC5: Reserved ................................................................................................................................................. 59
Chip Global Control Register (0xC6 – 0xC7): CGCR..................................................................................................... 59
Indirect Access Control Register (0xC8 – 0xC9): IACR ................................................................................................. 59
0xCA – 0xCF: Reserved ................................................................................................................................................. 60
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KSZ8851SNL/SNLI
Indirect Access Data Low Register (0xD0 – 0xD1): IADLR............................................................................................ 60
Indirect Access Data High Register (0xD2 – 0xD3): IADHR .......................................................................................... 60
Power Management Event Control Register (0xD4 – 0xD5): PMECR........................................................................... 60
Go-Sleep & Wake-Up Time Register (0xD6 – 0xD7): GSWUTR ................................................................................... 61
PHY Reset Register (0xD8 – 0xD9): PHYRR ................................................................................................................ 62
0xDA – 0xDF: Reserved ................................................................................................................................................. 62
0xE0 – 0xE3: Reserved .................................................................................................................................................. 62
PHY 1 MII-Register Basic Control Register (0xE4 – 0xE5): P1MBCR........................................................................... 62
PHY 1 MII-Register Basic Status Register (0xE6 – 0xE7): P1MBSR ............................................................................ 63
PHY 1 PHY ID Low Register (0xE8 – 0xE9): PHY1ILR ................................................................................................. 64
PHY 1 PHY ID High Register (0xEA – 0xEB): PHY1IHR ............................................................................................... 64
PHY 1 Auto-Negotiation Advertisement Register (0xEC – 0xED): P1ANAR ................................................................. 64
PHY 1 Auto-Negotiation Link Partner Ability Register (0xEE – 0xEF): P1ANLPR......................................................... 64
0xF0 – 0xF3: Reserved .................................................................................................................................................. 65
Port 1 PHY Special Control/Status, LinkMD (0xF4 – 0xF5): P1SCLMD ........................................................................ 65
Port 1 Control Register (0xF6 – 0xF7): P1CR................................................................................................................ 66
Port 1 Status Register (0xF8 – 0xF9): P1SR ................................................................................................................. 67
0xFA – 0xFF: Reserved.................................................................................................................................................. 68
MIB (Management Information Base) Counters............................................................................................................... 69
Additional MIB Information ............................................................................................................................................. 70
Absolute Maximum Ratings ............................................................................................................................................... 71
Operating Ratings ............................................................................................................................................................... 71
Electrical Characteristics ................................................................................................................................................... 71
Timing Specifications ......................................................................................................................................................... 73
SPI Input and Output Timing .......................................................................................................................................... 73
Auto Negotiation Timing ................................................................................................................................................. 74
Reset Timing................................................................................................................................................................... 75
EEPROM Timing ............................................................................................................................................................ 76
Selection of Isolation Transformers.................................................................................................................................. 77
Selection of Reference Crystal .......................................................................................................................................... 77
Package Information ........................................................................................................................................................... 78
Acronyms and Glossary..................................................................................................................................................... 79
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KSZ8851SNL/SNLI
List of Figures
Figure 1. KSZ8851SNL/SNLI Functional Diagram.................................................................................................................. 1
®
Figure 2. 32-Pin (5mm x 5mm) MLF .................................................................................................................................. 10
Figure 3. Typical Straight Cable Connection ........................................................................................................................ 17
Figure 4. Typical Crossover Cable Connection .................................................................................................................... 18
Figure 5. Auto Negotiation and Parallel Operation ............................................................................................................... 19
Figure 6. SPI Interface to KSZ8851SNL ............................................................................................................................... 22
Figure 7. Internal I/O Register Read Timing ......................................................................................................................... 23
Figure 8. Internal I/O Register Write Timing ......................................................................................................................... 23
Figure 9. RXQ FIFO Read Timing......................................................................................................................................... 24
Figure 10. TXQ FIFO Write Timing ....................................................................................................................................... 24
Figure 11. Host TX Single Frame in Manual Enqueue Flow Diagram .................................................................................. 27
Figure 12. Host TX Multiple Frames in Auto- Enqueue Flow Diagram ................................................................................. 28
Figure 13. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram .................................................................. 30
Figure 14. PHY Port 1 Near-end (Remote) and Host Far-end (Local) Loopback Paths....................................................... 32
Figure 15. SPI Interface Data Input Timing........................................................................................................................... 73
Figure 16. SPI Interface Data Output Timing........................................................................................................................ 73
Figure 17. Auto Negotiation Timing ...................................................................................................................................... 74
Figure 18. Reset Timing........................................................................................................................................................ 75
Figure 19. EEPROM Read Cycle Timing Diagram ............................................................................................................... 76
®
Figure 20. 32-Pin (5mm x 5mm) MLF (QFN per JDEC) Package ...................................................................................... 78
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KSZ8851SNL/SNLI
List of Tables
Table 1. Internal Function Blocks Status .............................................................................................................................. 13
Table 2. MDI/MDI-X Pin Definitions ...................................................................................................................................... 17
Table 3. Address Filtering Scheme....................................................................................................................................... 21
Table 4. SPI Operation for Registers Access ....................................................................................................................... 22
Table 5. SPI Operation for TXQ/RXQ FIFO Access ............................................................................................................. 23
Table 6. Frame Format for Transmit Queue ......................................................................................................................... 25
Table 7. Transmit Control Word Bit Fields ............................................................................................................................ 25
Table 8. Transmit Byte Count Format................................................................................................................................... 25
Table 9. Registers Setting for Transmit Function Block........................................................................................................ 26
Table 10. Frame Format for Receive Queue ........................................................................................................................ 29
Table 11. Registers Setting for Receive Function Block....................................................................................................... 29
Table 12. KSZ8851SNL EEPROM Format ........................................................................................................................... 31
Table 13. Format of MIB Counters........................................................................................................................................ 69
Table 14. Port 1 MIB Counters Indirect Memory Offsets ...................................................................................................... 70
Table 15. Electrical Characteristics....................................................................................................................................... 72
Table 16. SPI Data Input and Output Timing Parameters .................................................................................................... 73
Table 17. Auto Negotiation Timing Parameters .................................................................................................................... 74
Table 18. Reset Timing Parameters ..................................................................................................................................... 75
Table 19. EEPROM Timing Parameters ............................................................................................................................... 76
Table 20. Transformer Selection Criteria .............................................................................................................................. 77
Table 21. Qualified Single Port Magnetics............................................................................................................................ 77
Table 22. Typical Reference Crystal Characteristics ............................................................................................................ 77
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KSZ8851SNL/SNLI
Pin Configuration
®
Figure 2. 32-Pin (5mm x 5mm) MLF
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KSZ8851SNL/SNLI
Pin Description
Pin Number
Pin Name
Type
Pin Function
1
LED0
Opu
Programmable LED output to indicate PHY activity/status.
LED is ON when output is LOW; LED is OFF when output is HIGH.
1
LED indicators defined as follows:
Chip Global Control Register: CGCR bit [9]
0 (Default)
1
LED1 (pin 32)
100BT
ACT
LED0 (pin 1)
LINK/ACT
LINK
Link (up) = LED On; Activity = LED Blink; Link/Act = LED On/Blink;
Speed = LED On (100BASE-T); LED Off (10BASE-T)
2
PME
Opu
Power Management Event (default active low)
It is asserted (low or high depends on polarity set in PMECR register) when one of the
wake-on-LAN events is detected by KSZ8851SNL. The KSZ8851SNL is requesting the
system to wake up from low power mode.
3
INTRN
Opu
Interrupt Not
An active low signal to host CPU to indicate an interrupt status bit is set. This pin needs
an external 4.7K pull-up resistor.
4
DGND
Gnd
5
VDD_CO1.8
P
Digital IO ground.
1.8V regulator output . This 1.8V output pin provides power to pins 9 (VDD_A1.8) and 23
(VDD_D1.8) for core VDD supply.
If VDD_IO is set for 1.8V then this pin should be left floating, pins 9 (VDDA_1.8) and 23
(VDD_D1.8) will be sourced by the external 1.8V supply that is tied to pins 25 and 30
(VDD_IO) with appropriate filtering.
6
EED_IO
Ipd/O
In/Out Data from/to external EEPROM
Config Mode: The pull-up/pull-down value is latched as with/without EEPROM during
power-up / reset. See “Strapping Options” section for details.
7
EESK
Opd
EEPROM Serial Clock
A 4μs (OBCR[1:0]=11 on-chip bus speed @ 25MHz) or 800ns (OBCR[1:0]=00 on-chip
bus speed @ 125 MHz) serial output clock to load configuration data from the serial
EEPROM.
8
AGND
Gnd
Analog ground.
9
VDD_A1.8
P
10
EECS
Opd
11
RXP
I/O
Physical receive (MDI) or transmit (MDIX) signal (+ differential).
12
RXM
I/O
Physical receive (MDI) or transmit (MDIX) signal (– differential).
13
AGND
Gnd
Analog ground.
14
TXP
I/O
Physical transmit (MDI) or receive (MDIX) signal (+ differential).
15
TXM
I/O
Physical transmit (MDI) or receive (MDIX) signal (– differential).
16
VDD_A3.3
P
17
ISET
O
1.8V analog power supply from VDD_CO1.8 (pin 5) with appropriate filtering. If VDD_IO is
1.8V, this pin must be supplied power from the same source as pins 25 and 30 (VDD_IO)
with appropriate filtering.
EEPROM Chip Select
This signal is used to select an external EEPROM device.
3.3V analog VDD input power supply with well decoupling capacitors.
Set physical transmits output current.
Pull-down this pin with a 3.01K 1% resistor to ground.
18
AGND
Gnd
Analog ground.
19
RSTN
Ipu
Reset Not.
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Pin Number
KSZ8851SNL/SNLI
Pin Name
Type
Pin Function
Hardware reset pin (active Low). This reset input must be held low for a minimum of 10ms
after stable supply voltage 3.3V.
20
X1
I
25MHz crystal or oscillator clock connection.
21
X2
O
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant
oscillator and X2 is a no connect.
Note: Clock requirement is +/- 50ppm for either crystal or oscillator.
22
DGND
Gnd
23
VDD_D1.8
P
24
DGND
Gnd
25
VDD_IO
P
26
CSN
Ipu
Digital IO ground
1.8V digital power supply from VDD_CO1.8 (pin 5) with appropriate filtering. If VDD_IO is
1.8V, this pin must be supplied power from the same source as pins 25 and 30 (VDD_IO)
with appropriate filtering.
Digital IO ground
3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
SPI slave mode: Chip Select Not
Active low input pin for SPI interface.
27
SO
O
SPI slave mode: Serial data out for SPI interface. This SO is tri-stated output when CSN
is negated and this pin must have external 4.7K pull-up to keep the SO line high while the
driver is tri-stated.
28
SCLK
I
SPI slave mode: Serial clock input for SPI interface. This clock speed can run up to
40MHz.
29
DGND
Gnd
30
VDD_IO
P
Digital IO ground
3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
31
SI
Ipd
SPI slave mode: Serial data in for SPI interface.
32
LED1
Opu
Programmable LED1 output to indicate PHY activity/status (see LED0 description at pin1)
Legend:
P = Power supply Gnd = Ground
I/O = Bi-directional I = Input O = Output.
Ipd = Input with internal pull-down (58K +/-30%).
Ipu = Input with internal pull-up (58K +/-30%).
Opd = Output with internal pull-down (58K +/-30%).
Opu = Output with internal pull-up (58K +/-30%).
Ipu/O = Input with internal pull-up (58K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (58K +/-30%) during power-up/reset; output pin otherwise.
Strapping Options
Pin Number
Pin Name
Type
Pin Function
6
EED_IO
Ipd/O
EEPROM select:
Pull-up = EEPROM present
Floating (NC) or Pull-down = EEPROM not present (default)
During power-up / reset, this pin value is latched into register CCR, bit 9
Note: Ipd/O = Input with internal pull-down (58K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset.
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KSZ8851SNL/SNLI
Functional Description
The KSZ8851SNL is a single-chip Fast Ethernet MAC/PHY controller consisting of a 10/100 physical layer transceiver
(PHY), a MAC, and an industry standard Serial Peripheral Interface (SPI). The host CPU is via SPI interface to read/write
KSZ8851SNL internal registers either byte (8-bit), word (16-bit) or double word (32-bit) and to access KSZ8851SNL
RXQ/TXQ FIFOs for packet receive/transmit.
The KSZ8851SNL is fully compliant to IEEE802.3u standards.
Functional Overview
Power Management
The KSZ8851SNL supports enhanced power management feature in low power state with energy detection to ensure lowpower dissipation during device idle periods. There are four operation modes under the power management function
which is controlled by two bits in PMECR (0xD4) register as shown below:
PMECR[1:0] = 00 Normal Operation Mode
PMECR[1:0] = 01 Energy Detect Mode
PMECR[1:0] = 10 Soft Power Down Mode
PMECR[1:0] = 11 Power Saving Mode
Table 1 indicates all internal function blocks status under four different power management operation modes.
KSZ8851SNL
Function Blocks
Power Management Operation Modes
Normal mode
Power saving mode
Energy detect mode
Soft power down mode
Enabled
Enabled
Disabled
Disabled
Tx/Rx PHY
Enabled
Rx unused block disabled
Energy detect at Rx
Disabled
MAC
Enabled
Enabled
Disabled
Disabled
SPI Interface
Enabled
Enabled
Disabled
Disabled
Internal PLL Clock
Table 1. Internal Function Blocks Status
Normal Operation Mode
This is the default setting bit[1:0]=00 in PMECR register after the chip power-up or hardware reset (pin 67). When
KSZ8851SNL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host interface is
ready for CPU read or write.
During the normal operation mode, the host CPU can set the bit[1:0] in PMECR register to transit the current normal
operation mode to any one of the other three power management operation modes.
Energy Detect Mode
The energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8851SNL is not connected to an active link partner. For example, if cable is not present or it is connected to a
powered down partner, the KSZ8851SNL can automatically enter to the low power state in energy detect mode. Once
activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851SNL can automatically
power up to normal power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the
KSZ8851SNL reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The
energy detect mode is entered by setting bit[1:0]=01 in PMECR register. When the KSZ8851SNL is in this mode, it will
monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit[7:0] GoSleep time in GSWUTR register, KSZ8851SNL will go into a low power state. When KSZ8851SNL is in low power state, it
will keep monitoring the cable energy. Once the energy is detected from the cable and is continuously presented for a
time longer than pre-configured value at bit[15:8] Wake-Up time in GSWUTR register, the KSZ8851SNL will enter either
the normal power state if the auto-wakeup enable bit[7] is set in PMECR register or the normal operation mode if both
auto-wakeup enable bit[7] and wakeup to normal operation mode bit[6] are set in PMECR register.
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The KSZ8851SNL will also assert PME output pin if the corresponding enable bit[8] is set in PMECR (0xD4) register or
generate interrupt to signal an energy detect event occurred if the corresponding enable bit[2] is set in IER (0x90) register.
Once the power management unit detects the PME output asserted or interrupt active, it will power up the host CPU and
issue a wakeup command which is any one of registers read or write access to wake up the KSZ8851SNL from the low
power state to the normal power state in case the auto-wakeup enable bit[7] is disabled. When KSZ8851SNL is at normal
power state, it is able to transmit or receive packet from the cable.
Soft Power Down Mode
The soft power down mode is entered by setting bit[1:0]=10 in PMECR register. When KSZ8851SNL is in this mode, all
PLL clocks are disabled, the PHY and the MAC are off, all internal registers value will not change, and the host interface
is only used to wake-up this device from current soft power down mode to normal operation mode.
In order to go back the normal operation mode from this soft power down mode, the only way to leave this mode is
through a host wake-up command which the CPU issues any one of registers read or write access.
Power Saving Mode
The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting
bit[1:0]=11 in PMECR register and bit [10]=1 in P1SCLMD register. When KSZ8851SNL is in this mode, all PLL clocks are
enabled, MAC is on, all internal registers value will not change, and host interface is ready for CPU read or write. In this
mode, it mainly controls the PHY transceiver on or off based on line status to achieve power saving. The PHY remains
transmitting and only turns off the unused receiver block. Once activity resumes due to plugging a cable or attempting by
the far end to establish link, the KSZ8851SNL can automatically enabled the PHY power up to normal power state from
power saving mode.
During this power saving mode, the host CPU can program the bit[1:0] in PMECR register and set bit[10]=0 in P1SCLMD
register to transit the current power saving mode to any one of the other three power management operation modes.
Wake-on-LAN
Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the
network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote
administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device is
pre-programmed by the policy owner or other software with information on how to identify wake frames from other network
traffic. The KSZ8851SNL controller can be programmed to notify the host of the wake-up frame detection with the
assertion of the interrupt signal (INTRN) or assertion of the power management event signal (PME).
A wake-up event is a request for hardware and/or software external to the network device to put the system into a
powered state (working).
A wake-up signal is caused by:
1. Detection of energy signal over a pre-configured value (bit 2 in ISR register)
2. Detection of a linkup in the network link state (bit 3 in ISR register)
3. Receipt of a Magic Packet (bit 4 in ISR register)
4. Receipt of a network wake-up frame (bit 5 in ISR register)
There are also other types of wake-up events that are not listed here as manufacturers may choose to implement these in
their own way.
Detection of Energy
The energy is detected from the cable and is continuously presented for a time longer than pre-configured value,
especially when this energy change may impact the level at which the system should re-enter to the normal power state.
Detection of Linkup
Link status wake events are useful to indicate a linkup in the network’s connectivity status.
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Wake-up Packet
Wake-up packets are certain types of packets with specific CRC values that a system recognizes as a ‘wake up’ frame.
The KSZ8851SNL supports up to four users defined wake-up frames as below:
1. Wake-up frame 0 is defined in wakeup frame registers (0x30 – 0x3B) and is enabled by bit 0 in wakeup frame control
register (0x2A).
2. Wake-up frame 1 is defined in wakeup frame registers (0x40 – 0x4B) and is enabled by bit 1 in wakeup frame control
register (0x2A).
3. Wake-up frame 2 is defined in wakeup frame registers (0x50 – 0x5B) and is enabled by bit 2 in wakeup frame control
register (0x2A).
4. Wake-up frame 3 is defined in wakeup frame registers (0x60 – 0x6B) and is enabled by bit 3 in wakeup frame control
register (0x2A).
Magic Packet
Magic Packet technology is used to remotely wake up a sleeping or powered off PC on a LAN. This is accomplished by
sending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capable of
receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller, and when the LAN
controller receives a Magic Packet frame, it will alert the system to wake up.
Magic Packet is a standard feature integrated into the KSZ8851SNL. The controller implements multiple advanced powerdown modes including Magic Packet to conserve power and operate more efficiently.
Once the KSZ8851SNL has been put into Magic Packet Enable mode (WFCR[7]=1), it scans all incoming frames
addressed to the node for a specific data sequence, which indicates to the controller this is a Magic Packet (MP) frame.
A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as Source Address
(SA), Destination Address (DA), which may be the receiving station’s IEEE address or a multicast or broadcast address
and CRC.
The specific sequence consists of 16 duplications of the IEEE address of this node, with no breaks or interruptions. This
sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The
synchronization stream allows the scanning state machine to be much simpler. The synchronization stream is defined as
6 bytes of FFh. The device will also accept a broadcast frame, as long as the 16 duplications of the IEEE address match
the address of the machine to be awakened.
Example:
If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be
scanning for the data sequence (assuming an Ethernet frame):
DESTINATION SOURCE – MISC - FF FF FF FF FF FF - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 11 22 33 44 55 66 - MISC - CRC.
There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet or an
IPX packet. The frame may be bridged or routed across the network without affecting its ability to wake-up a node at the
frame’s destination.
If the LAN controller scans a frame and does not find the specific sequence shown above, it discards the frame and takes
no further action. If the KSZ8851SNL controller detects the data sequence, however, it then alerts the PC’s power
management circuitry (assert the PME pin) to wake up the system.
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Physical Layer Transceiver (PHY)
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion,
and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further
converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external 3.01kΩ (1%) resistor is
connected to pin 17 (ISET) for the 1:1 transformer ratio sets the output current.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance,
overshoot, and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE-TX driver.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock
recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable.
Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its characteristics to
optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming
signal strength against some known cable characteristics, and then tunes itself for optimization. This is an ongoing process and
self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to
convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B decoder.
Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC.
PLL Clock Synthesizer (Recovery)
The internal PLL clock synthesizer can generate either 125MHz, 62.5MHz, 41.66MHz, or 25MHz clocks by setting the on-chip
bus control register (0x20) for KSZ8851SNL system timing. These internal clocks are generated from an external 25MHz crystal
or oscillator.
Scrambler/De-scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and
baseline wander.
Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler generates
a 2047-bit non-repetitive sequence. Then the receiver de-scrambles the incoming data stream using the same sequence as at
the transmitter.
10BASE-T Transmit
The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics. They
are internally wave-shaped and pre-emphasized into outputs with typical 2.4V amplitude. The harmonic contents are at least
27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and a
phase-locked loop (PLL) perform the decoding function.
The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels
less than 400mV or with short pulse widths to prevent noise at the RXP or RXM input from falsely triggering the decoder. When
the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8851SNL decodes a data frame. The
receiver clock is maintained active during idle periods in between data reception.
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MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8851SNL supports HP-Auto MDI/MDI-X and
IEEE 802.3u standard MDI/MDI-X auto crossover. HP-Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns the transmit and receive pairs for
the KSZ8851SNL device. This feature is extremely useful when end users are unaware of cable types in addition to
saving on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port
control registers. The IEEE 802.3u standard MDI and MDI-X definitions are as below:
MDI
MDI-X
RJ45 Pins
Signals
RJ45 Pins
Signals
1
TD+
1
RD+
2
TD-
2
RD-
3
RD+
3
TD+
6
RD-
6
TD-
Table 2. MDI/MDI-X Pin Definitions
Straight Cable
A straight cable connects an MDI device to an MDI-X device or an MDI-X device to an MDI device. The following diagram
shows a typical straight cable connection between a network interface card (NIC) and a switch, or hub (MDI-X).
10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Media Dependent Interface
1
1
2
2
Transmit Pair
Receive Pair
3
Straight
Cable
3
4
4
5
5
6
6
7
7
8
8
Receive Pair
Transmit Pair
Modular Connector
(RJ-45)
HUB
(Repeater or Switch)
Modular Connector
(RJ-45)
NIC
Figure 3. Typical Straight Cable Connection
Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The
following diagram shows a typical crossover cable connection between two chips or hubs (two MDI-X devices).
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KSZ8851SNL/SNLI
10/100 Ethernet
Media Dependent Interface
1
Receive Pair
10/100 Ethernet
Media Dependent Interface
Crossover
Cable
1
Receive Pair
2
2
3
3
4
4
5
5
6
6
7
7
8
8
Transmit Pair
Transmit Pair
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Figure 4. Typical Crossover Cable Connection
Auto Negotiation
The KSZ8851SNL conforms to the auto negotiation protocol as described by the 802.3 committee to allow the port to
operate at either 10Base-T or 100Base-TX.
Auto negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In auto
negotiation, the link partners advertise capabilities across the link to each other. If auto negotiation is not supported or the
link partner to the KSZ8851SNL is forced to bypass auto negotiation, the mode is set by observing the signal at the
receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the
receiver is listening for advertisements or a fixed signal protocol.
The link setup is shown in the following flow diagram (Figure 5).
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Start Auto Negotiation
Force Link Setting
NO
Parallel
Operation
YES
By pass Auto Ne go tiation
and Set Link Mode
Attempt Auto
Negotiation
Listen for 100BASE-TX
Idles
Listen for 10BASE-T Link
Pulses
Join Flow
NO
Link Mode Set ?
YES
Link Mode Set
Figure 5. Auto Negotiation and Parallel Operation
®
LinkMD Cable Diagnostics
®
The KSZ8851SNL LinkMD uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling
problems such as open circuits, short circuits, and impedance mismatches.
®
LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes
the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with a
maximum distance of 200m and an accuracy of ±2m. Internal circuitry displays the TDR information in a user-readable
digital format in register P1SCLMD[8:0].
Note: cable diagnostics are only valid for copper connections – fiber-optic operation is not supported.
Access
®
®
LinkMD is initiated by accessing register P1SCLMD, the PHY special control/status and LinkMD register (0xF4).
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Usage
®
LinkMD can be run at any time by ensuring that Auto-MDIX has been disabled. To disable Auto-MDIX, write a ‘1’ to
®
P1CR[10] to enable manual control over the pair used to transmit the LinkMD pulse. The self-clearing cable diagnostic
test enable bit, P1SCLMD [12], is set to ‘1’ to start the test on this pair.
When bit P1SCLMD[12] returns to ‘0’, the test is complete. The test result is returned in bits P1SCLMD[14:13] and the
distance is returned in bits P1SCLMD[8:0]. The cable diagnostic test results are as follows:
00 = Valid test, normal condition
01 = Valid test, open circuit in cable
10 = Valid test, short circuit in cable
®
11 = Invalid test, LinkMD failed
If P1SCLMD[14:13]=11, this indicates an invalid test, and occurs when the KSZ8851SNL is unable to shut down the link
partner. In this instance, the test is not run, as it is not possible for the KSZ8851SNL to determine if the detected signal is
a reflection of the signal generated or a signal from another source.
Cable distance can be approximated by the following formula:
P1SCLMD[8:0] x 0.4m for port 1 cable distance
This constant may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies
significantly from the norm.
Media Access Control (MAC) Operation
The KSZ8851SNL strictly abides by IEEE 802.3 standards to maximize compatibility.
Inter Packet Gap (IPG)
If a frame is successfully transmitted, then the minimum 96-bit time for IPG is measured between two consecutive
packets. If the current packet is experiencing collisions, the minimum 96-bit time for IPG is measured from carrier sense
(CRS) to the next transmit packet.
Back-Off Algorithm
The KSZ8851SNL implements the IEEE standard 802.3 binary exponential back-off algorithm in half-duplex mode. After
16 collisions, the packet is dropped.
Late Collision
If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.
Flow Control
The KSZ8851SNL supports standard 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KSZ8851SNL receives a pause control frame, the KSZ8851SNL will not transmit the next
normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the
current timer expires, the timer will be updated with the new value in the second pause frame. During this period (while it
is flow controlled), only flow control packets from the KSZ8851SNL are transmitted.
On the transmit side, the KSZ8851SNL has intelligent and efficient ways to determine when to invoke flow control. The
flow control is based on availability of the system resources.
There are three programmable low watermark register FCLWR (0xB0), high watermark register FCHWR (0xB2) and
overrun watermark register FCOWR (0xB4) for flow control in RXQ FIFO. The KSZ8851SNL will send PAUSE frame
when the RXQ buffer hit the high watermark level (default 3.072 KByte available) and stop PAUSE frame when the RXQ
buffer hit the low watermark level (default 5.12 KByte available). The KSZ8851SNL will drop packet when the RXQ buffer
hit the overrun watermark level (default 256-Byte available).
The KSZ8851SNL issues a flow control frame (Xoff, or transmitter off), containing the maximum pause time defined in
IEEE standard 802.3x. Once the resource is freed up, the KSZ8851SNL sends out the another flow control frame (Xon, or
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transmitter on) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is
provided to prevent the flow control mechanism from being constantly activated and deactivated.
Half-Duplex Backpressure
A half-duplex backpressure option (non-IEEE 802.3 standards) is also provided. The activation and deactivation
conditions are the same as in full-duplex mode. If backpressure is required, the KSZ8851SNL sends preambles to defer
the other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8851SNL
discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other
stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to
send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are
transmitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until
chip resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is
generated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet
reception.
Address Filtering Function
The KSZ8851SNL supports 11 different address filtering schemes as shown in the following Table 3. The Ethernet
destination address (DA) field inside the packet is the first 6-byte field which uses to compare with either the host MAC
address registers (0x10 – 0x15) or the MAC address hash table registers (0xA0 – 0xA7) for address filtering operation.
The first bit (bit 40) of the destination address (DA) in the Ethernet packet decides whether this is a physical address if bit
40 is “0” or a multicast address if bit 40 is “1”.
Receive Control Register (0x74 – 0x75): RXCR1
Address Filtering
RX Physical
RX Multicast
Item
RX All RX Inverse
Mode
Address
Address
(Bit 4)
(Bit 1)
(Bit 11)
(Bit 8)
1
Perfect
0
0
1
1
2
Inverse perfect
0
1
1
1
3
Hash only
0
0
0
0
4
Inverse hash only
0
1
0
0
5
Hash perfect
(Default)
0
0
1
0
6
Inverse hash
perfect
0
1
1
0
Promiscuous
1
1
0
0
7
8
9
10
11
Hash only with
Multicast address
passed
Perfect with
Multicast address
passed
Hash only with
Physical address
passed
Perfect with
Physical address
passed
1
0
0
0
1
0
1
1
1
0
1
0
1
0
0
1
Description
All Rx frames are passed only if the DA exactly matches the
MAC address in MARL, MARM and MARH registers.
All Rx frames are passed if the DA is not matching the MAC
address in MARL, MARM and MARH registers.
All Rx frames with either multicast or physical destination
address are filtering against the MAC address hash table.
All Rx frames with either multicast or physical destination
address are filtering not against the MAC address hash table.
All Rx frames which are filtering out at item 3 (Hash only) only
are passed in this mode.
All Rx frames are passed with Physical address (DA) matching
the MAC address and to enable receive multicast frames that
pass the hash table when Multicast address is matching the
MAC address hash table.
All Rx frames which are filtering out at item 5 (Hash perfect) only
are passed in this mode.
All Rx frames are passed without any conditions.
All Rx frames are passed with Physical address (DA) matching
the MAC address hash table and with Multicast address without
any conditions.
All Rx frames are passed with Physical address (DA) matching
the MAC address and with Multicast address without any
conditions.
All Rx frames are passed with Multicast address matching the
MAC address hash table and with Physical address without any
conditions.
All Rx frames are passed with Multicast address matching the
MAC address and with Physical address without any conditions.
Note 1: Bit 0 (RX Enable), Bit 5 (RX Unicast Enable) and Bit 6 (RX Multicast Enable) must set to 1 in RXCR1 register.
Note 2: The KSZ8851SNL will discard frame with SA same as the MAC address if bit[0] is set in RXCR2 register.
Table 3. Address Filtering Scheme
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Clock Generator
The X1 and X2 pins are connected to a 25MHz crystal. X1 can also serve as the connector to a 3.3V, 25MHz oscillator
(as described in the pin description).
Serial Peripheral Interface (SPI)
The KSZ8851SNL supports a SPI interface in slave mode. In this mode, a external SPI master device (micro-controller or
CPU) supplies the operating serial clock (SCLK), chip select (CSN) and serial input data (SI) which is clocked in on the
rising edge of SCLK to KSZ8851SNL device. Serial output data (SO) is driven out by the KSZ8851SNL on the falling edge
of SCLK to external SPI master device. The falling edge of CSN is starting the SPI operation and the rising edge of CSN
is ending the SPI operation. The SCLK stays low state when SPI operation is idle. Figure 6 shows the SPI interface
connection for KSZ8851SNL.
Figure 6. SPI Interface to KSZ8851SNL
There are four SPI operations depending on the opcode inside the command phase:
•
Internal I/O registers read (opcode = 00)
•
Internal I/O registers write (opcode = 01)
•
RXQ FIFO read to receive packet (opcode = 10)
•
TXQ FIFO write to transmit packet (opcode = 11)
As shown in Table 4 and 5, there are two phases in each SPI operation, the first is command phase and the following is
data phase. Command phase is two bytes long for internal I/O registers access and one byte long for TXQ/RXQ FIFOs
access. Data phase on internal I/O registers access is in the range of one to four bytes long depending on the specified
byte enable bits B[3:0] in command phase, and data phase on TXQ or RXQ FIFOs access is limited up to 6 Kbytes for
TXQ access or 12 Kbytes for RXQ access.
Command Phase (SI pin)
SPI
Operation
Byte 0 [7:0]
Opcode Byte enable
Internal I/O
Register Read
Internal I/O
Register Write
Byte 1 [7:0]
Register Address
Data Phase
(SO or SI pins)
Don’t care bits
0 0
B3 B2 B1 B0 A7 A6 A5 A4 A3 A2
X X X X
0 1
B3 B2 B1 B0 A7 A6 A5 A4 A3 A2
X X X X
1 to 4 Bytes
(read data on SO pin)
1 to 4 Bytes
(write data on SI pin)
Note: In Command phase, A[7:2] access register address location in double word and B[3:0] enable which byte to
access during read or write. In Data phase, the byte 0 is first in/out and byte 3 is last in/out during read or write.
B[3:0] -> 1: enable byte, 0: disable byte.
Table 4. SPI Operation for Registers Access
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Command Phase (SI pin)
SPI Operation
Byte 0 [7:0]
Data Phase
(SO or SI pins)
Opcode
Don’t care bits
RXQ FIFO Read
(12 KByte)
1 0
X X X X X X
1 to 12 KBytes
(DMA read data on SO pin)
TXQ FIFO Write
(6 KByte)
1 1
X X X X X X
1 to 6 KBytes
(DMA write data on SI pin)
Note: The Start DMA Access bit 3 in RXQCR register must set to “1” before FIFO
read/write commands. This bit must be clear to “0” when DMA operation is finished.
Table 5. SPI Operation for TXQ/RXQ FIFO Access
SPI Internal I/O Registers Access Operation Timing
As shown in Figures 7 and 8 illustrate the SPI internal I/O registers read and write operation timing, the first two command
byte 0/1 contain opcode (00: read command, 01: write command), B[3:0] Byte enable bits to indicate which data byte is
available in data phase (1: byte enable, 0: byte disable) and A[7:2] address bits to access register location. The following
is data phase either 1, 2, 3, or 4 bytes depending on B[3:0] setting.
Figure 7. Internal I/O Register Read Timing
Figure 8. Internal I/O Register Write Timing
SPI TXQ/RXQ FIFOs Access Operation Timing
As shown in Figures 9 and 10 illustrate the SPI TXQ/RXQ FIFOs write and read operation timing, the first command byte
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0 contains only opcode (10: read command, 11: write command) and the following is read/write data phase.
CSN
SCLK
1
SI
0
X
X
X
X
X
X
High Impedance
SO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
RXQ Read Command Byte 0
Read Data Byte 1
Read Data Byte 2
CSN
SCLK
SI
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SO
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Read Data Byte 3
Read Data Byte 4
Read Data Byte N
Figure 9. RXQ FIFO Read Timing
Figure 10. TXQ FIFO Write Timing
Queue Management Unit (QMU)
The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It has
built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). Each
queue contains 12KB for RXQ and 6KB for TXQ of memory with back-to-back, non-blocking frame transfer performance.
It provides a group of control registers for system control, frame status registers for current packet transmit/receive status,
and interrupts to inform the host of the real time TX/RX status.
Transmit Queue (TXQ) Frame Format
The frame format for the transmit queue is shown in the following Table 6. The first word contains the control information
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for the frame to transmit. The second word is used to specify the total number of bytes of the frame. The packet data
follows. The packet data area holds the frame itself. It may or may not include the CRC checksum depending upon
whether hardware CRC checksum generation is enabled in TXCR (bit 1) register.
Multiple frames can be pipelined in both the transmit queue and receive queue as long as there is enough queue memory,
thus avoiding overrun. For each transmitted frame, the transmit status information for the frame is located in the TXSR
(0x72) register.
Packet Memory
Address Offset
Bit 15
nd
2 Byte
Bit 0
st
1 Byte
0
Control Word
2
Byte Count
4 - up
Transmit Packet Data
(maximum size is 2000)
Table 6. Frame Format for Transmit Queue
Since multiple packets can be pipelined into the TX packet memory for transmit, the transmit status reflects the status of
the packet that is currently being transferred on the MAC interface, which may or may not be the last queued packet in the
TX queue.
The transmit control word is the first 16-bit word in the TX packet memory, followed by a 16-bit byte count. It must be word
aligned. Each control word corresponds to one TX packet. Table 7 gives the transmit control word bit fields.
Bit
Description
15
TXIC Transmit Interrupt on Completion
When this bit is set, the KSZ8851SNL sets the transmit interrupt after the present frame has
been transmitted.
14-6
Reserved.
5-0
TXFID Transmit Frame ID
This field specifies the frame ID that is used to identify the frame and its associated status
information in the transmit status register.
Table 7. Transmit Control Word Bit Fields
The transmit Byte Count specifies the total number of bytes to be transmitted from the TXQ. Its format is given in Table 8.
Bit
Description
15-11
Reserved.
10-0
TXBC Transmit Byte Count
Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer
memory for better utilization of the packet memory.
Note: The hardware behavior is unknown if an incorrect byte count information is written to this
field. Writing a 0 value to this field is not permitted.
Table 8. Transmit Byte Count Format
The data area contains six bytes of Destination Address (DA) followed by six bytes of Source Address (SA), followed by a
variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
KSZ8851SNL does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by
the KSZ8851SNL. It is treated transparently as data both for transmit operations.
Frame Transmitting Path Operation in TXQ
This section describes the typical register settings for transmitting packets from host processor to KSZ8851SNL with
generic bus interface. User can use the default value for most of the transmit registers. The following Table 9 describes all
registers which need to be set and used for transmitting single or multiple frames.
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Register Name
[bit](offset)
Description
TXCR[3:0](0x70)
Set transmit control function as below:
TXCR[8:5](0x70)
Set bit 3 to enable transmitting flow control. Set bit 2 to enable transmitting padding.
Set bit 1 to enable transmitting CRC. Set bit 0 to enable transmitting block operation.
Set transmit checksum generation for ICMP, UDP, TCP and IP packet.
TXMIR[12:0](0x78)
The amount of free transmit memory available is represented in units of byte. The TXQ memory (6 KByte)
is used for both frame payload and control word.
TXQCR[0](0x80)
For single frame to transmit, set this bit 0 = 1(manual enqueue). the KSZ8851SNL will enable current TX
frame prepared in the TX buffer is queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to
be cleared before setting up another new TX frame.
TXQCR[1](0x80)
When this bit is written as 1, the KSZ8851SNL will generate interrupt (bit 6 in ISR register) to CPU when
TXQ memory is available based upon the total amount of TXQ space requested by CPU at TXNTFSR
(0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to
be cleared before set to 1 again
TXQCR[2](0x80)
For multiple frames to transmit, set this bit 2 = 1 (auto-enqueue). the KSZ8851SNL will enable current all
TX frames prepared in the TX buffer are queued to transmit automatically.
RXQCR[3](0x82)
Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data
frame)
TXFDPR[14](0x84)
Set bit 14 to enable TXQ transmit frame data pointer register increments automatically on accesses to the
data register.
IER[14][6](0x90)
Set bit 14 to enable transmit interrupt in Interrupt Enable Register
Set bit 6 to enable transmit space available interrupt in Interrupt Enable Register.
ISR[15:0](0x92)
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
TXNTFSR[15:0](0x9E)
The host CPU is used to program the total amount of TXQ buffer space which is required for next total
transmit frames size in double-word count.
Table 9. Registers Setting for Transmit Function Block
Driver Routine for Transmit Packet from Host Processor to KSZ8851SNL
The transmit routine is called by the upper layer to transmit a contiguous block of data through the Ethernet controller. It is
user’s choice to decide how the transmit routine is implemented. If the Ethernet controller encounters an error while
transmitting the frame, it’s the user’s choice to decide whether the driver should attempt to retransmit the same frame or
discard the data. The following Figures 11 and 12 shows the step-by-step for single and multiple transmit packets from
host processor to KSZ8851SNL.
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Host receives an Ethernet pkt from
upper layer and prepares transmit pkt
data (data, data_length, frame ID).
The transmit queue frame format is
shown in Table 6
Check if KSZ8851SNL TXQ
Memory size is available for this
transmit pkt?
(Read TXMIR Reg)
No
Write the total amount of TXQ buffer
space which is required for next
transmit frame size in double-word
count in TXNTFSR[15:0] register
Set bit 1=1 in TXQCR register to
enable the TXQ memory available
monitor
Yes
Write an 1?to RXQCR[3] reg to enable
TXQ write access, then Host issues a
SPI opcode=11 to start write transmit
data (control word, byte count and pkt
data) to TXQ memory. This is moving
transmit data from Host to KSZ8851SNL
TXQ memory until whole pkt is finished
Yes
Wait for interrupt
and check if the bit 6=1
(memory space available)
in ISR register
?
No
Write an 0?to RXQCR[3] reg to end
TXQ write access
Write an 1?to TXQCR[0] reg to issue a
transmit command (manual-enqueue)
to the TXQ. The TXQ will transmit this
pkt data to the PHY port
Option to Read ISR[14] reg, it indicates
that the TXQ has completed to transmit
at least one pkt to the PHY port, then
Write 1?to clear this bit
Figure 11. Host TX Single Frame in Manual Enqueue Flow Diagram
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Host receives an multiple Ethernet pkts
from upper layer and prepares transmit
pkts data (data, data_length, frame
ID). Each transmit queue frame format
is shown in Table 6
Write an ٛ1?to TXQCR[2] reg
to issue a transmit command (autoenqueue) to the TXQ. The TXQ will
transmit all data to the PHY port
Check if KSZ8851SNL TXQ
Memory size is available for these
transmit pkts?
(Read TXMIR Reg)
Write the total amount of TXQ buffer
space which is required for next
transmit total frames size in doubleword count in TXNTFSR[15:0] register
Set bit 1=1 in TXQCR register to
enable the TXQ memory available
monitor
No
Yes
Write an ٛ1?to RXQCR[3] reg to enable
TXQ write access, then Host issues a
SPI opcode=11 to start write transmit
data (control word, byte count and pkt
data) to TXQ memory. This is moving
transmit data from Host to
KSZ8851SNL TXQ memory until all
pkts are finished
Yes
Wait for interrupt
and check if the bit 6=1
(memory space available)
in ISR register
?
No
Write an ٛ0?to RXQCR[3] reg to end
TXQ write access
Option to read ISR[14] reg, it indicates
that the TXQ has completed to transmit
all pkts to the PHY port, then
Write ٛ1?to clear this bit
Figure 12. Host TX Multiple Frames in Auto- Enqueue Flow Diagram
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Receive Queue (RXQ) Frame Format
The frame format for the receive queue is shown in Table 10. The first word contains the status information for the frame
received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The
packet data area holds the frame itself. It includes the CRC checksum.
Packet Memory
Address Offset
Bit 15
0
Status Word
(see description in RXFHSR register)
2
Byte Count
(see description in RXFHBCR register)
4 - up
Receive Packet Data
(maximum size is 2000)
2
nd
Bit 0
st
Byte
1 Byte
Table 10. Frame Format for Receive Queue
Frame Receiving Path Operation in RXQ
This section describes the typical register settings for receiving packets from KSZ8851SNL to host processor with generic
bus interface. User can use the default value for most of the receive registers. The following Table 11 describes all
registers which need to be set and used for receiving single or multiple frames.
Register Name[bit](offset)
Description
RXCR1(0x74)
Set receive control function as below:
RXCR2(0x76)
Set RXCR1[10] to enable receiving flow control. Set RXCR1[0] to enable receiving block operation.
Set receive checksum check for ICMP, UDP, TCP and IP packet.
Set receive address filtering scheme as shown in the Table 3.
RXFHSR[15:0](0x7C)
This register (read only) indicates the current received frame header status information.
RXFHBCR[11:0](0x7E)
This register (read only) indicates the current received frame header byte count information.
RXQCR[12:3](0x82)
Set RXQ control function as below:
Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data
frame). Set bit 4 to automatically enable RXQ frame buffer dequeue. Set bit 5 to enable RX frame count
threshold and read bit 10 for status. Set bit 6 to enable RX data byte count threshold and read bit 11 for
status. Set bit 7 to enable RX frame duration timer threshold and read bit 12 for status. Set bit 9 enable
RX IP header two-byte offset.
RXFDPR[14](0x86)
Set bit 14 to enable RXQ address register increments automatically on accesses to the data register.
RXDTTR[15:0](0x8C)
To program received frame duration timer value. When Rx frame duration in RXQ exceeds this
threshold in 1 uS interval count and bit 7 of RXQCR register is set to 1, the KSZ8851SNL will generate
RX interrupt in ISR[13] and indicate the status in RXQCR[12].
RXDBCTR[15:0](0x8E)
To program received data byte count value. When the number of received bytes in RXQ exceeds this
threshold in byte count and bit 6 of RXQCR register is set to 1, the KSZ8851SNL will generate RX
interrupt in ISR[13] and indicate the status in RXQCR[11].
IER[13](0x90)
Set bit 13 to enable receive interrupt in Interrupt Enable Register.
ISR[15:0](0x92)
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
RXFCTR[15:8](0x9C)
Rx frame count read only. To indicate the total received frame in RXQ frame buffer when receive
interrupt (bit 13 in ISR) occurred.
RXFCTR[7:0](0x9C)
To program received frame count value. When the number of received frames in RXQ exceeds this
threshold value and bit 5 of RXQCR register is set to 1, the KSZ8851SNL will generate RX interrupt in
ISR[13] and indicate the status in RXQCR[10].
Table 11. Registers Setting for Receive Function Block
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Driver Routine for Receive Packet from KSZ8851SNL to Host Processor
The software driver receives data packet frames from the KSZ8851SNL device either as a result of polling or an interrupt
based service. When an interrupt is received, the OS invokes the interrupt service routine that is in the interrupt vector
table.
If your system has OS support, to minimize interrupt lockout time, the interrupt service routine should handle at interrupt
level only those tasks that require minimum execution time, such as error checking or device status change. The routine
should queue all the time-consuming work to transfer the packet from the KSZ8851SNL RXQ into system memory at task
level. The following Figure 13 shows the step-by-step for receive packets from KSZ8851SNL to host processor.
Note: Each DMA read operation from the host CPU to read RXQ frame buffer, the first read data (byte in 8-bit bus mode,
word in 16-bit bus mode and double word in 32-bit bus mode) is dummy data and must be discarded by host CPU.
Afterward, host CPU must read each frame data to align with double word boundary at end. For example, the host CPU
has to read up to 68 bytes if received frame size is 65 bytes.
Figure 13. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram
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In order to read received frames from RXQ without error, the software driver must use following steps:
1. When receive interrupt occurred and software driver writes “1” to clear the RX interrupt in ISR register; the
KSZ8851 will update Receive Frame Counter (RXFCTR) Register for this interrupt.
2. When software driver reads back Receive Frame Count (RXFCTR) Register; the KSZ8851 will update both
Receive Frame Header Status and Byte Count Registers (RXFHSR/RXFHBCR).
3. When software driver reads back both Receive Frame Header Status and Byte Count Registers
(RXFHSR/RXFHBCR); the KSZ8851 will update next receive frame header status and byte count registers
(RXFHSR/RXFHBCR).
EEPROM Interface
It is optional in the KSZ8851SNL to use an external EEPROM. The EED_IO (pin 6) must be pulled high to use external
EEPROM otherwise this pin pulled low or floating without EEPROM.
An external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information such as
the host MAC address. The KSZ8851SNL can detect if the EEPROM is a 1KB (93C46) or 4KB (93C66) EEPROM device
(the 93C46 and the 93C66 are typical EEPROM devices). The EEPROM must be organized as 16-bit mode.
If the EED_IO pin is pulled high, then the KSZ8851SNL performs an automatic read of the external EEPROM words 0H to
3H after the de-assertion of Reset. The EEPROM values are placed in certain host-accessible registers. EEPROM
read/write functions can also be performed by software read/writes to the EEPCR (0x22) registers.
The KSZ8851SNL EEPROM format is given in Table 12.
WORD
15
8
7
0H
Reserved
1H
Host MAC Address Byte 2
Host MAC Address Byte 1
2H
Host MAC Address Byte 4
Host MAC Address Byte 3
3H
Host MAC Address Byte 6
Host MAC Address Byte 5
4H – 6H
Reserved
7H-3FH
Not used for KSZ8851SNL (available for user to use)
0
Table 12. KSZ8851SNL EEPROM Format
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Loopback Support
The KSZ8851SNL provides two loopback modes, one is Near-end (Remote) loopback to support for remote diagnostic of
failure at line side, and the other is Far-end (Local) loopback to support for local diagnostic of failure at host side. In
loopback mode, the speed at the PHY port will be set to 100BASE-TX full-duplex mode.
Near-end (Remote) Loopback
Near-end (Remote) loopback is conducted at PHY port 1 of the KSZ8851SNL. The loopback path starts at the PHY port’s
receive inputs (RXP/RXM), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs
(TXP/TXM).
Bit [9] of register P1SCLMD (0xF4) is used to enable near-end loopback. The ports 1 near-end loopback path is illustrated
in the following Figure 14.
Far-end (Local) Loopback
Far-end (Local) loopback is conducted at Host of the KSZ8851SNL. The loopback path starts at the host SPI FIFO write
to transmit data, wraps around at the PHY port’s PMD/PMA, and ends at the host SPI FIFO read to receive data.
Bit [14] of register P1MBCR (0xE4) is used to enable far-end loopback at host side. The host far-end loopback path is
illustrated in the following Figure 14.
Figure 14. PHY Port 1 Near-end (Remote) and Host Far-end (Local) Loopback Paths
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SPI Interface to I/O Registers
The KSZ8851SNL provides a SPI interface for the host CPU to access its internal I/O registers. I/O registers serve as the
address that the microprocessor uses when communicating with the device. This is used for configuring operational
settings, reading or writing control, status information, and transferring packets.
I/O Registers
The following I/O Space Mapping Tables apply to 8-bit, 16-bit or 32-bit access. Depending upon the byte enable bits
B[3:0] settings in command phase, each I/O access can be performed the following operations as an 8-bit for 256 address
locations, 16-bit for 128 address locations or 32-bit for 64 address locations.
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Internal I/O Registers Space Mapping
I/O Register Offset Location
32-Bit
16-Bit
0x00
to
0x03
0x00 - 0x01
0x04
to
0x07
0x04 - 0x05
0x08
to
0x0B
0x08 - 0x09
0x02 - 0x03
0x06 - 0x07
0x0A - 0x0B
0x0C
to
0x0F
0x0C - 0x0D
0x10
to
0x13
0x10 - 0x11
0x14
to
0x17
0x14 - 0x15
0x18
to
0x1B
0x18 - 0x19
0x0E - 0x0F
0x12 - 0x13
0x16 - 0x17
0x1A - 0x1B
8-Bit
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
Register
Name
Default
Value
Reserved
Don’t care
None
Reserved
Don’t care
None
CCR
Read only
Chip Configuration Register [7:0]
Chip Configuration Register [15:8]
Reserved
Don’t care
None
Reserved
Don’t care
None
MARL
-
MARM
-
MARH
-
Reserved
Don’t care
None
Reserved
Don’t care
None
Reserved
Don’t care
None
OBCR
0x0000
On-Chip Bus Control Register [7:0]
On-Chip Bus Control Register [15:8]
Description
MAC Address Register Low [7:0]
MAC Address Register Low [15:8]
MAC Address Register Middle [7:0]
MAC Address Register Middle [15:8]
MAC Address Register High [7:0]
MAC Address Register High [15:8]
0x1C
to
0x1F
0x1C - 0x1D
0x20
to
0x23
0x20 - 0x21
0x22 - 0x23
0x22
0x23
EEPCR
0x0000
EEPROM Control Register [7:0]
EEPROM Control Register [15:8]
0x24
to
0x27
0x24 - 0x25
0x24
0x25
MBIR
0x1010
Memory BIST Info Register [7:0]
Memory BIST Info Register [15:8]
0x26 - 0x27
0x26
0x27
GRR
0x0000
Global Reset Register [7:0]
Global Reset Register [15:8]
0x28
to
0x2B
0x28 - 0x29
Reserved
Don’t care
WFCR
0x0000
Reserved
Don’t care
0x2C
to
0x2F
August 2009
0x1E - 0x1F
0x2A - 0x2B
0x2C - 0x2D
0x2E - 0x2F
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
34
None
Wakeup Frame Control Register [7:0]
Wakeup Frame Control Register [15:8]
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I/O Register Offset Location
Register
Name
Default
Value
WF0CRC0
0x0000
WF0CRC1
0x0000
WF0BM0
0x0000
0x36
0x37
WF0BM1
0x0000
0x38
0x39
WF0BM2
0x0000
WF0BM3
0x0000
Reserved
Don’t care
WF1CRC0
0x0000
32-Bit
16-Bit
8-Bit
0x30
to
0x33
0x30 - 0x31
0x30
0x31
0x34
to
0x37
0x34 - 0x35
0x36 - 0x37
0x38
to
0x3B
0x38 - 0x39
0x32 - 0x33
0x3A - 0x3B
0x32
0x33
0x34
0x35
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x3C
To
0x3F
0x3C - 0x3D
0x40
to
0x43
0x40 - 0x41
0x42 - 0x43
0x42
0x43
WF1CRC1
0x0000
0x44
to
0x47
0x44 - 0x45
0x44
0x45
WF1BM0
0x0000
0x46 - 0x47
0x46
0x47
WF1BM1
0x0000
0x48
to
0x4B
0x48 - 0x49
0x48
0x49
WF1BM2
0x0000
WF1BM3
0x0000
Reserved
Don’t care
WF2CRC0
0x0000
0x3E - 0x3F
0x4A - 0x4B
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x4C
to
0x4F
0x4C - 0x4D
0x50
to
0x53
0x50 - 0x51
0x52 - 0x53
0x52
0x53
WF2CRC1
0x0000
0x54
to
0x57
0x54 - 0x55
0x54
0x55
WF2BM0
0x0000
0x56 - 0x57
0x56
0x57
WF2BM1
0x0000
0x58
to
0x5B
0x58 - 0x59
0x58
0x59
WF2BM2
0x0000
WF2BM3
0x0000
Reserved
Don’t care
0x5C
to
0x5F
August 2009
0x4E - 0x4F
0x5A - 0x5B
0x5C - 0x5D
0x5E - 0x5F
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
35
Description
Wakeup Frame 0 CRC0 Register [7:0]
Wakeup Frame 0 CRC0 Register [15:8]
Wakeup Frame 0 CRC1 Register [7:0]
Wakeup Frame 0 CRC1 Register [15:8]
Wakeup Frame 0 Byte Mask 0 Register [7:0]
Wakeup Frame 0 Byte Mask 0 Register [15:8]
Wakeup Frame 0 Byte Mask 1 Register [7:0]
Wakeup Frame 0 Byte Mask 1 Register [15:8]
Wakeup Frame 0 Byte Mask 2 Register [7:0]
Wakeup Frame 0 Byte Mask 2 Register [15:8]
Wakeup Frame 0 Byte Mask 3 Register [7:0]
Wakeup Frame 0 Byte Mask 3 Register [15:8]
None
Wakeup Frame 1 CRC0 Register [7:0]
Wakeup Frame 1 CRC0 Register [15:8]
Wakeup Frame 1 CRC1 Register [7:0]
Wakeup Frame 1 CRC1 Register [15:8]
Wakeup Frame 1 Byte Mask 0 Register [7:0]
Wakeup Frame 1 Byte Mask 0 Register [15:8]
Wakeup Frame 1 Byte Mask 1 Register [7:0]
Wakeup Frame 1 Byte Mask 1 Register [15:8]
Wakeup Frame 1 Byte Mask 2 Register [7:0]
Wakeup Frame 1 Byte Mask 2 Register [15:8]
Wakeup Frame 1 Byte Mask 3 Register [7:0]
Wakeup Frame 1 Byte Mask 3 Register [15:8]
None
Wakeup Frame 2 CRC0 Register [7:0]
Wakeup Frame 2 CRC0 Register [15:8]
Wakeup Frame 2 CRC1 Register [7:0]
Wakeup Frame 2 CRC1 Register [15:8]
Wakeup Frame 2 Byte Mask 0 Register [7:0]
Wakeup Frame 2 Byte Mask 0 Register [15:8]
Wakeup Frame 2 Byte Mask 1 Register [7:0]
Wakeup Frame 2 Byte Mask 1 Register [15:8]
Wakeup Frame 2 Byte Mask 2 Register [7:0]
Wakeup Frame 2 Byte Mask 2 Register [15:8]
Wakeup Frame 2 Byte Mask 3 Register [7:0]
Wakeup Frame 2 Byte Mask 3 Register [15:8]
None
M9999-083109-2.0
Micrel, Inc.
KSZ8851SNL/SNLI
I/O Register Offset Location
Register
Name
Default
Value
32-Bit
16-Bit
8-Bit
0x60
to
0x63
0x60 - 0x61
0x60
0x61
WF3CRC0
0x0000
0x62 - 0x63
0x62
0x63
WF3CRC1
0x0000
0x64
to
0x67
0x64 - 0x65
0x64
0x65
WF3BM0
0x0000
0x66 - 0x67
0x66
0x67
WF3BM1
0x0000
0x68
to
0x6B
0x68 - 0x69
0x68
0x69
WF3BM2
0x0000
0x6A - 0x6B
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
WF3BM3
0x0000
Reserved
Don’t care
TXCR
0x0000
0x6C
to
0x6F
0x6C - 0x6D
0x70
to
0x73
0x70 - 0x71
0x72 - 0x73
0x72
0x73
TXSR
0x0000
0x74
to
0x77
0x74 - 0x75
0x74
0x75
RXCR1
0x0800
0x76 - 0x77
0x76
0x77
RXCR2
0x0004
0x78
to
0x7B
0x78 - 0x79
0x6E - 0x6F
0x7A - 0x7B
0x78
0x79
0x7A
0x7B
0x7C
0x7D
TXMIR
0x0000
Reserved
Don’t care
RXFHSR
0x0000
0x7C
to
0x7F
0x7C - 0x7D
0x7E - 0x7F
0x7E
0x7F
RXFHBCR
0x0000
0x80
to
0x83
0x80 - 0x81
0x80
0x81
TXQCR
0x0000
0x82 - 0x83
0x82
0x83
RXQCR
0x0000
0x84
to
0x87
0x84 - 0x85
0x84
0x85
TXFDPR
0x0000
0x88
to
0x8B
0x88 - 0x89
0x8C
to
0x8F
August 2009
0x86 - 0x87
0x8A - 0x8B
0x8C - 0x8D
0x8E - 0x8F
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
RXFDPR
0x0000
Reserved
Don’t care
RXDTTR
0x0000
0x8E
0x8F
RXDBCTR
0x0000
36
Description
Wakeup Frame 3 CRC0 Register [7:0]
Wakeup Frame 3 CRC0 Register [15:8]
Wakeup Frame 3 CRC1 Register [7:0]
Wakeup Frame 3 CRC1 Register [15:8]
Wakeup Frame 3 Byte Mask 0 Register [7:0]
Wakeup Frame 3 Byte Mask 0 Register [15:8]
Wakeup Frame 3 Byte Mask 1 Register [7:0]
Wakeup Frame 3 Byte Mask 1 Register [15:8]
Wakeup Frame 3 Byte Mask 2 Register [7:0]
Wakeup Frame 3 Byte Mask 2 Register [15:8]
Wakeup Frame 3 Byte Mask 3 Register [7:0]
Wakeup Frame 3 Byte Mask 3 Register [15:8]
None
Transmit Control Register [7:0]
Transmit Control Register [15:8]
Transmit Status Register [7:0]
Transmit Status Register [15:8]
Receive Control Register 1 [7:0]
Receive Control Register 1 [15:8]
Receive Control Register 2 [7:0]
Receive Control Register 2 [15:8]
TXQ Memory Information Register [7:0]
TXQ Memory Information Register [15:8]
None
Receive Frame Header Status Register [7:0]
Receive Frame Header Status Register [15:8]
Receive Frame Header Byte Count Register [7:0]
Receive Frame Header Byte Count Register [15:8]
TXQ Command Register [7:0]
TXQ Command Register [15:8]
RXQ Command Register [7:0]
RXQ Command Register [15:8]
TX Frame Data Pointer Register [7:0]
TX Frame Data Pointer Register [15:8]
RX Frame Data Pointer Register [7:0]
RX Frame Data Pointer Register [15:8]
None
RX Duration Timer Threshold Register [7:0]
RX Duration Timer Threshold Register [15:8]
RX Data Byte Count Threshold Register [7:0]
RX Data Byte Count Threshold Register [15:8]
M9999-083109-2.0
Micrel, Inc.
KSZ8851SNL/SNLI
I/O Register Offset Location
32-Bit
16-Bit
8-Bit
0x90
to
0x93
0x90 - 0x91
0x90
0x91
0x94
to
0x97
0x94 - 0x95
0x98
to
0x9B
0x98 - 0x99
0x92 - 0x93
0x96 - 0x97
0x9A - 0x9B
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
Register
Name
Default
Value
IER
0x0000
ISR
0x0300
Reserved
Don’t care
None
Reserved
Don’t care
None
RXFCTR
0x0000
Description
Interrupt Enable Register [7:0]
Interrupt Enable Register [15:8]
Interrupt Status Register [7:0]
Interrupt Status Register [15:8]
RX Frame Count & Threshold Register [7:0]
RX Frame Count & Threshold Register [15:8]
TX Next Total Frames Size Register [7:0]
TX Next Total Frames Size Register [15:8]
MAC Address Hash Table Register 0 [7:0]
MAC Address Hash Table Register 0 [15:8]
MAC Address Hash Table Register 1 [7:0]
MAC Address Hash Table Register 1 [15:8]
MAC Address Hash Table Register 2 [7:0]
MAC Address Hash Table Register 2 [15:8]
MAC Address Hash Table Register 3 [7:0]
MAC Address Hash Table Register 3 [15:8]
0x9C
to
0x9F
0x9C - 0x9D
0x9E - 0x9F
0x9E
0x9F
TXNTFSR
0x0000
0xA0
to
0xA3
0xA0 - 0xA1
0xA0
0xA1
MAHTR0
0x0000
0xA2 - 0xA3
0xA2
0xA3
MAHTR1
0x0000
0xA4
to
0xA7
0xA4 - 0xA5
0xA4
0xA5
MAHTR2
0x0000
MAHTR3
0x0000
0xA8
to
0xAB
0xA8 - 0xA9
Reserved
Don’t care
None
Reserved
Don’t care
None
FCLWR
0x0500
0xA6 - 0xA7
0xAA - 0xAB
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xAC
to
0xAF
0xAC - 0xAD
0xB0
to
0xB3
0xB0 - 0xB1
0xB2 - 0xB3
0xB2
0xB3
FCHWR
0x0300
0xB4
to
0xB7
0xB4 - 0xB5
0xB4
0xB5
FCOWR
0x0040
0xB6 - 0xB7
0xB6
0xB7
Reserved
Don’t care
None
0xB8
to
0xBB
0xB8 - 0xB9
Reserved
Don’t care
None
Reserved
Don’t care
None
0xBC
to
0xBF
August 2009
0xAE - 0xAF
0xBA - 0xBB
0xBC - 0xBD
0xBE - 0xBF
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
37
Flow Control Low Watermark Register [7:0]
Flow Control Low Watermark Register [15:8]
Flow Control High Watermark Register [7:0]
Flow Control High Watermark Register [15:8]
Flow Control Overrun Watermark Register [7:0]
Flow Control Overrun Watermark Register [15:8]
M9999-083109-2.0
Micrel, Inc.
KSZ8851SNL/SNLI
I/O Register Offset Location
Register
Name
Default
Value
0xC0
0xC1
CIDER
0x8870
0xC2
0xC3
Reserved
Don’t care
None
Reserved
Don’t care
None
CGCR
0x0835
IACR
0x0000
Reserved
Don’t care
None
Reserved
Don’t care
None
IADLR
0x0000
32-Bit
16-Bit
8-Bit
0xC0
to
0xC3
0xC0 - 0xC1
0xC2 - 0xC3
0xC4
to
0xC7
0xC8
to
0xCB
0xC4 - 0xC5
0xC6 - 0xC7
0xC8 - 0xC9
0xCA - 0xCB
0xCC
to
0xCF
0xCC - 0xCD
0xD0
to
0xD3
0xD0 - 0xD1
0xD4
to
0xD7
0xD8
to
0xDB
0xCE - 0xCF
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
Chip Global Control Register [7:0]
Chip Global Control Register [15:8]
Indirect Access Control Register [7:0]
Indirect Access Control Register [15:8]
Indirect Access Data Low Register [7:0]
Indirect Access Data Low Register [15:8]
Indirect Access Data High Register [7:0]
Indirect Access Data High Register [15:8]
Power Management Event Control Register [7:0]
Power Management Event Control Register [15:8]
Go-Sleep & Wake-Up Time Register [7:0]
Go-Sleep & Wake-Up Time Register [15:8]
PHY Reset Register [7:0]
PHY Reset Register [15:8]
0xD2
0xD3
IADHR
0x0000
0xD4 - 0xD5
0xD4
0xD5
PMECR
0x0080
0xD6 - 0xD7
0xD6
0xD7
GSWUTR
0X080C
0xD8 - 0xD9
0xD8
0xD9
PHYRR
0x0000
0xDA - 0xDB
0xDA
0xDB
Reserved
Don’t care
None
Reserved
Don’t care
None
Reserved
Don’t care
None
P1MBCR
0x3120
0xDC
0xDD
0xDE
0xDF
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xDC - 0xDD
0xE0
to
0xE3
0xE0 - 0xE1
0xE4
to
0xE7
0xE4 - 0xE5
0xE6 - 0xE7
0xE6
0xE7
P1MBSR
0x7808
0xE8
to
0xEB
0xE8 - 0xE9
0xE8
0xE9
PHY1ILR
0x1430
0xEA - 0xEB
0xEA
0xEB
PHY1IHR
0x0022
0xEC - 0xED
0xEC
0xED
P1ANAR
0x05E1
0xEE - 0xEF
0xEE
0xEF
P1ANLPR
0x0001
August 2009
Chip ID and Enable Register [7:0]
Chip ID and Enable Register [15:8]
0xD2 - 0xD3
0xDC
to
0xDF
0xEC
to
0xEF
Description
0xDE - 0xDF
0xE2 - 0xE3
38
PHY 1 MII-Register Basic Control Register [7:0]
PHY 1 MII-Register Basic Control Register [15:8]
PHY 1 MII-Register Basic Status Register [7:0]
PHY 1 MII-Register Basic Status Register [15:8]
PHY 1 PHY ID Low Register [7:0]
PHY 1 PHY ID Low Register [15:8]
PHY 1 PHY ID High Register [7:0]
PHY 1 PHY ID High Register [15:8]
PHY 1 Auto-Negotiation Advertisement Register [7:0]
PHY 1 Auto-Negotiation Advertisement
Register [15:8]
PHY 1 Auto-Negotiation Link Partner Ability Register [7:0]
PHY 1 Auto-Negotiation Link Partner Ability Register [15:8]
M9999-083109-2.0
Micrel, Inc.
KSZ8851SNL/SNLI
I/O Register Offset Location
32-Bit
16-Bit
0xF0
to
0xF3
0xF0 - 0xF1
0xF4
to
0xF7
0xF8
to
0xFB
0xFC
to
0xFF
August 2009
0xF2 - 0xF3
0xF4 - 0xF5
0xF6 - 0xF7
0xF8 - 0xF9
0xFA - 0xFB
0xFC - 0xFD
0xFE - 0xFF
8-Bit
0xF0
0xF1
0xF2
0xF3
0xF4
0xF5
0xF6
0xF7
0xF8
0xF9
0xFA
0xFB
0xFC
0xFD
0xFE
0xFF
Register
Name
Default
Value
Reserved
Don’t care
P1SCLMD
0x0000
P1CR
0x00FF
P1SR
0x8080
Reserved
Don’t care
None
Reserved
Don’t care
None
Description
None
®
39
Port 1 PHY Special Control/Status, LinkMD [7:0]
Port 1 PHY Special Control/Status, LinkMD® [15:8]
Port 1 Control Register [7:0]
Port 1 Control Register [15:8]
Port 1 Status Register [7:0]
Port 1 Status Register [15:8]
M9999-083109-2.0
Micrel, Inc.
KSZ8851SNL/SNLI
Register Map: MAC, PHY and QMU
Do not write to bit values or to registers defined as Reserved. Manipulating reserved bits or registers causes
unpredictable and often fatal results. If the user wants to write to these reserved bits, the user has to read back these
reserved bits (RO or RW) first, then “OR” with the read value of the reserved bits and write back to these reserved bits.
Bit Type Definition
RO = Read only.
WO = Write only.
RW = Read/Write.
W1C = Write 1 to Clear (writing an “1” to clear this bit).
0x00 – 0x07: Reserved
Chip Configuration Register (0x08 – 0x09): CCR
This register indicates the chip configuration mode based on strapping and bonding options
Bit
Default Value
R/W
Description
15-10
-
RO
Reserved
9
-
RO
EEPROM presence
The EED_IO (pin 6) value is latched into this bit druing power-up/reset.
8
-
RO
0: No external EEPROM, 1: Use external EEPROM.
SPI bus mode
To indicate this is SPI interface for host
0: No, 1: Yes.
7-4
0x0
RO
Reserved
3
0
RO
Reserved
2
0
RO
Reserved
1
0
RO
Reserved
0
-
RO
32-Pin Chip Package
To indicate this device is KSZ8851SNL.
0: No, 1: Yes
0x0A – 0x0F: Reserved
Host MAC Address Registers: MARL, MARM and MARH
These Host MAC address registers are loaded starting at word location 0x1 of the EEPROM upon hardware reset. The
software driver can read or write these registers value, but it will not modify the original Host MAC address value in the
EEPROM. These six bytes of Host MAC address in external EEPROM are loaded to these three registers as mapping
below:
MARL[15:0] = EEPROM 0x1(MAC Byte 2 and 1)
MARM[15:0] = EEPROM 0x2(MAC Byte 4 and 3)
MARH[15:0] = EEPROM 0x3(MAC Byte 6 and 5)
The Host MAC address is used to define the individual destination address that the KSZ8851SNL responds to when
receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are
received from left to right, and the bits within each byte are received from right to left (LSB to MSB). For example, the
actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101.
These three registers value for Host MAC address 01:23:45:67:89:AB will be held as below:
MARL[15:0] = 0x89AB
MARM[15:0] = 0x4567
August 2009
40
M9999-083109-2.0
Micrel, Inc.
KSZ8851SNL/SNLI
MARH[15:0] = 0x0123
Host MAC Address Register Low (0x10 – 0x11): MARL
The following table shows the register bit fields for Low word of Host MAC address.
Bit
Default Value
R/W
Description
15-0
-
RW
MARL MAC Address Low
The least significant word of the MAC address.
Host MAC Address Register Middle (0x12 – 0x13): MARM
The following table shows the register bit fields for middle word of Host MAC address.
Bit
Default Value
R/W
Description
15-0
-
RW
MARM MAC Address Middle
The middle word of the MAC address.
Host MAC Address Register High (0x14 – 0x15): MARH
The following table shows the register bit fields for high word of Host MAC address.
Bit
Default Value
R/W
Description
15-0
-
RW
MARH MAC Address High
The Most significant word of the MAC address.
0x16 – 0x1F: Reserved
On-Chip Bus Control Register (0x20 – 0x21): OBCR
This register controls the on-chip bus clock speed for the KSZ8851SNL. The default of the on-chip bus clock speed is 125
MHz. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best
performance.
Bit
Default Value
R/W
Description
15-7
-
RO
Reserved
6
0
RW
Output Pin Drive Strength
Bi-directional or output pad drive strength selection.
0: 8 mA
1: 16 mA
5-3
0x0
RO
Reserved
2
0
RW
On-Chip Bus Clock Selection
0: 125 MHz (default setting is divided by 1, Bit[1:0]=00)
1: NA (reserved)
1-0
0x0
RW
On-Chip Bus Clock Divider Selection
00: Divided by 1.
01: Divided by 2.
10: Divided by 3.
11: NA (reserved).
For example to contol the bus clock speed as below:
If Bit 2 = 0 and this value is set 00 to select 125 MHz.
If Bit 2 = 0 and this value is set 01 to select 62.5 MHz.
August 2009
41
M9999-083109-2.0
Micrel, Inc.
KSZ8851SNL/SNLI
EEPROM Control Register (0x22 – 0x23): EEPCR
To support an external EEPROM, pulled-up the EED_IO pin to High; otherwise, it is pulled-down to Low. If an external
EEPROM is not used, the software programs the host MAC address. If an EEPROM is used in the design, the chip host
MAC address is loaded from the EEPROM immediately after reset. The KSZ8851SNL allows the software to access (read
and write) the EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the
EEPROM Software Access bit is set.
Bit
Default Value
R/W
Description
15-6
-
RO
Reserved.
5
0
WO
EESRWA EEPROM Software Read or Write Access
0: software read enable to access EEPROM when software access enabled (bit 4 is “1”)
4
0
RW
1: software write enable to access EEPROM when software access enabled (bit 4 is “1”).
EESA EEPROM Software Access
1: enable software to access EEPROM through bit 3 to bit 0.
0: disable software to access EEPROM.
3
-
RO
EESB EEPROM Status Bit
Data Receive from EEPROM. This bit directly reads the EED_IO pin 6.
2-0
0x0
RW
EECB EEPROM Control Bits
Bit 2: Data Transmit to EEPROM. This bit directly controls the device’s EED_IO pin 6.
Bit 1: Serial Clock. This bit directly controls the device’s EESK pin 7.
Bit 0: Chip Select for EEPROM. This bit directly controls the device’s EECS pin 10.
Memory BIST Info Register (0x24 – 0x25): MBIR
This register indicates the build-in self test result for both TX and RX memories after power-up/reset.
Bit
Default Value
R/W
Description
15-13
0x0
RO
Reserved
12
-
RO
TXMBF TX Memory BIST Test Finish
When set, it indicates the Memory Built In Self Test completion for the TX Memory.
11
-
RO
TXMBFA TX Memory BIST Test Fail
When set, it indicates the TX Memory Built In Self Test has failed.
10-8
-
RO
TXMBFC TX Memory BIST Test Fail Count
To indicate the TX Memory Built In Self Test failed count
7-5
-
RO
Reserved
4
-
RO
RXMBF RX Memory Bist Finish
When set, it indicates the Memory Built In Self Test completion for the RX Memory.
3
-
RO
RXMBFA RX Memory Bist Fail
When set, it indicates the RX Memory Built In Self Test has failed.
2-0
-
RO
RXMBFC RX Memory BIST Test Fail Count
To indicate the RX Memory Built In Self Test failed count.
August 2009
42
M9999-083109-2.0
Micrel, Inc.
KSZ8851SNL/SNLI
Global Reset Register (0x26 – 0x27): GRR
This register controls the global and QMU reset functions with information programmed by the CPU.
Bit
Default Value
R/W
Description
15-2
0x0000
RO
Reserved
1
0
RW
QMU Module Soft Reset
1: Software reset is active to clear both TXQ and RXQ memories.
0: Software reset is inactive.
QMU software reset will flush out all TX/RX packet data inside the TXQ and RXQ
memories and reset all QMU registers to default value.
0
0
RW
Global Soft Reset
1: Software reset is active.
0: Software reset is inactive.
Global software reset will affect PHY, MAC, QMU, DMA, and the switch core, all registers
value are set to default value.
0x28 – 0x29: Reserved
Wakeup Frame Control Register (0x2A – 0x2B): WFCR
This register holds control information programmed by the CPU to control the wake up frame function.
Bit
Default Value
R/W
Description
15-8
0x00
RO
Reserved
7
0
RW
MPRXE
Magic Packet RX Enable
When set, it enables the magic packet pattern detection.
When reset, the magic packet pattern detection is disabled.
6-4
0x0
RO
Reserved
3
0
RW
WF3E
Wake up Frame 3 Enable
When set, it enables the Wake up frame 3 pattern detection.
When reset, the Wake up frame 3 pattern detection is disabled.
2
0
RW
WF2E
Wake up Frame 2 Enable
When set, it enables the Wake up frame 2 pattern detection.
When reset, the Wake up frame 2 pattern detection is disabled.
1
0
RW
WF1E
Wake up Frame 1 Enable
When set, it enables the Wake up frame 1 pattern detection.
When reset, the Wake up frame 1 pattern detection is disabled.
0
0
RW
WF0E
Wake up Frame 0 Enable
When set, it enables the Wake up frame 0 pattern detection.
When reset, the Wake up frame 0 pattern detection is disabled.
0x2C – 0x2F: Reserved
Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0
This register contains the expected CRC values of the Wake up frame 0 pattern.
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The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in
the wake up byte mask registers.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF0CRC0
Wake up Frame 0 CRC (lower 16 bits)
The expected CRC value of a Wake up frame 0 pattern.
Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1
This register contains the expected CRC values of the Wake up frame 0 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in
the wake up byte mask registers.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF0CRC1
Wake up Frame 0 CRC (upper 16 bits).
The expected CRC value of a Wake up frame 0 pattern.
Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0
This register contains the first 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the first byte
of the Wake up frame 0, setting bit 15 selects the 16th byte of the Wake up frame 0.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF0BM0
Wake up Frame 0 Byte Mask 0
The first 16 bytes mask of a Wake up frame 0 pattern.
Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1
This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 0. Setting bit 15 selects the 32nd byte of the Wake up frame 0.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF0BM1
Wake up Frame 0 Byte Mask 1.
The next 16 bytes mask covering bytes 17 to 32 of a Wake up frame 0 pattern.
Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2
This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 0. Setting bit 15 selects the 48th byte of the Wake up frame 0.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF0BM2
Wake-up Frame 0 Byte Mask 2.
The next 16 bytes mask covering bytes 33 to 48 of a Wake-up frame 0 pattern.
Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3
This register contains the last 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 0. Setting bit 15 selects the 64th byte of the Wake up frame 0.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF0BM3
Wake-up Frame 0 Byte Mask 3.
The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame 0 pattern.
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0x3C – 0x3F: Reserved
Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0
This register contains the expected CRC values of the Wake up frame 1 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in
the wake up byte mask registers.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF1CRC0
Wake-up frame 1 CRC (lower 16 bits).
The expected CRC value of a Wake-up frame 1 pattern.
Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1
This register contains the expected CRC values of the Wake up frame 1 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in
the wake up byte mask registers.
Bit
15-0
Default Value
0x0000
R/W
Description
RW
WF1CRC1
Wake-up frame 1 CRC (upper 16 bits).
The expected CRC value of a Wake-up frame 1 pattern.
Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0
This register contains the first 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the first byte
of the Wake up frame 1, setting bit 15 selects the 16th byte of the Wake up frame 1.
Bit
15-0
Default Value
0x0000
R/W
Description
RW
WF1BM0
Wake-up frame 1 Byte Mask 0.
The first 16 bytes mask of a Wake-up frame 1 pattern.
Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1
This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 1. Setting bit 15 selects the 32nd byte of the Wake up frame 1.
Bit
15-0
Default Value
0x0000
R/W
Description
RW
WF1BM1
Wake-up frame 1 Byte Mask 1.
The next 16 bytes mask covering bytes 17 to 32 of a Wake-up frame 1 pattern.
Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2
This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 1. Setting bit 15 selects the 48th byte of the Wake up frame 1.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF1BM2
Wake-up frame 1 Byte Mask 2.
The next 16 bytes mask covering bytes 33 to 48 of a Wake-up frame 1 pattern.
Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3
This register contains the last 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 1. Setting bit 15 selects the 64th byte of the Wake up frame 1.
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Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF1BM3
Wake-up frame 1 Byte Mask 3.
The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame 1 pattern.
0x4C – 0x4F: Reserved
Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0
This register contains the expected CRC values of the Wake up frame 2 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in
the wake up byte mask registers.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF2CRC0
Wake-up frame 2 CRC (lower 16 bits). The expected CRC value of a Wake-up frame 2
pattern.
Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1
This register contains the expected CRC values of the wake-up frame 2 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in
the wake up byte mask registers.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF2CRC1
Wake-up frame 2 CRC (upper 16 bits). The expected CRC value of a Wake-up frame 2
pattern.
Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0
This register contains the first 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the first byte
of the Wake up frame 2, setting bit 15 selects the 16th byte of the Wake up frame 2.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF2BM0
Wake-up frame 2 Byte Mask 0. The first 16 bytes mask of a Wake-up frame 2 pattern.
Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1
This register contains the next 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 2. Setting bit 15 selects the 32nd byte of the Wake up frame 2.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF2BM1
Wake-up frame 2 Byte Mask 1. The next 16 bytes mask covering bytes 17 to 32 of a
Wake-up frame 2 pattern.
Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2
This register contains the next 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 2. Setting bit 15 selects the 48th byte of the Wake up frame 2.
Bit
Default Value
R/W
Description
15-0
0
RW
WF2BM2
Wake-up frame 2 Byte Mask 2. The next 16 bytes mask covering bytes 33 to 48 of a
Wake-up frame 2 pattern.
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Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3
This register contains the last 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 2. Setting bit 15 selects the 64th byte of the Wake up frame 2.
Bit
Default Value
R/W
Description
15-0
0
RW
WF2BM3
Wake-up frame 2 Byte Mask 3. The last 16 bytes mask covering bytes 49 to 64 of a
Wake-up frame 2 pattern.
0x5C – 0x5F: Reserved
Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0
This register contains the expected CRC values of the Wake up frame 3 pattern. The value of the CRC calculated is
based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake-up byte mask registers.
Bit
Default Value
R/W
Description
15-0
0
RW
WF3CRC0
Wake-up frame 3 CRC (lower 16 bits). The expected CRC value of a Wake up frame 3
pattern.
Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1
This register contains the expected CRC values of the Wake up frame 3 pattern. The value of the CRC calculated is
based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in
the wake-up byte mask registers.
Bit
Default Value
R/W
Description
15-0
0
RW
WF3CRC1
Wake-up frame 3 CRC (upper 16 bits). The expected CRC value of a Wake up frame 3
pattern.
Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0
This register contains the first 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the first byte
of the Wake up frame 3, setting bit 15 selects the 16th byte of the Wake up frame 3.
Bit
Default Value
R/W
Description
15-0
0
RW
WF3BM0
Wake up Frame 3 Byte Mask 0. The first 16 byte mask of a Wake up frame 3 pattern.
Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1
This register contains the next 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 3. Setting bit 15 selects the 32nd byte of the Wake up frame 3.
Bit
15-0
Default Value
0
R/W
Description
RW
WF3BM1
Wake up Frame 3 Byte Mask 1. The next 16 bytes mask covering bytes 17 to 32 of a
Wake up frame 3 pattern.
Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2
This register contains the next 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 3. Setting bit 15 selects the 48th byte of the Wake up frame 3.
Bit
Default Value
R/W
Description
15-0
0
RW
WF3BM2
Wake up Frame 3 Byte Mask 2. The next 16 bytes mask covering bytes 33 to 48 of a
Wake up frame 3 pattern.
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Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3
This register contains the last 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 3. Setting bit 15 selects the 64th byte of the Wake up frame 3.
Bit
Default Value
R/W
Description
15-0
0
RW
WF3BM3
Wake up Frame 3 Byte Mask 3. The last 16 bytes mask covering bytes 49 to 64 of a
Wake up frame 3 pattern.
0x6C – 0x6F: Reserved
Transmit Control Register (0x70 – 0x71): TXCR
This register holds control information programmed by the CPU to control the QMU transmit module function.
Bit
Default Value
R/W
Description
15-9
-
RO
Reserved
8
0x0
RW
TCGICMP Transmit Checksum Generation for ICMP
When this bit is set, The KSZ8851SNL is enabled to transmit ICMP frame (only for nonfragment frame) checksum generation.
7
0x0
RO
Reserved
6
0x0
RW
TCGTCP Transmit Checksum Generation for TCP
When this bit is set, The KSZ8851SNL is enabled to transmit TCP frame checksum
generation.
5
0x0
RW
TCGIP Transmit Checksum Generation for IP
When this bit is set, The KSZ8851SNL is enabled to transmit IP header checksum
generation.
4
0x0
RW
FTXQ Flush Transmit Queue
When this bit is set, The transmit queue memory is cleared and TX frame pointer is reset.
Note: Disable the TXE transmit enable bit[0] first before set this bit, then clear this bit to
normal operation.
3
0x0
RW
TXFCE Transmit Flow Control Enable
When this bit is set and the KSZ8851SNL is in full-duplex mode, flow control is enabled.
The KSZ8851SNL transmits a PAUSE frame when the Receive Buffer capacity reaches a
threshold level that will cause the buffer to overflow.
When this bit is set and the KSZ8851SNL is in half-duplex mode, back-pressure flow
control is enabled. When this bit is cleared, no transmit flow control is enabled.
2
0x0
RW
TXPE Transmit Padding Enable
When this bit is set, the KSZ8851SNL automatically adds a padding field to a packet
shorter than 64 bytes.
Note: Setting this bit requires enabling the add CRC feature (bit1=1) to avoid CRC errors
for the transmit packet.
1
0x0
RW
TXCE Transmit CRC Enable
When this bit is set, the KSZ8851SNL automatically adds a 32-bit CRC checksum field to
the end of a transmit frame.
0
0x0
RW
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a running state. When
reset, the transmit process is placed in the stopped state after the transmission of the
current frame is completed.
Transmit Status Register (0x72 – 0x73): TXSR
This register keeps the status of the last transmitted frame.
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Bit
Default Value
R/W
Description
15-14
0x0
RO
Reserved
13
0x0
RO
TXLC Transmit Late Collision
This bit is set when a transmit Late Collision occurs.
12
0x0
RO
TXMC Transmit Maximum Collision
This bit is set when a transmit Maximum Collision is reached.
11-6
-
RO
Reserved
5-0
-
RO
TXFID Transmit Frame ID
This field identifies the transmitted frame. All of the transmit status information in this
register belongs to the frame with this ID.
Receive Control Register 1 (0x74 – 0x75): RXCR1
This register holds control information programmed by the CPU to control the receive function.
Bit
Default Value
R/W
Description
15
0x0
RW
FRXQ Flush Receive Queue
When this bit is set, The receive queue memory is cleared and RX frame pointer is reset.
Note: Disable the RXE receive enable bit[0] first before set this bit, then clear this bit to
normal operation.
14
0x0
RW
RXUDPFCC Receive UDP Frame Checksum Check Enable
When this bit is set, the KSZ8851SNL will check for correct UDP checksum for incoming
UDP frames. Any received UDP frames with incorrect checksum will be discarded.
13
0x0
RW
RXTCPFCC Receive TCP Frame Checksum Check Enable
When this bit is set, the KSZ8851SNL will check for correct TCP checksum for incoming
TCP frames. Any received TCP frames with incorrect checksum will be discarded.
12
0x0
RW
RXIPFCC Receive IP Frame Checksum Check Enable
When this bit is set, the KSZ8851SNL will check for correct IP header checksum for
incoming IP frames. Any received IP frames with incorrect checksum will be discarded.
11
0x1
RW
RXPAFMA Receive Physical Address Filtering with MAC Address Enable
When this bit is set, this bit enables the RX function to receive physical address that pass
the MAC address filtering mechanism (see Address Filtering Scheme in Table 3 for
detail).
10
0x0
RW
RXFCE Receive Flow Control Enable
When this bit is set and the KSZ8851SNL is in full-duplex mode, flow control is enabled,
and the KSZ8851SNL will acknowledge a PAUSE frame from the receive interface; i.e.,
the outgoing packets are pending in the transmit buffer until the PAUSE frame control
timer expires. This field has no meaning in half-duplex mode and should be programmed
to 0.
When this bit is cleared, flow control is not enabled.
9
0x0
RW
RXEFE Receive Error Frame Enable
When this bit is set, CRC error frames are allowed to be received into the RX queue.
When this bit is cleared, all CRC error frames are discarded.
8
0x0
RW
RXMAFMA Receive Multicast Address Filtering with MAC Address Enable
When this bit is set, this bit enables the RX function to receive multicast address that pass
the MAC address filtering mechanism (see Address Filtering Scheme in Table 3 for
detail).
7
0x0
RW
RXBE Receive Broadcast Enable
When this bit is set, the RX module receives all the broadcast frames.
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Bit
Default Value
R/W
Description
6
0x0
RW
RXME Receive Multicast Enable
When this bit is set, the RX module receives all the multicast frames (including broadcast
frames).
5
0x0
RW
RXUE Receive Unicast Enable
When this bit is set, the RX module receives unicast frames that match the 48-bit Station
MAC address of the module.
4
0x0
RW
RXAE Receive All Enable
When this bit is set, the KSZ8851SNL receives all incoming frames, regardless of the
frame’s destination address (see Address Filtering Scheme in Table 3 for detail).
3
0x0
RW
Reserved
2
0x0
RW
Reserved
1
0x0
RW
RXINVF Receive Inverse Filtering
When this bit is set, the KSZ8851SNL receives function with address check operation in
inverse filtering mode (see Address Filtering Scheme in Table 3 for detail).
0
0x0
RW
RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a running state.
When this bit is cleared, the receive process is placed in the stopped state upon
completing reception of the current frame.
Receive Control Register 2 (0x76 – 0x77): RXCR2
This register holds control information programmed by the CPU to control the receive function.
Bit
Default Value
R/W
Description
15-8
-
RO
Reserved
7-5
0x0
WO
SRDBL SPI Receive Data Burst Length
These three bits are used to define for SPI receive data burst length during DMA
operation from the host CPU to access RXQ frame buffer.
000: 4 Bytes data burst
001: 8 Bytes data burst
010: 16 Bytes data burst
011: 32 Bytes data burst
100: Single frame data burst
101-111: NA (reserved)
Note: It needs RXQ FIFO Read command byte before each data burst.
4
0x0
RW
IUFFP IPV4/IPV6/UDP Fragment Frame Pass
When this bit is set, the KSZ8851SNL will pass the checksum check at receive side for
IPv4/IPv6 UDP frame with fragment extension header.
When this bit is cleared, the KSZ8851SNL will perform checksum operation based on
configuration and doesn’t care whether it’s a fragment frame or not.
3
0x0
RW
RXIUFCEZ Receive IPV4/IPV6/UDP Frame Checksum Equal Zero
When this bit is set, the KSZ8851SNL will pass the filtering for Ipv4/IPV6 UDP frame with
UDP checksum equal to zero.
When this bit is cleared, the KSZ8851SNL will drop IPV4/IPV6 UDP packet with UDP
checksum equal to zero.
2
0x1
RW
UDPLFE UDP Lite Frame Enable
When this bit is set, the KSZ8851SNL will check the checksum at receive side and
generate the checksum at transmit side for UDP Lite frame.
When this bit is cleared, the KSZ8851SNL will pass the checksum check at receive side
and skip the checksum generation at transmit side for UDP Lite frame.
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Bit
Default Value
R/W
Description
1
0x0
RW
RXICMPFCC Receive ICMP Frame Checksum Check Enable
When this bit is set, the KSZ8851SNL will check for correct ICMP checksum for incoming
ICMP frames (only for non-fragment frame). Any received ICMP frames with incorrect
checksum will be discarded.
0
0x0
RW
RXSAF Receive Source Address Filtering
When this bit is set, the KSZ8851SNL will drop the frame if the source address is same as
MAC address in MARL, MARM, MARH registers.
TXQ Memory Information Register (0x78 – 0x79): TXMIR
This register indicates the amount of free memory available in the TXQ of the QMU module.
Bit
Default Value
R/W
Description
15-13
-
RO
Reserved
12-0
-
RO
TXMA Transmit Memory Available
The amount of memory available is represented in units of byte. The TXQ memory is
used for both frame payload, control word.
Note: Software must be written to ensure that there is enough memory for the next
transmit frame including control information before transmit data is written to the TXQ.
0x7A – 0x7B: Reserved
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR
This register indicates the received frame header status information, the received frames are reported in RXFCTR
register. This register contains the status information for the frame received and the CPU can read so many times same
as the frame count value in the RXFCTR.
Bit
Default Value
R/W
Description
15
-
RO
RXFV Receive Frame Valid
When this bit is set, it indicates that the present frame in the receive packet memory is
valid. The status information currently in this location is also valid.
When clear, it indicates that there is either no pending receive frame or that the current
frame is still in the process of receiving.
14
-
RO
Reserved
13
-
RO
RXICMPFCS Receive ICMP Frame Checksum Status
When this bit is set, the KSZ8851SNL received ICMP frame checksum field is incorrect.
12
-
RO
RXIPFCS Receive IP Frame Checksum Status
When this bit is set, the KSZ8851SNL received IP header checksum field is incorrect.
11
-
RO
RXTCPFCS Receive TCP Frame Checksum Status
When this bit is set, the KSZ8851SNL received TCP frame checksum field is incorrect.
10
-
RO
RXUDPFCS Receive UDP Frame Checksum Status
When this bit is set, the KSZ8851SNL received UDP frame checksum field is incorrect.
9-8
-
RO
Reserved
7
-
RO
RXBF Receive Broadcast Frame
When this bit is set, it indicates that this frame has a broadcast address.
6
-
RO
RXMF Receive Multicast Frame
When this bit is set, it indicates that this frame has a multicast address (including the
broadcast address).
5
-
RO
RXUF Receive Unicast Frame
When this bit is set, it indicates that this frame has a unicast address.
4
-
RO
RXMR Receive MII Error
When set, it indicates that there is an MII symbol error on the received frame.
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Bit
Default Value
R/W
Description
3
-
RO
RXFT Receive Frame Type
When this bit is set, it indicates that the frame is an Ethernet-type frame (frame length is
greater than 1500 bytes). When clear, it indicates that the frame is an IEEE 802.3 frame.
2
-
RO
This bit is not valid for runt frames.
RXFTL Receive Frame Too Long
When this bit is set, it indicates that the frame length exceeds the maximum size of 2000
bytes. Frames that are too long are passed to the host only if the pass bad frame bit is
set.
Note: Frame too long is only a frame length indication and does not cause any frame
truncation.
1
-
RO
0
-
RO
RXRF Receive Runt Frame
When this bit is set, it indicates that a frame was damaged by a collision or had a
premature termination before the collision window passed.
Runt frames are passed to the host only if the pass bad frame bit is set.
RXCE Receive CRC Error
When this bit is set, it indicates that a CRC error has occurred on the current received
frame.
CRC error frames are passed to the host only if the pass bad frame bit is set.
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR
This register indicates the received frame header byte count information, the received frames are reported in RXFCTR
register. This register contains the total number of bytes information for the frame received and the CPU can read so
many times same as the frame count value in the RXFCTR.
Bit
Default Value
R/W
Description
15-12
-
RO
Reserved
11-0
-
RO
RXBC Receive Byte Count
This field indicates the present received frame byte size.
TXQ Command Register (0x80 – 0x81): TXQCR
This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in
the TXQ memory is queued for transmit.
Bit
Default Value
R/W
Description
15-3
-
RW
Reserved
2
0x0
RW
AETFE Auto-Enqueue TXQ Frame Enable
When this bit is written as 1, the KSZ8851SNL will enable current all TX frames prepared
in the TX buffer are queued to transmit automatically.
The bit 0 METFE has to be set 0 when this bit is set to 1 in this register.
1
0x0
RW
0
0x0
RW
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TXQMAM TXQ Memory Available Monitor
When this bit is written as 1, the KSZ8851SNL will generate interrupt (bit 6 in ISR register)
to CPU when TXQ memory is available based upon the total amount of TXQ space
requested by CPU at TXNTFSR (0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should
wait for the bit to be cleared before set to 1 again.
METFE Manual Enqueue TXQ Frame Enable
When this bit is written as 1, the KSZ8851SNL will enable current TX frame prepared in
the TX buffer is queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should
wait for the bit to be cleared before setting up another new TX frame.
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RXQ Command Register (0x82 – 0x83): RXQCR
This register is programmed by the Host CPU to issue DMA read or write command to the RXQ and TXQ. This register
also is used to control all RX thresholds enable and status.
Bit
Default Value
R/W
Description
15-13
-
RW
Reserved
12
-
RO
RXDTTS RX Duration Timer Threshold Status
When this bit is set, it indicates that RX interrupt is due to the time start at first received
frame in RXQ buffer exceeds the threshold set in RX Duration Timer Threshold Register
(0x8C, RXDTT).
This bit will be updated when write 1 to bit 13 in ISR register.
11
-
RO
RXDBCTS RX Data Byte Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received bytes in
RXQ buffer exceeds the threshold set in RX Data Byte Count Threshold Register (0x8E,
RXDBCT).
This bit will be updated when write 1 to bit 13 in ISR register.
10
-
RO
RXFCTS RX Frame Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received frames
in RXQ buffer exceeds the threshold set in RX Frame Count Threshold Register (0x9C,
RXFCT).
This bit will be updated when write 1 to bit 13 in ISR register.
9
0x0
RW
RXIPHTOE RX IP Header Two-Byte Offset Enable
When this bit is written as 1, the KSZ8851SNL will enable to add two bytes before frame
header in order for IP header inside the frame contents to be aligned with double word
boundary to speed up software operation.
8
-
RW
Reserved
7
0x0
RW
RXDTTE RX Duration Timer Threshold Enable
When this bit is written as 1, the KSZ8851SNL will enable RX interrupt (bit 13 in ISR)
when the time start at first received frame in RXQ buffer exceeds the threshold set in RX
Duration Timer Threshold Register (0x8C, RXDTT).
6
0x0
RW
RXDBCTE RX Data Byte Count Threshold Enable
When this bit is written as 1, the KSZ8851SNL will enable RX interrupt (bit 13 in ISR)
when the number of received bytes in RXQ buffer exceeds the threshold set in RX Data
Byte Count Threshold Register (0x8E, RXDBCT).
5
0x0
RW
RXFCTE RX Frame Count Threshold Enable
When this bit is written as 1, the KSZ8851SNL will enable RX interrupt (bit 13 in ISR)
when the number of received frames in RXQ buffer exceeds the threshold set in RX
Frame Count Threshold Register (0x9C, RXFCT).
4
0x0
RW
ADRFE Auto-Dequeue RXQ Frame Enable
When this bit is written as 1, the KSZ8851SNL will automatically enable RXQ frame buffer
dequeue. The read pointer in RXQ frame buffer will be automatically adjusted to next
received frame location after current frame is completely read by the host.
3
0x0
WO
SDA Start DMA Access
When this bit is written as 1, the KSZ8851SNL allows a DMA operation from the host
CPU to access either read RXQ frame buffer or write TXQ frame buffer with SPI
command operation for RXQ/TXQ FIFO read/write (see Table 5). All registers access are
disabled except this register during this DMA operation.
This bit must be set to 0 when DMA operation is finished in order to access the rest of
registers.
2-1
-
August 2009
RW
Reserved
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Bit
Default Value
R/W
Description
0
0x0
RW
RRXEF Release RX Error Frame
When this bit is written as 1, the current RX error frame buffer is released.
Note: This bit is self-clearing after the frame memory is released. The software should
wait for
the bit to be cleared before processing new RX frame.
TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR
The value of this register determines the address to be accessed within the TXQ frame buffer. When the AUTO increment
is set, It will automatically increment the pointer value on write accesses to the data register.
The counter is incremented by one for every byte access, by two for every word access, and by four for every double
word access.
Bit
Default Value
R/W
Description
15
-
RO
Reserved
14
0x0
RW
TXFPAI TX Frame Data Pointer Auto Increment
When this bit is set, the TX Frame data pointer register increments automatically on
accesses to the data register. The increment is by one for every byte access, by two for
every word access, and by four for every doubleword access.
When this bit is reset, the TX frame data pointer is manually controlled by user to access
the TX frame location.
13-11
-
RO
Reserved
10-0
0x000
RO
TXFP TX Frame Pointer
TX Frame Pointer index to the Frame Data register for access.
This field reset to next available TX frame location when the TX Frame Data has been
enqueued through the TXQ command register.
RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR
The value of this register determines the address to be accessed within the RXQ frame buffer. When the Auto Increment
is set, it will automatically increment the RXQ Pointer on read accesses to the data register.
The counter is incremented is by one for every byte access, by two for every word access, and by four for every double
word access.
Bit
Default Value
R/W
Description
15
-
RO
Reserved
14
0x0
RW
RXFPAI RX Frame Pointer Auto Increment
When this bit is set, the RXQ Address register increments automatically on accesses to
the data register. The increment is by one for every byte access, by two for every word
access, and by four for every double word access.
When this bit is reset, the RX frame data pointer is manually controlled by user to access
the RX frame location.
13-11
-
RO
Reserved
10-0
0x000
WO
RXFP RX Frame Pointer
RX Frame data pointer index to the Data register for access.
This pointer value must reset to 0x000 before each DMA operation from the host CPU to
read RXQ frame buffer.
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0x88 – 0x8B: Reserved
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR
This register is used to program the received frame duration timer threshold.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
RXDTT Receive Duration Timer Threshold
To program received frame duration timer threshold value in 1us interval. The maximum value is
0xCFFF.
When bit 7 set to 1 in RXQCR register, the KSZ8851SNL will set RX interrupt (bit 13 in ISR) after
the time starts at first received frame in RXQ buffer and exceeds the threshold set in this register.
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR
This register is used to program the received data byte count threshold.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
RXDBCT Receive Data Byte Count Threshold
To program received data byte threshold value in byte count.
When bit 6 set to 1 in RXQCR register, the KSZ8851SNL will set RX interrupt (bit 13 in ISR)
when the number of received bytes in RXQ buffer exceeds the threshold set in this register.
Interrupt Enable Register (0x90 – 0x91): IER
This register enables the interrupts from the QMU and other sources.
Bit
Default Value
R/W
Description
15
0x0
RW
LCIE Link Change Interrupt Enable
When this bit is set, the link change interrupt is enabled.
When this bit is reset, the link change interrupt is disabled.
14
0x0
RW
TXIE Transmit Interrupt Enable
When this bit is set, the transmit interrupt is enabled.
When this bit is reset, the transmit interrupt is disabled.
13
0x0
RW
RXIE Receive Interrupt Enable
When this bit is set, the receive interrupt is enabled.
When this bit is reset, the receive interrupt is disabled.
12
0x0
RW
Reserved
11
0x0
RW
RXOIE Receive Overrun Interrupt Enable
When this bit is set, the Receive Overrun interrupt is enabled.
When this bit is reset, the Receive Overrun interrupt is disabled.
10
0x0
RW
Reserved
9
0x0
RW
TXPSIE Transmit Process Stopped Interrupt Enable
When this bit is set, the Transmit Process Stopped interrupt is enabled.
When this bit is reset, the Transmit Process Stopped interrupt is disabled.
8
0x0
RW
RXPSIE Receive Process Stopped Interrupt Enable
When this bit is set, the Receive Process Stopped interrupt is enabled.
When this bit is reset, the Receive Process Stopped interrupt is disabled.
7
0x0
RW
Reserved
6
0x0
RW
TXSAIE Transmit Space Available Interrupt Enable
When this bit is set, the Transmit memory space available interrupt is enabled.
When this bit is reset, the Transmit memory space available interrupt is disabled.
5
0x0
RW
RXWFDIE Receive Wake-up Frame Detect Interrupt Enable
When this bit is set, the Receive wakeup frame detect interrupt is enabled.
When this bit is reset, the Receive wakeup frame detect interrupt is disabled.
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Bit
Default Value
R/W
Description
4
0x0
RW
RXMPDIE Receive Magic Packet Detect Interrupt Enable
When this bit is set, the Receive magic packet detect interrupt is enabled.
When this bit is reset, the Receive magic packet detect interrupt is disabled.
3
0x0
RW
LDIE Linkup Detect Interrupt Enable
When this bit is set, the wake-up from linkup detect interrupt is enabled.
When this bit is reset, the linkup detect interrupt is disabled.
2
0x0
RW
EDIE Energy Detect Interrupt Enable
When this bit is set, the wake-up from energy detect interrupt is enabled.
When this bit is reset, the energy detect interrupt is disabled.
1
0x0
RW
SPIBEIE SPI Bus Error Interrupt Enable
When this bit is set, the SPI bus error interrupt is enabled.
When this bit is reset, the SPI bus error interrupt is disabled.
0
0x0
RW
DEDIE Delay Energy Detect Interrupt Enable
When this bit is set, the delay energy detect interrupt is enabled.
When this bit is reset, the delay energy detect interrupt is disabled.
Note: the delay energy detect interrupt till device is ready for host access.
Interrupt Status Register (0x92 – 0x93): ISR
This register contains the status bits for all QMU and other interrupt sources.
When the corresponding enable bit is set, it causes the interrupt pin to be asserted.
This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register
bits are not cleared when read. The user has to write “1” to clear.
Bit
Default Value
R/W
Description
15
0x0
RO
(W1C)
LCIS Link Change Interrupt Status
When this bit is set, it indicates that the link status has changed from link up to link down,
or link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
14
0x0
RO
(W1C)
TXIS Transmit Interrupt Status
When this bit is set, it indicates that the TXQ MAC has transmitted at least a frame on the
MAC interface and the QMU TXQ is ready for new frames from the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
13
0x0
RO
(W1C)
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has received at least a frame from the
MAC interface and the frame is ready for the host CPU to process.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
12
0x0
RO
Reserved
11
0x0
RO
(W1C)
RXOIS Receive Overrun Interrupt Status
When this bit is set, it indicates that the Receive Overrun status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
10
0x0
RO
Reserved
9
0x1
RO
(W1C)
TXPSIS Transmit Process Stopped Interrupt Status
When this bit is set, it indicates that the Transmit Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
8
0x1
RO
(W1C)
RXPSIS Receive Process Stopped Interrupt Status
When this bit is set, it indicates that the Receive Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
7
0x0
RO
Reserved
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Bit
Default Value
R/W
Description
6
0x0
RO
(W1C)
TXSAIS Transmit Space Available Interrupt Status
When this bit is set, it indicates that Transmit memory space available status has
occurred.
When this bit is reset, the Transmit memory space available interrupt is disabled.
5
0x0
RO
RXWFDIS Receive Wakeup Frame Detect Interrupt Status
When this bit is set, it indicates that Receive wakeup frame detect status has occurred.
Write “1000” to PMECR[5:2] to clear this bit
4
0x0
RO
RXMPDIS Receive Magic Packet Detect Interrupt Status
When this bit is set, it indicates that Receive magic packet detect status has occurred.
Write “0100” to PMECR[5:2] to clear this bit.
3
0x0
RO
LDIS Linkup Detect Interrupt Status
When this bit is set, it indicates that wake-up from linkup detect status has occurred.
Write “0010” to PMECR[5:2] to clear this bit.
2
0x0
RO
EDIS Energy Detect Interrupt Status
When this bit is set and bit 2=1, bit 0=0 in IER register, it indicates that wake-up from
energy detect status has occurred. When this bit is set and bit 2, 0=1 in IER register, it
indicates that wake-up from delay energy detect status has occurred.
Write “0001” to PMECR[5:2] to clear this bit.
1
0x0
RO
(W1C)
SPIBEIS SPI Bus Error Interrupt Status
When this bit is set, it indicates that SPI bus error status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
0
0x0
RO
Reserved
0x94 – 0x9B: Reserved
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR
This register indicates the current total amount of received frame count in RXQ frame buffer and also is used to program
the received frame count threshold.
Bit
Default Value
R/W
Description
15-8
0x00
RO
RXFC RX Frame Count
To indicate the total received frames in RXQ frame buffer when receive interrupt (bit13=1
in ISR) occurred and write “1” to clear this bit 13 in ISR. The host CPU can start to read
the updated receive frame header information in RXFHSR/RXFHBCR registers after read
this RX frame count register.
7-0
0x00
RW
RXFCT Receive Frame Count Threshold
To program received frame count threshold value.
When bit 5 set to 1 in RXQCR register, the KSZ8851SNL will set RX interrupt (bit 13 in
ISR) when the number of received frames in RXQ buffer exceeds the threshold set in this
register.
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR
This register is used by the host CPU to program the total amount of TXQ buffer space requested for the next transmit.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
TXNTFS TX Next Total Frames Size
The host CPU is used to program the total amount of TXQ buffer space which is required
for next total transmit frames size in double-word count.
When bit 1 (TXQ memory available monitor) is set to 1 in TXQCR register, the
KSZ8851SNL will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is
available based upon the total amount of TXQ space requested by CPU at this register.
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MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0
The 64-bit MAC address table is used for group address filtering and it is enabled by selecting item 5 “Hash perfect” mode
in Table 3 (Address Filtering Scheme). This value is defined as the six most significant bits from CRC circuit calculation
result that is based on 48-bit of DA input. The two most significant bits select one of the four registers to be used, while
the others determine which bit within the register.
Multicast table register 0.
Bit
Default Value
R/W
Description
15-0
0x0
RW
HT0 Hash Table 0
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1
Multicast table register 1.
Bit
Default Value
R/W
Description
15-0
0x0
RW
HT1 Hash Table 1
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1,
all multicast addresses are received regardless of the multicast table value.
MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2
Multicast table register 2.
Bit
Default Value
R/W
Description
15-0
0x0
RW
HT2 Hash Table 2
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1,
all multicast addresses are received regardless of the multicast table value.
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3
Multicast table register 3.
Bit
Default Value
R/W
Description
15-0
0x0
RW
HT3 Hash Table 3
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1,
all multicast addresses are received regardless of the multicast table value.
0xA8 – 0xAF: Reserved
Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR
This register is used to control the flow control for low watermark in QMU RX queue.
Bit
Default Value
R/W
Description
15-12
-
RW
Reserved
11-0
0x0500
RW
FCLWC Flow Control Low Watermark Configuration
These bits are used to define the QMU RX queue low watermark configuration. It is in
double words count and default is 5.12 KByte available buffer space out of 12 KByte.
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Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR
This register is used to control the flow control for high watermark in QMU RX queue.
Bit
Default Value
R/W
Description
15-12
-
RW
Reserved
11-0
0x0300
RW
FCHWC Flow Control High Watermark Configuration
These bits are used to define the QMU RX queue high watermark configuration. It is in
double words count and default is 3.072 KByte available buffer space out of 12 KByte.
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR
This register is used to control the flow control for overrun watermark in QMU RX queue
Bit
Default Value
R/W
Description
15-12
-
RW
Reserved
11-0
0x0040
RW
FCLWC Flow Control Overrun Watermark Configuration
These bits are used to define the QMU RX queue overrun watermark configuration. It is in
double words count and default is 256 Bytes available buffer space out of 12 Kbyte.
0xB6 – 0xBF: Reserved
Chip ID and Enable Register (0xC0 – 0xC1): CIDER
This register contains the chip ID and the chip enable bit.
Bit
Default
R/W
Description
15-8
0x88
RO
Family ID
Chip family ID
7-4
0x7
RO
Chip ID
0x7 is assigned to KSZ8851SNL
3-1
0x1
RO
Revision ID
0
0x0
RW
Reserved
0xC2 – 0xC5: Reserved
Chip Global Control Register (0xC6 – 0xC7): CGCR
This register contains the global control for the chip function.
Bit
Default
R/W
Description
15-12
0x0
RW
Reserved
11-10
0x2
RW
Reserved
9
0x0
RW
LEDSEL0
This bit sets the LEDSEL0 selection for LED1 and LED0.
PHY port LED indicators, defined as below:
LED1 (pin32)
LED0 (pin1)
8
0x0
R/W
Reserved
7-0
0x35
RW
Reserved
LEDSEL0
0
1
100BT
ACT
LINK/ACT
LINK
Indirect Access Control Register (0xC8 – 0xC9): IACR
This register contains the indirect control for the MIB counter (Write IACR triggers a command. Read access is
determined by bit 12).
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Bit
Default
R/W
Description
15-13
0x0
RW
Reserved.
12
0x0
RW
Read Enable
1 = Read cycle is enabled (MIB counter will clear after read).
0 = No operation.
11-10
0x0
RW
Table Select
00 = reserved.
01 = reserved.
10 = reserved.
11 = MIB counter selected.
9-5
-
RW
Reserved
4-0
0x00
RW
Indirect Address
Bit 4-0 of indirect address for 32 MIB counter locations.
0xCA – 0xCF: Reserved
Indirect Access Data Low Register (0xD0 – 0xD1): IADLR
This register contains the indirect data (low word) for MIB counter.
Bit
Default
R/W
Description
15-0
0x0000
RW
Indirect Low Word Data
Bit 15-0 of indirect data.
Indirect Access Data High Register (0xD2 – 0xD3): IADHR
This register contains the indirect data (high word) for MIB counter.
Bit
Default
R/W
Description
15-0
0x0000
RW
Indirect High Word Data
Bit 31-16 of indirect data.
Power Management Event Control Register (0xD4 – 0xD5): PMECR
This register is used to control the KSZ8851SNL power management event, capabilities and status.
Bit
Default Value
R/W
Description
15
-
RO
Reserved
14
0
RW
PME Delay Enable
This bit is used to enable the delay of PME output pin 2 assertion.
When this bit is set to 1, the device will not assert the PME output till the device’s all
clocks are running and ready for host access.
When this bit is set to 0, the device will assert the PME output without delay.
This bit is only valid when Auto Wake-Up Enable (bit7) is set to 1 in this register.
13
0
RW
Reserved
12
0
RW
PME Output Polarity
This bit is used to control the PME output pin 2 polarity.
When this bit is set to 1, the PME output pin 2 is active high.
When this bit is set to 0, the PME output pin 2 is active low.
11-8
0x0
RW
Wake-on-LAN to PME Output Enable
These four bits are used to enable the PME output pin 2 asserted when one of these
wake-on-LAN events is detected:
Bit 11: is corresponding to receive wake-up frame.
Bit 10: is corresponding to receive magic packet.
Bit 9: is corresponding to link change from down to up.
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Bit
Default Value
R/W
Description
Bit 8: is corresponding to signal energy detected.
When the bit is set to 1, the PME pin 2 will be asserted when a corresponding wake-onLAN event is occurred.
When this bit is set to 0, the PME pin 2 will be not asserted when a corresponding wakeon-LAN event is occurred.
7
0
RW
6
0
RW
Auto Wake-Up Enable
This bit is used to enable automatically wake-up from low power state to normal power
state in energy detect mode if carrier (signal energy) is present more than wake-up time in
GSWUTR register. During the normal power state, the device can receive and transmit
packets.
When this bit is set to 1, the auto wake-up is enabled in energy detect mode.
When this bit is set to 0, the auto wake-up is disabled in energy detect mode.
Wake-Up to Normal Operation Mode
This bit is used to control the device wake-up from low power state in energy detect mode
to normal operation mode if signal energy is detected longer than the programmed wakeup time in GSWUTR register.
When this bit is set to 1, the device will automatically go to the normal operation mode
from energy detect mode.
When this bit is set to 0, the device will not automatically go to the normal mode from
energy detect mode.
This bit is only valid when Auto Wake-Up Enable (bit7) is set to 1.
5-2
0x0
RO
(W1C)
1-0
0x0
RW
Wake-Up Event Indication
These four bits are used to indicate the KSZ8851SNL wake-up event status as below:
0000: No wake-up event.
0001: Wake-up from energy event detected. (Bit 2 also set to 1 in ISR register)
0010: Wake-up from link up event detected. (Bit 3 also set to 1 in ISR register)
0100: Wake-up from magic packet event detected.
1000: Wake-up from wakeup frame event detected.
If Wake-on-LAN to PME Output Enable bit[11:8] are set, the KSZ8851SNL also asserts
the PME pin 2. These bits are cleared on power up reset or by write 1. It is not modified
by either hardware or software reset. When these bits are cleared, the KSZ8851SNL deasserts the PME pin.
Power Management Mode
These two bits are used to control the KSZ8851SNL power management mode as below:
00: Normal Operation Mode.
01: Energy Detect Mode. (two states in this mode either low power or normal power)
10: Soft Power Down Mode.
11: Power Saving Mode.
In energy detect mode under low power state, it can wake-up to normal operation mode
either from line or host wake-up (host CPU issues any one of registers read or write
access).
In soft power down mode, it can wake-up to normal operation mode only from host wakeup (host CPU issues any one of registers read or write access).
Go-Sleep & Wake-Up Time Register (0xD6 – 0xD7): GSWUTR
This register contains the value which is used to control minimum Go-Sleep time period when the device from normal
power state to low power state or to control minimum Wake-Up time period when the device from low power state to
normal power state in energy detect mode.
Bit
Default
R/W
Description
15-8
0x08
RW
Wake-up Time
This value is used to control the minimum period that the energy has to be detected
consecutively before the device is waked-up from the low power state. The unit is 16ms
+/-80%, the default wake-up time is 128 ms (16ms x 8). Zero time (0x00) is not allowed
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Bit
Default
R/W
Description
7-0
0x0C
RW
Go-sleep Time
This value is used to control the minimum period that the no energy event has to be
detected consecutively before the device enters the low power state when the energy
detect mode is on. The unit is 1 sec +/-80%, the default go-sleep time is 12 sec (1s x 12).
Zero time (0x00) is not allowed.
PHY Reset Register (0xD8 – 0xD9): PHYRR
This register contains a control bit to reset PHY block when write an “1”.
Bit
Default
R/W
Description
15-1
-
RW
Reserved.
0
0
WO
PHY Reset Bit
(Self
clear)
This bit is write only and self clear after write an “1”, it is used to reset PHY block circuitry.
0xDA – 0xDF: Reserved
0xE0 – 0xE3: Reserved
PHY 1 MII-Register Basic Control Register (0xE4 – 0xE5): P1MBCR
This register contains Media Independent Interface (MII) register for port 1 as defined in the IEEE 802.3 specification.
Bit
Default
R/W
Description
Bit is same as:
15
0
RO
Reserved
14
0
RW
Local (far-end) loopback (llb)
1 = perform local loopback at host
(host SPI Tx -> PHY -> host SPI Rx,
see Figure 14)
0 = normal operation
13
1
RW
Force 100
1 = force 100Mbps if AN is disabled (bit 12)
0 = force 10Mbps if AN is disabled (bit 12)
Bit 6 in P1CR
12
1
RW
AN Enable
1 = auto-negotiation enabled.
0 = auto-negotiation disabled.
Bit 7 in P1CR
11-10
0
RW
Reserved
9
0
RW
Restart AN
1 = restart auto-negotiation.
0 = normal operation.
Bit 13 in P1CR
8
1
RW
Force Full Duplex
1 = force full duplex
0 = force half duplex.
if AN is disabled (bit 12) or AN is enabled but failed.
Reserved
Bit 5 in P1CR
7-6
0
RO
5
1
R/W
HP_mdix
1 = HP Auto MDI-X mode.
0 = Micrel Auto MDI-X mode.
Bit 15 in P1SR
4
0
RW
Force MDI-X
1 = force MDI-X.
0 = normal operation.
Bit 9 in P1CR
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Bit
Default
R/W
Description
Bit is same as:
3
0
RW
Disable MDI-X
1 = disable auto MDI-X.
0 = normal operation.
Bit 10 in P1CR
2
0
RW
Reserved.
1
0
RW
Disable Transmit
1 = disable transmit.
0 = normal operation.
Bit 14 in P1CR
0
0
RW
Disable LED
1 = disable all LEDs.
0 = normal operation.
Bit 15 in P1CR
PHY 1 MII-Register Basic Status Register (0xE6 – 0xE7): P1MBSR
This register contains the MII register status for the chip function.
Bit
Default
R/W
Description
15
0
RO
T4 Capable
1 = 100 BASE-T4 capable.
0 = not 100 BASE-T4 capable.
14
1
RO
100 Full Capable
1 = 100BASE-TX full-duplex capable.
0 = not 100BASE-TX full duplex.capable.
13
1
RO
100 Half Capable
1= 100BASE-TX half-duplex capable.
0= not 100BASE-TX half-duplex capable.
12
1
RO
10 Full Capable
1 = 10BASE-T full-duplex capable.
0 = not 10BASE-T full-duplex capable.
11
1
RO
10 Half Capable
1 = 10BASE-T half-duplex capable.
0 = not 10BASE-T half-duplex capable.
10-7
0x0
RO
Reserved.
6
0
RO
Preamble suppressed
Not supported.
5
0
RO
AN Complete
1 = auto-negotiation complete.
0 = auto-negotiation not completed.
4
0
RO
Reserved
3
1
RO
AN Capable
1 = auto-negotiation capable.
0 = not auto-negotiation capable.
2
0
RO
Link Status
1 = link is up; 0 = link is down.
1
0
RO
Jabber test
Not supported.
0
0
RO
Extended Capable
1 = extended register capable.
0 = not extended register capable.
August 2009
Bit is same as:
63
Bit 6 in P1SR
Bit 5 in P1SR
M9999-083109-2.0
Micrel, Inc.
KSZ8851SNL/SNLI
PHY 1 PHY ID Low Register (0xE8 – 0xE9): PHY1ILR
This register contains the PHY ID (low) for the chip.
Bit
Default
R/W
Description
15-0
0x1430
RO
PHYID Low
Low order PHYID bits.
PHY 1 PHY ID High Register (0xEA – 0xEB): PHY1IHR
This register contains the PHY ID (high) for the chip.
Bit
Default
R/W
Description
15-0
0x0022
RO
PHYID High
High order PHYID bits.
PHY 1 Auto-Negotiation Advertisement Register (0xEC – 0xED): P1ANAR
This register contains the auto-negotiation advertisement for the PHY function.
Bit
Default
R/W
Description
Bit is same as:
15
0
RO
Next page
Not supported.
14
0
RO
Reserved
13
0
RO
Remote fault
Not supported.
12-11
0x0
RO
Reserved
10
1
RW
Pause (flow control capability)
1 = advertise pause capability.
0 = do not advertise pause capability.
9
0
RW
Reserved.
8
1
RW
Adv 100 Full
1 = advertise 100 full-duplex capability.
0 = do not advertise 100 full-duplex capability
Bit 3 in P1CR
7
1
RW
Adv 100 Half
1= advertise 100 half-duplex capability.
0 = do not advertise 100 half-duplex capability.
Bit 2 in P1CR
6
1
RW
Adv 10 Full
1 = advertise 10 full-duplex capability.
0 = do not advertise 10 full-duplex capability.
Bit 1 in P1CR
5
1
RW
Adv 10 Half
1 = advertise 10 half-duplex capability.
0 = do not advertise 10 half-duplex capability.
Bit 0 in P1CR
4-0
0x01
RO
Selector Field
802.3
Bit 4 in P1CR
PHY 1 Auto-Negotiation Link Partner Ability Register (0xEE – 0xEF): P1ANLPR
This register contains the auto-negotiation link partner ability for the chip function.
Bit
Default
R/W
Description
15
0
RO
Next page
Not supported.
14
0
RO
LP ACK
Not supported.
August 2009
Bit is same as:
64
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KSZ8851SNL/SNLI
Bit
Default
R/W
Description
Bit is same as:
13
0
RO
Remote fault
Not supported.
12-11
0x0
RO
Reserved
10
0
RO
Pause
Link partner pause capability.
9
0
RO
Reserved.
8
0
RO
Adv 100 Full
Link partner 100 full capability.
Bit 3 in P1SR
7
0
RO
Adv 100 Half
Link partner 100 half capability.
Bit 2 in P1SR
6
0
RO
Adv 10 Full
Link partner 10 full capability.
Bit 1 in P1SR
5
0
RO
Adv 10 Half
Link partner 10 half capability.
Bit 0 in P1SR
4-0
0x01
RO
Reserved
Bit 4 in P1SR
0xF0 – 0xF3: Reserved
Port 1 PHY Special Control/Status, LinkMD (0xF4 – 0xF5): P1SCLMD
This register contains the special control, status and LinkMD information of PHY1.
Bit
Default
R/W
Description
15
0
RO
Reserved
14-13
0x0
RO
Vct_result
Bit is same as:
VCT result.
[00] = normal condition.
[01] = open condition has been detected in cable.
[10] = short condition has been detected in cable.
[11] = cable diagnostic test is failed.
12
0
RW
Vct_en
(SelfClear)
Vct enable.
1 = the cable diagnostic test is enabled. It is self-cleared
after the VCT test is done.
0 = it indicates the cable diagnostic test is completed and
the status information is valid for read.
11
0
RW
Force_lnk
Force link.
1 = force link pass; 0 = normal operation.
10
0
RO
Reserved
9
0
RW
Remote (Near-end) loopback (rlb)
1 = perform remote loopback at PHY (RXP/RXM ->
TXP/TXM, see Figure 14)
0 = normal operation
8-0
0x000
RO
Vct_fault_count
VCT fault count.
Distance to the fault. It’s approximately
0.4m*vct_fault_count.
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Port 1 Control Register (0xF6 – 0xF7): P1CR
This register contains the global per port control for the chip function.
Bit
Default
R/W
Description
Bit is same as:
15
0
RW
LED Off
Bit 0 in P1MBCR
1 = Turn off all of the port 1 LEDs (P1LED3, P1LED2,
P1LED1, P1LED0). These pins are driven high if this bit is
set to one.
0 = normal operation.
14
0
RW
Txids
Bit 1 in P1MBCR
1 = disable the port’s transmitter.
0 = normal operation.
13
0
RW
Restart AN
1 = restart auto-negotiation.
0 = normal operation.
12
0
RW
Reserved
11
0
RW
Reserved
10
0
RW
Disable auto MDI/MDI-X
1 = disable auto MDI/MDI-X function.
0 = enable auto MDI/MDI-X function.
Bit 3 in P1MBCR
9
0
RW
Force MDI-X
1= if auto MDI/MDI-X is disabled, force PHY into MDI-X
mode.
0 = do not force PHY into MDI-X mode.
Bit 4 in P1MBCR
8
0
RW
Reserved
7
1
RW
Auto Negotiation Enable
1 = auto negotiation is enabled.
0 = disable auto negotiation, speed, and duplex are decided
by bits 6 and 5 of the same register.
Bit 12 in P1MBCR
6
1
RW
Force Speed
1 = force 100BT if AN is disabled (bit 7).
0 = force 10BT if AN is disabled (bit 7).
Bit 13 in P1MBCR
5
1
RW
Force Duplex
1 = force full duplex if (1) AN is disabled or (2) AN is
enabled but failed.
0 = force half duplex if (1) AN is disabled or (2) AN is
enabled but failed.
Bit 8 in P1MBCR
4
1
RW
Advertised flow control capability.
1 = advertise flow control (pause) capability.
0 = suppress flow control (pause) capability from
transmission to link partner.
Bit 10 in P1ANAR
3
1
RW
Advertised 100BT full-duplex capability.
Bit 8 in P1ANAR
Bit 9 in P1MBCR
1 = advertise 100BT full-duplex capability.
0 = suppress 100BT full-duplex capability from transmission
to link partner.
2
1
RW
Advertised 100BT half-duplex capability.
1 = advertise 100BT half-duplex capability.
0 = suppress 100BT half-duplex capability from transmission
to link partner.
Bit 7 in P1ANAR
1
1
RW
Advertised 10BT full-duplex capability.
Bit 6 in P1ANAR
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Bit
Default
R/W
Description
1 = advertise 10BT full-duplex capability.
0 = suppress 10BT full-duplex capability from transmission
to link partner.
Bit is same as:
0
1
RW
Advertised 10BT half-duplex capability.
1 = advertise 10BT half-duplex capability.
0 = suppress 10BT half-duplex capability from transmission
to link partner.
Bit 5 in P1ANAR
Port 1 Status Register (0xF8 – 0xF9): P1SR
This register contains the PHY port status for the chip function.
Bit
Default
R/W
Description
Bit is same as:
15
1
RW
HP_mdix
1 = HP Auto MDI-X mode.
0 = Micrel Auto MDI-X mode.
Bit 5 in P1MBCR
14
0
RO
Reserved
13
0
RO
Polarity Reverse
1 = polarity is reversed.
0 = polarity is not reversed.
12-11
0
RO
Reserved
10
0
RO
Operation Speed
1 = link speed is 100Mbps.
0 = link speed is 10Mbps.
9
0
RO
Operation Duplex
1 = link duplex is full.
0 = link duplex is half.
8
0
RO
Reserved
7
1
RO
MDI-X status
1 = MDI.
0 = MDI-X.
6
0
RO
AN Done
1 = AN done.
0 = AN not done.
Bit 5 in P1MBSR
5
0
RO
Link Good
1= link good.
0 = link not good.
Bit 2 in P1MBSR
4
0
RO
Partner flow control capability.
1 = link partner flow control (pause) capable.
0 = link partner not flow control (pause) capable.
Bit 10 in P1ANLPR
3
0
RO
Partner 100BT full-duplex capability.
1 = link partner 100BT full-duplex capable.
0 = link partner not 100BT full-duplex capable.
Bit 8 in P1ANLPR
2
0
RO
Partner 100BT half-duplex capability.
1 = link partner 100BT half-duplex capable.
0= link partner not 100BT half-duplex capable.
Bit 7 in P1ANLPR
1
0
RO
Partner 10BT full-duplex capability.
1= link partner 10BT full-duplex capable.
0 = link partner not 10BT full-duplex capable.
Bit 6 in P1ANLPR
0
0
RO
Partner 10BT half-duplex capability.
Bit 5 in P1ANLPR
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Bit
Default
KSZ8851SNL/SNLI
R/W
Description
Bit is same as:
1 = link partner 10BT half-duplex capable.
0 = link partner not 10BT half-duplex capable.
0xFA – 0xFF: Reserved
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MIB (Management Information Base) Counters
The KSZ8851SNL provides 32 MIB counters to monitor the port activity for network management. The MIB counters are
formatted as shown below.
Bit
Name
R/W
Description
Default
31-0
Counter values
RO
Counter value (read clear)
0x00000000
Table 13. Format of MIB Counters
Ethernet port MIB counters are read using indirect memory access. The address offset range is 0x00 to 0x1F.
Offset
Counter Name
Description
0x0
RxByte
Rx octet count including bad packets
0x1
Reserved
Reserved.
0x2
RxUndersizePkt
Rx undersize packets w/ good CRC
0x3
RxFragments
Rx fragment packets w/ bad CRC, symbol errors or alignment errors
0x4
RxOversize
Rx oversize packets w/ good CRC (max: 1536 bytes)
0x5
RxJabbers
Rx packets longer than 1536 bytes w/ either CRC errors, alignment errors, or symbol errors
0x6
RxSymbolError
Rx packets w/ invalid data symbol and legal packet size.
0x7
RxCRCError
Rx packets within (64,2000) bytes w/ an integral number of bytes and a bad CRC
0x8
RxAlignmentError
Rx packets within (64,2000) bytes w/ a non-integral number of bytes and a bad CRC
0x9
RxControl8808Pkts
Number of MAC control frames received by a port with 88-08h in EtherType field
0xA
RxPausePkts
Number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType (8808h), DA, control opcode (00-01), data length (64B min), and a valid CRC
0xB
RxBroadcast
Rx good broadcast packets (not including error broadcast packets or valid multicast packets)
0xC
RxMulticast
Rx good multicast packets (not including MAC control frames, error multicast packets or valid
broadcast packets)
0xD
RxUnicast
Rx good unicast packets
0xE
Rx64Octets
Total Rx packets (bad packets included) that were 64 octets in length
0xF
Rx65to127Octets
Total Rx packets (bad packets included) that are between 65 and 127 octets in length
0x10
Rx128to255Octets
Total Rx packets (bad packets included) that are between 128 and 255 octets in length
0x11
Rx256to511Octets
Total Rx packets (bad packets included) that are between 256 and 511 octets in length
0x12
Rx512to1023Octets
Total Rx packets (bad packets included) that are between 512 and 1023 octets in length
0x13
Rx1024to1521Octets
Total Rx packets (bad packets included) that are between 1024 and 1521 octets in length
0x14
Rx1522to2000Octets
Total Rx packets (bad packets included) that are between 1522 and 2000 octets in length
0x15
TxByte
Tx good octet count, including PAUSE packets
0x16
TxLateCollision
The number of times a collision is detected later than 512 bit-times into the Tx of a packet
0x17
TxPausePkts
Number of PAUSE frames transmitted by a port
0x18
TxBroadcastPkts
Tx good broadcast packets (not including error broadcast or valid multicast packets)
0x19
TxMulticastPkts
Tx good multicast packets (not including error multicast packets or valid broadcast packets)
0x1A
TxUnicastPkts
Tx good unicast packets
0x1B
TxDeferred
Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium
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KSZ8851SNL/SNLI
Offset
Counter Name
Description
0x1C
TxTotalCollision
Tx total collision, half duplex only
0x1D
TxExcessiveCollision
A count of frames for which Tx fails due to excessive collisions
0x1E
TxSingleCollision
Successfully Tx frames on a port for which Tx is inhibited by exactly one collision
0x1F
TxMultipleCollision
Successfully Tx frames on a port for which Tx is inhibited by more than one collision
Table 14. Port 1 MIB Counters Indirect Memory Offsets
Example:
1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E)
Write to reg. IACR (0xC8) with 0x1C0E (set indirect address and trigger a read MIB counters operation)
Then
Read reg. IADHR (MIB counter value 31-16)
Read reg. IADLR (MIB counter value 15-0)
Additional MIB Information
In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all
the counters at least every 30 seconds.
MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read.
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Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VDD_A3.3, VDD_IO) ......... –0.5V to +4.0V
Input Voltage (All Inputs).............................. –0.5V to +4.0V
Output Voltage (All Outputs) ........................ –0.5V to +4.0V
Lead Temperature (soldering, 20sec.) ....................... 260°C
Storage Temperature (Ts) ......................... –65°C to +150°C
Maximum Junction Temperature (TJ)....................... +125°C
HBM ESD Rating .......................................................... 6KV
Supply Voltage
VDD_A3.3 .......................................... +3.1V to +3.5V
VDD_IO (3.3V) ................................... +3.1V to +3.5V
VDD_IO (2.5V) ............................... +2.35V to +2.65V
VDD_IO (1.8V) ................................... +1.7V to +1.9V
Ambient Operating Temperature (TA)
Commercial (SNL)…………….……………...0°C to +70°C
Industrial (SNLI)……………….…………...-40°C to +85°C
(3)
Thermal Resistance
Junction-to-Ambient (θJA) ...............................34°C/W
Junction-to-Case (θJC) ......................................6°C/W
Electrical Characteristics(4, 5)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Supply Current for 100BASE-TX Operation (Single Port@100% Utilization)
Idd1
100BASE-TX
(analog core + PLL + digital
core + transceiver + digital I/O)
VDD_A3.3, VDD_IO = 3.3V; Chip only (no
transformer)
85
mA
VDD_A3.3=3.3V, VDD_IO = 2.5V; Chip only
(no transformer)
85
mA
VDD_A3.3=3.3V, VDD_IO = 1.8V; Chip only
(no transformer)
85
mA
VDD_A3.3, VDD_IO = 3.3V; Chip only (no
transformer)
75
mA
VDD_A3.3=3.3V, VDD_IO = 2.5V; Chip only
(no transformer)
75
mA
VDD_A3.3=3.3V, VDD_IO = 1.8V; Chip only
(no transformer)
75
mA
Supply Current for 10BASE-T Operation ( Single Port@100% Utilization)
Idd2
10BASE-T
(analog core + PLL + digital
core + transceiver + digital I/O)
Power Management Mode
(6)
Idd3
Power Saving Mode
Ethernet cable disconnected & Auto-Neg
70
mA
Idd4
Soft Power Down Mode
Set Bit [1:0] = 10 in PMECR register
2
mA
Idd5
Energy Detect Mode
At low power state
2
mA
TTL Inputs (VDD_IO = 3.3V/2.5V/1.8V)
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Current
2.0/2.0
/1.3
VIN = GND ~ VDD_IO
-10
V
0.8/0.6
/0.3
V
10
µA
TTL Outputs (VDD_IO = 3.3V/2.5V/1.8V)
VOH
Output High Voltage
IOH = -8mA
VOL
Output Low Voltage
IOL = 8mA
|IOZ|
Output Tri-state Leakage
2.4/1.9
/1.5
V
0.4/0.4
/0.2
V
10
µA
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to a appropriate logic voltage level (Ground
to VDD_IO).
3. No (HS) heat spreader in this package. The θJC/θJA is under air velocity 0m/s.
4. TA = 25°C. Specification for packaged product only.
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Electrical Characteristics(4, 5)
Symbol
Parameter
Condition
Min
Typ
Max
Units
100BaseTX Transmit (measured differentially after 1:1 transformer)
VO
Peak Differential Output Voltage
Vimb
Output Voltage Imbalance
tr, / tf
Rise/Fall Time
Rise/Fall Time Imbalance
100Ω termination on the diff. output
±0.95
±1.05
V
2
%
3
5
ns
0
0.5
ns
±0.25
ns
5
%
100Ω termination on the diff. output
Duty Cycle Distortion
Overshoot
VSET
Reference Voltage of ISET
Output Jitter
0.5
Peak-to-peak
0.7
5MHz square wave
400
V
1.4
ns
10BaseT Receive
Vsq
Squelch Threshold
mV
10BaseT Transmit (measured differentially after 1:1 transformer)
Vp
Peak Differential Output Voltage
100Ω termination on the differential output
Jitter Added
100Ω termination on the differential output
(Peak-to-peak)
2.2
2.5
2.8
V
1.8
3.5
ns
Table 15. Electrical Characteristics
Notes:
5. Single Port’s transformer consumes an additional 45mA @3.3V for 100BASE-TX and 70mA @3.3V for 10BASE-T.
6. Single Port’s transformer consumes less than 1mA during the Power Saving Mode.
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Timing Specifications
SPI Input and Output Timing
CSN
t1
1/fSCLK
t5
t4
SCLK
t2
t3
LSB bit
MSB bit
SI
High Impedance
SO
Figure 15. SPI Interface Data Input Timing
CSN
t5
1/fSCLK
SCLK
t6
SO
SI
t7
LSB bit
MSB bit
LSB in
Don’t Care
Figure 16. SPI Interface Data Output Timing
Symbol
Parameter
fSCLK
SPI Clock Frequency
Min
Typ
Max
Unit
40
MHz
t1
CSN active setup time
8
ns
t2
SI data input setup time
3
ns
t3
SI data input hold time
3
ns
t4
CSN active hold time
8
ns
t5
CSN disable high time
8
ns
t6
SCLK falling edge to SO data output valid
7.5
9
ns
1
ns
(note)
t7
CSN inactive to SO data output invalid
Note: The last SI data falling edge of SCLK starts output data on SO from KSZ8851SNL
Table 16. SPI Data Input and Output Timing Parameters
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Auto Negotiation Timing
Figure 17. Auto Negotiation Timing
Timing Parameter
Description
Min
Typ
Max
Unit
tBTB
FLP burst to FLP burst
8
16
24
ms
tFLPW
FLP burst width
tPW
Clock/Data pulse width
tCTD
Clock pulse to data pulse
55.5
64
69.5
µs
tCTC
Clock pulse to clock pulse
111
128
139
µs
Number of Clock/Data pulses per burst
17
2
ms
100
ns
33
Table 17. Auto Negotiation Timing Parameters
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Reset Timing
As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing
requirement for the KSZ8851SNL supply voltages (3.3V).
The reset timing requirement is summarized in the Figure 18 and Table 18.
Supply
Voltage
tsr
RSTN
Figure 18. Reset Timing
Symbol
tsr
Parameter
Min
Stable supply voltages to reset High
10
Max
Unit
ms
Table 18. Reset Timing Parameters
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EEPROM Timing
EECS
*1
EESK
1
tc y c
E E D _ IO
( o u tp u t)
11
0
An
A0
ts
th
E E D _ IO
( in p u t)
H ig h - Z
D 15
D14
D1
D13
D0
* 1 S ta r t b it
Figure 19. EEPROM Read Cycle Timing Diagram
Timing Parameter
Description
Min
Typ
tcyc
Clock cycle
ts
Setup time
20
ns
th
Hold time
20
ns
0.8 (OBCR[1:0]=00 on-chip
bus speed @ 125 MHz)
Max
Unit
μs
Table 19. EEPROM Timing Parameters
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Selection of Isolation Transformers
A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke
is recommended for exceeding FCC requirements.
Table 20 gives recommended transformer characteristics.
Parameter
Value
Test Condition
Turns ratio
1 CT : 1 CT
Open-circuit inductance (min)
350μH
100mV, 100kHz, 8mA
Leakage inductance (max)
0.4μH
1MHz (min)
Inter-winding capacitance (max)
12pF
D.C. resistance (max)
0.9Ω
Insertion loss (max)
1.0dB
HIPOT (min)
1500Vrms
0MHz – 65MHz
Table 20. Transformer Selection Criteria
Magnetic Manufacturer
Part Number
Auto MDI-X
Number of Port
Pulse
H1102
Yes
1
Pulse (low cost)
H1260
Yes
1
Transpower
HB726
Yes
1
Bel Fuse
S558-5999-U7
Yes
1
Delta
LF8505
Yes
1
LanKom
LF-H41S
Yes
1
TDK (Mag Jack)
TLA-6T718
Yes
1
Table 21. Qualified Single Port Magnetics
Selection of Reference Crystal
Chacteristics
Value
Units
Frequency
25
MHz
Frequency tolerance (max)
±50
ppm
Load capacitance (max)
20
pF
Series resistance
40
Ω
Table 22. Typical Reference Crystal Characteristics
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Package Information
®
Figure 20. 32-Pin (5mm x 5mm) MLF (QFN per JDEC) Package
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Acronyms and Glossary
BIU
Bus Interface Unit
The host interface function that performs code conversion,
buffering, and the like required for communications to and from a
network.
BPDU
Bridge Protocol Data Unit
A packet containing ports, addresses, etc. to make sure data
being passed through a bridged network arrives at its proper
destination.
CMOS
Complementary Metal Oxide Semiconductor
A common semiconductor manufacturing technique in which
positive and negative types of transistors are combined to form a
current gate that in turn forms an effective means of controlling
electrical current through a chip.
CRC
Cyclic Redundancy Check
A common technique for detecting data transmission errors. CRC
for Ethernet is 32 bits long.
Cut-through Switch
A switch typically processes received packets by reading
in the full packet (storing), then processing the packet to determine
where it needs to go, then forwarding it. A cut-through switch
simply reads in the first bit of an incoming packet and forwards the
packet. Cut-through switches do not store the packet.
DA
Destination Address
The address to send packets.
DMA
Direct Memory Access
A design in which memory on a chip is controlled independently of
the CPU.
EEPROM
Electronically Erasable Programmable
A design in which memory on a chip can be erased by
Read-only Memory
exposing it to an electrical charge.
EISA
Extended Industry Standard Architecture
A bus architecture designed for PCs using 80x86 processors, or
an Intel 80386, 80486 or Pentium microprocessor. EISA buses
are 32 bits wide and support multiprocessing.
EMI
Electro-Magnetic Interference
A naturally occurring phenomena when the electromagnetic field
of one device disrupts, impedes or degrades the electromagnetic
field of another device by coming into proximity with it. In computer
technology, computer devices are susceptible to EMI because
electromagnetic fields are a byproduct of passing electricity
through a wire. Data lines that have not been properly shielded
are susceptible to data corruption by EMI.
FCS
Frame Check Sequence
See CRC.
FID
Frame or Filter ID
Specifies the frame identifier. Alternately is the filter identifier.
IGMP
Internet Group Management Protocol
The protocol defined by RFC 1112 for IP multicast transmissions.
IPG
Inter-Packet Gap
A time delay between successive data packets mandated by the
network standard for protocol reasons. In Ethernet, the medium
has to be "silent" (i.e., no data transfer) for a short period of time
before a node can consider the network idle and start to transmit.
IPG is used to correct timing differences between a transmitter
and receiver. During the IPG, no data is transferred, and
information in the gap can be discarded or additions inserted
without impact on data integrity.
ISI
Inter-Symbol Interference
The disruption of transmitted code caused by adjacent pulses
affecting or interfering with each other.
ISA
Industry Standard Architecture
A bus architecture used in the IBM PC/XT and PC/AT.
Jumbo Packet
MDI
August 2009
A packet larger than the standard Ethernet packet (1500 bytes).
Large packet sizes allow for more efficient use of bandwidth, lower
overhead, less processing, etc.
Medium Dependent Interface
An Ethernet port connection that allows network hubs or switches
to connect to other hubs or switches without a null-modem, or
crossover, cable. MDI provides the standard interface to a
particular media (copper or fiber) and is therefore 'media
dependent.'
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MDI-X
Medium Dependent Interface Crossover
An Ethernet port connection that allows networked end stations
(i.e., PCs or workstations) to connect to each other using a nullmodem, or crossover, cable. For 10/100 full-duplex networks, an
end point (such as a computer) and a switch are wired so that
each transmitter connects to the far end receiver. When
connecting two computers together, a cable that crosses the TX
and RX is required to do this. With auto MDI-X, the PHY senses
the correct TX and RX roles, eliminating any cable confusion.
MIB
Management Information Base
The MIB comprises the management portion of network devices.
This can include things like monitoring traffic levels and faults
(statistical), and can also change operating parameters in network
nodes (static forwarding addresses).
MII
Media Independent Interface
The MII accesses PHY registers as defined in the IEEE 802.3
specification.
NIC
Network Interface Card
An expansion board inserted into a computer to allow it to be
connected to a network. Most NICs are designed for a particular
type of network, protocol, and media, although some can serve
multiple networks.
NPVID
Non Port VLAN ID
The Port VLAN ID value is used as a VLAN reference.
PLL
Phase-Locked Loop
An electronic circuit that controls an oscillator so that it maintains a
constant phase angle (i.e., lock) on the frequency of an input, or
reference, signal. A PLL ensures that a communication signal is
locked on a specific frequency and can also be used to generate,
modulate, and demodulate a signal and divide a frequency.
PME
Power Management Event
An occurrence that affects the directing of power to different
components of a system.
QMU
Queue Management Unit
Manages packet traffic between MAC/PHY interface and the
system host. The QMU has built-in packet memories for receive
and transmit functions called TXQ (Transmit Queue) and RXQ
(Receive Queue).
SA
Source Address
The address from which information has been sent.
TDR
Time Domain Reflectometry
TDR is used to pinpoint flaws and problems in underground and
aerial wire, cabling, and fiber optics. They send a signal down the
conductor and measure the time it takes for the signal -- or part of
the signal -- to return.
UTP
Unshielded Twisted Pair
Commonly a cable containing 4 twisted pairs of wires. The wires
are twisted in such a manner as to cancel electrical interference
generated in each wire, therefore shielding is not required.
VLAN
Virtual Local Area Network
A configuration of computers that acts as if all computers are
connected by the same physical network but which may be
located virtually anywhere.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2008 Micrel, Incorporated.
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