KSZ8041(R)

KSZ8041NL/RNL
10Base-T/100Base-TX
Physical Layer Transceiver
Revision 1.5
General Description
The KSZ8041NL is a single supply 10Base-T/100Base-TX
physical layer transceiver, which provides MII/RMII
interfaces to transmit and receive data. A unique mixed
signal design extends signaling distance while reducing
power consumption.
HP Auto MDI/MDI-X provides the most robust solution for
eliminating the need to differentiate between crossover
and straight-through cables.
The KSZ8041NL represents a new level of features and
performance and is an ideal choice of physical layer
transceiver for 10Base-T/100Base-TX applications.
The KSZ8041RNL is an enhanced RMII version of the
KSZ8041NL that does not require a 50MHz system clock.
It uses a 25MHz crystal for its input reference clock and
outputs a 50MHz RMII reference clock to the MAC.
The KSZ8041NL and KSZ8041RNL are available in 32pin, lead-free QFN packages (see Ordering Information).
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Diagram
TX+
TX-
Transmitter
10/100
Pulse
Shaper
NRZ/NRZI
MLT3 Encoder
4B/5B Encoder
Scrambler
Parallel/Serial
MDC
MDIO
TX_EN
TXD1
TXD0
Parallel/Serial
Manchester Encoder
REXT
RMII
Adaptive EQ
Base Line
Wander Correction
MLT3 Decoder
NRZI/NRZ
RX+
RX-
Clock
Recovery
4B/5B Decoder
Descrambler
Serial/Parallel
CRS_DV
RXD1
RXD0
RX_ER
REF_CLK
Auto
Negotiation
Manchester Decoder
Serial/Parallel
10Base-T
Receiver
INTRP
Power Down
RST#
Power Saving
XI
PLL
XO
KSZ8041NL
LED
LED0
Driver
LED1
KSZ8041RNL
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
February 4, 2015
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Features
Applications
• Single-chip 10Base-T/100Base-TX physical layer
solution
• Fully compliant to IEEE 802.3u standard
• Low power CMOS design, power consumption of
<180mW
• HP auto MDI/MDI-X for reliable detection and correction
for straight-through and crossover cables with disable
and enable option
• Robust operation over standard cables
• Power down and power saving modes
• MII interface support (KSZ8041NL only)
• RMII interface support with external 50MHz system
clock (KSZ8041NL only)
• RMII interface support with 25MHz crystal/clock input
and 50MHz reference clock output to MAC
(KSZ8041RNL only)
• MIIM (MDC/MDIO) management bus to 6.25MHz for
rapid PHY register configuration
• Interrupt pin option
• Programmable LED outputs for link, activity and speed
• ESD rating (6kV)
• Single power supply (3.3V)
• Built-in 1.8V regulator for core
• Available in 32-pin 5mm × 5mm QFN package
•
•
•
•
•
•
February 4, 2015
2
Printer
LOM
Game console
IPTV
IP phone
IP set-top box
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Ordering Information
For the device marking (second column in the Ordering Information table), the fifth character of line 3 indicates whether
the device has gold wire bonding or silver wire bonding, as follows:
 Gold wire bonding:
 Silver wire bonding:
The letter “S” is not present as the fifth character of line 3.
The letter “S” is present as the fifth character of line 3.
For line three, the presence or non-presence of the letter “S” is preceded by YYWW, indicating the last two digits of the
year and the two digits work week for the chip date code, and is followed by xxx, indicating the chip revision and assembly
site.
Part Number
Device
Marking
Package
Temperature
Range
Wire
Bonding
KSZ8041NL
KSZ8041NL
YYWWxxx
32-Pin QFN
0°C to 70°C
Gold
MII, Commercial Temperature, Gold
Wire Bonding, 32-Pin QFN, Pb-Free
SPNZ801162(1)
KSZ8041NL
YYWWSxxx
32-Pin QFN
0°C to 70°C
Silver
MII, Commercial Temperature, Silver
Wire Bonding, 32-Pin QFN, Pb-Free
KSZ8041NLI
KSZ8041NLI
YYWWxxx
32-Pin QFN
40°C to 85°C
Gold
MII, Industrial Temperature, Gold Wire
Bonding, 32-Pin QFN, Pb-Free
SPNY801162(1)
KSZ8041NLI
YYWWSxxx
32-Pin QFN
40°C to 85°C
Silver
MII, Industrial Temperature, Silver Wire
Bonding, 32-Pin QFN, Pb-Free
KSZ8041NL AM(1)
KSZ8041NL
AM
YYWWxxx
32-Pin QFN
40°C to 85°C
Gold
MII, Industrial Temperature, Gold Wire
Bonding, 32-Pin QFN, Pb-Free,
Automotive Qualified Device.
KSZ8041RNLU(1)
KSZ8041
RNLU
YYWWxxx
32-Pin QFN
40°C to 85°C
Gold
RMII with 50MHz clock output, Industrial
Temperature, Gold Wire Bonding, 32-Pin
QFN, Pb-Free, Automotive Qualified
Device.
KSZ8041RNL
KSZ8041RNL
YYWWxxx
32-Pin QFN
0°C to 70°C
Gold
RMII with 50MHz clock output,
Commercial Temperature, Gold Wire
Bonding, 32-Pin QFN, Pb-Free
SPNZ801164(1)
KSZ8041RNL
YYWWSxxx
32-Pin QFN
0°C to 70°C
Silver
RMII with 50MHz clock output,
Commercial Temperature, Silver Wire
Bonding, 32-Pin QFN, Pb-Free
KSZ8041RNLI
KSZ8041RNLI
YYWWxxx
32-Pin QFN
40°C to 85°C
Gold
RMII with 50MHz clock output, Industrial
Temperature, Gold Wire Bonding, 32-Pin
QFN, Pb-Free
SPNY801164(1)
KSZ8041RNLI
YYWWSxxx
32-Pin QFN
40°C to 85°C
Silver
RMII with 50MHz clock output, Industrial
Temperature, Silver Wire Bonding, 32Pin QFN, Pb-Free
Description
Note:
1. Contact factory for availability.
February 4, 2015
3
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Revision History
Revision
Date
1.0
10/13/06
Data sheet created.
4/27/07
Added maximum MDC clock speed.
Added 40K ±30% to Note 1 of Pin Description and Strapping Options tables for internal pull-ups/pulldowns.
Changed Model Number in Register 3h – PHY Identifier 2.
Changed polarity (swapped definition) of DUPLEX strapping pin.
Removed DUPLEX strapping pin update to Register 4h – Auto-Negotiation Advertisement bits [8, 6].
Set “Disable power saving” as the default for Register 1Fh bit [10].
Corrected LED1 (pin 31) definition for Activity in LED mode 01.
Added Symbol Error to MII/RMII Receive Error description and Register 15h – RXER Counter.
Added a 100pF capacitor on REXT (pin 10) in Pin Description table.
1.1
1.2
7/18/08
Summary of Changes
Added Automotive Qualified part number to Ordering Information.
Added maximum case temperature.
Added thermal resistance (θJC).
Added chip maximum current consumption.
1.3
12/11/09
Added Automotive Qualified part number, KSZ8041NL EAM, to Ordering Information.
Changed MDIO hold time (min) from 10ns to 4ns.
Added LED drive current.
Renamed Register 3h bits [3:0] to “manufacturer’s revision number” and changed default value to
“Indicates silicon revision.”
Updated RMII output delay for CRSDV and RXD[1:0] output pins.
Added support for Asymmetric PAUSE in register 4h bit [11].
Added control bits for 100Base-TX preamble restore (register 14h bit [7]) and 10Base-T preamble restore
(register 14h bit [6]).
Changed strapping pin definition for CONFIG[2:0] = 100 from “PCS Loopback” to “MII 100Mbps Preamble
Restore.”
Corrected MII timing for tRLAT, tCRS1, tCRS2.
Added KSZ8041RNL device and updated entire data sheet accordingly.
1.4
1/19/10
Removed part number (KSZ8041NL EAM) from Ordering Information.
Removed chip maximum current consumption.
1.5
2/2/15
February 4, 2015
Added automotive qualified part number, KSZ8041RNLU.
Changed VDDPLL_1.8 (Pin 2) decoupling capacitor value from 10µF to 1.0µF.
Specified minimum 250µs rise time for 3.3V input supply voltages (VDDIO_3.3, VDDA_3.3).
Add the part numbers of the silver wire bonding in Ordering Information.
4
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Contents
List of Figures .......................................................................................................................................................................... 7
List of Tables ........................................................................................................................................................................... 8
Pin Configuration − KSZ8041NL ............................................................................................................................................. 9
Pin Description − KSZ8041NL .............................................................................................................................................. 10
Strapping Options − KSZ8041NL .......................................................................................................................................... 14
Pin Configuration − KSZ8041RNL ........................................................................................................................................ 15
Pin Description − KSZ8041RNL ............................................................................................................................................ 16
Strapping Options − KSZ8041RNL ....................................................................................................................................... 19
Functional Description ........................................................................................................................................................... 20
100Base-TX Transmit........................................................................................................................................................ 20
100Base-TX Receive ......................................................................................................................................................... 20
PLL Clock Synthesizer ...................................................................................................................................................... 20
Scrambler/De-Scrambler (100Base-TX only) .................................................................................................................... 20
10Base-T Transmit ............................................................................................................................................................ 20
10Base-T Receive ............................................................................................................................................................. 21
SQE and Jabber Function (10Base-T only) ...................................................................................................................... 21
Auto-Negotiation ................................................................................................................................................................ 21
MII Management (MIIM) Interface ..................................................................................................................................... 23
Interrupt (INTRP) ............................................................................................................................................................... 23
MII Data Interface (KSZ8041NL only) ............................................................................................................................... 23
MII Signal Definition (KSZ8041NL only) ............................................................................................................................ 24
Transmit Clock (TXC) .................................................................................................................................................... 24
Transmit Enable (TXEN) ................................................................................................................................................ 24
Transmit Data [3:0] (TXD[3:0]) ....................................................................................................................................... 24
Receive Clock (RXC) ..................................................................................................................................................... 24
Receive Data Valid (RXDV) ........................................................................................................................................... 25
Receive Data [3:0] (RXD[3:0]) ....................................................................................................................................... 25
Receive Error (RXER).................................................................................................................................................... 25
Carrier Sense (CRS) ...................................................................................................................................................... 25
Collision (COL) ............................................................................................................................................................... 25
Reduced MII (RMII) Data Interface ................................................................................................................................ 25
RMII Signal Definition ........................................................................................................................................................ 26
Reference Clock (REF_CLK) ......................................................................................................................................... 26
Transmit Enable (TX_EN) .............................................................................................................................................. 26
Transmit Data [1:0] (TXD[1:0]) ....................................................................................................................................... 26
Carrier Sense/Receive Data Valid (CRS_DV) ............................................................................................................... 27
Receive Data [1:0] (RXD[1:0]) ....................................................................................................................................... 27
Receive Error (RX_ER).................................................................................................................................................. 27
Collision Detection ......................................................................................................................................................... 27
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
RMII Signal Diagram ......................................................................................................................................................... 27
Straight Cable ................................................................................................................................................................ 29
Crossover Cable ............................................................................................................................................................ 29
Power Management .......................................................................................................................................................... 30
Power Saving Mode ....................................................................................................................................................... 30
Power-Down Mode ............................................................................................................................................................ 30
Reference Clock Connection Options ............................................................................................................................... 30
Reference Circuit for Power and Ground Connections ..................................................................................................... 31
Register Map ......................................................................................................................................................................... 32
Register Description .............................................................................................................................................................. 33
Absolute Maximum Ratings .................................................................................................................................................. 42
Operating Ratings ................................................................................................................................................................. 42
Electrical Characteristics ....................................................................................................................................................... 42
Timing Diagrams ................................................................................................................................................................... 44
MII Transmit Timing (10Base-T) ........................................................................................................................................ 45
MII Receive Timing (10Base-T) ......................................................................................................................................... 46
MII Transmit Timing (100Base-TX) ................................................................................................................................... 47
MII Receive Timing (100Base-TX) .................................................................................................................................... 48
RMII Timing ....................................................................................................................................................................... 49
Auto-Negotiation Timing .................................................................................................................................................... 50
MDC/MDIO Timing ............................................................................................................................................................ 51
Power-Up/Reset Timing .................................................................................................................................................... 52
Reset Circuit .......................................................................................................................................................................... 53
Reference Circuits for LED Strapping Pins ........................................................................................................................... 54
Selection of Isolation Transformer ........................................................................................................................................ 55
Selection of Reference Crystal.............................................................................................................................................. 55
Package Information and Recommended Landing Pattern .................................................................................................. 56
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
List of Figures
Figure 1. Auto-Negotiation Flow Chart ................................................................................................................................ 22
Figure 2. KSZ8041NL RMII Interface .................................................................................................................................. 27
Figure 3. KSZ8041RNL RMII Interface ............................................................................................................................... 28
Figure 4. Typical Straight Cable Connection ...................................................................................................................... 29
Figure 5. Typical Crossover Cable Connection .................................................................................................................. 29
Figure 6. 25MHz Crystal/Oscillator Reference Clock ......................................................................................................... 30
Figure 7. 50MHz Oscillator Reference Clock fo KSZ8041NL RMII Mode .......................................................................... 30
Figure 8. KSZ8041NL/RNL Power and Ground Connections ............................................................................................. 31
Figure 9. MII SQE Timing (10Base-T) ................................................................................................................................ 44
Figure 10. MII Transmit Timing (10Base-T) .......................................................................................................................... 45
Figure 11. MII Receive Timing (10Base-T) ........................................................................................................................... 46
Figure 12. MII Transmit Timing (100Base-TX)...................................................................................................................... 47
Figure 13. MII Receive Timing (100Base-TX)....................................................................................................................... 48
Figure 14. RMII Timing – Data Received from RMII ............................................................................................................. 49
Figure 15. RMII Timing – Data Input to RMII ........................................................................................................................ 49
Figure 16. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................. 50
Figure 17. MDC/MDIO Timing............................................................................................................................................... 51
Figure 18. Power-Up/Reset Timing ....................................................................................................................................... 52
Figure 19. Recommended Reset Circuit ............................................................................................................................... 53
Figure 20. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output....................................................... 53
Figure 21. Reference Circuits for LED Strapping Pins ......................................................................................................... 54
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
List of Tables
Table 1. MII Management Frame Format ........................................................................................................................... 23
Table 2. MII Signal Definition .............................................................................................................................................. 24
Table 3. RMII Signal Description – KSZ8041NL ................................................................................................................. 26
Table 4. RMII Signal Description – KSZ8041RNL .............................................................................................................. 26
Table 5. MDI/MDI-X Pin Description ................................................................................................................................... 28
Table 6. KSZ8041NL/RNL Power Pin Description .............................................................................................................. 31
Table 7. MII SQE Timing (10Base-T) Parameters .............................................................................................................. 44
Table 8. MII Transmit Timing (10Base-T) Parameters ....................................................................................................... 45
Table 9. MII Receive Timing (10Base-T) Parameters ........................................................................................................ 46
Table 10. MII Transmit Timing (100Base-TX) Parameters ................................................................................................... 47
Table 11. MII Receive Timing (100Base-TX) Parameters .................................................................................................... 48
Table 12. RMII Timing Parameters – KSZ8041NL ............................................................................................................... 49
Table 13. RMII Timing Parameters – KSZ8041RNL ............................................................................................................. 49
Table 14. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ................................................................................ 50
Table 15. MDC/MDIO Timing Parameters ............................................................................................................................ 51
Table 16. Power-Up/Reset Timing Parameters .................................................................................................................... 52
Table 17. Transformer Selection Criteria .............................................................................................................................. 55
Table 18. Qualified Single Port Magnetics ............................................................................................................................ 55
Table 19. Typical Reference Crystal Characteristics ............................................................................................................ 55
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Pin Configuration − KSZ8041NL
32-Pin 5mm × 5mm QFN
February 4, 2015
9
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Pin Description − KSZ8041NL
Pin
Number
Pin
Name
Type
1
GND
Gnd
2
VDDPLL_1.8
P
1.8V Analog VDD
Decouple with 1.0µF and 0.1µF capacitors to ground.
3
VDDA_3.3
P
3.3V Analog VDD.
4
RX-
I/O
Physical receive or transmit signal (- differential).
5
RX+
I/O
Physical receive or transmit signal (+ differential).
6
TX-
I/O
Physical transmit or receive signal (- differential).
7
TX+
I/O
Physical transmit or receive signal (+ differential).
(2)
Pin Function
Ground.
8
XO
O
Crystal Feedback.
This pin is used only in MII mode when a 25MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII mode is
selected.
9
XI /
REFCLK
I
Crystal / Oscillator / External Clock Input:
MII Mode: 25MHz ±50ppm (crystal, oscillator, or external clock)
RMII Mode: 50MHz ±50ppm (oscillator, or external clock only)
10
REXT
I/O
11
MDIO
I/O
12
MDC
I
13
RXD3 /
PHYAD0
14
RXD2 /
PHYAD1
Set physical transmit output current.
Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground on this pin. See
KSZ8041NL reference schematics.
Management Interface (MII) Data I/O
This pin requires an external 4.7KΩ pull-up resistor.
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
(3)
Ipu/O
MII Mode: Receive Data Output[3] /.
Config Mode: The pull-up/pull-down value is latched as PHYADDR[0] during power-up /
reset. See Strapping Options − KSZ8041NL for details.
Ipd/O
MII Mode: Receive Data Output[2] /
Config Mode: The pull-up/pull-down value is latched as PHYADDR[1] during power-up /
reset. See Strapping Options − KSZ8041NL for details.
(3)
Notes:
2. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipd = Input with internal pull-down (40K +/-30%).
Ipu = Input with internal pull-up (40K +/-30%).
Opu = Output with internal pull-up (40K +/-30%).
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
3. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the MII.
RXD[3..0] is invalid when RXDV is de-asserted.
4. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered data
are sent from the PHY.
5. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through the
MII. TXD[3..0] has no effect when TXEN is de-asserted.
6. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are received
by the PHY from the MAC.
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Pin Description − KSZ8041NL (Continued)
Pin
Number
Pin
Name
15
RXD1 /
RXD[1] /
PHYAD2
Type
(2)
Pin Function
(3)
Ipd/O
MII Mode: Receive Data Output[1] /.
(4)
RMII Mode: Receive Data Output[1] /.
Config Mode: The pull-up/pull-down value is latched as PHYADDR[2] during power-up /
reset. See Strapping Options − KSZ8041NL for details.
16
RXD0 /
RXD[0] /
DUPLEX
Ipu/O
MII Mode: Receive Data Output[0] /.
(4)
RMII Mode: Receive Data Output[0] /.
Config Mode: Latched as DUPLEX (register 0h, bit 8) during power-up / reset. See
Strapping Options − KSZ8041NL for details.
17
VDDIO_3.3
P
18
RXDV /
CRSDV /
CONFIG2
Ipd/O
19
RXC
O
20
RXER /
RX_ER /
ISO
(3)
3.3V Digital VDD.
MII Mode: Receive Data Valid Output /.
RMII Mode: Carrier Sense/Receive Data Valid Output /.
Config Mode: The pull-up/pull-down value is latched as CONFIG2 during power-up / reset.
See Strapping Options − KSZ8041NL for details.
MII Mode: Receive Clock Output.
Ipd/O
MII Mode: Receive Error Output.
RMII Mode: Receive Error Output.
Config Mode: The pull-up/pull-down value is latched as ISOLATE during power-up / reset.
See Strapping Options − KSZ8041NL for details.
Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming the interrupt
conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt output to
active low (default) or active high.
21
INTRP
Opu
22
TXC
O
MII Mode: Transmit Clock Output.
23
TXEN /
TX_EN
I
MII Mode: Transmit Enable Input /.
RMII Mode: Transmit Enable Input.
24
TXD0 /
TXD[0]
I
25
TXD1 /
TXD[1]
I
26
TXD2
I
MII Mode: Transmit Data Input[0]
(5)
/.
(6)
RMII Mode: Transmit Data Input[0] .
MII Mode: Transmit Data Input[1]
(5)
/.
(6)
RMII Mode: Transmit Data Input[1] .
MII Mode: Transmit Data Input[2]
(5)
/.
MII Mode: Transmit Data Input[3]
(5)
/.
27
TXD3
I
28
COL /
CONFIG0
Ipd/O
MII Mode: Collision Detect Output /.
Config Mode: The pull-up/pull-down value is latched as CONFIG0 during power-up / reset.
See Strapping Options − KSZ8041NL for details.
29
CRS /
CONFIG1
Ipd/O
MII Mode: Carrier Sense Output /.
Config Mode: The pull-up/pull-down value is latched as CONFIG1 during power-up / reset.
See Strapping Options − KSZ8041NL for details.
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Pin Description − KSZ8041NL (Continued)
Pin
Number
Pin
Name
Type
(2)
Pin Function
LED Output: Programmable LED0 Output /.
Config Mode: Latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up /
reset. See Strapping Options − KSZ8041NL for details.
The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as follows:
LED Mode = [00]
30
LED0 /
NWAYEN
Link/Activity
Pin State
LED Definition
No Link
H
OFF
Link
L
ON
Activity
Toggle
Blinking
Link
Pin State
LED Definition
No Link
H
OFF
Link
L
ON
Ipu/O
LED Mode = [01]
LED Mode = [10]
Reserved
LED Mode = [11]
Reserved
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Pin Description − KSZ8041NL (Continued)
Pin
Number
Pin
Name
Type
(2)
Pin Function
LED Output: Programmable LED1 Output /
Config Mode: Latched as SPEED (register 0h, bit 13) during power-up / reset. See
Strapping Options − KSZ8041NL for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as follows:
LED Mode = [00]
31
LED1 /
SPEED
Speed
Pin State
LED Definition
10BT
H
OFF
100BT
L
ON
Activity
Pin State
LED Definition
No Activity
H
OFF
Activity
Toggle
Blinking
Ipu/O
LED Mode = [01]
LED Mode = [10]
Reserved.
LED Mode = [11]
Reserved.
32
RST#
I
PADDLE
GND
Gnd
February 4, 2015
Chip Reset (active low).
Ground.
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Strapping Options − KSZ8041NL
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this case,
it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE
mode, or is not configured with an incorrect PHY Address.
Pin
Number
Pin
Name
15
14
13
PHYAD2
PHYAD1
PHYAD0
Type
(7)
Ipd/O
Ipd/O
Ipu/O
Pin Function
The PHY Address is latched at power-up / reset and is configurable to any value from 1 to 7.
The default PHY Address is 00001.
PHY Address bits [4:3] are always set to ‘00’.
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as follows:
18
29
28
20
31
16
30
CONFIG2
CONFIG1
CONFIG0
ISO
SPEED
DUPLEX
NWAYEN
Ipd/O
Ipd/O
Ipd/O
CONFIG[2:0]
Mode
000
MII (default)
001
RMII
010
Reserved – not used
011
Reserved – not used
100
MII 100Mbps Preamble Restore
101
Reserved – not used
110
Reserved – not used
111
Reserved – not used
Ipd/O
ISOLATE Mode:
Pull-up = Enable
Pull-down (default) = Disable
During power-up / reset, this pin value is latched into register 0h bit 10.
Ipu/O
SPEED Mode:
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed Select, and
also is latched into register 4h (Auto-Negotiation Advertisement) as the Speed capability
support.
Ipu/O
DUPLEX Mode:
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex Mode.
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
Note:
7. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
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KSZ8041NL/RNL
RST#
LED1 /
SPEED
LED0 /
NWAYEN
CONFIG1
CONFIG0
NC
NC
TXD1
Pin Configuration − KSZ8041RNL
32
31
30
29
28
27
26
25
VDDA_3.3
3
22
NC
RX-
4
Paddle
Ground
21
INTRP
RX+
5
(on bottom of chip)
20
RX_ER /
ISO
TX-
6
19
REF_CLK
TX+
7
18
CRS_DV /
CONFIG2
XO
8
17
VDDIO_3.3
9
10
11
12
13
14
15
16
RXD0 /
DUPLEX
TX_EN
RXD1 /
PHYAD2
23
PHYAD1
2
PHYAD0
VDDPLL_1.8
MDC
TXD0
MDIO
24
REXT
1
XI
GND
32-Pin 5mm × 5mm QFN
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KSZ8041NL/RNL
Pin Description − KSZ8041RNL
Pin
Number
Pin
Name
Type
1
GND
Gnd
2
VDDPLL_1.8
P
1.8V Analog VDD.
Decouple with 1.0µF and 0.1µF capacitors to ground.
3
VDDA_3.3
P
3.3V Analog VDD.
4
RX-
I/O
Physical receive or transmit signal (- differential).
5
RX+
I/O
Physical receive or transmit signal (+ differential).
6
TX-
I/O
Physical transmit or receive signal (- differential).
7
TX+
I/O
Physical transmit or receive signal (+ differential).
8
XO
O
Crystal Feedback – for 25MHz Crystal.
This pin is a no connect if oscillator or external clock source is used.
9
XI
I
Crystal / Oscillator / External Clock Input.
25MHz ±50ppm.
10
REXT
I/O
11
MDIO
I/O
12
MDC
I
13
PHYAD0
Ipu/O
The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset. See
Strapping Options − KSZ8041RNL for details.
14
PHYAD1
Ipd/O
The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset. See
Strapping Options − KSZ8041RNL for details.
15
RXD1 /
PHYAD2
Ipd/O
RMII Mode: RMII Receive Data Output[1] /
Config Mode: The pull-up/pull-down value is latched as PHYADDR[2] during power-up /
reset. See Strapping Options − KSZ8041RNL for details.
16
RXD0 /
DUPLEX
Ipu/O
RMII Mode: RMII Receive Data Output[0] /
Config Mode: Latched as DUPLEX (register 0h, bit 8) during power-up / reset. See
Strapping Options − KSZ8041RNL for details.
(8)
Pin Function
Ground.
Set physical transmit output current.
Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground on this pin. See
KSZ8041RNL reference schematics.
Management Interface (MII) Data I/O.
This pin requires an external 4.7KΩ pull-up resistor.
Management Interface (MII) Clock Input.
This pin is synchronous to the MDIO data interface.
(9)
(9)
Notes:
8. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Opu = Output with internal pull-up (40K ±30%).
Ipu/O = Input with internal pull-up (40K ±30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K ±30%) during power-up/reset; output pin otherwise.
9. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered data
are sent from the PHY.
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KSZ8041NL/RNL
Pin Description − KSZ8041RNL (Continued)
Pin
Number
Pin
Name
17
VDDIO_3.3
P
18
CRS_DV /
CONFIG2
Ipd/O
19
REF_CLK
O
20
RX_ER /
ISO
Ipd/O
RMII Mode: RMII Receive Error Output /
Config Mode: The pull-up/pull-down value is latched as ISOLATE during power-up / reset.
See Strapping Options − KSZ8041RNL for details.
Interrupt Output: Programmable Interrupt Output.
Register 1Bh is the Interrupt Control/Status Register for programming the interrupt
conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt output to
active low (default) or active high.
Type
(8)
Pin Function
3.3V Digital VDD
RMII Mode: Carrier Sense/Receive Data Valid Output /.
Config Mode: The pull-up/pull-down value is latched as CONFIG2 during power-up / reset.
See Strapping Options − KSZ8041RNL for details.
50MHz Clock Output.
This pin provides the 50MHz RMII reference clock output to the MAC.
21
INTRP
Opu
22
NC
O
No Connect.
23
TX_EN
I
RMII Transmit Enable Input.
24
TXD0
I
RMII Transmit Data Input[0]
(10)
(10)
.
.
25
TXD1
I
RMII Transmit Data Input[1]
26
NC
I
No Connect.
27
NC
I
No Connect.
28
CONFIG0
Ipd/O
The pull-up/pull-down value is latched as CONFIG0 during power-up / reset. See
Strapping Options − KSZ8041RNL for details.
29
CONFIG1
Ipd/O
The pull-up/pull-down value is latched as CONFIG1 during power-up / reset. See
Strapping Options − KSZ8041RNL for details.
Note:
10. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are received
by the PHY from the MAC.
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KSZ8041NL/RNL
Pin Description − KSZ8041RNL (Continued)
Pin
Number
Pin
Name
Type
(8)
Pin Function
LED Output: Programmable LED0 Output /.
Config Mode: Latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up /
reset. See Strapping Options − KSZ8041RNL for details.
The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as follows:
LED Mode = [00]
30
LED0 /
NWAYEN
Ipu/O
Link/Activity
Pin State
LED Definition
No Link
H
OFF
Link
L
ON
Activity
Toggle
Blinking
Link
Pin State
LED Definition
No Link
H
OFF
Link
L
ON
LED Mode = [01]
LED Mode = [10] , [11]
Reserved.
LED Output: Programmable LED1 Output /.
Config Mode: Latched as SPEED (register 0h, bit 13) during power-up / reset. See
Strapping Options − KSZ8041RNL for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as follows:
LED Mode = [00]
31
LED1 /
SPEED
Ipu/O
Speed
Pin State
LED Definition
10BT
H
OFF
100BT
L
ON
Activity
Pin State
LED Definition
No Activity
H
OFF
Activity
Toggle
Blinking
LED Mode = [01]
LED Mode = [10], [11]
Reserved.
32
RST#
I
PADDLE
GND
Gnd
February 4, 2015
Chip Reset (active low).
Ground.
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KSZ8041NL/RNL
Strapping Options − KSZ8041RNL
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched high. In this case, it is
recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE mode,
or is not configured with an incorrect PHY Address.
Pin
Number
Pin
Name
15
14
13
PHYAD2
PHYAD1
PHYAD0
Type
(1)
Ipd/O
Ipd/O
Ipu/O
Pin Function
The PHY Address is latched at power-up / reset and is configurable to any value from 1 to 7.
The default PHY Address is 00001.
PHY Address bits [4:3] are always set to ‘00’.
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as follows:
18
29
28
20
31
16
30
CONFIG2
CONFIG1
CONFIG0
ISO
SPEED
DUPLEX
NWAYEN
Ipd/O
Ipd/O
Ipd/O
CONFIG[2:0]
Mode
000
Reserved – not used
001
RMII
010
Reserved – not used
011
Reserved – not used
100
Reserved – not used
101
Reserved – not used
110
Reserved – not used
111
Reserved – not used
Ipd/O
ISOLATE Mode:
Pull-up = Enable
Pull-down (default) = Disable
During power-up / reset, this pin value is latched into register 0h bit 10.
Ipu/O
SPEED Mode:
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed Select,
and also is latched into register 4h (Auto-Negotiation Advertisement) as the Speed capability
support.
Ipu/O
DUPLEX Mode:
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex Mode.
Ipu/O
Nway Auto-Negotiation Enable:
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
Note:
11. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
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KSZ8041NL/RNL
Functional Description
The KSZ8041NL is a single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3u Specification.
On the media side, the KSZ8041NL supports 10Base-T and 100Base-TX with HP auto MDI/MDI-X for reliable detection of
and correction for straight-through and crossover cables.
The KSZ8041NL offers a choice of MII or RMII data interface connection with the MAC processor. The MII management
bus option gives the MAC processor complete access to the KSZ8041NL control and status registers. Additionally, an
interrupt pin eliminates the need for the processor to poll for PHY status change.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the
design more efficient and allow for lower power consumption and smaller chip die size.
The KSZ8041RNL is an enhanced RMII version of the KSZ8041NL that does not require a 50MHz system clock. It uses a
25MHz crystal for its input reference clock and outputs a 50MHz RMII reference clock to the MAC.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is
further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output.
The output current is set by an external 6.49kΩ 1% resistor for the 1:1 transformer ratio. It has typical rise/fall times of 4
ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The waveshaped 10Base-T output drivers are also incorporated into the 100Base-TX drivers.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8041NL/RNL generates 125MΗz, 25MΗz and 20MΗz clocks for system timing. Internal clocks are generated
from an external 25MHz crystal or oscillator. For the KSZ8041NL in RMII mode, these internal clocks are generated from
an external 50MHz oscillator or system clock.
Scrambler/De-Scrambler (100Base-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers also perform internal wave-shaping and pre-emphasize, and output 10Base-T signals with a typical amplitude
of 2.5V peak. The 10Base-T signals have harmonic contents that are at least 27dB below the fundamental frequency
when driven by an all-ones Manchester-encoded signal.
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KSZ8041NL/RNL
10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and
a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data.
A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at the RX+ and
RX- inputs from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming
signal and the KSZ8041NL/RNL decodes a data frame. The receive clock is kept active during idle periods in between
data reception.
SQE and Jabber Function (10Base-T only)
In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE Test is required
as a test of the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the
10Base-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the 10BaseT transmitter is re-enabled and COL is de-asserted (returns to low).
Auto-Negotiation
The KSZ8041NL/RNL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification.
Auto-negotiation is enabled by either hardware pin strapping (pin 30) or software (register 0h bit 12).
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link
partners advertise their capabilities to each other, and then compare their own capabilities with those they received from
their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode
of operation.
The following list shows the speed and duplex operation mode from highest to lowest.
•
•
•
•
Priority 1:
Priority 2:
Priority 3:
Priority 4:
100Base-TX, full-duplex
100Base-TX, half-duplex
10Base-T, full-duplex
10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8041NL/RNL link partner is forced to bypass auto-negotiation, the
KSZ8041NL/RNL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and
allows the KSZ8041NL/RNL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation
advertisement protocol.
The auto-negotiation link up process is shown in the flow chart illustrated as Figure 1.
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KSZ8041NL/RNL
Start Auto Negotiation
Force Link Setting
N
o
Parallel
Operation
Yes
Bypass Auto Negotiation
and Set Link Mode
Attempt Auto
Negotiation
Listen for 100BASE-TX
Idles
Listen for 10BASE-T
Link Pulses
No
Join
Flow
Link Mode Set ?
Yes
Link Mode Set
Figure 1. Auto-Negotiation Flow Chart
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KSZ8041NL/RNL
MII Management (MIIM) Interface
The KSZ8041NL/RNL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input /
Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the
KSZ8041NL/RNL. An external device with MIIM capability is used to read the PHY status and/or configure the PHY
settings. Further details on the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the aforementioned physical connection that allows a external controller to
communicate with one or more PHY devices. Each KSZ8041NL/RNL device is assigned a unique PHY address
between 1 and 7 by its PHYAD[2:0] strapping pins. Also, every KSZ8041NL/RNL device supports the broadcast PHY
address 0, as defined per the IEEE 802.3 Specification, which can be used to read/write to a single KSZ8041NL/RNL
device, or write to multiple KSZ8041NL/RNL devices simultaneously.
• A set of 16-bit MDIO registers. Register [0:6] are required, and their functions are defined per the IEEE 802.3
Specification. The additional registers are provided for expanded functionality.
Table 1 shows the MII Management frame format for the KSZ8041NL/RNL.
Table 1. MII Management Frame Format
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data Bits [15:0]
Read
32 1’s
01
10
00AAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
01
00AAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Idle
Interrupt (INTRP)
INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8041NL/RNL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to
enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and
are used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register
1Bh.
Bit 9 of register 1Fh sets the interrupt level to active high or active low.
MII Data Interface (KSZ8041NL only)
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3 Specification. It provides a common
interface between physical layer and MAC layer devices, and has the following key characteristics:
•
•
•
•
Supports 10Mbps and 100Mbps data rates.
Uses a 25MHz reference clock, sourced by the PHY.
Provides independent 4-bit wide (nibble) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission and the other for reception.
By default, the KSZ8041NL is configured to MII mode after it is power-up or reset with the following:
• A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
• CONFIG[2:0] (pins 18, 29, 28) set to ‘000’ (default setting).
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KSZ8041NL/RNL
MII Signal Definition (KSZ8041NL only)
Table 2 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
Table 2. MII Signal Definition
MII
Signal Name
Direction
(with respect to PHY,
KSZ8041NL signal)
Direction
(with respect to MAC)
TXC
Output
Input
TXEN
Input
Output
Transmit Enable
TXD[3:0]
Input
Output
Transmit Data [3:0]
RXC
Output
Input
Receive Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
RXDV
Output
Input
Receive Data Valid
RXD[3:0]
Output
Input
Receive Data [3:0]
RXER
Output
Input, or (not required)
Receive Error
CRS
Output
Input
Carrier Sense
COL
Output
Input
Collision Detection
Description
Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated
prior to the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
Transmit Data [3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission
by the PHY. TXD[3:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[3:0] while TXEN
is de-asserted are ignored by the PHY.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
• In 10Mbps mode, RXC is recovered from the line while carrier is active. RXC is derived from the PHY’s reference clock
when the line is idle, or link is down.
• In 100Mbps mode, RXC is continuously recovered from the line. If link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
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KSZ8041NL/RNL
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
• In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), “5D”, and remains
asserted until the end of the frame.
• In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
Receive Data [3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
Receive Error (RXER)
RXER is asserted for one or more RXC periods to indicate that a Symbol Error (e.g. a coding error that a PHY is capable
of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame
presently being transferred from the PHY.
RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC.
Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
• In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
• In 100Mbps mode, CRS is asserted when a start-of-stream delimiter, or /J/K symbol pair is detected. CRS is deasserted when an end-of-stream delimiter, or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts CRS
if IDLE symbols are received without /T/R.
Collision (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This is
used to inform the MAC that a collision has occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXC and RXC.
Reduced MII (RMII) Data Interface
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides
a common interface between physical layer and MAC layer devices, and has the following key characteristics:
•
•
•
•
Supports 10Mbps and 100Mbps data rates.
Uses a 50MHz reference clock.
Provides independent 2-bit wide (di-bit) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission and the other for reception.
The KSZ8041NL is configured in RMII mode after it is power-up or reset with the following:
• A 50MHz reference clock connected to REFCLK (pin 9).
• CONFIG[2:0] (pins 18, 29, 28) set to ‘001’.
The KSZ8041RNL is configured in RMII mode and outputs the 50MHz RMII reference clock to the MAC on REF_CLK (pin
19) after it is power-up or reset with the following:
• A 25MHz crystal connected to XI (pin 9) and XO (pin 8), or a 25MHz reference clock connected to XI (pin 9).
• CONFIG[2:0] (pins 18, 29, 28) set to ‘001’.
In RMII mode, unused MII signals, TXD[3:2] (pins 27, 26), are tied to ground.
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KSZ8041NL/RNL
RMII Signal Definition
Table 3 and Table 4 describe the RMII signals for KSZ8041NL and KSZ8041RNL. Refer to RMII Specification for detailed
information.
Table 3. RMII Signal Description – KSZ8041NL
RMII
Signal Name
Direction
(with respect to PHY,
KSZ8041NL signal)
Direction
(with respect to MAC)
REF_CLK
Input
Input, or Output
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data [1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data [1:0]
RX_ER
Output
Input, or (not required)
Description
Synchronous 50 MHz clock reference for receive, transmit
and control interface
Receive Error
Table 4. RMII Signal Description – KSZ8041RNL
RMII
Signal Name
Direction
(with respect to PHY,
KSZ8041RNL signal)
Direction
(with respect to MAC)
REF_CLK
Output
Input
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data [1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data [1:0]
RX_ER
Output
Input, or (not required)
Description
Synchronous 50 MHz clock reference for receive, transmit
and control interface
Receive Error
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and
RX_ER.
The KSZ8041NL inputs the 50MHz REF_CLK from the MAC or system board.
The KSZ8041RNL generates the 50MHz RMII REF_CLK and outputs it to the MAC.
Transmit Enable (TX_EN)
TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated
prior to the first REF_CLK following the final di-bit of a frame.
TX_EN transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for
transmission by the PHY. TXD[1:0] is ”00” to indicate idle when TX_EN is de-asserted. Values other than “00” on TXD[1:0]
while TX_EN is de-asserted are ignored by the PHY.
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Micrel, Inc.
KSZ8041NL/RNL
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of
carrier. This is when squelch is passed in 10Mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
So long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered di-bit of the
frame through the final recovered di-bit, and it is negated prior to the first REF_CLK that follows the final di-bit. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is "00" until proper receive signal decoding takes place.
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers
two bits of recovered data from the PHY. RXD[1:0] is "00" to indicate idle when CRS_DV is de-asserted. Values other
than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC.
Receive Error (RX_ER)
RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is
capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the
frame presently being transferred from the PHY.
RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the
MAC.
Collision Detection
The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV.
RMII Signal Diagram
The KSZ8041NL RMII pin connections to the MAC are shown in Figure 2.
RMII MAC
KSZ8041NL
CRS_DV
CRS_DV
RXD[1:0]
RXD[1:0]
RX_ER
RX_ER
TX_EN
TX_EN
TXD[1:0]
TXD[1:0]
REF_CLK
REFCLK
50 MHz
OSC
Figure 2. KSZ8041NL RMII Interface
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
The KSZ8041RNL RMII pin connections to the MAC are shown in Figure 3.
RMII MAC
KSZ8041RNL
CRS_DV
CRS_DV
RXD[1:0]
RXD[1:0]
RX_ER
RX_ER
TX_EN
TX_EN
TXD[1:0]
TXD[1:0]
REF_CLK
REF_CLK
XI
XO
25 MHz
XTAL
22 pF
22 pF
Figure 3. KSZ8041RNL RMII Interface
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable
between the KSZ8041NL/RNL and its link partner. This feature allows the KSZ8041NL/RNL to use either type of cable to
connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive
pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8041NL/RNL accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to register 1F bit 13. MDI and MDI-X mode is
selected by register 1F bit 14 if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X.
The IEEE 802.3 Standard defines MDI and MDI-X as in Table 5:
Table 5. MDI/MDI-X Pin Description
MDI
MDI-X
RJ-45 Pin
Signal
RJ-45 Pin
Signal
1
TD+
1
RD+
2
TD-
2
RD-
3
RD+
3
TD+
6
RD-
6
TD-
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Micrel, Inc.
KSZ8041NL/RNL
Straight Cable
A straight cable connects a MDI device to a MDI-X device, or a MDI-X device to a MDI device. Figure 4 depicts a typical
straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Media Dependent Interface
1
1
2
2
Receive Pair
Transmit Pair
3
Straight
Cable
3
4
4
5
5
6
6
Receive Pair
Transmit Pair
7
7
8
8
Modular Connector
(RJ-45)
HUB
(Repeater or Switch)
Modular Connector
(RJ-45)
NIC
Figure 4. Typical Straight Cable Connection
Crossover Cable
A crossover cable connects a MDI device to another MDI device, or a MDI-X device to another MDI-X device. Figure 5
depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices).
10/100 Ethernet
Media Dependent Interface
1
Receive Pair
10/100 Ethernet
Media Dependent Interface
Crossover
Cable
1
Receive Pair
2
2
3
3
4
4
5
5
6
6
7
7
8
8
Transmit Pair
Transmit Pair
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Figure 5. Typical Crossover Cable Connection
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Power Management
The KSZ8041NL/RNL offers the following power-management modes:
Power Saving Mode
This mode is used to reduce power consumption when the cable is unplugged. It is in effect when auto-negotiation mode
is enabled, cable is disconnected, and register 1F bit 10 is set to 1. Under power saving mode, the KSZ8041NL/RNL
shuts down all transceiver blocks, except for transmitter, energy detect and PLL circuits. Additionally, for the KSZ8041NL
in MII mode, the RXC clock output is disabled. RXC clock is enabled after the cable is connected and link is established.
Power-saving mode is disabled by writing a zero to register 1F bit 10.
Power-Down Mode
This mode is used to power down the entire KSZ8041NL/RNL device when it is not in use. Power down mode is enabled
by writing a one to register 0 bit 11. In the power down state, the KSZ8041NL/RNL disables all internal functions, except
for the MII management interface.
Reference Clock Connection Options
A crystal or clock source, such as an oscillator, is used to provide the reference clock for the KSZ8041NL/RNL.
Figure 6 illustrates how to connect the 25MHz crystal and oscillator reference clock.
Figure 6. 25MHz Crystal/Oscillator Reference Clock
For the KSZ8041NL, Figure 7 illustrates how to connect the 50MHz oscillator reference clock for RMII mode.
Figure 7. 50MHz Oscillator Reference Clock for KSZ8041NL RMII Mode
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Micrel, Inc.
KSZ8041NL/RNL
Reference Circuit for Power and Ground Connections
The KSZ8041NL/RNL is a single 3.3V supply device with a built-in 1.8V low-noise regulator. The power and ground
connections are shown in Figure 8 and Table 6.
Ferrite
Bead
`
`
22uF
VOUT
VIN
3
VDDA_3.3
1.8V Low Noise
Regulator
(integrated)
0.1uF
1.0uF
0.1uF
VDDPLL_1.8
2
17
3.3V
VDDIO_3.3
`
22uF
0.1uF
KSZ8041NL/RNL
GND
1
Paddle
Figure 8. KSZ8041NL/RNL Power and Ground Connections
Table 6. KSZ8041NL/RNL Power Pin Description
Power Pin
Pin Number
Description
VDDPLL_1.8
2
Decouple with 1.0uF and 0.1uF capacitors to ground.
VDDA_3.3
3
Connect to board’s 3.3V supply through ferrite bead.
VDDIO_3.3
17
Connect to board’s 3.3V supply.
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KSZ8041NL/RNL
Register Map
Register Number (Hex)
Description
0h
Basic Control
1h
Basic Status
2h
PHY Identifier 1
3h
PHY Identifier 2
4h
Auto-Negotiation Advertisement
5h
Auto-Negotiation Link Partner Ability
6h
Auto-Negotiation Expansion
7h
Auto-Negotiation Next Page
8h
Link Partner Next Page Ability
9h – 13h
Reserved
14h
MII Control
15h
RXER Counter
16h – 1Ah
Reserved
1Bh
Interrupt Control/Status
1Ch – 1Dh
Reserved
1Eh
PHY Control 1
1Fh
PHY Control 2
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Register Description
Address
Name
(12)
Description
Mode
Default
RW/SC
0
Register 0h – Basic Control
0.15
Reset
1 = Software reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is
written to it.
0.14
Loop-Back
1 = Loop-back mode
0 = Normal operation
RW
0
Speed Select (LSB)
1 = 100Mbps
0 = 10Mbps
This bit is ignored if auto-negotiation
is enabled (register 0.12 = 1).
RW
Set by SPEED strapping pin.
See “Strapping Options” section for
details.
0.12
Auto-Negotiation Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
If enabled, auto-negotiation result
overrides settings in register 0.13 and
0.8.
RW
0.11
Power Down
1 = Power-down mode
0 = Normal operation
RW
Isolate
1 = Electrical isolation of PHY from
MII and TX+/TX0 = Normal operation
RW
1 = Restart auto-negotiation process
0 = Normal operation.
This bit is self-cleared after a ‘1’ is
written to it.
RW/SC
0.13
0.10
Set by NWAYEN strapping pin.
See Strapping Options −
KSZ8041NL and Strapping Options
− KSZ8041RNL sections for details.
0
Set by ISO strapping pin.
See Strapping Options −
KSZ8041NL and Strapping Options
− KSZ8041RNL sections for details.
Register 0h – Basic Control
0.9
Restart Auto-Negotiation
0
Inverse of DUPLEX strapping pin
value.
0.8
Duplex Mode
1 = Full-duplex
0 = Half-duplex
RW
See Strapping Options −
KSZ8041NL and Strapping Options
− KSZ8041RNL sections for details.
0.7
Collision Test
1 = Enable COL test
0 = Disable COL test
RW
0
0.6:1
Reserved
RO
000_000
0.0
Disable
Transmitter
RW
0
0 = Enable transmitter
1 = Disable transmitter
Note:
12. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(12)
Description
Mode
Default
Register 1h – Basic Status
1.15
100Base-T4
1 = T4 capable
0 = Not T4 capable
RO
0
1.14
100Base-TX Full Duplex
1 = Capable of 100Mbps full-duplex
0 = Not capable of 100Mbps fullduplex
RO
1
1.13
100Base-TX Half Duplex
1 = Capable of 100Mbps half-duplex
0 = Not capable of 100Mbps halfduplex
RO
1
1.12
10Base-T Full Duplex
1 = Capable of 10Mbps full-duplex
0 = Not capable of 10Mbps fullduplex
RO
1
1.11
10Base-T Half Duplex
1 = Capable of 10Mbps half-duplex
0 = Not capable of 10Mbps halfduplex
RO
1
1.10:7
Reserved
RO
0000
1.6
No Preamble
1 = Preamble suppression
0 = Normal preamble
RO
1
1.5
Auto-Negotiation Complete
1 = Auto-negotiation process
completed
0 = Auto-negotiation process not
completed
RO
0
1.4
Remote Fault
1 = Remote fault
0 = No remote fault
RO/LH
0
1.3
Auto-Negotiation Ability
1 = Capable to perform autonegotiation
0 = Not capable to perform autonegotiation
RO
1
1.2
Link Status
1 = Link is up
0 = Link is down
RO/LL
0
1.1
Jabber Detect
1 = Jabber detected
0 = Jabber not detected (default is
low)
RO/LH
0
1.0
Extended Capability
1 = Supports extended capabilities
registers
RO
1
Assigned to the 3rd through 18th bits
of the Organizationally Unique
Identifier (OUI). Kendin
Communication’s OUI is 0010A1
(hex)
RO
0022h
Register 2h – PHY Identifier 1
2.15:0
PHY ID Number
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Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(12)
Description
Mode
Default
RO
0001_01
Register 3h – PHY Identifier 2
3.15:10
PHY ID Number
Assigned to the 19th through 24th
bits of the Organizationally Unique
Identifier (OUI). Kendin
Communication’s OUI is 0010A1
(hex)
3.9:4
Model Number
Six bit manufacturer’s model number
RO
01_0001
3.3:0
Revision Number
Four bit manufacturer’s revision
number
RO
Indicates silicon revision
RW
0
RO
0
RW
0
RO
0
RW
00
RO
0
Register 4h – Auto-Negotiation Advertisement
4.15
Next Page
4.14
Reserved
4.13
Remote Fault
4.12
Reserved
1 = Next page capable
0 = No next page capability.
1 = Remote fault supported
0 = No remote fault
4.11:10
Pause
[00] = No PAUSE
[10] = Asymmetric PAUSE
[01] = Symmetric PAUSE
[11] = Asymmetric & Symmetric
PAUSE
4.9
100Base-T4
1 = T4 capable
0 = No T4 capability
100Base-TX Full-Duplex
1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability
4.7
100Base-TX Half-Duplex
1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex
capability
RW
4.6
10Base-T Full-Duplex
1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability
RW
1
4.5
10Base-T Half-Duplex
1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability
RW
1
4.4:0
Selector Field
[00001] = IEEE 802.3
RW
0_0001
Set by SPEED strapping pin.
4.8
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35
RW
See Strapping Options −
KSZ8041NL and Strapping Options
− KSZ8041RNL sections for details.
Set by SPEED strapping pin.
See Strapping Options −
KSZ8041NL and Strapping Options
− KSZ8041RNL sections for details.
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(12)
Description
Mode
Default
Register 5h – Auto-Negotiation Link Partner Ability
5.15
Next Page
1 = Next page capable
0 = No next page capability
RO
0
5.14
Acknowledge
1 = Link code word received from
partner
0 = Link code word not yet received
RO
0
5.13
Remote Fault
1 = Remote fault detected
0 = No remote fault
RO
0
5.12
Reserved
RO
0
RO
00
5.11:10
Pause
[00] = No PAUSE
[10] = Asymmetric PAUSE
[01] = Symmetric PAUSE
[11] = Asymmetric & Symmetric
PAUSE
5.9
100Base-T4
1 = T4 capable
0 = No T4 capability
RO
0
5.8
100Base-TX Full-Duplex
1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability
RO
0
5.7
100Base-TX Half-Duplex
1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex
capability
RO
0
5.6
10Base-T Full-Duplex
1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability
RO
0
5.5
10Base-T Half-Duplex
1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability
RO
0
5.4:0
Selector Field
[00001] = IEEE 802.3
RO
0_0001
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(12)
Description
Mode
Default
RO
0000_0000_000
Parallel Detection Fault
1 = Fault detected by parallel
detection
0 = No fault detected by parallel
detection.
RO/LH
0
Link Partner Next Page Able
1 = Link partner has next page
capability
0 = Link partner does not have next
page capability
RO
0
6.2
Next Page Able
1 = Local device has next page
capability
0 = Local device does not have next
page capability
RO
1
6.1
Page Received
1 = New page received
0 = New page not received yet
RO/LH
0
6.0
Link Partner AutoNegotiation Able
1 = Link partner has auto-negotiation
capability
0 = Link partner does not have autonegotiation capability
RO
0
RW
0
RO
0
Register 6h – Auto-Negotiation Expansion
6.15:5
6.4
6.3
Reserved
Register 7h – Auto-Negotiation Next Page
1 = Additional next page(s) will follow
0 = Last page
7.15
Next Page
7.14
Reserved
7.13
Message Page
1 = Message page
0 = Unformatted page
RW
1
7.12
Acknowledge2
1 = Will comply with message
0 = Cannot comply with message
RW
0
7.11
Toggle
1 = Previous value of the transmitted
link code word equaled logic one
0 = Logic zero
RO
0
7.10:0
Message Field
11-bit wide field to encode 2048
messages
RW
000_0000_0001
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(12)
Description
Mode
Default
Register 8h – Link Partner Next Page Ability
8.15
Next Page
1 = Additional Next Page(s) will follow
0 = Last page
RO
0
8.14
Acknowledge
1 = Successful receipt of link word
0 = No successful receipt of link word
RO
0
8.13
Message Page
1 = Message page
0 = Unformatted page
RO
0
8.12
Acknowledge2
1 = Able to act on the information
0 = Not able to act on the information
RO
0
8.11
Toggle
1 = Previous value of transmitted link
code
word equal to logic zero
0 = Previous value of transmitted link
code
word equal to logic one
RO
0
8.10:0
Message Field
RO
000_0000_0000
RO
0000_0000
Register 14h – MII Control
14.15:8
Reserved
0 or
1 (if CONFIG[2:0] = 100)
100Base-TX Preamble
Restore
1 = Restore received preamble to MII
output (random latency)
0 = Consume 1-byte preamble before
sending frame to MII output for fixed
latency
RW
14.6
10Base-T Preamble
Restore
1 = Restore received preamble to MII
output
0 = Remove all 7-bytes of preamble
before sending frame (starting with
SFD) to MII
output
RW
0
14.5:0
Reserved
RO
00_0001
RO/SC
0000h
14.7
See Strapping Options −
KSZ8041NL and Strapping
Options − KSZ8041RNL sections
for details.
Register 15h – RXER Counter
15.15:0
RXER Counter
February 4, 2015
Receive error counter for Symbol
Error frames
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(12)
Description
Mode
Default
Register 1Bh – Interrupt Control/Status
1b.15
Jabber Interrupt Enable
1 = Enable Jabber Interrupt
0 = Disable Jabber Interrupt
RW
0
1b.14
Receive Error Interrupt
Enable
1 = Enable Receive Error Interrupt
0 = Disable Receive Error Interrupt
RW
0
1b.13
Page Received Interrupt
Enable
1 = Enable Page Received Interrupt
0 = Disable Page Received Interrupt
RW
0
1b.12
Parallel Detect Fault
Interrupt Enable
1 = Enable Parallel Detect Fault
Interrupt
0 = Disable Parallel Detect Fault
Interrupt
RW
0
1b.11
Link Partner Acknowledge
Interrupt Enable
1 = Enable Link Partner Acknowledge
Interrupt
0 = Disable Link Partner
Acknowledge Interrupt
RW
0
1b.10
Link Down Interrupt Enable
1= Enable Link Down Interrupt
0 = Disable Link Down Interrupt
RW
0
1b.9
Remote Fault Interrupt
Enable
1 = Enable Remote Fault Interrupt
0 = Disable Remote Fault Interrupt
RW
0
1b.8
Link Up Interrupt Enable
1 = Enable Link Up Interrupt
0 = Disable Link Up Interrupt
RW
0
1b.7
Jabber Interrupt
1 = Jabber occurred
0 = Jabber did not occurred
RO/SC
0
1b.6
Receive Error Interrupt
1 = Receive Error occurred
0 = Receive Error did not occurred
RO/SC
0
1b.5
Page Receive Interrupt
1 = Page Receive occurred
0 = Page Receive did not occurred
RO/SC
0
1b.4
Parallel Detect Fault
Interrupt
1 = Parallel Detect Fault occurred
0 = Parallel Detect Fault did not
occurred
RO/SC
0
1b.3
Link Partner Acknowledge
Interrupt
1= Link Partner Acknowledge
occurred
0= Link Partner Acknowledge did not
occurred
RO/SC
0
1b.2
Link Down Interrupt
1= Link Down occurred
0= Link Down did not occurred
RO/SC
0
1b.1
Remote Fault Interrupt
1= Remote Fault occurred
0= Remote Fault did not occurred
RO/SC
0
1b.0
Link Up Interrupt
1= Link Up occurred
0= Link Up did not occurred
RO/SC
0
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(12)
Description
Mode
Default
RW
00
Register 1Eh – PHY Control 1
1e:15:14
LED mode
[00] =
LED1 : Speed
LED0 : Link/Activity
[01] =
LED1 : Activity
LED0 : Link
[10], [11] = Reserved
1e.13
Polarity
1e.12
Reserved
1e.11
MDI/MDI-X State
1e:10:8
Reserved
1e:7
Remote loopback
1e:6:0
Reserved
0 = Polarity is not reversed
1 = Polarity is reversed
RO
RO
0
0 = MDI
1 = MDI-X
RO
0 = Normal mode
1 = Remote (analog) loop back is
enable
RW
0
HP_MDIX
0 = Micrel Auto MDI/MDI-X mode
1 = HP Auto MDI/MDI-X mode
RW
1
1f:14
MDI/MDI-X Select
When Auto MDI/MDI-X is disabled,
0 = MDI Mode
Transmit on TX+/- (pins 7, 6) and
Receive on RX+/- (pins 5, 4)
1 = MDI-X Mode
Transmit on RX+/- (pins 5,4) and
Receive on TX+/- (pins 7, 6)
RW
0
1f:13
Pair Swap Disable
1 = Disable auto MDI/MDI-X
0 = Enable auto MDI/MDI-X
RW
0
1f.12
Energy Detect
1 = Presence of signal on RX+/analog wire pair
0 = No signal detected on RX+/-
RO
0
Force Link
1 = Force link pass
0 = Normal link operation
This bit bypasses the control logic
and allow transmitter to send pattern
even if there is no link.
RW
0
Register 1Fh – PHY Control 2
1f:15
1f.11
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Register Description (Continued)
Address
Name
(12)
Description
Mode
Default
RW
0
Register 1Fh – PHY Control 2 (Continued)
1f.10
Power Saving
1 = Enable power saving
0 = Disable power saving
If power saving mode is enabled and
the cable is disconnected, the RXC
clock output (in MII mode) is disabled.
RXC clock is enabled after the cable
is connected and link is established.
1f.9
Interrupt Level
1 = Interrupt pin active high
0 = Interrupt pin active low
RW
0
1f.8
Enable Jabber
1 = Enable jabber counter
0 = Disable jabber counter
RW
1
1f.7
Auto-Negotiation Complete
1 = Auto-negotiation process
completed
0 = Auto-negotiation process not
completed
RW
0
1f.6
Enable Pause (Flow
Control)
1 = Flow control capable
0 = No flow control capability
RO
0
1f.5
PHY Isolate
1 = PHY in isolate mode
0 = PHY in normal operation
RO
0
1f.4:2
Operation Mode Indication
[000] = still in auto-negotiation
[001] = 10Base-T half-duplex
[010] = 100Base-TX half-duplex
[011] = reserved
[101] = 10Base-T full-duplex
[110] = 100Base-TX full-duplex
[111] = reserved
RO
000
1f.1
Enable SQE test
1 = Enable SQE test
0 = Disable SQE test
RW
0
1f.0
Disable Data Scrambling
1 = Disable scrambler
0 = Enable scrambler
RW
0
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KSZ8041NL/RNL
Absolute Maximum Ratings(13)
Operating Ratings(14)
Supply Voltage
(VDDPLL_1.8) .............................................. −0.5V to +2.4V
(VDDIO_3.3, VDDA_3.3) .................................. −0.5V to +4.0V
Input Voltage (all inputs) .............................. −0.5V to +4.0V
Output Voltage (all outputs) .......................... -0.5V to +4.0V
Lead Temperature (soldering, 10s) ............................ 260°C
Storage Temperature (Ts) ......................... −55°C to +150°C
(15)
ESD Rating ................................................................ 6kV
Supply Voltage
(VDDIO_3.3, VDDA_3.3) .......................... +3.135V to +3.465V
Ambient Temperature
(TA , Commercial) ...................................... 0°C to +70°C
(TA , Industrial) ....................................... -40°C to +85°C
(TA , Automotive Qualified) ..................... -40°C to +85°C
Maximum Junction Temperature (TJ maximum) ........ 125°C
Maximum Case Temperature (TC maximum) ............. 150°C
Thermal Resistance (θJA) ......................................... 34°C/W
Thermal Resistance (θJC) ........................................... 6°C/W
Electrical Characteristics(16)
Symbol
Parameter
Supply Current
Condition
Min.
Typ.
Max.
Units
(17)
IDD1
100Base-TX
Chip only (no transformer);
Full-duplex traffic @ 100% utilization
53.0
mA
IDD2
10Base-T
Chip only (no transformer);
Full-duplex traffic @ 100% utilization
38.0
mA
IDD3
Power-Saving Mode
Ethernet cable disconnected (reg. 1F.10 = 1)
32.0
mA
IDD4
Power-Down Mode
Software power-down (reg. 0.11 = 1)
4.0
mA
TTL Inputs
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Current
2.0
VIN = GND ~ VDDIO
V
-10
0.8
V
10
µA
TTL Outputs
VOH
Output High Voltage
IOH = −4mA
VOL
Output Low Voltage
IOL = 4mA
|Ioz|
Output Tri-State Leakage
2.4
V
0.4
V
10
µA
LED Outputs
ILED
Output Drive Current
Each LED pin (LED0, LED1)
8
mA
Notes:
13. Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent
damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is
not implied. Maximum conditions for extended periods may affect reliability.
14. The device is not guaranteed to function outside its operating rating.
15. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
16. TA = 25°C. Specification for packaged product only.
17. Current consumption is for the single 3.3V supply KSZ8041NL/RNL device only, and includes the 1.8V supply voltage (VDDPLL_1.8) that is provided by
the KSZ8041NL/RNL. The PHY port’s transformer consumes an additional 45mA @ 3.3V for 100Base-TX and 70mA @ 3.3V for 10Base-T.
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Micrel, Inc.
KSZ8041NL/RNL
Electrical Characteristics(16) (Continued)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
1.05
V
2
%
100Base-TX Transmit (measured differentially after 1:1 transformer)
VO
Peak Differential Output Voltage
100Ω termination across differential output
VIMB
Output Voltage Imbalance
100Ω termination across differential output
tr , tf
0.95
Rise/Fall Time
3
5
ns
Rise/Fall Time Imbalance
0
0.5
ns
+0.25
ns
5
%
Duty Cycle Distortion
Overshoot
VSET
Reference Voltage of ISET
Output Jitter
V
0.65
Peak-to-peak
0.7
1.4
ns
2.8
V
3.5
ns
10Base-T Transmit (measured differentially after 1:1 transformer)
VP
tr, tf
Peak Differential Output Voltage
100Ω termination across differential output
Jitter Added
Peak-to-peak
Rise/Fall Time
2.2
25
ns
400
mV
10Base-T Receive
VSQ
Squelch Threshold
February 4, 2015
5MHz square wave
43
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Timing Diagrams
Figure 9. MII SQE Timing (10Base-T)
Table 7. MII SQE Timing (10Base-T) Parameters
Timing Parameter
Description
tP
TXC Period
400
ns
tWL
TXC Pulse Width Low
200
ns
tWH
TXC Pulse Width High
200
ns
tSQE
COL (SQE) Delay After TXEN De-Asserted
2.5
us
tSQEP
COL (SQE) Pulse Duration
1.0
us
February 4, 2015
Min.
44
Typ.
Max.
Unit
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
MII Transmit Timing (10Base-T)
Figure 10. MII Transmit Timing (10Base-T)
Table 8. MII Transmit Timing (10Base-T) Parameters
Timing Parameter
Description
tP
TXC Period
400
ns
tWL
TXC Pulse Width Low
200
ns
tWH
TXC Pulse Width High
200
ns
tSU1
TXD[3:0] Setup to Rising Edge of TXC
10
ns
tSU2
TXEN Setup to Rising Edge of TXC
10
ns
tHD1
TXD[3:0] Hold from Rising Edge of TXC
0
ns
tHD2
TXEN Hold from Rising Edge of TXC
0
ns
tCRS1
TXEN High to CRS Asserted Latency
160
ns
tCRS2
TXEN Low to CRS De-Asserted Latency
510
ns
February 4, 2015
Min.
45
Typ.
Max.
Unit
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
MII Receive Timing (10Base-T)
Figure 11. MII Receive Timing (10Base-T)
Table 9. MII Receive Timing (10Base-T) Parameters
Timing Parameter
Description
tP
RXC Period
400
ns
tWL
RXC Pulse Width Low
200
ns
tWH
RXC Pulse Width High
200
ns
tOD
(RXD[3:0], RXER, RXDV) Output Delay from Rising Edge of RXC
tRLAT
CRS to (RXD[3:0], RXER, RXDV) Latency
February 4, 2015
Min.
Typ.
182
225
6.5
46
Max.
Unit
ns
us
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
MII Transmit Timing (100Base-TX)
Figure 12. MII Transmit Timing (100Base-TX)
Table 10. MII Transmit Timing (100Base-TX) Parameters
Timing Parameter
Description
tP
TXC Period
40
ns
tWL
TXC Pulse Width Low
20
ns
tWH
TXC Pulse Width High
20
ns
tSU1
TXD[3:0] Setup to Rising Edge of TXC
10
ns
tSU2
TXEN Setup to Rising Edge of TXC
10
ns
tHD1
TXD[3:0] Hold from Rising Edge of TXC
0
ns
tHD2
TXEN Hold from Rising Edge of TXC
0
ns
tCRS1
TXEN High to CRS Asserted Latency
34
ns
tCRS2
TXEN Low to CRS De-Asserted Latency
33
ns
February 4, 2015
Min.
47
Typ.
Max.
Unit
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
MII Receive Timing (100Base-TX)
Figure 13. MII Receive Timing (100Base-TX)
Table 11. MII Receive Timing (100Base-TX) Parameters
Timing Parameter
Description
tP
RXC Period
40
ns
tWL
RXC Pulse Width Low
20
ns
tWH
RXC Pulse Width High
tOD
(RXD[3:0], RXER, RXDV) Output Delay from Rising Edge of RXC
tRLAT
February 4, 2015
Min.
Typ.
Max.
20
19
Unit
ns
25
ns
CRS to RXDV Latency
140
ns
CRS to RXD[3:0] Latency
52
ns
CRS to RXER Latency
60
ns
48
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
RMII Timing
Figure 14. RMII Timing – Data Received from RMII
Figure 15. RMII Timing – Data Input to RMII
Table 12. RMII Timing Parameters – KSZ8041NL
Timing Parameter
Description
Min.
Typ.
Max.
tcyc
Clock Cycle
t1
Setup Time
4
ns
t2
Hold Time
2
ns
tod
Output Delay
3
20
Unit
ns
9
ns
Max.
Unit
Table 13. RMII Timing Parameters – KSZ8041RNL
Timing Parameter
Description
tcyc
Clock Cycle
t1
Setup Time
4
ns
t2
Hold Time
1
ns
tod
Output Delay
9
February 4, 2015
Min.
Typ.
20
49
11
ns
13
ns
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Auto-Negotiation Timing
Figure 16. Auto-Negotiation Fast Link Pulse (FLP) Timing
Table 14. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Timing Parameter
Description
tBTB
FLP Burst to FLP Burst
tFLPW
FLP Burst Width
tPW
Clock/Data Pulse Width
tCTD
Clock Pulse to Data Pulse
55.5
64
69.5
µs
tCTC
Clock Pulse to Clock Pulse
111
128
139
µs
Number of Clock/Data Pulse per FLP Burst
17
February 4, 2015
50
Min.
Typ.
Max.
Units
8
16
24
ms
2
ms
100
ns
33
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
MDC/MDIO Timing
Figure 17. MDC/MDIO Timing
Table 15. MDC/MDIO Timing Parameters
Timing Parameter
Description
tP
MDC Period
Min.
Typ.
400
Max.
Unit
ns
t1MD1
MDIO (PHY Input) Setup to Rising Edge of MDC
10
ns
tMD2
MDIO (PHY Input) Hold from Rising Edge of MDC
4
ns
tMD3
MDIO (PHY Output) Delay from Rising Edge of MDC
February 4, 2015
51
222
ns
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Power-Up/Reset Timing
The KSZ8041NL/RNL reset timing requirement is summarized in the following figure and table.
Figure 18. Power-Up/Reset Timing
Table 16. Power-Up/Reset Timing Parameters
Parameter
Description
Min
Max
Units
tVR
Supply Voltage (VDDIO_3.3, VDDA_3.3) Rise Time
250
µs
tsr
Stable Supply Voltage to Reset High
10
ms
tcs
Configuration Setup Time
5
ns
tch
Configuration Hold Time
5
ns
trc
Reset to Strap-In Pin Output
6
ns
The supply voltage (VDDIO_3.3 and VDDA_3.3) power-up waveform should be monotonic. The 250µs minimum rise time is from
10% to 90%.
After the de-assertion of reset, it is recommended to wait a minimum of 100µs before starting programming on the MIIM
(MDC/MDIO) Interface.
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Reset Circuit
The reset circuit in Figure 19 is recommended for powering up the KSZ8041NL/RNL if reset is triggered by the power
supply.
3.3V
D1: 1N4148
D1
KSZ8041NL/RNL
R 10K
RST#
C 10uF
Figure 19. Recommended Reset Circuit
The reset circuit in Figure 20 is recommended for applications where reset is driven by another device (e.g., CPU or
FPGA). At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8041NL/RNL device. The
RST_OUT_n from CPU/FPGA provides the warm reset after power-up.
3.3V
KSZ8041NL/RNL
R 10K
D1
CPU/FPGA
RST#
RST_OUT_n
D2
C 10uF
D1, D2: 1N4148
Figure 20. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output.
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Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Reference Circuits for LED Strapping Pins
The Figure 21 shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins.
3.3V
Pull-up
4.7ΚΩ
220Ω
ΚSZ8041NL/RNL
LED pin
3.3V
Float
220Ω
ΚSZ8041NL/RNL
LED pin
3.3V
Pull-down
220Ω
ΚSZ8041NL/RNL
LED pin
1Κ
Ω
Figure 21. Reference Circuits for LED Strapping Pins
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Micrel, Inc.
KSZ8041NL/RNL
Selection of Isolation Transformer
A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes
is recommended for exceeding FCC requirements.
Table 17 gives recommended transformer characteristics.
Table 17. Transformer Selection Criteria
Parameter
Value
Test Condition
Turns Ratio
1 CT : 1 CT
Open-Circuit Inductance (minimum)
350µH
100mV, 100kHz, 8mA
Leakage Inductance (maximum)
0.4µH
1MHz (minimum)
Inter-Winding Capacitance (typical)
12pF
DC Resistance (typical)
0.9Ω
−1.0dB
Insertion Loss (maximum)
HIPOT (minimum)
0MHz – 65MHz
1500Vrms
Table 18. Qualified Single Port Magnetics
Magnetic Manufacturer
Part Number
Auto MDI-X
Number of Port
Bel Fuse
S558-5999-U7
Yes
1
Bel Fuse (Mag Jack)
SI-46001
Yes
1
Bel Fuse (Mag Jack)
SI-50170
Yes
1
LF8505
Yes
1
LF-H41S
Yes
1
Pulse
H1102
Yes
1
Pulse (low cost)
H1260
Yes
1
Transpower
HB726
Yes
1
TLA-6T718
Yes
1
Delta
LanKom
TDK (Mag Jack)
Selection of Reference Crystal
Table 19. Typical Reference Crystal Characteristics
Characteristics
Value
Units
Frequency
25
MHz
Frequency Tolerance (maximum)
±50
ppm
Load Capacitance
20
pF
Series Resistance
40
Ω
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55
Revision 1.5
Micrel, Inc.
KSZ8041NL/RNL
Package Information and Recommended Landing Pattern(8)
32-Pin 5mm × 5mm QFN
Note:
18. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
February 4, 2015
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Revision 1.5
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KSZ8041NL/RNL
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timing & communications
markets. The Company’s products include advanced mixed-signal, analog & power semiconductors; high-performance communication, clock
management, MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs. Company
customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products.
Corporation headquarters and state-of-the-art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and
advanced technology design centers situated throughout the Americas, Europe, and Asia. Additionally, the Company maintains an extensive network
of distributors and reps worldwide.
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this datasheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
February 4, 2015
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