BM6101FV-C : Power Management

Datasheet
Gate Driver Providing Galvanic isolation Series
Isolation voltage 2500Vrms
1ch Gate Driver Providing Galvanic Isolation
BM6101FV-C
●General Description
The BM6101FV-C is a gate driver with isolation voltage
2500Vrms, I/O delay time of 350ns, and minimum input
pulse width of 180ns, and incorporates the fault signal
output functions, undervoltage lockout (UVLO) function,
thermal protection function, and short current protection
(SCP, DESAT) function.
●Features
 Providing Galvanic Isolation
 Active Miller Clamping
 Fault signal output function
(Adjustable output holding time)
 Undervoltage lockout function
 Thermal protection function
 Short current protection function
(Adjustable reset time)
 Soft turn-off function for short current protection
(Adjustable turn-off time)
 Supporting Negative VEE
 UL1577 Recognized:File No. E356010
(Note 1)
 AEC-Q100 Qualified
(Note 1:Grade1)
●Key Specifications
 Isolation voltage:
 Maximum gate drive voltage:
 I/O delay time:
 Minimum input pulse width:
●Package
SSOP-B20W
2500Vrms(Max.)
24V(Max.)
350ns(Max.)
180ns(Max.)
W(Typ.) x D(Typ.) x H(Max.)
6.50mm x 8.10mm x 2.01mm
●Applications
■
Automotive isolated IGBT/MOSFET inverter gate drive
■
Automotive DC-DC converter
■
Industrial inverters system
■
UPS system
●Typical Application Circuits
GND1
PROOUT
LOGIC
S
PRE
DRIVER
Q
INB
OUT1
R
MASK
FLTRLS
VCC2
LOGIC
VCC1
UVLO
FLT
FB
MASK
TIMER
INA
ECU
FLT
ENA
CFLT RLS
CVCC1
VEE2
FLT
TIMER
VEE2
OUT2
MASK
SCPIN
MASK
MASK
TEST
Input side
chip
MASK
GND1
VREG
UVLO
CVCC2
RFLT RLS
NC
GND2
VEE2
Output side
chip
VTSIN
Temp Sensor
Figure 1. For using 4-pin IGBT (for using SCP function)
GND1
PROOUT
LOGIC
S
Q
R
MASK
FLTRLS
VCC1
MASK
TIMER
INA
ECU
CFLTRLS
ENA
C VCC1
VCC2
LOGIC
UVLO
FB
FLT
VEE2
OUT1
FLT
TIMER
FLT
VEE2
VREG
UVLO
OUT2
MASK
SCPIN
MASK
VCC2
R
INB
PRE
DRIVER
C
FLTRLS
NC
GND2
MASK
TEST
GND1
MASK
Input side
chip
Output side
chip
VEE2
VTSIN
Temp Sensor
Figure 2. For using 3-pin IGBT (for using DESAT function)
○Product structure：Silicon integrated circuit ○This product is not designed protection against radioactive rays
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●Recommended range of external constants
Pin Name
Recommended Value
Symbol
Min.
Typ.
Max.
Unit
CFLTRLS
-
0.01
0.47
uF
RFLTRLS
50
200
1000
kΩ
VREG
CVREG
1.0
3.3
10.0
uF
VCC1
CVCC1
0.1
1.0
-
uF
VCC2
CVCC2
0.33
-
-
uF
FLTRLS
●Pin Configuration
SSOP-B20W
(TOP VIEW)
1pin
Figure 3. Pin configuration
●Pin Description
Pin No.
Pin Name
Function
1
VTSIN
Thermal detection pin
2
VEE2
Output-side negative power supply pin
3
GND2
Output-side ground pin
4
SCPIN
Short current detection pin
5
OUT2
MOS FET control pin for Miller Clamp
6
VREG
Power supply pin for driving MOS FET for Miller Clamp
7
VCC2
Output-side positive power supply pin
8
OUT1
Output pin
9
VEE2
Output-side negative power supply pin
10
PROOUT
11
GND1
12
NC
Soft turn-off pin
Input-side ground pin
No Connect
13
INB
14
FLTRLS
Invert / non-invert selection pin
15
VCC1
16
FLT
Fault output pin
17
INA
Control input pin
18
ENA
Input enabling signal input pin
19
TEST
Mode setting pin
20
GND1
Input-side ground pin
Fault output holding time setting pin
Input-side power supply pin
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●Description of pins and cautions on layout of board
1) VCC1 (Input-side power supply pin)
The VCC1 pin is a power supply pin on the input side. To suppress voltage fluctuations due to the current to drive
internal transformers, connect a bypass capacitor between the VCC1 and the GND1 pins.
2) GND1 (Input-side ground pin)
The GND1 pin is a ground pin on the input side.
3) VCC2 (Output-side positive power supply pin)
The VCC2 pin is a positive power supply pin on the output side. To reduce voltage fluctuations due to OUT1 pin output
current and due to the current to drive internal transformers, connect a bypass capacitor between the VCC2 and the
GND2 pins.
4) VEE2 (Output-side negative power supply pin)
The VEE2 pin is a power supply pin on the output side. To suppress voltage fluctuations due to OUT1 pin output current and
due to the current to drive internal transformers, connect a bypass capacitor between the VEE2 and the GND2 pins. To use
no negative power supply, connect the VEE2 pin to the GND2 pin.
5) GND2 (Output-side ground pin)
The GND2 pin is a ground pin on the output side. Connect the GND2 pin to the emitter / source of a power device.
6) IN (Control input terminal)
The IN pin is a pin used to determine output logic.
ENA
INB
INA
H
X
X
L
L
L
L
L
H
L
H
L
L
H
H
OUT1
L
L
H
H
L
7) FLT (Fault output pin)
The FLT pin is an open drain pin used to output a fault signal when a fault occurs (i.e., when the undervoltage lockout
function (UVLO), short current protection function (SCP) or thermal protection function is activated).
This pin is I/O pin and if L voltage is externally input, the output is set to L status regardless of other input logic.
Consequently, be sure to connect the pull-up resistor between VCC1 pin and the FLT pin even if this pin is not used.
Pin
FLT
While in normal operation
Hi-Z
When an Fault occurs
L
(When UVLO, SCP or thermal protection is activated)
8) FLTRLS (Fault output holding time setting pin)
The FLTRLS pin is a pin used to make setting of time to hold a Fault signal. Connect a capacitor between the FLTRLS
pin and the GND1 pin, and a resistor between it and the VCC1 pin.
The Fault signal is held until the FLTRLS pin voltage exceeds a voltage set with the V FLTRLS parameter. To set holding
time to 0 ms, do not connect the capacitor. Short-circuiting the FLTRLS pin to the VCC1 pin will cause a high current to
flow in the FLTRLS pin and, in an open state, may cause the IC to malfunction. To avoid such trouble, be sure to connect
a resistor between the FLTRLS and the VCC1 pins.
9) OUT1 (Output pin)
The OUT1 pin is a pin used to drive the gate of a power device.
10) OUT2 (MOS FET control pin for Miller Clamp)
The OUT2 pin is a pin for controlling the external MOS switch for preventing increase in gate voltage due to the miller
current of the power device connected to OUT1 pin.
11) VREG (Power supply pin for driving MOS FET for Miller Clamp)
The VREG pin is a power supply pin for driving MOS FET for Miller Clamp. Be sure to connect a capacitor between
VREG pin and VEE2 pin for preventing the oscillation and to reduce voltage fluctuations due to OUT2 pin output current.
12) PROOUT (Soft turn-off pin)
The PROOUT pin is a pin used to put the soft turn-off function of a power devise in operation when the SCP function is
activated. This pin combines with the gate voltage monitoring pin for Miller Clamp.
13) SCPIN (Short current detection pin)
The SCPIN pin is a pin used to detect current for short current protection. When the SCPIN pin voltage exceeds a
voltage set with the VSCDET parameter, the SCP function will be activated. This may cause the IC to malfunction in an
open state. To avoid such trouble, short-circuit the SCPIN pin to the GND2 pin if the short current protection is not used.
In order to prevent the wrong detection due to noise, the noise mask time t SCPMSK is set.
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14) VTSIN (Thermal detection pin)
The VTSIN pin is a temperature sensor voltage input pin, which can be used for thermal protection of an output device.
If VTSIN pin voltage becomes VTSDET or less, OUT pin is set to L. In the open status, the IC may malfunction, so be sure
to supply the VTSPIN more than VTSDET if the thermal protection function is not used. In order to prevent the wrong
detection due to noise, the noise mask time tTSMSK is set.
15) TEST(Mode setting pin)
The TEST pin is an operation mode setting pin. This pin is usually connected to GND1 pin. If the TEST pin is
connected to the VCC1 pin, Input-side UVLO function is disabled.
●Description of functions and examples of constant setting
1) Miller Clamp function
When OUT1=L and PROOUT pin voltage < VOUT2ON, H is output from OUT2 pin and the external MOS switch is turned
ON. When OUT1=H, L is output from OUT2 pin and the external MOS switch is turned OFF. While the short-circuit
protection function is activated, L is output from OUT2 pin and the external MOS switch is turned OFF.
Short current
SCPIN
IN
PROOUT
OUT2
Detected
Not less than
VSCDET
X
X
L
X
L
Not less than VOUT2ON
Hi-Z
X
L
Not more than VOUT2ON
H
X
H
X
L
Not detected
VCC2
PREDRIV ER
OUT1
PREDRIV ER
PROOUT
PREDRIV ER
LOGIC
VREG
REGULATOR
PREDRIV ER
OUT2
PREDRIV ER
VOUT2ON
+
GND2
VEE2
Figure 4. Block diagram of Miller Clamp function
tPOFF
tPON
IN
OUT1
PROOUT
(Monitor the gate voltage)
VOUT2ON
tOUT2ON
OUT2
Figure 5. Timing chart of Miller Clamp function
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2) Fault status output
This function is used to output a fault signal from the FLT pin when a fault occurs (i.e., when the undervoltage lockout
function (UVLO), short current protection function (SCP) or thermal protection function is activated) and hold the Fault
signal until the set Fault output holding time is completed. The Fault output holding time t FLTRLS is given as the following
equation with the settings of capacitor CFLTRLS and resistor RFLTRLS connected to the FLTRLS pin. For example, when
CFLTRLS is set to 0.01F and RFLTRLS is set to 200k, the holding time will be set to 2 ms.
tFLTRLS [ms]= CFLTRLS [F]•RFLTRLS [k]
To set the fault output holding time to “0” ms, only connect the resistor RFLTRLS.
Status
FLT pin
Normal
Hi-Z
Fault occurs
L
Fault occurs
(The UVLO, SCP or thermal protection)
Status
UVLO
SCP
VFLTRLS
VTS
C FLTRLS RFLTRLS
FLTRLS
Hi-Z
FLT
L
H
MASK
MASK
MASK
FLT
S
R
VCC1
FLTRLS
-
+
FLT
MASK
OUT
L
ECU
Fault output holding time (tFLTRLS)
Figure 6. Fault Status Output Timing Chart
LOGIC
GND1
Figure
7. Fault
Output Block Diagram
Fig.3
エラー出力ブロック図
3) Undervoltage Lockout (UVLO) function
The BM6101FV-C incorporates the undervoltage lockout (UVLO) function both on the low and the high voltage sides.
When the power supply voltage drops to the UVLO ON voltage, the OUT pin and the FLT pin both will output the “L”
signal. When the power supply voltage rises to the UVLO OFF voltage, these pins will be reset. However, during the fault
output holding time set in “2) Fault status output” section, the OUT pin and the FLT pin will hold the “L” signal. In addition,
to prevent malfunctions due to noises, mask time tUVLO1MSK and tUVLO2MSK are set on both low and high voltage sides.
H
L
IN
VUVLO1H
VUVLO1L
VCC1
FLT
OUT1
Figure 8. Input-side UVLO Function Operation Timing Chart
Hi-Z
L
H
L
H
L
IN
VUVLO2H
VUVLO2L
VCC2
Hi-Z
L
H
Hi-Z
L
FLT
OUT1
Figure 9. Output-side UVLO Operation Timing Chart
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4) Short current protection function (SCP, DESAT)
When the SCPIN pin voltage exceeds a voltage set with the VSCDET parameter, the SCP function will be activated.
When the SCP function is activated, the OUT1 pin voltage will be set to the “Hi-Z” level first, and then the PROOUT pin
voltage to the “L” level (soft turn-off).Next, after tSTO has passed after the short-circuit current falls below the threshold
value, OUT pin becomes L and PROOUT pin becomes L. Finally, when the fault output holding time set in “2) fault status
output” section on page 5 is completed, the SCP function will be released.
When OUT1=L or Hi-Z, internal MOSFET connected to SCPIN pin turns ON to discharge CBLANK. When OUT1=H,
internal MOSFET connected to SCPIN turns OFF.
VCOLLECTOR/VDRAIN which Desaturation Protection starts operation (VDESAT) and the blanking time (tBLANK) can be
calculated by the formula below;
R3  R 2
 VFD
R3
R3  R 2  R1
VCC 2MIN V   VSCDET 
R3
R 2  R1
R3  R 2  R1 VSCDET
t BLANKouternals   
 R3  (C BLANK  27  10 12 )  ln(1 

)  0.65  10 6
R3  R 2  R1
R3
VCC 2
VDESAT V   VSCDET 
Reference Value
VDESAT
R1
R2
R3
4.0V
15 kΩ
39 kΩ
6.8 kΩ
4.5V
15 kΩ
43 kΩ
6.8 kΩ
5.0V
15 kΩ
36 kΩ
5.1 kΩ
5.5V
15 kΩ
39 kΩ
5.1 kΩ
6.0V
15 kΩ
43 kΩ
5.1 kΩ
6.5V
15 kΩ
62 kΩ
6.8 kΩ
7.0V
15 kΩ
68 kΩ
6.8 kΩ
7.5V
15 kΩ
82 kΩ
7.5 kΩ
8.0V
15 kΩ
91 kΩ
8.2 kΩ
8.5V
15 kΩ
82 kΩ
6.8 kΩ
9.0V
15 kΩ
130 kΩ
10 kΩ
9.5V
15 kΩ
91 kΩ
6.8 kΩ
10.0V
15 kΩ
130 kΩ
9.1 kΩ
VCC1
R1
VCC2
PREDRIVER
OUT
IN
RFLTRLS
LOGIC
LOGIC
PREDRIVER
PROOUT RSTO
PREDRIVER
S
R2
VTFLTRLS
SCPIN
R3
VSCDET
ECU
C BLANK
SCPMSK
-
CFLTRLS
R
+
FLT
+
FLTRLS
GND1
GND2
VEE2
Input Side
Output Side
Figure 10. Block Diagram for DESAT
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H
L
IN
VSCDET
SCPIN
H
Hi-Z
L
H
Hi-Z
L
OUT1
OUT2
Hi-Z
L
Hi-Z
L
PROOUT
FLT
tSTO
tSTO
Fault output holding time
*7
Fault output holding time
*7: “2)
*7
Fault status output” section on page 5
Figure 11. SCP Operation Timing Chart
INA
OUT1
OUT2
PROOUT
tSCPMSK+t comp_delay
(Typ. 0.95us)
SCPIN
VSCDET (Typ. 0.7V)
tSCPMSK+t comp_delay
VSCDET
FLT
tBLANKouternal
tBLANK
tBLANKouternal
tBLANK
tcomp_delay : Detection delay time of internal comparator
Figure 12. DESAT sequence
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Start
OUT1=L, OUT2=H
No
VSCPIN>VSCDET
No
VFLTRLS>VTFLTRLS
Yes
Yes
No
Exceed mask time
Yes
FLT=Hi-Z
OUT1=Hi-Z, OUT2=L,
PROOUT=L, FLT=L
No
IN=H
No
VSCPIN<VSCDET
Yes
OUT1=H, OUT2=L, PROOUT=Hi-Z
Yes
No
Exceed tSTO
Yes
Figure 13. SCP Operation Status Transition Diagram
VCC2
VCC1
PREDRIVER
OUT
IN
RFLTRLS
LOGIC
LOGIC
PROOUT RSTO
PREDRIVER
S
VTFLTRLS
SCPIN
VSCDET
ECU
RSCP
SCPMSK
-
CFLTRLS
R
+
FLT
+
FLTRLS
PREDRIVER
GND1
GND2
VEE2
Input Side
Output Side
Figure 14. Block Diagram for SCP
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5）I/O condition table
Input
No.
1
2
S
C
P
I
N
F
L
T
E
N
A
I
N
B
I
N
A
P
R
O
O
U
T
O
U
T
1
O
U
T
2
P
R
O
O
U
T
F
L
T
VCC1
VCC2
V
T
S
I
N
X
X
X
H
X
X
X
X
X
Hi-Z
L
L
L
UVLO
X
X
L
X
X
X
X
H
L
Hi-Z
Hi-Z
L
UVLO
X
X
L
X
X
X
X
L
L
H
Hi-Z
L
X
UVLO
X
L
X
X
X
X
H
L
Hi-Z
Hi-Z
L
X
UVLO
X
L
X
X
X
X
L
L
H
Hi-Z
L
○
○
L
L
X
X
X
X
H
L
Hi-Z
Hi-Z
L
○
○
L
L
X
X
X
X
L
L
H
Hi-Z
L
○
○
H
L
L
X
X
X
H
L
Hi-Z
Hi-Z
Hi-Z
○
○
H
L
L
X
X
X
L
L
H
Hi-Z
Hi-Z
○
○
H
L
H
H
X
X
H
L
Hi-Z
Hi-Z
Hi-Z
○
○
H
L
H
H
X
X
L
L
H
Hi-Z
Hi-Z
○
○
H
L
H
L
L
L
H
L
Hi-Z
Hi-Z
Hi-Z
○
○
H
L
H
L
L
L
L
L
H
Hi-Z
Hi-Z
Status
SCP
Output
VCC1UVLO
3
4
VCC2UVLO
5
6
7
Thermal protection
8
9
FLT external input
10
Disable
11
12
13
Non-invert operation
L input
14
Non-invert operation
H input
○
○
H
L
H
L
L
H
X
H
L
Hi-Z
Hi-Z
15
Invert operation L
input
○
○
H
L
H
L
H
L
X
H
L
Hi-Z
Hi-Z
Invert operation H
input
○
○
H
L
H
L
H
H
H
L
Hi-Z
Hi-Z
Hi-Z
○
○
H
L
H
L
H
16
17
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H
L
L
H
Hi-Z Hi-Z
○: VCC1 or VCC2 > UVLO, X:Don't care
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BM6101FV-C
6) Power supply startup / shutoff sequence
H
L
IN
VUVLO1L
VCC1
VCC2
VUVLO2H
VUVLO1L
VUVLO1L
VUVLO2H
VUVLO2H
0V
0V
VEE2
H
Hi-Z
L
H
Hi-Z
L
Hi-Z
L
Hi-Z
L
OUT1
OUT2
PROOUT
FLT
H
L
IN
VCC1
VCC2
VUVLO1L
VUVLO1H
VUVLO2H
VUVLO1H
VUVLO2L
0V
VUVLO2L
VEE2
OUT2
PROOUT
FLT
H
L
IN
VCC1
VUVLO1L
VUVLO2H
VUVLO1L
VUVLO2H
VUVLO1H
0V
VUVLO2L
VEE2
OUT2
PROOUT
FLT
H
L
IN
VCC2
0V
0V
H
Hi-Z
L
H
Hi-Z
L
Hi-Z
L
Hi-Z
L
OUT1
VCC1
0V
0V
H
Hi-Z
L
H
Hi-Z
L
Hi-Z
L
Hi-Z
L
OUT1
VCC2
0V
VUVLO1H
VUVLO1H
VUVLO2L
VUVLO1H
VUVLO2L
VEE2
0V
VUVLO2L
0V
0V
H
Hi-Z
L
H
Hi-Z
L
Hi-Z
L
Hi-Z
L
OUT1
OUT2
PROOUT
FLT
: Since the VCC2 to VEE2 pin voltage is low and the output MOS does not turn ON,
the output pins become Hi-Z conditions.
: Since the VCC1 pin voltage is low and the FLT output MOS does not turn ON, the
output pins become Hi-Z conditions.
Figure 15. Power supply startup / shutoff sequence
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●Absolute Maximum Ratings
Parameter
Symbol
Input-side supply voltage
Limits
VCC1
Output-side positive supply voltage
-0.3 to +7.0
VCC2
Output-side negative supply voltage
VEE2
Maximum difference
between output-side positive and negative voltages
VMAX2
-0.3 to +30.0
V
-15.0 to +0.3
*2
V
36.0
V
VFLT
-0.3 to +VCC1+0.3 or 7.0
*1
V
VFLTRLS
-0.3 to +VCC1+0.3 or 7.0
*1
V
FLT pin input voltage
VVTSIN
-0.3 to +10.0
*2
V
-0.3 to +10.0
*2
V
SCPIN pin input voltage
VSCPIN
VREG pin output current
IVREG
10
OUT1 pin output current (DC)
IOUT1
0.4
OUT1 pin output current (Peak 1us)
IOUT1PEAK
OUT2 pin output current (DC)
0.1
IOUT2PEAK
PROOUT pin output current
*3
A
A
*3
A
1
IPROOUT
FLT output current
mA
5.0
IOUT2
OUT2 pin output current (Peak 1us)
V
*1
VIN
VTSIN pin input voltage
V
*2
-0.3 to +VCC1+0.3 or 7.0
INA, INB, ENA pin input voltage
FLTRLS pin input voltage
Unit
*1
0.2
IFLT
A
*3
A
10
1.19
mA
*4
Power dissipation
Pd
W
Operating temperature range
Topr
-40 to +125
℃
Storage temperature range
Tstg
-55 to +150
℃
Junction temperature
Tjmax
+150
℃
*1 Relative to GND1.
*2 Relative to GND2.
*3 Should not exceed Pd and Tj=150C.
*4 Derate above Ta=25C at a rate of 9.5mW/C. Mounted on a glass epoxy of 70 mm  70 mm  1.6 mm.
●Recommended Operating Ratings
Parameter
Symbol
Min.
Max.
Units
VCC1
*5
4.5
5.5
V
VCC2
*6
14
24
V
Output-side negative supply voltage
VEE2
*6
-12
0
V
Maximum difference
between output-side positive and negative voltages
VMAX2
14
32
V
0
5
V
Input-side supply voltage
Output-side positive supply voltage
VTSIN pin input voltage
VVTSIN
*6
*5 Relative to GND1.
*6 Relative to GND2.
●Insulation related characteristics
Parameter
Symbol
Characteristic
Insulation Resistance (VIO=500V)
RS
>10
Insulation Withstand Voltage / 1min
VISO
2500
Vrms
Insulation Test Voltage / 1sec
VISO
3000
Vrms
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
11/31
9
Units
Ω
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
BM6101FV-C
●Electrical Characteristics
（Unless otherwise specified Ta=-40℃ to 125℃, V CC1=4.5V to 5.5V, VCC2=14V to 24V, VEE2=-12V to 0V）
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
General
Input side circuit current 1
ICC1
0.20
0.45
0.70
mA
OUT=L
Input side circuit current 2
Input side circuit current 3
ICC12
ICC13
0.20
1.2
0.45
2.0
0.70
2.8
mA
mA
OUT=H
INA=10kHz, Duty=50%
Input side circuit current 4
Output side circuit current 1
ICC14
ICC21
2.1
1.9
3.5
3.2
4.9
4.5
mA
mA
INA=20kHz, Duty=50%
VCC2=14V, OUT=L
Output side circuit current 2
Output side circuit current 3
ICC22
ICC23
1.3
2.1
2.1
3.5
2.9
4.9
mA
mA
VCC2=14V, OUT=H
VCC2=18V, OUT=L
Output side circuit current 4
Output side circuit current 5
ICC24
ICC25
1.4
2.4
2.4
4.0
3.4
5.6
mA
mA
VCC2=18V, OUT=H
VCC2=24V, OUT=H
Output side circuit current 6
Logic block
Logic high level input voltage
Logic low level input voltage
ICC26
1.6
2.7
3.8
mA
VCC2=24V, OUT=L
VINH
VINL
0.7×VCC1
0
-
VCC1
0.3×VCC1
V
V
INA, INB, ENA, FLT
INA, INB, ENA, FLT
Logic pull-down resistance
Logic pull-up resistance
RIND
RINU
25
25
50
50
100
100
kΩ
kΩ
INA, INB
ENA
tINMSK
tFLTMSK
80
4
130
10
180
20
ns
μs
INA, INB
ENA, FLT
Output
OUT1 ON resistance (Source)
RONH
0.7
1.8
4.0
Ω
IOUT=40mA
OUT1 ON resistance (Sink)
RONL
0.4
0.9
2.0
Ω
OUT1 maximum current
IOUTMAX
3.0
4.5
-
A
PROOUT ON resistance
Turn ON time
RONPRO
tPON
0.4
0.9
2.0
180
265
350
Ω
ns
IOUT=40mA
VCC2=18V
Design assurance
IPROOUT=40mA
Turn OFF time
tPOFF
180
265
350
ns
Propagation distortion
Rise time
tPDIST
tRISE
-60
-
0
50
60
100
ns
ns
tPOFF - tPON
Fall time
OUT2 ON resistance (Source)
tFALL
RON2H
RON2L
2.0
50
4.5
100
9.0
10nF between OUT1-VEE2
3.5
2
7.0
2.2
ns
Ω
Ω
V
Relative to VEE2
Logic input mask time
ENA, FLT mask time
10nF between OUT1-VEE2
IOUT2=40mA
IOUT2=40mA
OUT2 ON resistance (Sink)
OUT2 ON threshold voltage
VOUT2ON
1.5
1.8
OUT2 output delay time
VREG output voltage
tOUT2ON
VREG
9
15
10
50
11
ns
V
Relative to VEE2
CM
100
-
-
kV/μs
Design assurance
VCC1 UVLO OFF voltage
VCC1 UVLO ON voltage
VUVLO1H
VUVLO1L
4.05
3.95
4.25
4.15
4.45
4.35
V
V
VCC1 UVLO mask time
VCC2 UVLO OFF voltage
tUVLO1MSK
VUVLO2H
4
11.5
10
12.5
30
13.5
μs
V
VCC2 UVLO ON voltage
VCC2 UVLO mask time
VUVLO2L
tUVLO2MSK
10.5
4
11.5
10
12.5
30
V
μs
SCPIN Input voltage
SCP detection voltage
VSCPIN
VSCDET
0.665
0.1
0.700
0.22
0.735
V
V
SCP detection mask time
Soft turn OFF release time
tSCPMSK
tSTO
0.55
30
0.8
1.05
110
μs
Thermal detection voltage
Thermal detection mask time
VTSDET
tTSMSK
1.60
4
1.70
10
1.80
30
V
μs
VFLTL
0.64×VCC1
-0.1
0.18
0.40
0.64×VCC1
+0.1
V
Common Mode Transient Immunity
Protection functions
FLT output low voltage
FLTRLS threshold
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
VTFLTRLS
0.64×VCC1
12/31
ISCPIN=1mA
IFLT=5mA
V
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
BM6101FV-C
50%
INA
50%
tPON
tPOFF
90%
50%
OUT1
90%
10%
tFALL
tRISE
50%
10%
Figure 16. INA-OUT1 Timing Chart
●Typical Performance Curves
0.7
0.7
Ta=125℃
0.6
ICC11 [mA]
ICC11 [mA]
0.6
0.5
0.4
0.5
0.4
Vcc1=5.5V
Vcc1=5.0V
Vcc1=4.5V
Ta=25℃
0.3
0.3
Ta=-40℃
0.2
4.50
0.2
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 17. Input side circuit current (at OUT1=L)
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TSZ22111・15・001
13/31
-40
-20
0
20
40
60
Ta [℃]
80
100
120
Figure 18. Input side circuit current (at OUT1=L)
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
BM6101FV-C
0.7
0.7
0.6
0.6
ICC12 [mA]
ICC12 [mA]
Ta=125℃
0.5
0.4
0.5
0.4
Vcc1=5.5V
Vcc1=5.0V
Ta=25℃
Vcc1=4.5V
0.3
0.3
Ta=-40℃
0.2
4.50
0.2
4.75
5.00
VCC1 [V]
5.25
5.50
-40
Figure 19. Input side circuit current (at OUT1=H)
-20
0
20
80
100
120
Figure 20. Input side circuit current (at OUT1=H)
2.8
2.8
Ta=-40℃
Vcc1=5.5V
2.4
2.4
ICC13 [mA]
ICC13 [mA]
40
60
Ta [℃]
2.0
2.0
Vcc1=5.0V
Ta=25℃
1.6
1.6
Vcc1=4.5V
Ta=125℃
1.2
4.50
1.2
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 21. Input side circuit current
(at INA=10kHz and Duty=50%)
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
-40
-20
0
20
40
60
Ta [℃]
80
100
120
Figure 22. Input side circuit current
(at INA=10kHz and Duty=50%)
14/31
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
BM6101FV-C
4.9
4.9
4.5
4.5
Ta=-40℃
Vcc1=5.5V
4.1
ICC14 [mA]
ICC14 [mA]
4.1
3.7
3.3
2.9
3.7
3.3
2.9
Vcc1=4.5V
Ta=25℃
2.5
2.1
4.50
Vcc1=5.0V
2.5
Ta=125℃
2.1
4.75
5.00
VCC1 [V]
5.25
5.50
-40
Figure 23. Input side circuit current
(at INA=20kHz and Duty=50%)
-20
0
20
40
60
Ta [℃]
80
100
120
Figure 24. Input side circuit current
(at INA=20kHz and Duty=50%)
5.6
5.6
5.2
5.2
4.8
4.8
Ta=125℃
4.4
4.4
4.0
4.0
ICC2x [mA]
ICC2x [mA]
Vcc2=24V
3.6
3.2
2.8
Ta=-40℃
2.4
3.6
3.2
2.8
Ta=25℃
2.0
2.0
1.6
1.6
1.2
1.2
14
16
18
20
VCC2 [V]
22
24
Figure 25. Output side circuit current (at
OUT1=L)
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
Vcc2=14V
2.4
-40
-20
0
20
Vcc2=18V
40
60
Ta [℃]
80
100
120
Figure 26. Output side circuit current (at OUT1=L)
15/31
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
5.6
5.6
5.2
5.2
4.8
4.8
4.4
4.4
4.0
4.0
3.6
ICC2x [mA]
ICC2x [mA]
BM6101FV-C
Ta=125℃
3.2
3.2
2.8
2.8
2.4
2.4
2.0
2.0
Ta=25℃
1.6
Vcc2=24V
3.6
Vcc2=18V
1.6
Vcc2=14V
Ta=-40℃
1.2
1.2
14
16
18
20
VCC2 [V]
22
-40
24
Figure 27. Output side circuit current (at OUT1=H)
-20
0
20
40
60
Ta [℃]
80
100
120
Figure 28. Output side circuit current (at OUT1=H)
24
5.0
4.5
Ta=125℃
Ta=25℃
Ta=-40℃
4.0
Vcc1=5V
16
H level
3.0
OUT1 [V]
VINH / VINL [V]
3.5
20
2.5
2.0
12
L level
1.5
8
Ta=-40℃
Ta=25℃
Ta=125℃
1.0
4
0.5
0.0
4.50
0
4.75
5.00
VCC1 [V]
5.25
5.50
1
2
3
4
INA [V]
Figure 29. Logic (INA/INB/ENA) High/Low level
input voltage
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
0
Figure 30. Logic (INA/INB/ENA) High/Low level
input voltage at Ta=25℃
16/31
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
5
BM6101FV-C
75.0
75.0
RINU [kΩ ]
100.0
RIND [kΩ ]
100.0
Ta=-40℃
50.0
Ta=-40℃
50.0
25.0
4.50
4.75
Ta=25℃
Ta=25℃
Ta=125℃
Ta=125℃
5.00
VCC1 [V]
5.25
25.0
4.50
5.50
Figure 31. Logic pull-down resistance
4.75
5.00
VCC1 [V]
180.0
160.0
160.0
Ta=125℃
Ta=125℃
tINMSK [ns]
tINMSK [ns]
5.50
Figure 32. Logic pull-up resistance
180.0
140.0
120.0
5.25
Ta=25℃
140.0
120.0
Ta=-40℃
Ta=25℃
Ta=-40℃
100.0
100.0
80.0
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 33. Logic (INA/INB) input mask time
(High pulse)
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
80.0
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 34. Logic (INA/INB) input mask time
(Low pulse)
17/31
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
20
20
16
16
tFLTMSK [us]
tFLTMSK [us]
BM6101FV-C
Ta=-40℃
12
8
Ta=-40℃
12
8
Ta=25℃
Ta=25℃
Ta=125℃
4
4.50
4.75
5.00
VCC1 [V]
Ta=125℃
5.25
4
4.50
5.50
Figure 35. ENA input mask time
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 36. FLT input mask time
2.0
3.7
1.6
3.1
Ta=125℃
RONL [Ω ]
RONH [Ω ]
Ta=125℃
2.5
Ta=25℃
1.2
Ta=25℃
1.9
0.8
Ta=-40℃
1.3
Ta=-40℃
0.4
0.7
14
16
18
20
VCC2 [V]
22
24
Figure 37. OUT1 ON resistance (Source)
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
14
16
18
20
VCC2 [V]
22
24
Figure 38. OUT1 ON resistance (Sink)
18/31
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
BM6101FV-C
2.0
340
Ta=125℃
1.2
Ta=25℃
Ta=125℃
Ta=-40℃
300
tPON [n]
RONPRO [Ω ]
1.6
260
Ta=25℃
0.8
220
Ta=-40℃
0.4
180
14
16
18
20
VCC2 [V]
22
24
14
Figure 39. PROOUT ON resistance
16
18
20
VCC2 [V]
22
24
Figure 40. Turn ON time
400
100
90
350
Ta=125℃
80
300
tRISE [ns]
tPOFF [ns]
70
Ta=-40℃
Ta=125℃
250
60
50
40
Ta=25℃
30
Ta=25℃
Ta=-40℃
200
20
10
150
0
14
16
18
20
VCC2 [V]
22
24
Figure 41. Turn OFF time
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TSZ22111・15・001
14
16
18
20
VCC2 [V]
22
24
Figure 42. Rise time (10nF between OUT1-VEE2)
19/31
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
BM6101FV-C
9.0
100
90
8.0
80
Ta=125℃
RON2H [Ω ]
tFALL [ns]
Ta=125℃
7.0
70
60
50
40
6.0
Ta=25℃
5.0
Ta=25℃
30
Ta=-40℃
4.0
Ta=-40℃
20
3.0
10
2.0
0
14
16
18
20
VCC2 [V]
22
14
24
16
18
20
VCC2 [V]
22
24
Figure 44. OUT2 ON resistance (Source)
Figure 43. Fall time (10nF between OUT1-VEE2)
2.2
6.5
Ta=125℃
2.1
Ta=125℃
VOUT2ON [V]
RON2L [Ω ]
5.5
4.5
Ta=25℃
3.5
2.0
Ta=25℃
Ta=-40℃
Ta=-40℃
1.9
2.5
1.5
1.8
14
16
18
20
VCC2 [V]
22
24
Figure 45. OUT2 ON resistance (Sink)
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TSZ22111・15・001
14
16
18
20
VCC2 [V]
22
24
Figure 46. OUT2 ON threshold voltage
20/31
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
BM6101FV-C
11.0
50
40
10.5
30
VREG [V]
tOUT2ON [ns]
Ta=-40℃
Ta=125℃
20
10.0
Ta=25℃
Ta=125℃
9.5
10
Ta=25℃
Ta=-40℃
0
9.0
14
16
18
20
VCC2 [V]
22
24
14
Figure 47. OUT2 output delay time
18
20
VCC2 [V]
22
24
Figure 48. VREG output voltage
5
11.0
Vcc2=24V
Vcc2=18V
Vcc2=14V
10.5
4
Ta=125℃
Ta=125℃
Ta=-40℃
Ta=-40℃
Ta=25℃
Ta=25℃
3
FLT [V]
VREG [V]
16
10.0
2
9.5
1
9.0
-40
-20
0
20
40 60
Ta [℃]
80
0
3.95
100 120
Figure 49. VREG output voltage
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TSZ22111・15・001
4.05
4.15
4.25
VCC1 [V]
4.35
4.45
Figure 50. VCC1 UVLO ON/OFF voltage
21/31
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
BM6101FV-C
6
28
5
4
20
Ta=125℃
Ta=125℃
FLT [V]
tUVLO1MSK [us]
24
16
12
2
8
1
4
-40
-20
0
20
40
60
Ta [℃]
80
100
Ta=25℃
3
Ta=25℃
0
10.5
120
Ta=-40℃
Ta=-40℃
11.5
12.5
13.5
VCC2 [V]
Figure 51. VCC1 UVLO mask time
Figure 52. VCC2 UVLO ON/OFF voltage
(at VCC1=5V)
0.22
28
Ta=125℃
20
VSCPIN [V]
tUVLO2MSK [us]
24
16
Ta=25℃
0.11
Ta=-40℃
12
8
0.00
4
-40
-20
0
20
40
60
Ta [℃]
80
100
14
120
Figure 53. VCC2 UVLO mask time
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TSZ22111・15・001
Figure 54.
22/31
16
18
20
VCC2 [V]
22
24
SCPIN input voltage (at ISCPIN=1mA)
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
BM6101FV-C
0.73
1.05
0.95
tSCPMSK [us]
VSCDET [V]
Ta=-40℃
Ta=25℃
0.70
Ta=-40℃
0.85
0.75
Ta=25℃
Ta=125℃
Ta=125℃
0.65
0.67
0.55
14
16
18
20
VCC2 [V]
22
24
14
Figure 55. SCP detection voltage
16
18
20
VCC2 [V]
22
24
Figure 56. SCP detection mask time
110
1.8
Vcc2=14V
Vcc2=18V
Vcc2=24V
70
VTSDET [V]
tSTO [us]
90
Vcc2=14V
Vcc2=18V
Vcc2=24V
Ta=25℃
Ta=125℃
Ta=-40℃
1.7
Max.
50
Min.
30
1.6
-40
-20
0
20
40
60
Ta [℃]
80
100 120
Figure 57. Soft turn OFF release time
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TSZ22111・15・001
14
16
18
20
VCC2 [V]
22
24
Figure 58. Thermal detection voltage
23/31
TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
BM6101FV-C
0.4
28.0
Ta=125℃
0.3
20.0
VFLTL [V]
tTSMSK [us]
24.0
Ta=-40℃
16.0
Ta=25℃
0.2
Ta=25℃
Ta=125℃
12.0
0.1
Ta=-40℃
8.0
4.0
14
16
18
20
VCC2 [V]
22
24
Figure 59. Thermal detection mask time
0.0
4.50
4.75
5.00
VCC2 [V]
5.25
5.50
Figure 60. FLT output low voltage (IFLT=5mA)
3.62
Ta=-40℃
Ta=25℃
Ta=125℃
VTFLTRLS [V]
3.41
3.20
2.99
2.78
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 61. FLTRLS threshold
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TSZ22111・15・001
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TSZ02201-0717ABH00090-1-2
20.May.2015 Rev.002
BM6101FV-C
●Selection of Components Externally Connected
Recommended
ROHM
RSR025N3
RSS065N03
Recommended
ROHM
MCR03EZP
GND1
PROOUT
RFLT RLS
NC
S
LOGIC
Q
INB
PRE
DRIVER
OUT1
R
MASK
VEE2
FLTRLS
VCC2
VCC1
FLT
UVLO
FB
MASK
TIMER
FLT
ENA
CFLT RLS
VCC1
C
VREG
UVLO
OUT2
MASK
INA
ECU
VEE2
FLT
TIMER
TEST
Input side
chip
MASK
SCPIN
MASK
MASK
GND1
CVCC2
LOGIC
GND2
VEE2
Output side
chip
VTSIN
Figure 62. For using 4-pin IGBT (for using SCP function)
Temp Sensor
Recommended
ROHM
MCR03EZP
Recommended
ROHM
RSR025N3
RSS065N03
GND1
PROOUT
S
LOGIC
Q
R
INB
PRE
DRIVER
FLTRLS
FLT
CFLTRLS
ENA
C VCC1
VCC2
LOGIC
UVLO
FB
MASK
TIMER
INA
ECU
OUT1
R
MASK
VCC1
VEE2
FLT
FLT
TIMER
VEE2
VREG
UVLO
OUT2
MASK
SCPIN
MASK
VCC2
FLTRLS
NC
C
Recommended
ROHM
MCR03EZP
GND2
MASK
TEST
GND1
MASK
Input side
chip
Output side
chip
VEE2
VTSIN
Temp Sensor
Figure 63. For using 3-pin IGBT (for using DESAT function)
Recommended
ROHM
MCR03EZP
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BM6101FV-C
●Power Dissipation
Measurement machine：TH156（Kuwano Electric）
Measurement condition：ROHM board
3
Board size：70×70×1.6mm
1-layer board：θja=105.3℃/W
Power Dissipation:Pd[W]
1.5
1.19W
1.0
0.5
0
0
25
50
75
100
125
150
Ambient Temperature:Ta[℃]
Figure 64. SSOP-B20W Derating Curve
●Thermal design
Please design that the IC’s chip temperature Tj is not over 150℃, while considering the IC’s power consumption (W),
package power (Pd) and ambient temperature (Ta). When Tj=150℃ is exceeded the functions as a semiconductor do not
operate and some problems (ex. Abnormal operation of various parasitic elements and increasing of leak current) occur.
Constant use under these circumstances leads to deterioration and eventually IC may destruct. Tjmax=150℃ must be strictly
obeyed under all circumstances.
The IC’s consumed power (P) can be estimated roughly with following equation.
2
2
P＝VCC1・ICC1 + VCC2・IGND2 +（VCC2 + VEE2）
・
（ICC2-IGND2）+ ION ・RONH・tON・fPWM + IOFF ・RONL・tOFF・fPWM
fPWM : PWM frequency
ION : OUT pin outflow current when OUT is H state.
tON : Current outflow time from OUT pin when OUT is H state.
IOFF : OUT pin inflow current when OUT is L state.
tOFF : Current inflow time to OUT pin when OUT is L state.
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●I/O equivalence circuits
Name
Pin No.
I/O equivalence circuits
Function
VTSIN
VCC2
Internal pow er supply
1
Thermal detection pin
SCPIN
VTSIN
SCPIN
GND2
Short current detection pin
VEE2
4
VCC2
OUT2
Internal pow er supply
5
MOS FET control pin for Miller Clamp
VREG
VREG
OUT2
Power supply pin for driving MOS FET
for Miller Clamp
VEE2
6
VCC2
OUT
8
OUT1
Output pin
VEE2
VREG
PROOUT
VCC2
10
PROOUT
Soft turn-off pin
VEE2
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BM6101FV-C
Name
Pin No.
I/O equivalence circuits
Function
VCC1
FLTRLS
FLTRLS
14
Fault output holding time setting pin
GND1
VCC1
FLT
FLT
16
Fault output pin
GND1
INB
VCC1
13
Invert / non-invert selection pin
INA, INB
INA
17
Control input pin
GND1
VCC1
ENA
18
ENA
Input enabling signal input pin
GND1
VCC1
TEST
TEST
19
Test mode setting pin
GND1
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●Operational Notes
(1) Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc.,
can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open
circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection
devices, such as fuses.
(2) Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power
supply lines. An external direction diode can be added.
(3) Power supply Lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply
line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply
terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic
capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures.
(4) GND1 Potential
The potential of GND1 pin must be minimum potential in all operating conditions. (Input side ; 11pin to 20pin)
(5) VEE2 Potential
The potential of VEE2 pin must be minimum potential in all operating conditions. (Output side ; 1pin to 10pin)
(6) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
(7) Inter-pin shorts and mounting errors
When attaching to a printed circuit board, pay close attention to the direction of the IC and displacement. Improper
attachment may lead to destruction of the IC. There is also possibility of destruction from short circuits which can be
caused by foreign matter entering between outputs or an output and the power supply or GND.
(8) Operation in a strong electric field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
(9) Inspection of the application board
During inspection of the application board, if a capacitor is connected to a pin with low impedance there is a possibility
that it could cause stress to the IC, therefore an electrical discharge should be performed after each process. Also, as a
measure again electrostatic discharge, it should be earthed during the assembly process and special care should be
taken during transport or storage. Furthermore, when connecting to the jig during the inspection process, the power
supply should first be turned off and then removed before the inspection.
(10) Input terminal of IC
Between each element there is a P+ isolation for element partition and a P substrate. This P layer and each element’s
N layer make up the P-N junction, and various parasitic elements are made up.
For example, when the resistance and transistor are connected to the terminal as shown in figure 65,
○When GND＞(Terminal A) at the resistance and GND＞(Terminal B) at the transistor (NPN), the P-N
junction operates as a parasitic diode.
○Also, when GND＞(Terminal B) at the transistor (NPN), The parasitic NPN transistor operates with the
N layers of other elements close to the aforementioned parasitic diode.
Because of the IC’s structure, the creation of parasitic elements is inevitable from the electrical potential relationship.
The operation of parasitic elements causes interference in circuit operation, and can lead to malfunction and
destruction. Therefore, be careful not to use it in a way which causes the parasitic elements to operate, such as by
applying voltage that is lower than the GND (P substrate) to the input terminal.
Resistor
Transistor (NPN)
Terminal A
Terminal B
C
Terminal B
B
Terminal A
E
N
N
P+
N
P+
P
N
P substrate
Parasitic element
P+
Parasitic
element
N
P+
P
B
N
C
E
P substrate
GND
GND
Parasitic
element
GND
GND
Parasitic
element
Other adjacent elements
Figure 65. Pattern Diagram of Parasitic Element
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(11) Ground Wiring Patterns
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change
the GND wiring pattern potential of any external components, either.
●Ordering Information
B
M
6
1
0
1
F
V
-
Package
FV:SSOP-B20W
Part Number
CE 2
Product class
C : for Automotive applications
Packaging and forming specification
E2: Embossed tape and reel
●Physical Dimension Tape and Reel Information
●Marking Diagram
SSOP-B20W(TOP VIEW)
Part Number Marking
B M 6 1 0 1
LOT Number
1PIN MARK
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BM6101FV-C
●Revision History
Date
Revision
24.Jun.2013
001
20.May.2015
002
Changes
New Release
P.1 Features Adding item (UL1577 Recognized, AEC-Q100 Qualified)
P.4 Description of Pins Adding TEST pin
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Datasheet
Notice
Precaution on using ROHM Products
1.
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001