FEATURES 2-channel, 256-position potentiometers End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ Compact 10-lead MSOP (3 mm × 4.9 mm) package Fast settling time: tS = 5 µs typical on power-up Full read/write of wiper register Power-on preset to midscale Extra package address decode pins: AD0 and AD1 (AD5248 only) Computer software replaces microcontroller in factory programming applications Single supply: 2.7 V to 5.5 V Low temperature coefficient: 35 ppm/°C Low power: IDD = 6 µA maximum Wide operating temperature: −40°C to +125°C Evaluation board available FUNCTIONAL BLOCK DIAGRAMS A1 W1 B1 A2 W2 B2 VDD WIPER REGISTER 1 WIPER REGISTER 2 GND AD5243 SDA 04109-0-001 Data Sheet Dual, 256-Position, I2C-Compatible Digital Potentiometers AD5243/AD5248 PC INTERFACE SCL Figure 1. AD5243 W1 B1 W2 B2 APPLICATIONS VDD RDAC REGISTER 2 RDAC REGISTER 1 GND AD0 AD1 SDA SCL ADDRESS DECODE /8 SERIAL INPUT REGISTER AD5248 04109-0-002 Systems calibrations Electronics level settings Mechanical trimmers replacement in new designs Permanent factory PCB setting Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment Figure 2. AD5248 GENERAL DESCRIPTION The AD5243 and AD5248 provide a compact 3 mm × 4.9 mm packaged solution for dual, 256-position adjustment applications. The AD5243 performs the same electronic adjustment function as a 3-terminal mechanical potentiometer, and the AD5248 performs the same adjustment function as a 2-terminal variable resistor. Available in four end-to-end resistance values (2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ), these low temperature coefficient devices are ideal for high accuracy and stability-variable resistance adjustments. The wiper settings are controllable through the I2C-compatible digital interface. The AD5248 has extra package address decode pins, AD0 and AD1, allowing multiple parts to share the same I2C, 2-wire bus on a PCB. The resistance between 1 the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC latch.1 Operating from a 2.7 V to 5.5 V power supply and consuming less than 6 µA allows the AD5243/AD5248 to be used in portable battery-operated applications. For applications that program the AD5243/AD5258 at the factory, Analog Devices, Inc., offers device programming software running on Windows® NT/2000/XP operating systems. This software effectively replaces the need for external I2C controllers, which in turn enhances the time to market of systems. An AD5243/ AD5248 evaluation kit and software are available. The kit includes a cable and instruction manual. The terms digital potentiometer, VR, and RDAC are used interchangeably. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved. AD5243/AD5248 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits ..................................................................................... 12 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 13 Functional Block Diagrams ............................................................. 1 Programming the Variable Resistor and Voltage ................... 13 General Description ......................................................................... 1 Programming the Potentiometer Divider ............................... 14 Revision History ............................................................................... 2 ESD Protection ........................................................................... 14 Specifications..................................................................................... 3 Terminal Voltage Operating Range ......................................... 14 Electrical Characteristics: 2.5 kΩ Version ................................. 3 Power-Up Sequence ................................................................... 14 Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ Versions.......................................................................................... 4 Layout and Power Supply Bypassing ....................................... 14 Timing Characteristics: All Versions ......................................... 5 I C Interface .................................................................................... 16 Absolute Maximum Ratings............................................................ 6 I2C Compatible, 2-Wire Serial Bus .......................................... 16 ESD Caution .................................................................................. 6 I2C Controller Programming .................................................... 18 Pin Configurations and Function Descriptions ........................... 7 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 19 Constant Bias to Retain Resistance Setting............................. 15 2 REVISION HISTORY 4/12—Rev. A to Rev. B 4/09—Rev. 0 to Rev. A Changes to Rheostat Operation Section, Table 7, and Table 8 ...............................................................................................13 Changes to Voltage Output Operation Section ...........................14 Deleted Evaluation Board Section and Figure 45, Renumbered Sequentially ......................................................................................15 Changes to Table 13 .........................................................................17 Updated Outline Dimensions ........................................................19 Changes to Ordering Guide ...........................................................19 Changes to DC Characteristics—Rheostat Mode Parameter and to DC Characteristics—Potentiometer Divider Mode Parameter, Table 1 ................................................................................................. 3 Moved Figure 3 .................................................................................. 5 Updated Outline Dimensions ........................................................ 19 Changes to Ordering Guide ........................................................... 19 1/04—Revision 0: Initial Version Rev. B | Page 2 of 20 Data Sheet AD5243/AD5248 SPECIFICATIONS ELECTRICAL CHARACTERISTICS: 2.5 kΩ VERSION VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity 2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance 3 Resistance Temperature Coefficient Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE 4 Differential Nonlinearity 5 Integral Nonlinearity5 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range 6 Capacitance A, B 7 Capacitance W7 Shutdown Supply Current 8 Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance7 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation 9 Power Supply Sensitivity DYNAMIC CHARACTERISTICS 10 Bandwidth, −3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Density Symbol Conditions Min Typ 1 Max Unit R-DNL R-INL ∆RAB (∆RAB/RAB )/∆T RWB RWB, VA = no connect RWB, VA = no connect TA = 25°C VAB = VDD, wiper = no connect Code = 0x00, VDD = 5 V −2 −14 −20 ±0.1 ±2 +2 +14 +55 LSB LSB % ppm/°C Ω DNL INL (∆VW/VW)/∆T VWFSE VWZSE VA, VB, VW CA, CB CW IA_SD ICM VIH VIL VIH VIL IIL CIL 35 160 −1.5 −2 Code = 0x80 Code = 0xFF Code = 0x00 −14 0 ±0.1 ±0.6 15 −5.5 4.5 GND f = 1 MHz, measured to GND, code = 0x80 f = 1 MHz, measured to GND, code = 0x80 VDD = 5.5 V VA = VB = VDD/2 VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 200 +1.5 +2 0 12 VDD LSB LSB ppm/°C LSB LSB 45 V pF 60 pF 0.01 1 1 2.4 0.8 2.1 0.6 ±1 5 VDD RANGE IDD PDISS PSS VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = 5 V ± 10%, code = midscale 2.7 ±0.02 BW THDW tS eN_WB Code = 0x80 VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 5 V, VB = 0 V, ±1 LSB error band RWB = 1.25 kΩ, RS = 0 4.8 0.1 1 3.2 3.5 5.5 6 30 ±0.08 µA nA V V V V µA pF V µA µW %/% MHz % µs nV/√Hz Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic. 3 VA = VDD, VB = 0 V, wiper (VW) = no connect. 4 Specifications apply to all VRs. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 7 Guaranteed by design, but not subject to production test. 8 Measured at the A terminal. The A terminal is open circuited in shutdown mode. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use VDD = 5 V. 1 2 Rev. B | Page 3 of 20 AD5243/AD5248 Data Sheet ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < 125°C; unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity 2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance 3 Resistance Temperature Coefficient Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE 4 Differential Nonlinearity 5 Integral Nonlinearity5 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range 6 Capacitance A, B 7 Capacitance W7 Shutdown Supply Current 8 Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance POWER SUPPLIES Power Supply Range Supply Current Power Dissipation Power Supply Sensitivity DYNAMIC CHARACTERISTICS Bandwidth, −3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Density Symbol Conditions Min Typ 1 Max Unit R-DNL R-INL ∆RAB (∆RAB/RAB )/∆T RWB RWB, VA = no connect RWB, VA = no connect TA = 25°C VAB = VDD, wiper = no connect Code = 0x00, VDD = 5 V −1 −2.5 −20 ±0.1 ±0.25 +1 +2.5 +20 LSB LSB % ppm/°C Ω DNL INL (∆VW/VW)/∆T VWFSE VWZSE VA, VB, VW CA, CB CW IA_SD ICM VIH VIL VIH VIL IIL CIL VDD RANGE IDD PDISS PSS BW THDW tS eN_WB 35 160 −1 −1 Code = 0x80 Code = 0xFF Code = 0x00 −2.5 0 ±0.1 ±0.3 15 −1 1 GND f = 1 MHz, measured to GND, code = 0x80 f = 1 MHz, measured to GND, code = 0x80 VDD = 5.5 V VA = VB = VDD/2 VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 200 +1 +1 0 2.5 VDD LSB LSB ppm/°C LSB LSB 45 V pF 60 pF 0.01 1 1 2.4 0.8 2.1 0.6 ±1 5 2.7 5.5 6 30 ±0.08 µA nA V V V V µA pF V µA µW %/% VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = 5 V ± 10%, code = midscale 3.5 RAB = 10 kΩ/50 kΩ/100 kΩ, code = 0x80 VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ VA = 5 V, VB = 0 V, ±1 LSB error band RWB = 5 kΩ, RS = 0 600/100/40 0.1 kHz % 2 9 µs nV/√Hz ±0.02 Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic. 3 VA = VDD, VB = 0 V, wiper (VW) = no connect. 4 Specifications apply to all VRs. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 7 Guaranteed by design, but not subject to production test. 8 Measured at the A terminal. The A terminal is open circuited in shutdown mode. 1 2 Rev. B | Page 4 of 20 Data Sheet AD5243/AD5248 TIMING CHARACTERISTICS: ALL VERSIONS VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted. Table 3. Parameter I2C INTERFACE TIMING CHARACTERISTICS1 SCL Clock Frequency Bus-Free Time Between Stop and Start, tBUF Hold Time (Repeated Start), tHD;STA Symbol fSCL t1 t2 Low Period of SCL Clock, tLOW High Period of SCL Clock, tHIGH Setup Time for Repeated Start Condition, tSU;STA Data Hold Time, tHD;DAT2 Data Setup Time, tSU;DAT Fall Time of Both SDA and SCL Signals, tF Rise Time of Both SDA and SCL Signals, tR Setup Time for Stop Condition, tSU;STO 2 Min After this period, the first clock pulse is generated. t3 t4 t5 t6 t7 t8 t9 t10 Typ 0 1.3 0.6 Max Unit 400 kHz μs μs 1.3 0.6 0.6 0.9 100 300 300 0.6 See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 45 to Figure 48). The maximum tHD:DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal. t8 t6 t2 t9 SCL t2 t4 t3 t8 t7 t10 t5 t9 SDA t1 P S S 2 Figure 3. I C Interface Detailed Timing Diagram Rev. B | Page 5 of 20 P 04109-0-021 1 Conditions μs μs μs μs ns ns ns μs AD5243/AD5248 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND VA, VB, VW to GND Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx1 Pulsed Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance, θJA for 10-Lead MSOP2 Rating −0.3 V to +7 V VDD ±20 mA ±5 mA 0 V to 7 V −40°C to +125°C 150°C −65°C to +150°C 300°C 230°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION The maximum terminal current is bound by the maximum current handling of the switches, the maximum power dissipation of the package, and the maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 The package power dissipation is (TJMAX − TA)/θJA. 1 Rev. B | Page 6 of 20 Data Sheet AD5243/AD5248 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 10 W1 B1 1 A1 2 9 B2 AD0 2 W2 3 AD5248 GND 4 TOP VIEW AD5243 8 A2 GND 4 TOP VIEW 7 SDA VDD 5 6 SCL VDD 5 Figure 4. AD5243 Pin Configuration 10 W1 9 B2 8 AD1 7 SDA 6 SCL 04109-0-028 W2 3 04109-0-027 B1 1 Figure 5. AD5248 Pin Configuration Table 5. AD5243 Pin Function Descriptions Table 6. AD5248 Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic B1 A1 W2 GND VDD SCL Pin No. 1 2 Mnemonic B1 AD0 3 4 5 6 W2 GND VDD SCL 7 8 9 10 SDA A2 B2 W1 7 8 SDA AD1 9 10 B2 W1 Description B1 Terminal. A1 Terminal. W2 Terminal. Digital Ground. Positive Power Supply. Serial Clock Input. Positive-edge triggered. Serial Data Input/Output. A2 Terminal. B2 Terminal. W1 Terminal. Rev. B | Page 7 of 20 Description B1 Terminal. Programmable Address Bit 0 for Multiple Package Decoding. W2 Terminal. Digital Ground. Positive Power Supply. Serial Clock Input. Positive-edge triggered. Serial Data Input/Output. Programmable Address Bit 1 for Multiple Package Decoding. B2 Terminal. W1 Terminal. AD5243/AD5248 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 0.5 TA = 25°C RAB = 10kΩ 1.0 VDD = 2.7V 0.5 0 VDD = 5.5V –0.5 RAB = 10kΩ 0.4 POTENTIOMETER MODE DNL (LSB) –1.0 –1.5 0.3 0.2 0.1 VDD = 2.7V; TA = –40°C, +25°C, +85°C, +125°C 0 –0.1 –0.2 –0.3 32 64 96 128 160 192 224 256 CODE (DECIMAL) –0.5 04109-0-030 0 0 32 128 160 192 224 256 Figure 9. DNL vs. Code vs. Temperature 1.0 0.5 TA = 25°C RAB = 10kΩ 0.3 0.2 VDD = 2.7V 0.1 0 –0.1 –0.2 VDD = 5.5V –0.3 TA = 25°C RAB = 10kΩ 0.8 POTENTIOMETER MODE INL (LSB) 0.4 0.6 0.4 VDD = 5.5V 0.2 0 VDD = 2.7V –0.2 –0.4 –0.6 –0.8 –0.4 0 32 64 96 128 160 192 224 256 CODE (DECIMAL) –1.0 04109-0-031 –0.5 0 32 64 96 128 160 192 224 256 CODE (DECIMAL) 04109-0-034 RHEOSTAT MODE DNL (LSB) 96 CODE (DECIMAL) Figure 6. R-INL vs. Code vs. Supply Voltages Figure 10. INL vs. Code vs. Supply Voltages Figure 7. R-DNL vs. Code vs. Supply Voltages 0.5 0.5 RAB = 10kΩ 0.3 VDD = 5.5V TA = –40°C, +25°C, +85°C, +125°C 0.2 0.1 0 –0.1 VDD = 2.7V TA = –40°C, +25°C, +85°C, +125°C –0.2 TA = 25°C RAB = 10kΩ 0.4 POTENTIOMETER MODE DNL (LSB) 0.4 –0.3 0.3 0.2 0.1 VDD = 2.7V 0 –0.1 VDD = 5.5V –0.2 –0.3 –0.4 –0.4 –0.5 0 32 64 96 128 160 192 CODE (DECIMAL) 224 256 04109-0-032 POTENTIOMETER MODE INL (LSB) 64 04109-0-033 –0.4 –2.0 –0.5 0 32 64 96 128 160 192 224 CODE (DECIMAL) Figure 11. DNL vs. Code vs. Supply Voltages Figure 8. INL vs. Code vs. Temperature Rev. B | Page 8 of 20 256 04109-0-035 RHEOSTAT MODE INL (LSB) 1.5 Data Sheet AD5243/AD5248 2.0 4.50 RAB = 10kΩ RAB = 10kΩ 1.0 0.5 0 VDD = 5.5V TA = –40°C, +25°C, +85°C, +125°C –0.5 –1.0 –1.5 0 32 64 96 128 160 192 224 256 CODE (DECIMAL) 3.00 2.25 VDD = 2.7V, VA = 2.7V 1.50 VDD = 5.5V, VA = 5.0V 0.75 0 –40 04109-0-036 –2.0 3.75 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 12. R-INL vs. Code vs. Temperature Figure 15. Zero-Scale Error vs. Temperature 10 0.5 RAB = 10kΩ 0.4 0.3 0.2 IDD, SUPPLY CURRENT (µA) RHEOSTAT MODE DNL (LSB) –25 04109-0-039 VDD = 2.7V TA = –40°C, +25°C, +85°C, +125°C ZSE, ZERO-SCALE ERROR (LSB) RHEOSTAT MODE INL (LSB) 1.5 VDD = 2.7V, 5.5V; TA = –40°C, +25°C, +85°C, +125°C 0.1 0 –0.1 –0.2 VDD = 5V 1 VDD = 3V –0.3 32 64 96 128 160 192 224 256 CODE (DECIMAL) 0.1 –40 –7 26 59 92 Figure 13. R-DNL vs. Code vs. Temperature Figure 16. Supply Current vs. Temperature 120 2.0 RAB = 10kΩ RAB = 10kΩ RHEOSTAT MODE TEMPCO (ppm/°C) 1.0 0.5 0 VDD = 5.5V, VA = 5.0V –0.5 VDD = 2.7V, VA = 2.7V –1.0 –1.5 –25 –10 5 20 35 50 65 80 95 TEMPERATURE (°C) 110 125 04109-0-038 FSE, FULL-SCALE ERROR (LSB) 1.5 –2.0 –40 125 TEMPERATURE (°C) 100 80 VDD = 2.7V TA = –40°C TO +85°C, –40°C TO +125°C 60 40 VDD = 5.5V TA = –40°C TO +85°C, –40°C TO +125°C 20 0 –20 0 32 64 96 128 160 192 224 CODE (DECIMAL) Figure 17. Rheostat Mode Tempco ΔRWB/ΔT vs. Code Figure 14. Full-Scale Error vs. Temperature Rev. B | Page 9 of 20 256 04109-0-041 0 04109-0-037 –0.5 04109-0-040 –0.4 AD5243/AD5248 Data Sheet 0 RAB = 10kΩ 0x80 –6 40 0x40 –12 30 GAIN (dB) 20 0x20 –18 VDD = 2.7V TA = –40°C TO +85°C, –40°C TO +125°C 10 0 0x10 –24 0x08 –30 0x04 –36 0x02 –42 –10 0x01 VDD = 5.5V TA = –40°C TO +85°C, –40°C TO +125°C –48 –20 0 32 64 96 128 160 192 224 256 CODE (DECIMAL) –60 1k 10k Figure 18. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code 0 0x80 0x80 –6 0x40 –12 0x40 –12 0x20 –18 0x20 –18 –24 GAIN (dB) 0x10 0x08 0x04 –30 –36 0x02 0x01 –42 0x10 –24 0x08 –30 0x04 –36 0x02 –42 –48 –54 –54 –60 10k 100k 1M 10M FREQUENCY (Hz) –60 1k 10k 100k 1M FREQUENCY (Hz) Figure 19. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ 04109-0-046 0x01 –48 04109-0-043 Figure 22. Gain vs. Frequency vs. Code, RAB = 100 kΩ 0 0 0x80 –6 –12 0x40 –18 0x20 –6 –12 GAIN (dB) 0x10 –24 0x08 –30 0x04 –36 0x02 0x01 –42 10kΩ 570kHz 2.5kΩ 2.2MHz –30 –36 –42 –54 –60 100k FREQUENCY (Hz) 1M 04109-0-044 –48 –54 10k 50kΩ 120kHz –24 –48 1k 100kΩ 60kHz –18 Figure 20. Gain vs. Frequency vs. Code, RAB = 10 kΩ –60 1k 10k 100k 1M FREQUENCY (Hz) Figure 23. –3 dB Bandwidth at Code = 0x80 Rev. B | Page 10 of 20 10M 04109-0-047 GAIN (dB) 1M Figure 21. Gain vs. Frequency vs. Code, RAB = 50 kΩ 0 –6 GAIN (dB) 100k FREQUENCY (Hz) 04109-0-045 –54 –30 04109-0-042 POTENTIOMETER MODE TEMPCO (ppm/°C) 50 Data Sheet AD5243/AD5248 10 1 VDD = 5.5V VW2 0.1 VDD = 2.7V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 DIGITAL INPUT VOLTAGE (V) 5.0 04109-0-052 0.01 04109-0-051 VW1 Figure 24. Supply Current vs. Digital Input Voltage Figure 27. Analog Crosstalk VW VW 04109-0-048 04109-0-053 SCL Figure 28. Midscale Glitch, Code 0x80 to Code 0x7F VW2 VW VW1 SCL 04109-0-050 Figure 25. Digital Feedthrough 04109-0-049 IDD, SUPPLY CURRENT (mA) TA = 25°C Figure 29. Large-Signal Settling Time Figure 26. Digital Crosstalk Rev. B | Page 11 of 20 AD5243/AD5248 Data Sheet TEST CIRCUITS Figure 30 through Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables (see Table 1 and Table 2). DUT +15V W VIN AD8610 B B VMS OFFSET GND –15V 2.5V Figure 30. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 34. Test Circuit for Gain vs. Frequency NO CONNECT RSW = DUT DUT A W VOUT 04109-0-009 W 04109-0-003 A V+ A V+ = VDD 1LSB = V+/2N DUT CODE = 0x00 W IW 0.1V ISW ISW B 0.1V VSS TO VDD Figure 31. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL) 04109-0-010 VMS 04109-0-004 B Figure 35. Test Circuit for Incremental On Resistance NC W IW = VDD/RNOMINAL B RW = [VMS1 – VMS2]/IW VMS1 W V+ B ∆VMS PSRR (dB) = 20 LOG ∆VDD ∆VMS% PSS (%/%) = ∆VDD% ( VMS VCM NC = NO CONNECT Figure 36. Test Circuit for Common-Mode Leakage Current ) 04109-0-006 ∆VDD A ICM B NC V+ = VDD ± 10% DUT W GND Figure 32. Test Circuit for Wiper Resistance VA A VDD VW 04109-0-005 A VMS2 DUT 04109-0-011 DUT Figure 33. Test Circuit for Power Supply Sensitivity (PSS, PSSR) Rev. B | Page 12 of 20 Data Sheet AD5243/AD5248 THEORY OF OPERATION The general equation determining the digitally programmed output resistance between W and B is The AD5243/AD5248 are 256-position, digitally controlled variable resistor (VR) devices. An internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. PROGRAMMING THE VARIABLE RESISTOR AND VOLTAGE Rheostat Operation The nominal resistance of the RDAC between Terminal A and Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal and the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. A A B B W 04109-0-012 W B D RAB 2 RW 256 (1) where: D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB is 10 kΩ and the A terminal is open circuited, the following output resistance, RWB, is set for the indicated RDAC latch codes. Table 7. Codes and Corresponding RWB Resistance D (Dec) 255 128 1 0 A W RWB (D) RWB (Ω) 10,281 5380 359 320 Output State Full scale (RAB − 1 LSB + 2 × RW) Midscale 1 LSB + 2 × RW Zero scale (wiper contact resistance) Figure 37. Rheostat Mode Configuration Assuming that a 10 kΩ part is used, the first connection of the wiper starts at the B terminal for Data 0x00. Because there is a 160 Ω wiper contact resistance, such a connection yields a minimum of 320 Ω (2 × 160 Ω) resistance between Terminal W and Terminal B. The second connection is the first tap point, which corresponds to 359 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 160 Ω) for Data 0x01. The third connection is the next tap point, representing 398 Ω (2 × 39 Ω + 2 × 160 Ω) for Data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,281 Ω (RAB + 2 × RW). A Note that in the zero-scale condition, a finite wiper resistance of 320 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact may occur. Similar to the mechanical potentiometer, the resistance of the RDAC between Wiper W and Terminal A also produces a digitally controlled complementary resistance, RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is RS RWA (D) D7 D6 D5 D4 D3 D2 D1 D0 RS 256 D RAB 2 RW 256 (2) When RAB is 10 kΩ and the B terminal is open circuited, the output resistance, RWA, is set according to the RDAC latch codes, as listed in Table 8. RS W Table 8. Codes and Corresponding RWA Resistance RDAC RS B 04109-0-013 LATCH AND DECODER D (Dec) 255 128 1 0 Figure 38. AD5243 Equivalent RDAC Circuit RWA (Ω) 359 5320 10,280 10,320 Output State Full scale Midscale 1 LSB + 2 × RW Zero scale Typical device-to-device matching is process-lot dependent and may vary by up to ±30%. Because the resistance element is processed in thin-film technology, the change in RAB with temperature has a very low temperature coefficient of 35 ppm/°C. Rev. B | Page 13 of 20 AD5243/AD5248 Data Sheet PROGRAMMING THE POTENTIOMETER DIVIDER TERMINAL VOLTAGE OPERATING RANGE Voltage Output Operation The AD5243/AD5248 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on the A, B, and W terminals that exceed VDD or GND are clamped by the internal forwardbiased diodes (see Figure 42). The digital potentiometer easily generates a voltage divider at wiper to B and wiper to A, proportional to the input voltage at A to B. Unlike the polarity of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity. VDD VI A A W VO B GND Figure 39. Potentiometer Mode Configuration Figure 42. Maximum Terminal Voltages Set by VDD and GND If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper to B, starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across Terminal A and Terminal B divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B is VW (D) = 256 − D D VA + VB 256 256 (3) Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Unlike in the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RWA and RWB, not on the absolute values. Therefore, the temperature drift reduces to 15 ppm/°C. ESD PROTECTION All digital inputs are protected with a series of input resistors and parallel Zener ESD structures, as shown in Figure 40 and Figure 41. This applies to the SDA, SCL, AD0, and AD1 digital input pins (AD5248 only). 340Ω GND 04109-0-015 LOGIC POWER-UP SEQUENCE Because the ESD protection diodes limit the voltage compliance at the A, B, and W terminals (see Figure 42), it is important to power VDD/GND before applying voltage to the A, B, and W terminals; otherwise, the diode is forward-biased such that VDD is powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VA, VB, and VW. The relative order of powering VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD/GND. LAYOUT AND POWER SUPPLY BYPASSING It is a good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 43). In addition, note that the digital ground should be joined remotely to the analog ground at one point to minimize the ground bounce. Figure 40. ESD Protection of Digital Pins VDD C3 10µF + VDD C1 0.1µF AD5243 04109-0-016 A, B, W GND 04109-0-017 B 04109-0-014 W GND 04109-0-018 Figure 41. ESD Protection of Resistor Terminals Figure 43. Power Supply Bypassing Rev. B | Page 14 of 20 Data Sheet AD5243/AD5248 CONSTANT BIAS TO RETAIN RESISTANCE SETTING For users who desire nonvolatility but cannot justify the additional cost of an EEMEM, the AD5243/AD5248 can be considered low cost alternatives by maintaining a constant bias to retain the wiper setting. The AD5243/AD5248 are designed specifically for low power applications, allowing low power consumption even in battery-operated systems. The graph in Figure 44 demonstrates the power consumption from a 3.4 V, 450 mAhr Li-Ion cell phone battery connected to the AD5243/AD5248. The measurement over time shows that the device draws approximately 1.3 µA and consumes negligible power. Over a course of 30 days, the battery is depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself. This demonstrates that constantly biasing the potentiometer can be a practical approach. Most portable devices do not require the removal of batteries for the purpose of charging. Although the resistance setting of the AD5243/AD5248 is lost when the battery needs replacement, such events occur rather infrequently such that this inconvenience is justified by the lower cost and smaller size offered by the AD5243/AD5248. If total power is lost, the user should be provided with a means to adjust the setting accordingly. 110 TA = 25°C 106 104 102 100 98 96 94 92 90 0 5 10 15 DAYS 20 25 30 04109-0-019 BATTERY LIFE DEPLETED (%) 108 Figure 44. Battery Operating Life Depletion Rev. B | Page 15 of 20 AD5243/AD5248 Data Sheet I2C INTERFACE I2C COMPATIBLE, 2-WIRE SERIAL BUS SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 45 and Figure 46). The 2-wire, I C-compatible serial bus protocol operates as follows: 2 1. The master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 45). The following byte is the slave address byte, which consists of the slave address followed by an R/W bit (this bit determines whether data is read from or written to the slave device). The AD5243 has a fixed slave address byte, whereas the AD5248 has two configurable address bits, AD0 and AD1 (see Figure 10). 3. Note that the channel of interest is the one that is previously selected in write mode. If users need to read the RDAC values of both channels, they need to program the first channel in write mode and then change to read mode to read the first channel value. After that, the user must return the device to write mode with the second channel selected and read the second channel value in read mode. It is not necessary for users to issue the Frame 3 data byte in write mode for subsequent readback operation. Users should refer to Figure 47 and Figure 48 for the programming format. The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is called the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master reads from the slave device. On the other hand, if the R/W bit is low, the master writes to the slave device. 2. In the write mode, the second byte is the instruction byte. The first bit (MSB) of the instruction byte is the RDAC subaddress select bit. A logic low selects Channel 1 and a logic high selects Channel 2. In the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the write mode, where there are eight data bits followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 47 and Figure 48). 4. The second MSB, SD, is a shutdown bit. A logic high causes an open circuit at Terminal A while shorting the wiper to Terminal B. This operation yields almost 0 Ω in rheostat mode or 0 V in potentiometer mode. It is important to note that the shutdown operation does not disturb the contents of the register. When the AD5243 or AD5248 is brought out of shutdown, the previous setting is applied to the RDAC. In addition, during shutdown, new settings can be programmed. When the part is returned from shutdown, the corresponding VR setting is applied to the RDAC. The remainder of the bits in the instruction byte are don’t care bits (see Figure 10). After acknowledging the instruction byte, the last byte in write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the Rev. B | Page 16 of 20 After all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition (see Figure 45 and Figure 46). In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, which goes high to establish a stop condition (see Figure 47 and Figure 48). A repeated write function provides the user with the flexibility of updating the RDAC output multiple times after addressing and instructing the part only once. For example, after the RDAC has acknowledged its slave address and instruction bytes in write mode, the RDAC output updates on each successive byte. If different instructions are needed, however, the write/read mode must restart with a new slave address, instruction, and data byte. Similarly, a repeated read function of the RDAC is also allowed. Data Sheet AD5243/AD5248 Write Mode Table 9. AD5243 Write Mode S 0 1 0 1 1 1 1 W A A0 SD Slave address byte X X X X X X A D7 D6 D5 Instruction byte D4 D3 D2 D1 D0 A P D0 A P Data byte Table 10. AD5248 Write Mode S 0 1 0 1 1 AD1 AD0 W A A0 SD Slave address byte X X X X X X A D7 D6 D5 Instruction byte D4 D3 D2 D1 Data byte Read Mode Table 11. AD5243 Read Mode S 0 1 0 1 1 1 Slave address byte 1 R A D7 D6 D5 D4 D3 Data byte D2 D1 D0 A P Table 12. AD5248 Read Mode S 0 1 0 1 1 AD1 Slave address byte AD0 R A D7 D6 D5 D4 D3 Data byte D2 D1 D0 A Table 13. SDA Bits Descriptions Bit S P A AD0, AD1 X W R A0 SD D7, D6, D5, D4, D3, D2, D1, D0 Description Start condition. Stop condition. Acknowledge. Package pin-programmable address bits. Don’t care. Write. Read. RDAC subaddress select bit. Shutdown connects wiper to B terminal and open circuits the A terminal. It does not change the contents of the wiper register. Data bits. Rev. B | Page 17 of 20 P AD5243/AD5248 Data Sheet I2C CONTROLLER PROGRAMMING Write Bit Patterns 1 9 9 1 1 9 SDA 0 1 0 1 1 1 1 R/W A0 SD X X X X X X ACK BY AD5243 START BY MASTER D7 D6 D5 D4 D2 D3 D1 FRAME 2 INSTRUCTION BYTE FRAME 1 SLAVE ADDRESS BYTE D0 ACK BY AD5243 ACK BY AD5243 04109-0-022 SCL STOP BY MASTER FRAME 3 DATA BYTE Figure 45. Writing to the RDAC Register—AD5243 1 9 9 1 1 9 SDA 0 1 0 1 1 AD1 AD0 R/W A0 SD X X X X X X ACK BY AD5248 START BY MASTER D7 D6 D5 D4 D2 D3 D1 FRAME 2 INSTRUCTION BYTE FRAME 1 SLAVE ADDRESS BYTE D0 ACK BY AD5248 ACK BY AD5248 04109-0-023 SCL STOP BY MASTER FRAME 3 DATA BYTE Figure 46. Writing to the RDAC Register—AD5248 Read Bit Patterns 1 9 1 9 SCL 0 1 0 1 1 1 1 R/W D7 D6 D5 D4 D3 D2 D1 ACK BY AD5243 START BY MASTER D0 NO ACK BY MASTER FRAME 2 RDAC REGISTER FRAME 1 SLAVE ADDRESS BYTE STOP BY MASTER 04109-0-024 SDA Figure 47. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5243 9 1 1 9 SCL 0 1 0 1 1 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 START BY MASTER D0 NO ACK BY MASTER ACK BY AD5248 FRAME 2 RDAC REGISTER FRAME 1 SLAVE ADDRESS BYTE STOP BY MASTER 04109-0-025 SDA Figure 48. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5248 Multiple Devices on One Bus (Applies Only to AD5248) RP SDA MASTER SCL 5V 5V SDA SCL SDA SCL 5V SDA SCL SCL AD1 AD1 AD1 AD0 AD0 AD0 AD0 AD5248 AD5248 AD5248 AD5248 Figure 49. Multiple AD5248 Devices on One I2C Bus Rev. B | Page 18 of 20 SDA AD1 04109-0-026 Figure 49 shows four AD5248 devices on the same serial bus. Each has a different slave address because the states of their AD0 and AD1 pins are different. This allows each device on the bus to be written to or read from independently. The master device output bus line drivers are open-drain pull-downs in a fully I2C-compatible interface. 5V RP Data Sheet AD5243/AD5248 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.23 0.13 6° 0° 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-BA 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 50. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 AD5243BRM2.5 AD5243BRM10 AD5243BRM10-RL7 AD5243BRM50 AD5243BRM50-RL7 AD5243BRM100 AD5243BRM100-RL7 AD5243BRMZ2.5 AD5243BRMZ2.5-RL7 AD5243BRMZ10 AD5243BRMZ10-RL7 AD5243BRMZ50 AD5243BRMZ50-RL7 AD5243BRMZ100 AD5243BRMZ100-RL7 EVAL-AD5243SDZ AD5248BRM2.5 AD5248BRM2.5-RL7 AD5248BRM10 AD5248BRM10-RL7 AD5248BRM50 AD5248BRM50-RL7 AD5248BRM100 AD5248BRM100-RL7 AD5248BRMZ2.5 AD5248BRMZ2.5-RL7 AD5248BRMZ10 AD5248BRMZ10-RL7 AD5248BRMZ50 AD5248BRMZ50-RL7 AD5248BRMZ100 AD5248BRMZ100-RL7 1 2 RAB 2.5 kΩ 10 kΩ 10 kΩ 50 kΩ 50 kΩ 100 kΩ 100 kΩ 2.5 kΩ 2.5 kΩ 10 kΩ 10 kΩ 50 kΩ 50 kΩ 100 kΩ 100 kΩ Temperature −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C 2.5 kΩ 2.5 kΩ 10 kΩ 10 kΩ 50 kΩ 50 kΩ 100 kΩ 100 kΩ 2.5 kΩ 2.5 kΩ 10 kΩ 10 kΩ 50 kΩ 50 kΩ 100 kΩ 100 kΩ −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding D0L D0M D0M D0N D0N D0P D0P D9X D9X D0M D0M D0N D0N D0P D0P RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 D1F D1F D1G D1G D1H D1H D1J D1J D1F D1F D8Z D8Z D90 D90 D91 D91 Z = RoHS Compliant Part. The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options. Rev. B | Page 19 of 20 AD5243/AD5248 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04109-0-4/12(B) Rev. B | Page 20 of 20