a FEATURES 12-Bit CMOS DAC with Output Amplifier and Reference Improved AD7245/AD7248: 12 V to 15 V Operation ⴞ1/2 LSB Linearity Grade Faster Interface—30 ns Typ Data Setup Time Extended Plastic Temperature Range (–40ⴗC to +85ⴗC) Single or Dual Supply Operation Low Power—65 mW Typ in Single Supply Parallel Loading Structure: AD7245A (8+4) Loading Structure: AD7248A LC2MOS 12-Bit DACPORTs AD7245A/AD7248A AD7245A FUNCTIONAL BLOCK DIAGRAM VDD ROFS REF OUT 2R RFB VOUT VREF DAC VSS AGND CS WR CLR DAC LATCH CONTROL LOGIC AD7245A GENERAL DESCRIPTION The AD7245A/AD7248A is an enhanced version of the industry standard AD7245/AD7248. Improvements include operation from 12 V to 15 V supplies, a ± 1/2 LSB linearity grade, faster interface times and better full scale and reference variations with VDD. Additional features include extended temperature range operation for commercial and industrial grades. The AD7245A/AD7248A is a complete, 12-bit, voltage output, digital-to-analog converter with output amplifier and Zener voltage reference on a monolithic CMOS chip. No external user trims are required to achieve full specified performance. Both parts are microprocessor compatible, with high speed data latches and double-buffered interface logic. The AD7245A accepts 12-bit parallel data that is loaded into the input latch on the rising edge of CS or WR. The AD7248A has an 8-bit-wide data bus with data loaded to the input latch in two write operations. For both parts, an asynchronous LDAC signal transfers data from the input latch to the DAC latch and updates the analog output. The AD7245A also has a CLR signal on the DAC latch which allows features such as power-on reset to be implemented. The on-chip 5 V buried Zener diode provides a low noise, temperature compensated reference for the DAC. For single supply operation, two output ranges of 0 V to 5 V and 0 V to 10 V are available, while these two ranges plus an additional ± 5 V range are available with dual supplies. The output amplifiers are capable of developing 10 V across a 2 kΩ load to GND. The AD7245A/AD7248A is fabricated in linear compatible CMOS (LC2MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic. The AD7245A is available in a small, 0.3" wide, 24-lead DIP and SOIC and in 28-terminal surface mount packages. The AD7248A is packaged in a small, 0.3" wide, 20-lead DIP and SOIC and in 20-terminal surface mount packages. 2R LDAC INPUT LATCH DB0 DB11 DGND AD7248A FUNCTIONAL BLOCK DIAGRAM VDD ROFS REF OUT 2R 2R RFB VOUT VREF DAC VSS AGND LDAC WR CSLSB CSMSB DAC LATCH CONTROL LOGIC AD7248A 4-BIT INPUT LATCH DB7 8-BIT INPUT LATCH DB0 DGND PRODUCT HIGHLIGHTS 1. The AD7245A/AD7248A is a 12-bit DACPORT® on a single chip. This single chip design and small package size offer considerable space saving and increased reliability over multichip designs. 2. The improved interface times on the part allows easy, direct interfacing to most modern microprocessors. 3. The AD7245A/AD7248A features a wide power supply range allowing operation from 12 V supplies. DACPORT is a registered trademark of Analog Devices, Inc. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD7245A/AD7248A–SPECIFICATIONS (V = +12 V to +15 V, V AGND = DGND = O V, R = 2 k⍀, C = 100 pF. All specifications T to T unless otherwise noted.) DD L L Parameter STATIC PERFORMANCE Resolution Relative Accuracy @ 25°C3 TMIN to TMAX TMIN to TMAX Differential Nonlinearity3 Unipolar Offset Error @ 25°C3 TMIN to TMAX Bipolar Zero Error @ 25°C3 TMIN to TMAX DAC Gain Error3, 6 Full-Scale Output Voltage Error7 @ 25°C ∆Full Scale/∆VDD ∆Full Scale/∆VSS Full-Scale Temperature Coefficient8 REFERENCE OUTPUT REF OUT @ 25°C ∆REF OUT/∆VDD Reference Temperature Coefficient Reference Load Change (∆REF OUT vs. ∆I) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance9 ANALOG OUTPUTS Output Range Resistors Output Voltage Ranges10 DC Output Impedance AC CHARACTERISTICS9 Voltage Output Settling Time Positive Full-Scale Change Negative Full-Scale Change Output Voltage Slew Rate Digital Feedthrough3 Digital-to-Analog Glitch Impulse POWER REQUIREMENTS VDD VSS IDD @ 25°C TMlN to TMAX ISS (Dual Supplies) MIN SS = O V or –12 V to –15 V,1 MAX A2 Version B2 Version T2 Version 12 ± 3/4 ±1 12 ± 1/2 ± 3/4 ± 1/2 ±1 ±3 ±5 ±2 ±4 ±2 ± 0.2 ± 0.06 ± 0.01 ± 30 12 ± 1/2 ± 3/4 ±1 ±3 ±5 ±3 ±5 ±2 ± 0.2 ± 0.06 ± 0.01 ± 40 1 Unit Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max % of FSR max % of FSR/V max % of FSR/V max ppm of FSR/°C max ±1 ±3 ±5 ±2 ±4 ±2 ± 0.2 ± 0.06 ± 0.01 ± 40 Test Conditions/Comments VDD = 15 V ± 10% Guaranteed Monotonic VSS = 0 V or –12 V to –15 V4 Typical Tempco is ± 3 ppm of FSR5/°C. ROFS connected to REF OUT; VSS = –12 V to –15 V4 Typical Tempco is ± 3 ppm of FSR5/°C. VDD = 15 V VDD = +12 V to +15 V4 VSS = –12 V to –15 V4 VDD = 15 V 4.99/5.01 4.99/5.01 2 2 ± 25 ± 25 4.99/5.01 V min/V max 2 mV/V max ± 35 ppm/°C typ VDD = 15 V VDD = 12 V to 15 V4 –1 –1 –1 mV max Reference Load Current Change (0–100 µA) 2.4 0.8 ± 10 8 2.4 0.8 ± 10 8 2.4 0.8 ± 10 8 V min V max µA max pF max 15/30 5, 10 5, 10, ±5 0.5 15/30 5, 10 5, 10, ±5 0.5 15/30 5, 10 5, 10, ±5 0.5 kΩ min/kΩ max V 7 7 2 10 30 7 7 2 10 30 10 10 1.5 10 30 µs max µs max V/µs min nV-s typ nV-s typ +10.8/ +16.5 –10.8/ –16.5 9 10 3 +10.8/ +16.5 –10.8/ –16.5 9 10 3 +10.8/ +16.5 –10.8/ –16.5 9 12 5 V min/ V max V min/ V max mA max mA max mA max VIN = 0 V to VDD VSS = 0 V; Pin Strappable VSS = –12 V to –15 V;4 Pin Strappable V Ω typ Settling Time to Within ± 1/2 LSB of Final Value DAC Latch All 0s to All 1s DAC Latch All 1s to All 0s; VSS = –12 V to –15 V4 For Specified Performance Unless Otherwise Stated For Specified Performance Unless Otherwise Stated Output Unloaded; Typically 5 mA Output Unloaded Output Unloaded; Typically 2 mA NOTES 1 Power supply tolerance is ± 10%. 2 Temperature ranges are as follows: A/B Versions; –40°C to +85°C; T Version; –55°C to +125°C. 3 See Terminology. 4 With appropriate power supply tolerances. 5 FSR means Full-Scale Range and is 5 V for the 0 V to 5 V output range and 10 V for both the 0 V to 10 V and ± 5 V output ranges. 6 This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for. 7 This error is calculated with respect to an ideal 4.9988 V on the 0 V to 5 V and ± 5 V ranges; it is calculated with respect to an ideal 9.9976 V on the 0 V to 10 V range. It includes the effects of internal voltage reference, gain and offset errors. 8 Full-Scale TC = ∆FS/∆T, where ∆FS is the full-scale change from T A = 25°C to TMIN or TMAX. 9 Guaranteed by design and characterization, not production tested. 10 0 V to 10 V output range is available only when V DD ≥ +14.25 V. Specifications subject to change without notice. –2– REV. B AD7245A/AD7248A SWITCHING CHARACTERISTICS1 (V Parameter DD = +12 V to +15 V;2 VSS = 0 V to –12 V to –15 V;2 See Figures 5 and 7.) A, B Versions T Version Unit Conditions @ 25°C TMIN to TMAX 55 80 55 100 ns typ ns min Chip Select Pulsewidth @ 25°C TMIN to TMAX 40 80 40 100 ns typ ns min Write Pulsewidth @ 25°C TMIN to TMAX 0 0 0 0 ns min ns min Chip Select to Write Setup Time @ 25°C TMIN to TMAX 0 0 0 0 ns min ns min Chip Select to Write Hold Time @ 25°C TMIN to TMAX 40 80 40 80 ns typ ns min Data Valid to Write Setup Time @ 25°C TMIN to TMAX 10 10 10 10 ns min ns min Data Valid to Write Hold Time @ 25°C TMIN to TMAX t8 (AD7245A Only) @ 25°C TMIN to TMAX 40 80 40 100 ns typ ns min Load DAC Pulsewidth 40 80 40 100 ns typ ns min Clear Pulsewidth t1 t2 t3 t4 t5 t6 t7 NOTES 1 Sample tested at 25°C to ensure compliance. 2 Power supply tolerance is ± 10%. ABSOLUTE MAXIMUM RATINGS 1 VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +34 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD VOUT to VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 24 V VOUT to VDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –32 V, 0 V REF OUT2 to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW Derates above 75°C by . . . . . . . . . . . . . . . . . . . . 6 mW/°C Operating Temperature Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 The output may be shorted to voltages in this range provided the power dissipation of the package is not exceeded. V OUT short circuit current is typically 80 mA. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7245A/AD7248A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3– WARNING! ESD SENSITIVE DEVICE AD7245A/AD7248A AD7245A ORDERING GUIDE DAC GAIN ERROR Model1 Temperature Range Relative Accuracy Package Option2 AD7245AAN AD7245ABN AD7245AAQ AD7245ATQ3 AD7245AAP AD7245AAR AD7245ABR AD7245ATE3 –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C ± 3/4 LSB ± 1/2 LSB ± 3/4 LSB ± 3/4 LSB ± 3/4 LSB ± 3/4 LSB ± 1/2 LSB ± 3/4 LSB N-24 N-24 Q-24 Q-24 P-28A R-24 R-24 E-28A DAC Gain Error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been allowed for. It is, therefore defined as: Measured Value—Offset—Ideal Value where the ideal value is calculated relative to the actual reference value. UNIPOLAR OFFSET ERROR Unipolar Offset Error is a combination of the offset errors of the voltage mode DAC and the output amplifier and is measured when the part is configured for unipolar outputs. It is present for all codes and is measured with all 0s in the DAC register. NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact our local sales office for military data sheet and availability. 2 E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. 3 This grade will be available to /883B processing only. BIPOLAR ZERO OFFSET ERROR Bipolar Zero Offset Error is measured when the part is configured for bipolar output and is a combination of errors from the DAC and output amplifier. It is present for all codes and is measured with a code of 2048 (decimal) in the DAC register. AD7248A ORDERING GUIDE SINGLE SUPPLY LINEARITY AND GAIN ERROR Model Temperature Range Relative Accuracy Package Option2 AD7248AAN AD7248ABN AD7248AAQ AD7248ATQ3 AD7248AAP AD7248AAR AD7248ABR –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –40°C to +85°C –40°C to +85°C –40°C to +85°C ± 3/4 LSB ± 1/2 LSB ± 3/4 LSB ± 3/4 LSB ± 3/4 LSB ± 3/4 LSB ± 1/2 LSB N-20 N-20 Q-20 Q-20 P-20A R-20 R-20 1 The output amplifier of the AD7245A/AD7248A can have a true negative offset even when the part is operated from a single positive power supply. However, because the lower supply rail to the part is 0 V, the output voltage cannot actually go negative. Instead the output voltage sits on the lower rail and this results in the transfer function shown. This is an offset effect and the transfer function would have followed the dotted line if the output voltage could have gone negative. Normally, linearity is measured after offset and full scale have been adjusted or allowed for. On the AD7245A/AD7248A the negative offset is allowed for by calculating the linearity from the code which the amplifier comes off the lower rail. This code is given by the negative offset specification. For example, the single supply linearity specification applies between Code 3 and Code 4095 for the 25°C specification and between Code 5 and Code 4095 over the TMIN to TMAX temperature range. Since gain error is also measured after offset has been allowed for, it is calculated between the same codes as the linearity error. Bipolar linearity and gain error are measured between Code 0 and Code 4095. NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact our local sales office for military data sheet and availability. 2 N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. 3 This grade will be available to /883B processing only. TERMINOLOGY RELATIVE ACCURACY Relative Accuracy, or endpoint nonlinearity, is a measure of the actual deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after allowing for zero and full scale and is normally expressed in LSBs or as a percentage of full-scale reading. OUTPUT VOLTAGE DIFFERENTIAL NONLINEARITY Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB max over the operating temperature range ensures monotonicity. 0V NEGATIVE OFFSET DIGITAL FEEDTHROUGH Digital Feedthrough is the glitch impulse injected from the digital inputs to the analog output when the inputs change state. It is measured with LDAC high and is specified in nV-s. –4– DAC CODE REV. B AD7245A/AD7248A AD7245A PIN FUNCTION DESCRIPTIONS (DIP PIN NUMBERS) Pin Mnemonic Description l VSS Negative Supply Voltage (0 V for single supply operation). 2 ROFS Bipolar Offset Resistor. This provides access to the on-chip application resistors and allows different output voltage ranges. 3 REF OUT Reference Output. The on-chip reference is provided at this pin and is used when configuring the part for bipolar outputs. 4 AGND Analog Ground. 5 DB11 Data Bit 11. Most Significant Bit (MSB). 6–11 DB10–DB5 Data Bit 10 to Data Bit 5. 12 DGND Digital Ground. 13–16 DB4–DB1 Data Bit 4 to Data Bit 1. 17 DB0 Data Bit 0. Least Significant Bit (LSB). 18 CS Chip Select Input (Active LOW). The device is selected when this input is active. Pin Mnemonic Description 19 WR Write Input (Active LOW). This is used in conjunction with CS to write data into the input latch of the AD7245A. 20 LDAC Load DAC Input (Active LOW). This is an asynchronous input which when active transfers data from the input latch to the DAC latch. 21 CLR Clear Input (Active LOW). When this input is active the contents of the DAC latch are reset to all 0s. 22 VDD Positive Supply Voltage. 23 RFB Feedback Resistor. This allows access to the amplifier’s feedback loop. 24 VOUT Output Voltage. Three different output voltage ranges can be chosen: 0 V to 5 V, 0 V to 10 V or –5 V to +5 V. AD7245A PIN CONFIGURATIONS PLCC DB5 11 14 DB3 DGND 12 13 DB4 21 CS DB8 10 20 DB0 DB7 11 19 DB1 VDD VSS NC RFB ROFS VOUT REF OUT VOUT RFB VSS NC VDD DB10 7 23 WR AD7245A TOP VIEW (NOT TO SCALE) NC 8 DB9 9 DB9 9 22 NC 21 CS DB8 10 20 DB0 DB7 11 19 DB1 12 13 14 15 16 17 18 12 13 14 15 16 17 18 NC = NO CONNECT NC = NO CONNECT REV. B 24 LDAC DB11 6 –5– DB2 15 DB2 22 NC 25 CLR AGND 5 DB3 DB6 10 TOP VIEW (NOT TO SCALE) NC 8 1 28 27 26 DB4 16 DB1 AD7245A DB6 DB7 9 DB10 7 23 WR 2 NC 17 DB0 (LSB) DB11 6 24 LDAC 3 DGND 18 CS 25 CLR AGND 5 4 DB5 19 WR 28 27 26 DB6 DB8 8 20 LDAC 1 DB2 DB9 7 TOP VIEW (NOT TO SCALE) 2 DB3 DB10 6 AD7245A 3 LCCC DB4 21 CLR AGND 4 (MSB) DB11 5 4 NC 22 VDD DGND 23 RFB REF OUT 3 ROFS 24 VOUT DB5 VSS 1 ROFS 2 REF OUT DIP and SOIC AD7245A/AD7248A AD7248A PIN FUNCTION DESCRIPTIONS (ANY PACKAGE) Pin Mnemonic Description Pin Mnemonic Description l VSS Negative Supply Voltage (0 V for single supply operation). 14 CSMSB 2 ROFS Bipolar Offset Resistor. This provides access to the on-chip application resistors and allows different output voltage ranges. Chip Select Input for MS Nibble. (Active LOW). This selects the upper 4 bits of the input latch. Input data is right justified. 15 CSLSB Reference Output. The on-chip reference is provided at this pin and is used when configuring the part for bipolar outputs. Chip Select Input for LS byte. (Active LOW). This selects the lower 8 bits of the input latch. 16 WR Write Input. This is used in conjunction with CSMSB and CSLSB to load data into the input latch of the AD7248A. 17 LDAC Load DAC Input (Active LOW). This is an asynchronous input which when active transfers data from the input latch to the DAC latch. 3 REF OUT 4 AGND Analog Ground. 5 DB7 Data Bit 7. 6 DB6 Data Bit 6. 7 DB5 Data Bit 5. 8 DB4 Data Bit 4. 18 VDD Positive Supply Voltage. 9 DB3 Data Bit 3. 19 RFB 10 DGND Digital Ground. Feedback Resistor. This allows access to the amplifier’s feedback loop. 11 DB2 Data Bit 2/Data Bit 10. 20 VOUT Output Voltage. Three different output voltage ranges can be chosen: 0 V to 5 V, 0 V to 10 V or –5 V to +5 V. 12 DB1 Data Bit 1/Data Bit 9. 13 DB0 Data Bit 0 (LSB)/Data Bit 8. AD7248A PIN CONFIGURATIONS DIP and SOIC 13 DB0 (LSB) DB3 9 12 DB1 DGND 10 11 DB2 VSS VOUT RFB REF OUT ROFS VSS VOUT 20 19 AGND 4 DB6 6 DB5 7 18 VDD 17 LDAC (MSB) DB7 5 AD7248A TOP VIEW (NOT TO SCALE) AGND 4 18 (MSB) DB7 5 17 16 WR DB6 6 15 CSLSB DB5 7 14 CSMSB DB4 8 RFB ROFS 1 PIN 1 IDENTIFIER AD7248A TOP VIEW (NOT TO SCALE) DB4 8 9 10 11 12 13 9 10 11 12 13 –6– VDD LDAC 16 WR 15 CSLSB 14 CSMSB (LSB) DB0 DB4 8 2 DB1 14 CSMSB 3 DB2 DB5 7 19 DB3 16 WR TOP VIEW (NOT TO SCALE) 15 CSLSB 20 DGND DB6 6 (MSB) DB7 5 1 (LSB) DB0 AD7248A 2 DB1 17 LDAC AGND 4 3 DB2 18 VDD DGND 19 RFB REF OUT 3 REF OUT 20 VOUT ROFS 2 LCCC DB3 VSS 1 PLCC REV. B Typical Performance Characteristics– AD7245A/AD7248A 7 4.995 IDD (VSS = –15V, V IN = V INL OR V INH) VDD = +15V IDD (VSS = –15V, V IN = 0V OR V DD) REFERENCE VOLTAGE – Volts POWER SUPPLY CURRENT – mA 6 5 IDD (VSS = 0V, V IN = 0V OR VDD) 4 3 2 ISS (VSS = –15V) 5.000 5.005 1 0 –55 –25 0 70 25 TEMPERATURE – ⴗC 85 5.010 –55 125 TPC 1. Power Supply Current vs. Temperature –25 0 25 70 TEMPERATURE – ⴗC 85 125 TPC 4. Reference Voltage vs. Temperature 500 VDD = 15V VSS = 0V TA = 25ⴗC OUTPUT WITH ALL 0s ON DAC DECOUPLING* 80 200 NO DECOUPLING REFERENCE (NO DECOUPLING) PSRR – dB nV Hz 100 REFERENCE (DECOUPLED*) 50 60 OUTPUT WITH ALL 1s ON DAC DECOUPLING 40 NO DECOUPLING 20 20 OUTPUT WITH ALL 0s ON DAC 10 50 100 200 500 1k 5k 2k FREQUENCY – Hz VDD = 15V WITH 100mV p-p SIGNAL 10k 20k 0 50k 1k 2k 100k 10k 20k FREQUENCY – Hz *POWER SUPPLY DECOUPLING CAPACITORS ARE 10F AND 0.1F *REFERENCE DECOUPLING COMPONENTS AS PER FIGURE 8 TPC 2. Noise Spectral Density vs. Frequency 50 100 200 TPC 5. Power Supply Rejection Ration vs. Frequency 1mV 1mV 100 100 90 90 10 10 0% 0% 2V 1s 2V TPC 3. Positive-Going Settling Time (VDD = +15 V, VSS = –15 V) REV. B 1s TPC 6. Negative Going Settling Time (VDD = +15 V, VSS = –15 V) –7– AD7245A/AD7248A The small signal (200 mV p-p) bandwidth of the output buffer amplifier is typically 1 MHz. The output noise from the amplifier is low with a figure of 25 nV/√Hz at a frequency of 1 kHz. The broadband noise from the amplifier has a typical peak-topeak figure of 150 µV for a 1 MHz output bandwidth. There is no significant difference in the output noise between single and dual supply operation. CIRCUIT INFORMATION D/A SECTION The AD7245A/AD7248A contains a 12-bit voltage mode digital-to-analog converter. The output voltage from the converter has the same positive polarity as the reference voltage allowing single supply operation. The reference voltage for the DAC is provided by an on-chip buried Zener diode. VOLTAGE REFERENCE The DAC consists of a highly stable, thin-film, R–2R ladder and twelve high-speed NMOS single-pole, double-throw switches. The simplified circuit diagram for this DAC is shown in Figure 1. 2R ROFS R R 2R R R 2R RFB VOUT R 2R 2R 2R 2R 2R DB0 DB1 DB9 DB10 DB11 VREF AGND SHOWN FOR ALL 1s ON DAC Figure 1. D/A Simplified Circuit Diagram The input impedance of the DAC is code dependent and can vary from 8 kΩ to infinity. The input capacitance also varies with code, typically from 50 pF to 200 pF. The AD7245A/AD7248A contains an internal low noise buried Zener diode reference which is trimmed for absolute accuracy and temperature coefficient. The reference is internally connected to the DAC. Since the DAC has a variable input impedance at its reference input the Zener diode reference is buffered. This buffered reference is available to the user to drive the circuitry required for bipolar output ranges. It can be used as a reference for other parts in the system provided it is externally buffered. The reference will give long-term stability comparable with the best discrete Zener reference diodes. The performance of the AD7245A/AD7248A is specified with internal reference, and all the testing and trimming is done with this reference. The reference should be decoupled at the REF OUT pin and recommended decoupling components are 10 µF and 0.1 µF capacitors in series with a 10 Ω resistor. A simplified schematic of the reference circuitry is shown in Figure 3. VDD OP AMP SECTION IC The output of the voltage mode D/A converter is buffered by a noninverting CMOS amplifier. The user has access to two gain setting resistors which can be connected to allow different output voltage ranges (discussed later). The buffer amplifier is capable of developing up to 10 V across a 2 kΩ load to GND. The output amplifier can be operated from a single positive power supply by tying VSS = AGND = 0 V. The amplifier can also be operated from dual supplies to allow a bipolar output range of –5 V to +5 V. The advantages of having dual supplies for the unipolar output ranges are faster settling time to voltages near 0 V, full sink capability of 2.5 mA maintained over the entire output range and elimination of the effects of negative offset on the transfer characteristic (outlined previously). Figure 2 shows the sink capability of the amplifier for single supply operation. AGND Figure 3. Internal Reference DIGITAL SECTION The AD7245A/AD7248A digital inputs are compatible with either TTL or 5 V CMOS levels. All data inputs are static protected MOS gates with typical input currents of less than 1 nA. The control inputs sink higher currents (150 µA max) as a result of the fast digital interfacing. Internal input protection of all logic inputs is achieved by on-chip distributed diodes. 4 ISINK – mA REF OUT IC IS TEMPERATURE COMPENSATION CURRENT 5 The AD7245A/AD7248A features a very low digital feedthrough figure of 10 nV-s in a 5 V output range. This is due to the voltage mode configuration of the DAC. Most of the impulse is actually as a result of feedthrough across the package. 3 INTERFACE LOGIC INFORMATION—AD7245A 2 Table I shows the truth table for AD7245A operation. The part contains two 12-bit latches, an input latch and a DAC latch. CS and WR control the loading of the input latch while LDAC controls the transfer of information from the input latch to the DAC latch. All control signals are level triggered; and therefore, either or both latches may be made transparent, the input latch by keeping CS and WR “LOW”, the DAC latch by keeping LDAC “LOW.” Input data is latched on the rising edge of WR. 1 TA = T MIN TO T MAX 0 TO DAC V-TO-I 0 1 2 6 3 4 5 7 OUTPUT VOLTAGE – Volts 8 9 10 Figure 2. Typical Single Supply Sink Current vs. Output Voltage –8– REV. B AD7245A/AD7248A The data held in the DAC latch determines the analog output of the converter. Data is latched into the DAC latch on the rising edge of LDAC. This LDAC signal is an asynchronous signal and is independent of WR. This is useful in many applications. However, in systems where the asynchronous LDAC can occur during a write cycle (or vice versa) care must be taken to ensure that incorrect data is not latched through to the output. For example, if LDAC goes LOW while WR is “LOW,” then the LDAC signal must stay LOW for t7 or longer after WR goes high to ensure correct data is latched through to the output. t1 5V CS 0V t3 t4 t2 5V LDAC t5 CS Function H H H H H H H L g L H H H H L g X H L H X L g H H X H L X H L L H H X H g L L L Both Latches are Transparent Both Latches are Latched Both Latches are Latched Input Latches Transparent Input Latches Latched DAC Latches Transparent DAC Latches Latched DAC Latches Loaded with all 0s DAC Latches Latched with All 0s and Output Remains at 0 V or –5 V Both Latches are Transparent and Output Follows Input Data t6 0V HIGH IMPEDANCE BUS VALID DATA Table I. AD7245A Truth Table LDAC WR 0V t7 DATA CLR 5V WR 5V 0V NOTES 1. SEE TIMING SPECIFICATIONS. 2. ALL INPUT RISE AND FALL TIMES MEASURES FROM 10% TO 90% OF 5V, tr = tf = 5ns. 3. TIMING MEASUREMENT REFERENCE LEVEL IS VINH + V INL 2 4. IF LDAC IS ACTIVATED WHILE WR IS LOW, LDAC MUST STAY LOW FOR t7 OR LONGER AFTER WR GOES HIGH. Figure 5. AD7245A Write Cycle Timing Diagram INTERFACE LOGIC INFORMATION—AD7248A The input loading structure on the AD7248A is configured for interfacing to microprocessors with an 8-bit wide data bus. The part contains two 12-bit latches—an input latch and a DAC latch. Only the data held in the DAC latch determines the analog output from the converter. The truth table for AD7248A operation is shown in Table II, while the input control logic diagram is shown in Figure 6. H = High State, L = Low State, X = Don’t Care DAC LATCH LDAC The contents of the DAC latch are reset to all 0s by a low level on the CLR line. With both latches transparent, the CLR line functions like a zero override with the output brought to 0 V in the unipolar mode and –5 V in the bipolar mode for the duration of the CLR pulse. If both latches are latched, a “LOW” pulse on the CLR input latches all 0s into the DAC latch and the output remains at 0 V (or –5 V) after the CLR line has returned “HIGH.” The CLR line can be used to ensure power-up to 0 V on the AD7245A output in unipolar operation and is also useful, when used as a zero override, in system calibration cycles. 12 4 CSMSB UPPER 4 BITS OF INPUT LATCH 8 LOWER 8 BITS OF INPUT LATCH CSLSB WR Figure 4 shows the input control logic for the AD7245A and the write cycle timing for the part is shown in Figure 5. 8 DB7 – DB0 LDAC Figure 6. AD7248A Input Control Logic DAC LATCH CLR WR CS INPUT LATCH INPUT DATA Figure 4. AD7245A Input Control Logic REV. B CSMSB, CSLSB and WR control the loading of data from the external data bus to the input latch. The eight data inputs on the AD7248A accept right justified data. This data is loaded to the input latch in two separate write operations. CSLSB and WR control the loading of the lower 8-bits into the 12-bit wide latch. The loading of the upper 4-bit nibble is controlled by CSMSB and WR. All control inputs are level triggered, and input data for either the lower byte or upper 4-bit nibble is latched into the input latches on the rising edge of WR (or either CSMSB or CSLSB). The order in which the data is loaded to the input latch (i.e., lower byte or upper 4-bit nibble first) is not important. –9– AD7245A/AD7248A The LDAC input controls the transfer of 12-bit data from the input latch to the DAC latch. This LDAC signal is also level triggered, and data is latched into the DAC latch on the rising edge of LDAC. The LDAC input is asynchronous and independent of WR. This is useful in many applications especially in the simultaneous updating of multiple AD7248A outputs. However, in systems where the asynchronous LDAC can occur during a write cycle (or vice versa) care must be taken to ensure that incorrect data is not latched through to the output. In other words, if LDAC goes low while WR and either CS input are low (or WR and either CS go low while LDAC is low), then the LDAC signal must stay low for t7 or longer after WR returns high to ensure correct data is latched through to the output. The write cycle timing diagram for the AD7248A is shown in Figure 7. t1 5V CSLSB t1 APPLYING THE AD7245A/AD7248A The internal scaling resistors provided on the AD7245A/ AD7248A allow several output voltage ranges. The part can produce unipolar output ranges of 0 V to 5 V or 0 V to 10 V and a bipolar output range of –5 V to +5 V. Connections for the various ranges are outlined below. UNIPOLAR (0 V TO 10 V) CONFIGURATION The first of the configurations provides an output voltage range of 0 V to 10 V. This is achieved by connecting the bipolar offset resistor, ROFS, to AGND and connecting RFB to VOUT. In this configuration the AD7245A/AD7248A can be operated single supply (VSS = 0 V = AGND). If dual supply performance is required, a VSS of –12 V to –15 V should be applied. Figure 8 shows the connection diagram for unipolar operation while the table for output voltage versus the digital code in the DAC latch is shown in Table III. 0V 10⍀ 5V CSMSB t3 t4 t3 t2 0.1F 10F 0V t4 t2 5V WR t7 VDD ROFS REF OUT 2R RFB 2R 0V 5V LDAC t5 t5 t6 VALID DATA VOUT DAC VREF t6 VALID DATA DATA IN REF 0V AD7245A/AD7248A* 5V DGND *DIGITAL CIRCUITRY OMITTED FOR CLARITY 0V VSS AGND Figure 7. AD7248A Write Cycle Timing Diagram An alternate scheme for writing data to the AD7248A is to tie the CSMSB and LDAC inputs together. In this case exercising CSLSB and WR latches the lower 8 bits into the input latch. The second write, which exercises CSMSB, WR and LDAC loads the upper 4-bit nibble to the input latch and at the same time transfers the 12-bit data to the DAC latch. This automatic transfer mode updates the output of the AD7248A in two write operations. This scheme works equally well for CSLSB and LDAC tied together provided the upper 4-bit nibble is loaded to the input latch followed by a write to the lower 8 bits of the input latch. Figure 8. Unipolar (0 to 10 V) Configuration Table III. Unipolar Code Table (0 V to 10 V Range) DAC Latch Contents MSB LSB Analog Output, VOUT 4095 1111 1111 1111 +2 VREF ⴛ 4096 1000 0000 0001 +2 VREF ⴛ 4096 1000 0000 0000 +2 VREF ⴛ = +VREF 4096 0111 1111 1111 +2 VREF ⴛ 4096 0000 0000 0001 0000 0000 0000 +2 VREF ⴛ 4096 0V 2049 Table II. AD7248A Truth Table CSLSB CSMSB WR LDAC Function L L g H H H H H H H H H H L L g H H L H L g L L g L H H L H H H H H H H L g L H Load LS Byte into Input Latch Latches LS Byte into Input Latch Latches LS Byte into Input Latch Loads MS Nibble into Input Latch Latches MS Nibble into Input Latch Latches MS Nibble into Input Latch Loads Input Latch into DAC Latch Latches Input Latch into DAC Latch Loads MS Nibble into Input Latch and Loads Input Latch into DAC Latch No Data Transfer Operation 2048 2047 1 1 NOTE: 1 LSB = 2 ⴛ VREF(2–12) = VREF 2048 H = High State, L = Low State –10– REV. B AD7245A/AD7248A UNIPOLAR (0 V TO 5 V) CONFIGURATION The 0 V to 5 V output voltage range is achieved by tying ROFS, RFB and VOUT together. For this output range the AD7245A/ AD7248A can be operated single supply (VSS = 0 V) or dual supply. The table for output voltage versus digital code is as in Table III, with 2 × VREF replaced by VREF. Note that for this range 1 1 LSB = VREF(2–12) = VREF ⴛ 4096 . In this case care must be taken to ensure that the maximum output voltage is not greater than VDD –3 V. The VDD–VOUT overhead must be greater than 3 V to ensure correct operation of the part. Note that VDD and VSS for the AD7245A/AD7248A must be referenced to DGND (system GND). The entire circuit can be operated in single supply with the VSS pin of the AD7245A/AD7248A connected to system GND. 10⍀ + BIPOLAR CONFIGURATION 10F 0.1F The bipolar configuration for the AD7245A/AD7248A, which gives an output voltage range from –5 V to +5 V, is achieved by connecting the ROFS input to REF OUT and connecting RFB and VOUT. The AD7245A/AD7248A must be operated from dual supplies to achieve this output voltage range. The code table for bipolar operation is shown in Table IV. 15V 2R DAC Latch Contents MSB LSB 1111 1111 Analog Output, VOUT 1000 0000 0001 1 +VREF × 2048 1000 0000 0000 0V 0111 1111 1111 –VREF × 2048 0000 0000 0001 –VREF × 2048 0000 0000 0000 –VREF × = –VREF 2048 –11 – 2047 +VREF × 2048 NOTE: 1 LSB = 2 × VREF(2 1 2047 ) = VREF PROGRAMMABLE CURRENT SINK Figure 10 shows how the AD7245A/AD7248A can be configured with a power MOSFET transistor, the VN0300M, to provide a programmable current sink from VDD or VSOURCE. The VN0300M is placed in the feedback of the AD7245A/ AD7248A amplifier. The entire circuit can be operated in single supply by tying the VSS of the AD7245A/AD7248A to AGND. The sink current, ISINK, can be expressed as: ISINK = D ×VREF R1 10⍀ VSOURCE + 0.1F 10F VDD ROFS 2R LOAD 2R RFB ISINK VN0300M REF VREF VOUT DAC AD7245A/AD7248A* where D is a fractional representation of the digital word in the DAC latch and VBIAS is the voltage applied to the AD7245A/ AD7248A AGND pin. VOUT = 2(VBIAS + D ⴛ VREF) SYSTEM GND Figure 9. AGND Bias Circuit The AD7245A/AD7248A AGND pin can be biased above system GND (AD7245A/AD7248A DGND) to provide an offset “zero” analog output voltage level. With unity gain on the amplifier (ROFS = VOUT = R FB) the output voltage, VOUT is expressed as: VOUT = VBIAS + D ⴛ VREF If a gain of 2 is used on the buffer amplifier the output voltage, VOUT is expressed as VSS DGND AD589 REF OUT Because the current flowing out of the AGND pin varies with digital code, the AGND pin should be driven from a low impedance source. A circuit configuration is outlined for AGND bias in Figure 9 using the AD589, a +1.23 V bandgap reference. VOUT DAC VREF AD7245A/AD7248A* 2048 1 2048 RFB *DIGITAL CIRCUITRY OMITTED FOR CLARITY. AGND BIAS REV. B REF VBIAS + 1111 2R 27k⍀ AGND Table IV. Bipolar Code Table VDD ROFS REF OUT R1 *DIGITAL CIRCUITRY OMITTED FOR CLARITY. DGND AGND VSS Figure 10. Programmable Current Sink Using the VN0300M, the voltage drop across the load can typically be as large as VSOURCE –6 V) with VOUT of the DAC at 5 V. Therefore, for a current of 50 mA flowing in the R1 (with all 1s in the DAC register) the maximum load is 200 Ω with VSOURCE = 15 V. The VN0300M can actually handle currents up to 500 mA and still function correctly in the circuit, but in practice the circuit must be used with larger values of VSOURCE otherwise it requires a very small load. –11– AD7245A/AD7248A Since the tolerance value on the reference voltage of the AD7245A/ AD7248A is ± 0.2%, then the absolute value of ISINK can vary by ± 0.2% from device to device for a fixed value of R1. Adjusting the triwave applied to the AD639 adjust the distortion performance of the sine wave output, (10 V in configuration shown). Amplitude, offset and symmetry of the triwave can affect the distortion. By adjusting these, via VR1 and VR2, an output sine wave with harmonic distortion of better than –50 dB can be achieved at low and intermediate frequencies. Because the input bias current of the AD7245A/AD7248A’s op amp is only of the order of picoamps, its effect on the sink current is negligible. Tying the ROFS input to RFB input reduces this effect even further and prevents noise pickup which could occur if the ROFS pin was left unconnected. Using the capacitor value shown in Figure 11 for CF (i.e., 680 pF) the output frequency range is 0 to 100 kHz over the digital input code range. The step size for frequency increments is 25 Hz. The accuracy of the output frequency is limited to 8 or 9 bits by the AD537, but is guaranteed monotonic to 12 bits. The circuit of Figure 10 can be modified to provide a programmable current source to AGND or –VSINK (for –VSINK, dual supplies are required on the AD7245A/AD7248A). The AD7245A/AD7248A is configured as before. The current through R1 is mirrored with a current mirror circuit to provide the programmable source current (see CMOS DAC Application Guide, Publication No. G872-30-10/84, for suitable current mirror circuit). As before the absolute value of the source current will be affected by the ±0.2% tolerance on VREF. In this case the performance of the current mirror will also affect the value of the source current. MICROPROCESSOR INTERFACING—AD7245 AD7245A—8086 INTERFACE Figure 12 shows the 8086 16-bit processor interfacing to the AD7245A. In the setup shown in Figure 12, the double buffering feature of the DAC is not used and the LDAC input is tied LOW. AD0–AD11 of the 16-bit data bus are connected to the AD7245A data bus (DB0–DB11). The 12-bit word is written to the AD7245A in one MOV instruction and the analog output responds immediately. In this example the DAC address is D000. A software routine for Figure 12 is given in Table V. FUNCTION GENERATOR WITH PROGRAMMABLE FREQUENCY Figure 11 shows how the AD7245A/AD7248A with the AD537, voltage-to-frequency converter and the AD639, trigonometric function generator to provide a complete function generator with programmable frequency. The circuit provides square wave, triwave and sine wave outputs, each output of ± 10 V amplitude. ADDRESS BUS 8086 16-BIT LATCH ALE The AD7245A/AD7248A provides a programmable voltage to the AD537 input. Since both the AD7245A/AD7248A and AD537 are guaranteed monotonic, the output frequency will always increase with increasing digital code. The AD537 provides a square wave output which is conditioned for ± 10 V by amplifier A1. The AD537 also provides a differential triwave output. This is conditioned by amplifiers A2 and A3 to provide the ±1.8 V triwave required at the input of the AD639. The triwave is further scaled by amplifier A4 to provide a ±10 V output. ADDRESS DECODE CS LDAC AD7245A* WR WR DB11 DB0 AD15 ADDRESS/DATA BUS AD0 *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 12. AD7245A to 8086 Interface +15V 33k⍀ ⴞ10V SQUARE WAVE +15V VDD AD7245A/ AD7248A A1 +VS 15k⍀ 20k⍀ REF OUT ROFS VSS DGND AGND 10⍀ A2 +15V +15V 22k⍀ + GND O/P DEC +VS 4.7k⍀ 10k⍀ VR1 C CF 680pF AD537 4.12k⍀ 56k⍀ 56k⍀ RFB VOUT 82k⍀ 5k⍀ VR2 3.9k⍀ ⴞ10V TRI WAVE A4 5.6k⍀ 3.9k⍀ 4.12k⍀ 22k⍀ +15V A3 C X1 VOS 20k⍀ –VS +VS X2 W U1 Z1 U2 Z2 ⴞ1V SINE WAVE COM + 0.1F 10F AD639 A1, A2, A3, A4 – 2 ⴛ AD712 Y2 UP –15V –VS –15V Figure 11. Programmable Function Generator –12– REV. B AD7245A/AD7248A Table V. Sample Program for Loading AD7245A from 8086 ASSUME DS: DACLOAD, CS: DACLOAD DACLOAD SEGMENT AT 000 00 8CC9 MOV CS, CS : DEFINE DATA SEGMENT REGISTER 02 8ED9 MOV DS, CX : EQUAL TO CODE SEGMENT REGISTER 04 BF00D0 0MOV DI, #D000 : LOAD DI WITH D000 ADDRESS DECODE AS CS LDAC DTACK AD7245A* WR R/W DB11 DB0 D0–D15 07 C705 MOV MEM, : DAC LOADED WITH WXYZ “YZWX” #YZWX 0B EA00 00 0E 00 FF ADDRESS BUS MC68000 DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY : CONTROL IS RETURNED TO THE MONITOR PROGRAM Figure 14. AD7245A to MC68000 Interface Table VI. Sample Routine for Loading AD7245A from 68000 In a multiple DAC system the double buffering of the AD7245A allows the user to simultaneously update all DACs. In Figure 13, a 12-bit word is loaded to the input latches of each of the DACs in sequence. Then, with one instruction to the appropriate address, CS4 (i.e., LDAC) is brought LOW, updating all the DACs simultaneously. 01000 ADDRESS BUS 8086 ALE 16-BIT LATCH ADDRESS DECODE CS4 WR AD15 DATA BUS AD0 CS1 CS MOVE.W #X,D0 The desired DAC data, X, is loaded into Data Register 0. X may be any value between 0 and 4094 (decimal) or 0 and OFFF (hexadecimal). MOVE.W D0,$E000 The Data X is transferred between D0 and the DAC Latch. MOVE.B #228,D7 TRAP #14 Control is returned to the System Monitor Program using these two instructions. AD7245A* LDAC WR DB11 DB0 CS AD7245A* LDAC WR DB11 DB0 CS AD7245A* LDAC WR DB11 DB0 *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 13. AD7245A to 8086 Multiple DAC Interface MICROPROCESSOR INTERFACE—AD7248A Figure 15 shows the connection diagram for interfacing the AD7248A to both the 8085A and 8088 microprocessors. This scheme is also suited to the Z80 microprocessor, but the Z80 address/data bus does not have to be demultiplexed. Data to be loaded to the AD7248A is right justified. The AD7248A is memory mapped with a separate memory address for the input latch high byte, the input latch low byte and the DAC latch. Data is first written to the AD7248A input latch in two write operations. Either the high byte or the low byte data can be written first to the AD7248A input latch. A write to the AD7248A DAC latch address transfers the input latch data to the DAC latch and updates the output voltage. Alternatively, the LDAC input can be asynchronous or can be common to a number of AD7248As for simultaneous updating of a number of voltage channels. AD7245A—MC68000 INTERFACE ADDRESS BUS A8–A15 Interfacing between the MC68000 and the AD7245A is accomplished using the circuit of Figure 14. Once again the AD7245A is used in the single buffered mode. A software routine for loading data to the AD7245A is given in Table VI. In this example the AD7245A is located at address E000, and the 12-bit word is written to the DAC in one MOVE instruction. ALE 8085A/8088 OCTAL LATCH ADDRESS DECODE WR CSLSB CSMSB LDAC WR AD7248A* DB0–DB7 AD0–AD7 ADDRESS/DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY. Figure 15. AD7248A to 8085A/8088 Interface REV. B –13– AD7245A/AD7248A A connection diagram for the interface between the AD7248A and 68008 microprocessor is shown in Figure 16. Once again the AD7248A acts as a memory mapped device and data is right justified. In this case the AD7248A is configured in the automatic transfer mode which means that the high byte of the input latch has the same address as the DAC latch. Data is written to the AD7248A by first writing data to the AD7248A low byte. Writing data to the high byte of the input latch also transfers the input latch contents to the DAC latch and updates the output. A0–A19 Figure 18 shows a connection diagram between the AD7248A and the 8051 microprocessor. The AD7248A is port mapped in this interface and is configured in the automatic transfer mode. Data to be loaded to the input latch low byte is output to Port 1. Output Line P3.0, which is connected to CSLSB of the AD7248A, is pulsed to load data into the low byte of the input latch. Pulsing the P3.1 line, after the high byte data has been set up on Port 1, updates the output of the AD7248A. The WR input of the AD7248A can be hardwired low in this application because spurious address strobes on CSLSB and CSMSB do not occur. ADDRESS BUS ADDRESS DECODE AS 68008 CSLSB P3.0 CSLSB P3.1 CSMSB LDAC CSMSB LDAC WR 8051 WR R/W AD7248A* P1.0 DB0 P1.1 DB1 P1.2 DB2 P1.3 DB3 P1.4 DB4 P1.5 DB5 Figure 16. AD7248A to 68008 Interface P1.6 DB6 An interface circuit for connections to the 6502 or 6809 microprocessors is shown in Figure 17. Once again, the AD7248A is memory mapped and data is right justified. The procedure for writing data to the AD7248A is as outlined for the 8085A/8088. For the 6502 microprocessor the φ2 clock is used to generate the WR, while for the 6809 the E signal is used. P1.7 DB7 AD7248A* DTACK DB0–DB7 D0–D7 DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 18. AD7248A to MCS-51 Interface ADDRESS BUS A0–A15 R/W *ADDITIONAL PINS OMITTED FOR CLARITY. EN ADDRESS DECODE 6502/6809 2 OR E CSLSB CSMSB LDAC WR AD7248A* DB0–DB7 D0–D7 DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY. Figure 17. AD7248A to 6502/6809 Interface –14– REV. B AD7245A/AD7248A MECHANICAL INFORMATION—AD7245A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic DIP (N-24) 1.228 (31.19) 1.126 (31.14) 24 13 1 12 0.260 ⴞ 0.001 (6.61 ⴞ 0.03) PIN 1 0.11 (2.79) 0.09 (2.28) 0.02 (0.5) 0.09 (2.28) 0.060 (1.52) 0.015 (0.38) 0.07 (1.78) 0.05 (1.27) 0.32 (8.128) 0.30 (7.62) 0.130 (3.30) 0.128 (3.25) 0.015 (0.381) 0.008 (0.204) SEATING PLANE LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN LEAD PLATED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 24-Lead Cerdip (Q-24) 24-Lead SOIC (R-24) 0.614 (15.6) 0.598 (15.2) 24 13 1 24 0.295 (7.493) MAX 13 0.299 (7.6) 0.291 (7.4) 1 PIN 1 0.419 (10.65) 0.394 (10.00) 12 PIN 1 0.019 (0.49) 0.014 (0.35) SEATING 0.013 (0.32) PLANE 0.009 (0.23) 0.075 (1.91) REF 0.458 (11.63) 0.442 (11.23) 0.458 SQ (11.63) MAX SQ 0.095 (2.41) 0.075 (1.90) 8ⴗ 0ⴗ 0.005 (0.13) 0.016 (0.40) 4 4 28 0.011 (0.28) 0.007 (0.18) R TYP 5 0.055 (1.40) 0.045 (1.14) PIN 1 IDENTIFIER 26 25 0.021 (0.533) 0.013 (0.331) 0.430 (10.5) 0.050 ⴞ 0.005 0.390 (9.9) (1.27 ⴞ 0.13) TOP VIEW (PINS DOWN) 0.050 (1.27) BSC 11 18 5 0.028 (0.71) 0.022 (0.56) BOTTOM VIEW 19 0.180 (4.51) 0.165 (4.20) 0.032 (0.812) 0.026 (0.661) 1 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37) 28-Terminal Plastic Leaded Chip Carrier (P-28A) 0.300 (7.62)2 BSC 0.150 (3.51) BSC 26 25 0.320 (8.128) 0.290 (7.366) 0.180 0.225 (4.572) (5.715) MAX SEATING MAX PLANE 0.125 0.070 (1.778) (3.175) 0.012 (0.305) MIN 0.021 (0.533) 0.110 (2.794) 0.020 (0.508) 15ⴗ 0.008 (0.203) 0.090 (2.286) 0ⴗ 0.015 (0.381) TYP TYP LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. CERDIP LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 28-Terminal Leadless Ceramic Chip Carrier (E-28A) 0.100 (2.54)1 0.064 (1.63) 0.070 (1.78) 0.030 (0.76) 1.290 (32.77) MAX 0.104 (2.65) 0.093 (2.35) 0.012 (0.30) 0.050 0.004 (0.10) (1.27) BSC 11 12 19 18 12 0.200 (5.08) BSC 0.456 (11.58) SQ 0.450 (11.43) 0.495 (12.57) SQ 0.485 (12.32) 45ⴗ TYP NOTES 1THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS. 2APPLIES TO ALL FOUR SIDES. ALL TERMINALS ARE GOLD PLATED REV. B 12 –15– 0.110 (2.79) 0.085 (2.16) AD7245A/AD7248A MECHANICAL INFORMATION —AD7248A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.11 (2.79) 0.09 (2.28) 1.07 (27.18) MAX 20 11 1 10 0.255 (6.477) 0.245 (6.223) 20 11 1 PIN 1 0.32 (8.128) 0.29 (7.366) 0.021 (0.533) 0.015 (0.381) 0.145 (3.683) MIN 0.125 (3.175) MIN 0.18 (4.57) 0.125 (3.18) 0.150 (3.81) MIN 0.02 (0.5) 0.016 (0.41) 0.070 (1.78) 0.030 (0.76) 20-Terminal Plastic Leaded Chip Carrier (P-20A) 0.045 ⴞ 0.003 (1.143 ⴞ 0.076) 0.419 (10.65) 0.404 (10.00) 19 18 PIN 1 IDENTIFIER TOP VIEW (PINS DOWN) 0.011 (0.275) 0.005 (0.125) 0.020 (0.51) MAX 0.107 (2.72) 0.089 (2.26) 0.022 (0.56) 0.014 (0.36) SEATING PLANE 0.015 (0.38) 0.007 (0.18) 8ⴗ 0ⴗ 0.020 (0.51) MIN 3 4 8 0.0500 (1.27) BSC 0.173 ⴞ 0.008 (4.385 ⴞ 0.185) 0.105 ⴞ 0.015 SQ (2.665 ⴞ 0.375) 11 0.299 (7.60) 0.291 (7.40) PIN 1 0.015 (0.38) 0.008 (0.20) SEATING 15° PLANE 0° LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42 0.5118 (13.00) 0.4961 (12.60) 10 0.060 (1.52) 0.015 (0.38) 0.15 (3.8) 0.125 (3.18) 20-Lead SOIC (R-20) 1 0.320 (8.13) 0.290 (7.37) 0.97 (24.64) 0.935 (23.75) 0.20 (5.0) 0.14 (3.18) 0.070 (1.77) 0.045 (1.15) 20 0.310 (7.87) 0.220 (5.59) 10 PIN 1 0.011 (0.28) 15ⴗ 0.009 (0.23) 0 LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42 0.021 (0.533) 0.015 (0.381) C00996–0–3/01 (B) 20-Lead Cerdip (Q-20) 20-Lead Plastic DIP (N-20) 9 14 13 0.390 ⴞ 0.005 SQ (9.905 ⴞ 0.125) 0.050 (1.27) BSC 0.017 ⴞ 0.004 (0.432 ⴞ 0.101) 0.029 ⴞ 0.003 (0.737 ⴞ 0.076) 0.025 (0.64) MIN 0.105 ⴞ 0.015 (2.665 ⴞ 0.375) 0.034 (0.86) 0.018 (0.46) Revision History Location Page Changed VDD = 15 V ± 5% to VDD = 15 V ± 10% in Static Performance section in Test Conditions/Comments column . . . . . . . . 2 Changed A Version of Full-Scale Temperature Coefficient from ± 30 to ± 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changed B and T Versions of VDD Power Requirements from +11.4/+15.75 to +10.8/+16.5 for V min. Changed B and T Versions of VSS Power Requirements from –11.4/–15.75 to –10.8/–16.5 for V max . . . . . . . . . . . . . . . . . . . . . 2 Change to Note 1 and Note 9 of Specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Change to Note 2 in Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to R-24 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 –16– REV. B PRINTED IN U.S.A. Data Sheet changed from REV. A to REV. B.