THM3561_Rev1.01_E THM3561 Stepping Motor Driver with LVDS Interface Overview Features THM3561 is a motor driver for driving a unipolar stepping motor. It contains four built-in high-voltage and low on-resistance transistors and these are controlled by writing a setting register by a serial interface. LVDS transmission is possible in the serial interface, therefore; it achieves high noise resistance, high speeds and long-distance transmission. To return a sensor signal for position detection, THM3561 contains a built-in serial interface. It is possible to significantly reduce the number of parts. The arrangement of the motor driver and the high flexibility of the connection are possible as the serial interface is used to register reading, which corresponds to the cascade connection and multi-drop. As it is a simple communication protocol, it reduces the load on the CPU and can be easily controlled. This product will operate at 5V using a built-in regulator, however a 3.3V system microcontroller can be directly connected by supplying 3.3V to the VIO pin. It is possible to have a built-in clamp diode to the driver output, and to reduce the number of parts. The design of the damper circuit can be easily performed. <Motor driver unit> ・2-phase stepping motor driver ・Unipolar constant voltage drive ・Maximum output current 1.5A/phase (Tj=25˚C) ・Maximum output voltage 48V ( recommended 45V) ・Phase input mode and clock input mode can be selected by a setting pin <Serial interface> ・Maximum serial clock frequency 10Mbps ・Single-end transmission and LVDS transmission can be selected ・Bridge function from 4-wire CMOS level to LVDS ・Repeater function of LVDS with waveform and timing correction ・Maximum device address : 30 ・Writing of all device batch registers is also possible ・Built-in 4-bit parallel-serial conversion function for sensor connection. <Other> ・Various built- protection functions (UVLO, OCP and TSD) ・Fault detect output (OCP and TSD) ・Input voltage range 8V to 45V, absolute maximum rating: 48V ・Built-in regulator for internal power supply generation 5V ・package: QFN48 (7mm x 7mm) ・RoHS directive compliant Application ・ Amusement device ・ Multi-functional printer (OA device) ・ Industrial equipment, monitoring camera, etc. Use Case Diagram Controller Motor Driver THM3561 Serial signal for motor control (Forward Serial) Serial signal for seNsor signal transfer (Reverse Serial) Motor Driver THM3561 Motor Driver THM3561 Motor Driver THM3561 Motor Driver THM3561 Figure 1. Use Case Diagram Copyright(C)2015 THine Electronics, Inc. 1/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Block Diagram Figure 2. Block Diagram Pin Configurations Figure 3. Pin Configurations Copyright(C)2015 THine Electronics, Inc. 2/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Pin List Table 1. Pin Overview Pin name SDR_OUTn SDR_OUTp SDA_INn SDA_INp SCL_INn SCL_INp SCL_OUTp SCL_OUTn SDA_OUTp SDA_OUTn SDR_INp SDR_INn Pin number 1 2 3 4 5 6 7 8 9 10 11 12 Type CLO *1 Description Serial signal output for sensor signal transfer (Reverse-Serial) Serial data input for motor control (Forward-Serial) CLI Serial clock input for motor control (Forward-Serial) Serial clock output for motor control (Forward-Serial) CLO Serial data output for motor control (Forward-Serial) CLI DMODE 13 IN ODSDRn 14 IN IMODE0 15 IN IMODE1 16 IN VREG5 17 IN VIO 18 PS TEST VCC 20 22 PS PDWN 23 IN DIOA 26 OM OUTA0 OUTA1 OUTB0 OUTB1 27,28 29,30 31,32 33,34 OM OM OM OM DIOB 35 OM FAULTn 38 OD GPIN0-3 A0-4 39,40,41,42 43,44,45,46,47 IN IN Serial signal input for sensor signal transfer (Reverse-Serial) Driver operation select mode High: clock input mode Low: Phase input mode For details, refer to “Driver operation mode” Sensor signal output select High: push-pull output Low: open drain output Interface select For details, refer to “Interface pin setting” Interface select For details, refer to “Interface pin setting” Internal LDO output (Typ. 5V) This pin usually gets connected to 4.7uF capacitor I/O power supply for interface input This pin usually gets connected to VREG5. This pin should be connected to a 3.3V power supply when you want to use the input directly from a 3.3V series host (microcomputer.) This pin must be connected to Low level Connect to power supply Power down input High: Low power state and internal logic reset Low: Normal operation High-side clamp diode A-phase output (A-phase A-phase common and cathode-side) A-phase output A-phase output B-phase output B-phase output High-side clamp diode B-phase output (B-phase, B-phase common and cathode-side) Fault detect output (OCP, TSD) Low: Fault detect / High-Z: Normal It will become an open-drain output. This pin is usually connected to 5V/3.3V with 1kohm or more pull-up resistor. General purpose digital input (Sensor signal input) Device address input Bit 0-4 Copyright(C)2015 THine Electronics, Inc. 3/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Pin List (continued) Table 2. Pin Overview (continued) Pin name Pin number Type*1 Description Internal oscillator frequency setting ROSC 48 IN Connect 47komh resistance between this pin and reference potential PGND 24,25,36,37 PS Power ground GND 19,21 PS Ground EXPGND 49 PS Exposed pad（Ground） *1: CLO = CMOS level or LVDS output, CLI = CMOS level or LVDS input, PS = Power supply, OD = Open drain output, OM = Motor drive output, IN = control input Interface Mode Pin Setting The #3_SDA_INn pin changes to “OMODE” pin (name) when used with 3-wire or 4-wire CMOS inputs The interface mode of the serial signal for motor control and serial signal for sensor signal transfers can be selected by setting IMODE1, IMODE0 pin and OMODE pin. Set as described in the following table depending on the connection point. ･Name of serial signal pin for motor control and name of serial signal for sensor signal transfer mentioned in the pin list are the pin names at the time of LVDS I/O setting. ･The #5_SCL_INn pin should be connected to “Low” level, if it uses a 3-wire CMOS input. Table 3. Interface Mode Setting Description Pin# LVDS input (IMODE0=H / IMODE1=L) LVDS output 3-wire CMOS input (IMODE0=L / IMODE1=H) LVDS output (OMODE=L) 4-wire CMOS input (IMODE0=H / IMODE1=H) 3-wire CMOS output (OMODE=H) 3-wire CMOS output (OMODE=H) LVDS output (OMODE=L) Serial signal for the motor control (Forward-Serial) Data input 3 4 SDA_INn (Diff.-) SDA_INp (Diff.+) OMODE（for details on High/Low settings, refer to the above mentioned） SDA_IN SI Clock input 5 SCL_INn (Diff.-) This should be connected to Low level, if it uses a 3-wire CMOS input 6 7 8 9 10 SCL_INp (Diff.+) SCL_OUTp (Diff.+) SCL_OUTn (Diff.-) SDA_OUTp (Diff.+) SDA_OUTn (Diff.-) Data output Clock output CSn SCL_IN SCL_OUTp SCL_OUTn SDA_OUTp SDA_OUTn SCK SCL_OUT (NC) SDA_OUT (NC) SCL_OUTp SCL_OUTn SDA_OUTp SDA_OUTn SCL_OUT (NC) SDA_OUT (NC) SDR_INp SDR_INn SDR_IN (NC) Serial signal for sensor signal transfer (Reverse-Serial) Output Input 1 2 11 12 SDR_OUTn(Diff.-) SDR_OUTp(Diff.+) SDR_INp(Diff.+) SDR_INn(Diff.-) (NC) SO SDR_INp SDR_INn Copyright(C)2015 THine Electronics, Inc. 4/21 SDR_IN (NC) THine Electronics, Inc. Security E THM3561_Rev1.01_E Absolute Maximum Rating * Table 4. Absolute Maximum Rating Symbol VCC VOUT VDIO VRDIO IMOT IF(PEAK) IF(RMS) VIO VDIN PD TSTG Tj Parameter VCC supply voltage Driver output pin voltage Diode output pin voltage High-side diode reverse voltage Driver output current High-side diode forward current (Peak) High-side diode forward current (RMS) Interface supply voltage Digital input voltage Power dissipation Storage temperature Junction temperature Conditions Tj=25deg. Tj=25deg. ,t<1us Ta=25 deg. - Min. Max. -0.4 48 -0.4 48 -0.4 48 48 Limited by OCP function 1.8 1.2 -0.5 6.0 -0.5 6.0 4.4 -55 150 150 Unit V V V V A/phase A/phase A/phase V V W deg. deg. * “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” specify conditions for device operation. Recommended Operation Conditions Table 5. Recommended Operation Conditions Symbol VCC VOUT VDIO VRDIO VIO VDIN IOUT(PEAK) IOUT(RMS) IF Ta Parameter VCC supply voltage Driver output pin voltage Diode output pin voltage High-side diode reverse voltage Interface supply voltage Digital input voltage (VREG5) Digital input voltage (VIO) Driver output current (Peak) one phase Driver output current (Peak) total phase Driver output current (RMS) one phase Driver output current (RMS) total phase High-side diode forward current (Peak) Operating ambient temperature Conditions Tj=25deg.,t<1us Tj=25deg.,t<1us Tj=25deg. Tj=25deg. Tj=25deg.,t<1us - Min. 8 -0.3 -0.3 3.0 -0.3 -0.3 - Max. 45 45 45 45 VREG5+0.3 5.5 VIO+0.3 1.5 2.0 1.2 1.6 1.2 85 -40 Unit V V V V V V V A/phase A A/phase A A/phase deg. Electrical Characteristics Table 6. DC Specifications Vcc=12V, Ta=25deg. unless otherwise specified. Symbol Parameter ICC Vcc supply current ICCS VTHUVLO VDUVLO Power down current UVLO threshold (VCC: L→H) UVLO hysteresis RON Driver output ON resistance IOFF VF Driver output leak current High-side diode forward voltage Conditions CMOS input (*1) CMOS output (*2) LVDS input (*1) LVDS output (*3) PWDN=High Tj=25deg., IOUT=700mA Tj=85deg., IOUT=700mA Tj=25deg. If=700mA Copyright(C)2015 THine Electronics, Inc. 5/21 Min. Typ. Max. Unit - - 25 mA - - 40 mA 7.0 - 7.5 0.5 0.55 0.8 2.5 100 8.0 10 - uA V V ohm ohm uA V THine Electronics, Inc. Security E THM3561_Rev1.01_E Electrical Characteristics (continued) Table 7. DC Specifications (continued) Vcc=12V, Ta=25deg. unless otherwise specified. Symbol Parameter IR High-side diode reverse leak current IOCP VREG5 Over current detection level Internal regulator output voltage Digital input high level voltage (VREG5 system) Digital input low level voltage (VREG5 system) Digital high level voltage (VIO system) Digital low level voltage (VIO system) Digital input leak current PDWN input high level voltage PDWN input low level voltage Digital output high level voltage (VREG5 system) Digital output low level voltage (VREG5 system) Digital output high level voltage (VIO system) Digital output low level voltage (VIO system) Open drain output low level voltage (FAULTn) LVDS input differential voltage LVDS input leak current LVDS output differential voltage (SCL_OUT/SDA_OUT) LVDS output differential voltage (SDR_OUT) LVD output common voltage VIH(VREG5) VIL(VREG5) VIH(VIO) VIL(VIO) IIDIG VIH(PDWN) VIH(PDWN) VOH(VREG5) VOL(VREG5) VOH(VIO) VOL(VIO) VOL(FAULTn) VIDF IIL VODF VOC Conditions Tj=25deg. Tj=150deg. IO = 0 to 50mA Min. 2.0 4.5 Typ. 2.5 - Max. 10 5 3.2 5.5 Unit uA mA A V Except the PWDN 4.0 - - V Except the PWDN - - 1.0 V VIO=VREG5 VIO=3.3V VIO=VREG5 VIO=3.3V - 4.0 2.8 4.0 - - 1.0 0.8 ±10 1.0 V V V V uA V V IOL=1mA 4.0 - - V IOL=1mA - - 0.5 V IOL=1mA VIO x 0.7 - - V IOL=1mA - - VIO x 0.3 V IOL=1mA - 0.55 1 V ±100 - - ±30 mV uA 100ohm terminal 280 370 460 mV 100ohm terminal 350 350 560 mV 1.1 1.21 1.4 V VIC=1.2V - - (*1) Current will increase if internal regulator (VREG5) uses the external circuits. (*2) No termination resistor. (*3) It uses the SCL_OUT, SDA_OUT, SDR_OUT terminal resistor and 100ohm connection. Figure 4. LVDS Specification Copyright(C)2015 THine Electronics, Inc. 6/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Electrical Characteristics (continued) Table 8. AC Specifications Vcc=12V, Ta=25deg. unless otherwise specified. Symbol fOSC Parameter Internal oscillator frequency Conditions ROSC = 47kohm Min. 1.2 Typ. 1.6 Max. 2 Unit MHz tDOUT Driver output delay time OFF→ON Phase input mode - 3.6 - us Clock input mode - 4.2 - us tDOUT Driver output delay time ON→OFF Phase input mode - 3 - us Clock input mode - 3.6 - us tROUT Driver output rise time - 125 - ns tFOUT Driver output fall time - 140 - ns tOCP OCP recovery time - 1.28 - ms 12V, 700mA, Resistance load 0% → 100% (*4) 12V, 700mA, Resistance load 100% → 0% (*4) - (*4) Driver output ON resistance x 700mA=0%, 12V=100% Driver Output Timing The setting is reflected to the driver output by the internal oscillator after write to register. In the case of phase input mode, output is switched to the following post of time after write to register: OFF→ON: about 3.6us (Typ.) ON→OFF: about 3.0us (Typ.) In the case of clock input mode, output is switched to the following post of time after write to register: OFF→ON: about 4.2us (Typ.) ON→OFF: about 3.6us (Typ.) In the case of performing settings by which OFF→ON and ON→OFF are generated simultaneously at different output pins (for example, at the time of change-over of output at OUTA0 pin and OUTA1 pin of 2-phase excitation etc.), the delay difference of 2 outputs becomes dead time (this is when both terminals are turned OFF). Register write timing (The standard is the rise of CSn of only the final Byte for 4-wire CMOS setting.) SCK / SCL_IN SI / SDA_IN BIT7 BIT2 BIT1 BIT0 tDOUT(ON) OUT** OFF→ON OFF ON tDOUT(OFF) OUT** ON→OFF tFOUT ON tROUT OFF **: It’s either A0, A1, B0 and B1. Figure 5. Output Driver Timing Copyright(C)2015 THine Electronics, Inc. 7/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Electrical Characteristics (continued) Table 9. LVDS Specifications 1 (Forward-Serial input and Reverse-Serial output) Vcc=12V, Ta=25deg. unless otherwise specified. Symbol fSCL tDAH tDAL tSTAH tDSU tDHO tRDO tRRPT Parameter SCL frequency (*5) SCL high time SCL low time (*5) Header condition hold time SDA setup time SDA hold time SDR_OUT output delay time (*5) SDR propagation delay time (*5) Conditions VIO=VREG5, 100ohm terminal VIO=VREG5, 100ohm terminal Min. 40 50 4 4 3 - Typ. 20 10 Max. 10 35 20 Unit MHz ns ns ns ns ns ns ns Table 10. LVDS Specifications 2 (Forward-Serial output and Reverse-Serial input) Vcc=12V, Ta=25deg. unless otherwise specified. Symbol tr, tf tSTAH tDSU tDHO tRSU tRHO tPWE tPD Parameter SCL/SDA output rise and fall time Header condition hold time SDA setup time SDA hold time SDR setup time SDR hold time End pulse width SCL propagation delay time Conditions 100ohm terminal - Min. 6 6 5 10 10 25 - Typ. 8 10 10 40 21 Max. 12 20 20 70 35 Unit ns ns ns ns ns ns ns ns (*5) This parameter is applicable to write a register and read sensor signals (shift register mode). SCL frequency and SCL low time are limited by cascaded stages and wiring length if it use read sensor signal (address assign mode). Figure 6. LVDS Timing Chart Copyright(C)2015 THine Electronics, Inc. 8/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Electrical Characteristics (continued) Table 11. 3-wire CMOS Specifications 1 (Forward-Serial input and Reverse-Serial output) Vcc=12V, Ta=25deg. unless otherwise specified. Symbol fSCL tDAH tDAL tSTAH tDSU tDHO tRDO tRRPT Parameter SCL frequency (*6) SCL high time SCL low time (*6) Header condition hold time SDA setup time SDA hold time SDR_OUT output delay time (*6) SDR propagation delay time (*6) Conditions VIO=VREG5, 100ohm terminal VIO=VREG5, 100ohm terminal Min. 40 50 4 4 3 - Typ. 21 12 Max. 10 35 20 Unit MHz ns ns ns ns ns ns ns Table 12. 3-wire CMOS Specifications 2 (Forward-Serial output and Reverse-Serial input) Vcc=12V, Ta=25deg. unless otherwise specified. Symbol tr, tf tSTAH tDSU tDHO tRSU tRHO tPWE tPD Parameter SCL/SDA output rise and fall time Header condition hold time SDA setup time SDA hold time SDR setup time SDR hold time End pulse width SCL propagation delay time Conditions C=10pF - Min. 6 6 5 10 10 25 - Typ. 10 10 10 40 21 Max. 15 20 20 70 35 Unit ns ns ns ns ns ns ns ns (*6) This parameter is applicable to write a register and read sensor signals (shift register mode). SCL frequency and SCL low time are limited by cascaded stages and wiring length if it use read sensor signal (address assign mode). Figure 7. 3-wire CMOS Timing Chart Copyright(C)2015 THine Electronics, Inc. 9/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Electrical Characteristics (continued) Table 13. 4-wire CMOS Specifications Vcc=12V, Ta=25deg. unless otherwise specified. Symbol fSCK tCH tCL tDVCH tCHDX tCHSL tSLCH tCHSH tSHCH tSHSL tROD Parameter SCK frequency (*7) SCK high time SCK low time (*7) SI setup time SI hold time CSn not active hold time CSn active setup time CSn active hold time CSn not active setup time CSn not active time SO output delay time (*7) tRRPT SDR_IN/SO propagation delay time (*7) Conditions VIO=VREG5 VIO=VREG5 VIO=3.3V Min. 40 50 10 10 40 40 40 40 200 - Typ. 10.5 12.5 15.4 Max. 10 35 20 25 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns (*7) This parameter is applicable to write a register and read sensor signals (shift register mode). SCL frequency and SCL low time are limited by cascaded stages and wiring length if it use read sensor signal (address assign mode). Figure 8. 4-wire CMOS Timing Chart Copyright(C)2015 THine Electronics, Inc. 10/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E 3-wire CMOS Input and LVDS Input Initialization In the case of using 3-wire CMOS and LVDS input, perform the initialization before writing in the register after turning the power supply (VCC) on. If initialization is not performed, the first register writing (“1st Byte” to “Last Byte”) may not be performed. Initialization is not needed if the first register writing is not required. In a case such as this continually refresh all the registers (R00-R18). For performing the initialization, the initialization of the 3-wire CMOS and LVDS input is performed for all the devices that are connected in the post-stage, based on the input of pulse of Active-Low (pulse width: Min. 200ns) to CSn at the initial stage 4-wire CMOS input. In the case of a cascade connection, a transmission delay time of a few minutes of the cascade stage is needed for completion of initialization of the 3-wire CMOS and LVDS. VCC CSn Host SCK THM3561 SCL THM3561 SDA SI 4-wire CMOS SCL SDA 3-wire CMOS or LVDS Initialization Pattern (ex.1) Low-active pulse input to the CSn pin. Power supply VCC 1ms_Min. 200ns_Min. CSn (High) 4-wire CMOS input SCK (High) SI SCL_OUT 3-wire CMOS output or LVDS output SDA_OUT Initialization Pattern Initialization Pattern (ex.2) 1st Byte(Device Address) =FFh input Power supply VCC 1ms_Min. CSn 7 6 5 4 3 2 1 0 4-wire CMOS input SCK (High) SI 7 6 5 4 3 2 1 0 3-wire CMOS output or LVDS output SCL_OUT SDA_OUT Initialization Pattern Figure 9. 3-wire CMOS Input and LVDS Input Initialization Copyright(C)2015 THine Electronics, Inc. 11/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Functional Description High-side clamp diode This device contains clamp diode with high-side of each output driver. Connect the DIOA pin and DIOB pin (cathode side of clamp diode) to the power supply of the motor in order to protect the output driver from reverse electricity by the driving of the inductor. It is also recommended that the condenser of 1uF standard be connected to the VM line near the DIOA/DIOB pin of the driver, in order to prevent a rise in the clamp voltage due to fluctuations in the power supply of the motor (VM) due to power supply impedance. As a configuration of clamp circuit, zener diode or a resistor may also be inserted between the DIOA pin, DIOB pin and power supply of the motor. In the case of using zener diode, take care that the sum of the motor Vz (zener voltage) and Vf of clamp diode (forward voltage) does not exceed the recommended operation range of the driver output pins (OUTA0 to OUTB1 pins) of this product. In the case of using the resistor, Vr that is determined by the product of motor current and resistance value is added to Vf and the motor voltage, instead of Vz. Take care that this value does not exceed the recommended operation range of the driver output pins (OUTA0 to OUTB1 pins) of this product. Figure 10. Example of High-side Clamp Circuit [Calculation example] Condition: Motor voltage 12V / motor current 700mA Vf = 2.5V (typ.)@700mA Hence, 45V (recommended operating voltage) > 12V + 2.5V + Vz. Therefore, Vz< 30.5 V. (The zener voltage is sometimes higher than the increase in the current in 2-phase excitation etc. Depending upon the configuration of the system side circuit. Keep adequate margins at the time of designing.) Copyright(C)2015 THine Electronics, Inc. 12/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Functional Description (continued) Over Current Protection (OCP) and Blanking Function Setting. This device contains an Over Current Protection (OCP) function. The output transistor stops if a current of more than 2.5A (typ.) flows through the output OUTA0 ~ OUTB1 pins (hereinafter, denoted as “OUT pin” in the case of showing all driver output pins). This time, phase A and B work independently. The correlation between the pin at which an over current has been detected and the pin at which the output stops is as given in table 14. This time, FAULTn pin outputs Low level. Table 14. Over Current Detect Function Over current detect OUTA0 OUTA1 OUTB0 OUTB1 Output pins OUTA0/OUTA1 OUTB0/OUTB1 OFF (Hi-Z) Keep state OFF (Hi-Z) Keep state Keep state OFF (Hi-Z) Keep state OFF (Hi-Z) The over current protection function automatically recovers after about 1.28ms (typ.) after becoming effective. At the time of automatic recovery, the FAULTn terminal stops Low level output and returns to High-Z output. The blank function is the one by which the over current protection function becomes temporarily ineffective (mask) at the time of change-over, in order to prevent the incorrect operation of the over current protection function due to a spike current generated at the time of change-over of ON/OFF of the output driver. This function can be used by taking BLANK_EN bit of register as 1. Set the blank function effective as 1. The blank time is different for OFF→ON and ON→OFF of the output transistor. At the initial stage (BLANK_SEL=0), OFF→ON time becomes 1CLK (0.625us, typ.) and ON→OFF time becomes 2CLK (1.25us, typ.) of the built-in oscillator. In the case of BLANK_SEL=1, the OFF→ON time becomes 3CLK (1.875us, typ.) and ON→OFF time becomes 4CLK (2.5us, typ.). Thermal Shutdown (TSD) This device contains a Thermal Shutdown (TSD) function. The OUT pin turns all channels OFF and the output of VREG5 stops when the junction temperature of the product rises further exceeding the absolute maximum rated value. This time, FAULTn pin outputs L level. This function is designed for protection from smoke generation and fire and it actuates outside the absolute maximum rated value. Do the thermal designing while keeping an adequate margin so that this function does not actuate. Under Voltage Lock Out (UVLO) This device contains an Under Voltage Lock Out (UVLO) function for stable operation at the VCC and VREG5 pin. This device stops operation when the VCC voltage falls below 7.5V (typ.), or VREG5 voltage falls below 3.5V (typ.). Internal Regulator (VREG5) This device contains a 5V (Typ.) output internal regulator (VREG5) for the internal circuit operation. VCC voltage is depressed to about 5V inside this LSI. The VREG5 pin usually bypasses to GND with 4.7uF for normal operation. In addition, the VREG5 pin can be supplied to some external circuits (ex. sensor). Supply current is 50mA (Typ.) The VREG5 pin bypasses to GND with 10uF if it used with an external circuit. Copyright(C)2015 THine Electronics, Inc. 13/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Functional Description (continued) The internal circuit of this product operates on VREG5 voltage. However, in the case of using a host device of a 3.3V system (microcontroller etc.), the device can be directly connected to the pre-stage interface by supplying 3.3V to the VIO pin. The target pre-stage interface terminal is the SCK / CSn / SI / OMODE input pin and SO output pin in 4-wire CMOS mode. When the host device, which is directly connected to the pre-stage interface, is a 5V system, the VIO pin is shorted to VREG5 pin over the substrate. In this case, the pre-stage interface pin operates on a 5V system (using VREG5 power supply). Power Down (PDWN) This product can be changed to a low power state (power down) on setting the PDWN pin to High level. The internal circuit gets reset on setting this pin to High level and the resistor and internal step change reverts to the initial state. All driver outputs change to OFF. In the case of using this pin as a reset pin, the condenser connected to VREG5 is discharged and hence, it is recommended that the PDWN pin be kept at High level for about 100ms. If the discharging of the condenser is inadequate, an operation such as an unstable interface output may occur temporarily. Internal Oscillator Frequency Select (ROSC) This device contains an oscillator for internal logic circuit. This pin is usually connected to GND with a 47kohm pull-down resistor for the oscillator reference current. FAULTn Pin The FAULTn pin outputs Low level at the time of detecting Over Current Protection function (OCP) and detecting Thermal Shutdown function (TSD). It generally becomes an open drain output and becomes High-Z. In the case of using this pin for detection of abnormalities, use this by pulling up to the power supply line below 5V. Driver Operation Mode The operation mode of the stepping motor control can be selected by setting DMODE pin. Perform the settings as set out in the table below according to the operation mode to be used. Table 15. Operation Mode (DMODE) Setting DMODE Description 0 Phase input mode 1 Clock input mode [Phase input mode] Functions as phase input mode based on fixing the DMODE pin to Low level. In phase input mode, the value set in the register is directly reflected on output. [Clock input mode] Functions as clock input mode based on fixing the DMODE terminal to High level. In the clock input mode, internal step advances and output is changed according to the step when CK bit changes from 0 to 1. Step direction and excitation mode can be selected by the PEM bit. The excitation mode corresponds to phase 1 excitation / phase 2 excitation / phase 1-2 excitations. For resistor details, see the Register Map section. * The behavior in the case of change-over of mode during operation cannot be guaranteed. Copyright(C)2015 THine Electronics, Inc. 14/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Functional Description (continued) ODSDRn Pin Settings In case of using the multi-drop connection, the sensor can be used based on setting SDR_OUT of the post-stage device as open drain and setting SDR_IN input of the pre-stage device as pull-up. SDR_OUT output pin becomes the open drain output by fixing the ODSDRn pin to Low level. Set the pull-up as ON in register settings (SDR_PUPn=0) in the opposite pre-stage device. When connection with a pre-stage device becomes the cascade connection (1:1), fix the ODSDRn pin to High level and use it as a push-pull output. It is recommended that at this time the pull-up be set to OFF in the register settings of the pre-stage device, since the electricity consumption for Low level output lowers. Address specification mode can be used at the time of multi drop connection. See the Communication Protocol section described below) and shift resistor mode cannot be used. Device Address Setting The least significant 5 bits out of the device address 8 bits of the serial interface are set using pins A0 to A4. The most significant 3 bits are fixed to 3’b010 and these are classified as the communication for the LED driver LSI THL35XX series (most significant 2 bits are 2’b00) made by our company. Table 16. Device Address Setting Pin setting A4 A3 0 0 0 0 (Internal fix) 0 1 0 1 1 0 0 A2 0 0 | 1 1 1 1 A5 – A0 A1 0 0 A0 0 1 1 1 0 1 Device operation Only work with broadcast address mode Work with broadcast and address assign mode. (Please use it within this range.) Register write-protected (use of repeater ) (Ref.) LED driver THL35xx series (Setting example) In the case of terminals A4=Low, A3=Low, A2=Low, A1=Low, A0=High, The device address is set to 8’b01000001 (=8’h41). When all pins A0 to A4 are set to High level (device address 8’b01011111=8’h5F), register writing on this device is disabled. In the case of using only 3-wire CMOS → 3-wire CMOS repeater function or 4-wire CMOS → 3-wire CMOS bridge function without using the motor driver output of the wire bridge function, set all A0 to A4 to High level. The device address 8’b01000000 (=8’h40) becomes the device address for writing on all the connected motor drivers (broadcast). When all A0 to A4 are set to Low level, the device operates only by broadcast specification. Set the device address within the range from 8’b01000001 (=8’h41) to 8’b01011110(=8’h3E). Copyright(C)2015 THine Electronics, Inc. 15/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Register Map This product controls the operation of the output transistor by setting a value in the internal register using serial communication. The function differs depending upon the operation mode and hence, check the mode that is set at the external pin (DMODE) in the following table. Table 17. Register Map (a) Register address (Run command) Bit Phase input mode (DMODE = “Low”) Default Function 7 0 SDR_PUPn 6 0 Reserved 5 0 BLANK_EN 4 0 BLANK_SEL 3 0 IN_B1 2 0 IN_B0 1 0 IN_A1 0 0 IN_A0 8'h00 (b) Register address (Run command) 8'h00 Description SDR_IN(*1) Pull-up setting 0:ON 1:OFF Reserved bit Please usually set to “0”. Blank function setting Please usually set to “1”. Blank time driver ON 0:1CLK 1:3CLK Setting(*2) driver OFF 0:2CLK 1:4CLK OUTB1 Output transistor 0:ON 1:OFF OUTB0 Output transistor 0:ON 1:OFF OUTA1 Output transistor 0:ON 1:OFF OUTA0 Output transistor 0:ON 1:OFF Clock input mode (DMODE = “High”) Bit Default Function 7 0 SDR_PUPn 6 0 Reserved 5 0 BLANK_EN 4 0 BLANK_SEL 3 0 2 0 1 0 CW/CCW 0 0 CK Description SDR_IN(*1) Pull-up setting 0:ON 1:OFF Reserved bit Please usually set to “0”. Blank function setting Please usually set to “1”. Blank time driver ON 0:1CLK 1:3CLK Setting(*2) driver OFF 0:2CLK 1:4CLK Set the excitations 2'b00: All output OFF 2'b10: 2phase excitation PEM 2'b01: 1phase excitation 2'b11: 1-2phase excitation Set the direction of step.(*2) 0: CW 1: CCW Advance the internal step. 0 → 1: Advanced step other: kept step (*1) The pin name varies depending upon the output mode. For details, see the Pin List. In case of LVDS output, the SDR_INp pin is used as an internal pull-up and the SDR_Inn pin is used as pull-down. In the case of CMOS output, the SDR_IN pin is used as an internal pull-up. (*2) CLK that becomes the standard of blank time becomes the internal OSCCLK (typ. 1.6MHz). (*3) For details of the output transistor operation by step forward direction settings, see the items of [Clock Input Mode] of Driver Operation Mode. Copyright(C)2015 THine Electronics, Inc. 16/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Communication Protocol The serial communication of this product is controlled by the following protocol. Table 18. Communication Protocol Byte Number 0 1 2~ Data type IN OUT Data type IN OUT Data type IN OUT 7 6 0 - 1 - CMD7 - CMD6 - DATA7 DATA7 DATA6 DATA6 Bit Number 4 3 2 Device address 0 A4 A3 A2 Run command CMD5 CMD4 CMD3 CMD2 Read and write data DATA5 DATA4 DATA3 DATA2 DATA5 DATA4 DATA3 DATA2 5 1 0 A1 - A0 - CMD1 - CMD0 - DATA1 DATA1 DATA0 DATA0 Data direction ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ The serial interface is a clock synchronization system, which performs writing in register and reading of sensor signals (GPIN3 to GPIN0 pin input). In the case of consolidating GPIN3 to GPIN0 pins to 4-bit, this has been denoted below as “GPIN Pin”. ・ The data length is 8-bit and MSB is first. For the specification method of the header bit (Header Condition), see the Electrical Characteristics section. ・ The first 8-bit including the header bit are denoted as “byte 0” and the next 8-bit are denoted as “byte 1”. ・ The address of the device that carries out the communication is specified by byte 0. All devices (only motor driver) are accessed on specifying the device address at 8’h40. Here, the device for which device address is set as 8’h5F at the pins A4 to A0 is excluded. ・ Execution command is specified by byte 1. For execution command, see Table 19. ・ Byte 2 onwards is writing and reading data. The content of write/read data vary depending upon the execution command specified by byte 1. Hence, check the details for each command. Table 19. Command Descriptions Command Run write to register write register read sensor signals (address assign mode) write register / read sensor signals (address assign mode) read sensor signals (shift register mode) read sensor signals (GPIN pin data) address assign shift register mode mode HEX BIN write register 8’h00 8’b00000000 ○ × × 8’h88 8’b10001000 × ○ × 8’h80 8’b10000000 ○ ○ × 8’hAA 8’b10101010 × × ○ Do not specify the commands other than those given above. If not particularly specified in this paragraph, the communication protocol/data example is seen from the host (CPU, microcontroller). Copyright(C)2015 THine Electronics, Inc. 17/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Serial interface Connections [Cascade Connection] Figure 11. Cascade Connection [Multi-drop Connection] Figure 12. Multi-drop Connection Copyright(C)2015 THine Electronics, Inc. 18/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Serial Interface Connections (continued) [Cascade and multi-drop connection] Figure 13. Cascade and Multi-drop Connection Only address specification mode can be used for sensor signals in the case of multi-drop connection and cascade / multi-drop mixed connection. In the case of using sensor signals, set the SDR_OUT output to which plurality of devices are connected, to open drain mode (ODSDRn pin =“L”). Also, set the SDR_IN input of the opposite device to internal pull-up ON (SDR_PUPn register = “L”). In the case of using sensor signals for multi-drop connection (including mixing with cascade connection), the transfer rate lowers drastically for CMOS connections when compared to the LVDS connection. In the case of selecting this configuration, the use of LVDS connection is recommended. For details on communication rate etc., see application note. Copyright(C)2015 THine Electronics, Inc. 19/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Package Figure 14. Package Copyright(C)2015 THine Electronics, Inc. 20/21 THine Electronics, Inc. Security E THM3561_Rev1.01_E Notices and Requests 1. 2. 3. 4. 5. 6. 7. 8. 9. The product specifications described in this material are subject to change without prior notice. The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. This product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the product. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. Please note that this product is not designed to be radiation-proof. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. THine Electronics, Inc. [email protected] Copyright(C)2015 THine Electronics, Inc. 21/21 THine Electronics, Inc. Security E