PLL Frequency Synthesizer ADF4108S 1.0. SCOPE This specification documents the detail requirements for space qualified product manufactured on Analog Devices, Inc.'s QML certified line per MIL-PRF-38535 Level V except as modified herein. The manufacturing flow described in the STANDARD SPACE LEVEL PRODUCTS PROGRAM brochure is to be considered a part of this specification. http://www.analog.com/aeroinfo This data sheet specifically details the space grade version of this product. A more detailed operational description and a complete data sheet for commercial product grades can be found at www.analog.com/ADF4108. 2.0. Part Number: The complete part number(s) of this specification follows: Part Number Description ADF4108L703F Radiation tested to 50Krads, 1 to 7 GHz PLL Frequency Synthesizer 3.0. Case Outline The case outline(s) are as designated in MIL-STD-1835 as follows: Outline letter X Descriptive designator CDFP4-F16 Terminals 16 lead Package style Bottom Brazed Flat Pack Package: F Pin Number Terminal Symbol Pin Type 1 Rset Analog Input 2 CP Analog Output 3 4 CPGND AGND Ground Ground 5 RFinB Analog Input 6 RFinA Analog Input 7 AVdd Power 8 REFin Analog Input 9 DGND Ground 10 CE Digital Input 11 CLK Digital Input 12 DATA Digital Input 13 LE Digital Input 14 MUXOUT Digital Output 15 DVdd Power 16 Vp Power Pin Description Bias for charge pump. Connecting a resistor between this pin and CPGND set the maximum charge pump current to: Icp max = 25.5 / Rset. The nominal output voltage is 0.66V Charge Pump Output. When enabled, this pin provides ±Icp to the external loop filter, which in turn drives the external VCO. Charge Pump Ground. Connect to low impedance ground. Analog Ground. Connect to low impedance ground. Complementary Input to the RF Prescaler. This pin must be decoupled to ground plane with a small bypass capacitor, typically 100pF. Input to the RF Prescaler. This pin must be ac-coupled to external VCO. Analog supply voltage. 3.2V to 3.6V. AVdd and DVdd should be tied together externally and properly bypassed. Reference Input. This is a CMOS input with a nominal threshold of Vdd/2 and a equivalent input resistance of 100kΩ. Digital Ground. Connect to low impedance ground. Chip Enable. High impedance CMOS input. A logic low on this pin powers down the part and puts the charge pump output into three-state mode. Serial Clock input. High impedance CMOS input. Used to clock in serial data to registers. Serial Data Input. High impedance CMOS input. Data loaded MSB first with the 2 LSBs being the control bits. Load Enable. High impedance CMOS input. When LE rises, shift register data is loaded into one of four latches selected using the control bits. Muxtiplexer Output. Allows either lock detect, or frequency divided RF or REF to accessed externally. Digital Supply Voltage. 3.2V to 3.6V. AVdd and DVdd should be tied together externally and properly bypassed. Charge Pump Power Supply. Must be greater than or equal to Vdd and less than 5.5V. Figure 1 - Terminal connections. ASD0016548 Rev.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2013 Analog Devices, Inc. All rights reserved. ADF4108S 4.0. Specifications 4.1. Absolute maximum ratings 1/ AVdd to GND ................................................................................................................................-0.3V to +3.9 V AVdd to DVdd................................................................................................................................-0.3V to +0.3 V Vp to GND ....................................................................................................................................-0.3V to +5.8 V Vp to AVdd....................................................................................................................................-0.3V to +5.8 V Digital I/O Voltage to GND ...................................................................................................-0.3V to Vdd + 0.3 V Analog I/O Voltage to GND .....................................................................................................-0.3V to Vp +0.3 V REFin, RFinA, RFinB to GND ...............................................................................................-0.3V to Vdd +0.3 V RFinA to RFinB ………………………................................................................................................. +/- 600 mV Operating Temperature Range ................................................................................................-55 ºC to +125 ºC Storage Temperature Range................................................................................................... –65°C to +150 °C Maximum Junction Temperature (TJ)........................................................................................................150 °C Lead Temperature (Soldering 60 Sec).....................................................................................................+300 °C Thermal resistance, junction-to-case (θJC)...........................................................................................31 °C/W 2/ Thermal resistance, junction-to-ambient (θJA)....................................................................................36 °C/W 2/ 4.2. Recommended operating conditions AVdd = DVdd ………………………................................................................................................3.2 V to 3.6 V Vp ………………………....................................................................................................................Vdd to 5.5 V Ambient Operating Temperature Range …………….............................................................. -55 ºC to +125 ºC 4.3. Nominal operating performance characteristics (TA = 25°C, AVDD = DVDD = 3.3V, GND = AGND = DGND = CPGND = 0V, VCP = 5V, RSET = 5.1kΩ, RFinB cap coupled to ground, unless otherwise noted) RF Frequency....................................................................................................................... 1.0 GHz to 7.0 GHz REF Frequency.................................................................................................................... 20 MHz to 250 MHz Phase Detector Max sampling Frequency ………………………................................................................................. 104 MHz Logic In Max Input Capacitance ……………………….......................................................................................... 10 pF REFin Max Input Capacitance ……………………….......................................................................................... 10 pF Noise Characteristics Normalized Phase Noise Floor (PNSYNTH)............................................................................... -223 dBc/Hz 3/ Normalized 1/f Noise (PN1_f) ................................................................................................. -122 dBc/Hz 4/ Phase Noise Performance 7900 MHz Output.......................................................................... -81 dBc/Hz 5/ Spurious Signals 7900 MHz Output.............................................................................................. -82 dBc 5/ NOTES 1/ Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2/ Measurement taken under absolute worst case condition and represents data taken with a thermal camera for highest power density location. See MIL-STD-1835 for average package Theta JC numbers. 3/ PLL loop B/W = 500 kHz, measured at 100 kHz offset. The synthesizers phase noise is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value) and 10log FPFD. So PNSYNTH = PNTOT – 10 log FPFD - 20 log N. 4/ 10 kHz offset; normalized to 1 GHz. The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) – 10log(fRF/ 1GHz). 5/ At VCO output and 1 kHz offset. fREFIN = 10MHz, dB RF Amp so that the PLL RFin = +5dBm. fPFD = 1MHz, fRF = 7900MHz, N = 7900; Loop B/W = 30kHZ, VCO = ZComm CRO8000Z with +10 ASD0016548 Rev. A | Page 2 of 21 ADF4108S TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS Parameter Symbol See notes at end of table RFin Charateristics, pin RFinA, RFinB RFin Input Frequency RFfreq Conditions 1/ Unless Otherwise Specified Tested at Vdd/Vcp = 3.6/3.6; 3.6/5.5; 3.2/3.2 M,D,P,L RFin Input Frequency RFin Input Sensitivity RFfreq 2/ RFlvl M,D,P,L Maximum Allowable Prescaler Output Frequency Fpresc 3/ PreScaler = 8, Tested at Vdd/Vcp = 3.6/5.5; 3.2/3.2 M,D,P,L SubGroup Limit Min Limit Max 4 1 5 5,6 1 5 4 1 5 4 5 7 5,6 5 7 4 -5 5 5,6 -5 5 4 -5 5 4 300 5,6 300 4 300 Units GHz GHz dBm MHz REFin Charateristics, pin REFin REFin Input Frequency REFfreq M,D,P,L REFin Input Sensitivity REFlvl AC coupling ensures bias = AVDD/2 M,D,P,L REFin Input High/Low Current REF_Iin M,D,P,L 4 20 250 5,6 20 250 4 20 250 4 0.8 VDD 5,6 0.8 VDD 4 0.8 VDD 4 -100 100 5,6 -100 100 4 -100 100 1 2.5 7.5 2,3 2.5 7.5 MHz Vp-p μA Charge Pump, pin CP Icp Sink/Source High Value Icp8 With Rset = 5.1KΩ M,D,P,L Icp Sink/Source Low Value Icp1 With Rset = 5.1KΩ M,D,P,L Icp Sink/Source Absolute Accuracy Icp Sink/Source Rset Range Icp Three-State Leakage Icp8AbsAcc M,D,P,L RsetRng 2/ ICP_lkg M,D,P,L See footnotes at end of table. ASD0016548 Rev. A | Page 3 of 21 1 2.5 7.5 1 0.125 1.250 2,3 0.125 1.250 1 0.125 1.250 1 -10 10 2,3 -10 10 1 -10 10 1 3.0 11.0 2,3 3.0 11.0 1 -15 15 -2,3 -15 15 1 -20 20 mA mA % kΩ nA ADF4108S TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Parameter See notes at end of table Charge Pump – continued Icp Sink/Source Current matching Icp Vs. Vcp Symbol ICP_m Conditions 1/ Unless Otherwise Specified Icp1- Icp8, With Rset = 5.1KΩ, M,D,P,L ICP_VCP With Rset = 5.1KΩ, 0.5 v ≤ Vcp ≤ Vp – 0.5 V M,D,P,L Icp Vs. temperature ICP_T Rset Output Voltage Vrset 2/ With Rset = 5.1KΩ, Vcp = Vp / 2 With Rset = 5.1KΩ, M,D,P,L SubGroup Limit Min Limit Max 1 -10 10 2,3 -10 10 1 -10 10 1 -8 8 2,3 -8 8 1 -8 8 1 -5 5 2,3 -5 5 1 0.5 0.7 2,3 0.5 0.7 1 0.5 0.7 Units % % % V Logic Inputs, pins CE, LE, CLOCK, DATA Input High Voltage ViH M,D,P,L Input Low Voltage ViL M,D,P,L Input High/Low Current IInH , IInL V of IInH = 3.2 V, V of IInL = 0.1 V M,D,P,L 1 1.4 Vdd 2,3 1.4 Vdd 1 1.4 Vdd 1 0 0.6 2,3 0 0.6 1 0 0.6 1 -1 1 2,3 -1 1 1 -1 1 1 1.4 2,3 1.4 1 1.4 1 Vdd – 0.4 2,3 Vdd – 0.4 1 Vdd – 0.4 V V μA Logic Outputs, pin MUXOUT N-channel Output High Voltage VOH 1 kΩ pull-up resistor to 1.8V M,D,P,L CMOS Output High Voltage VOH IOH = 500μA M,D,P,L Output Low Voltage Output High/ Low Leakage Current VOL IOL = 500μA V V 1 0.4 2,3 0.4 M,D,P,L 1 V of IOH = 3.2 V, V of IOL = 0.1 V, 1 -100 100 2,3 -100 100 1 -100 100 IOH , IOL MUXOUT tri-stated M,D,P,L See footnotes at end of table. ASD0016548 Rev. A | Page 4 of 21 V 0.4 μA ADF4108S TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Parameter See notes at end of table Timing Data to Clock setup time Symbol Conditions 1/ Unless Otherwise Specified t1 M,D,P,L Data to Clock hold time t2 M,D,P,L Clock high time t3 M,D,P,L Clock low time t4 M,D,P,L Data to LE setup time t5 M,D,P,L LE pulse width t6 M,D,P,L Figure 2 – Timing Diagram. ASD0016548 Rev. A | Page 5 of 21 SubGroup Limit Min 9 10 10,11 10 9 10 9 10 10,11 10 9 10 9 25 10,11 25 9 25 9 25 10,11 25 9 25 9 10 10,11 10 9 10 9 20 10,11 20 9 20 Limit Max Units nS nS nS nS nS nS ADF4108S TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Parameter See notes at end of table Power Supplies AVdd , DVdd Supply Voltage Symbol VDD Conditions 1/ Unless Otherwise Specified Pin AVdd, DVdd, with Avdd = DVdd M,D,P,L Vcp Supply Voltage VCP Pin Vp M,D,P,L 6/ pin Avdd, DVdd Idd Supply Current IDD Tested over supply range IDD = AIdd + DIdd, RF = 5GHz M,D,P,L 6/ Pin Vp Ip Supply Current Idd power down Current ICP IDIS Tested over supply range M,D,P,L 6/ 4/ AIdd + DIdd power down, Vcp power down M,D,P,L SubGroup Limit Min Limit Max 1 3.2 3.6 2,3 3.2 3.6 1 3.2 3.6 1 Vdd 5.5 2,3 Vdd 5.5 1 Vdd 5.5 1 17 2,3 17 1 17 1 0.4 2,3 0.4 1 0.4 1 10 2,3 10 1 15 Units V V mA mA μA TABLE I NOTES: 1/ TA Min = -55C, TA Max = 125C. AVDD = DVDD = 3.3V, GND = AGND = DGND = CPGND = 0V, VCP = 5V, RSET = 5.1kΩ, RF level = 0 dBm, REF level = 0.8 Vpp, RFinB cap coupled to ground unless otherwise noted. Values are relative to 50 Ω. 2/ Parameter is part of device initial characterization which is only repeated after design and process changes or with subsequent wafer lots. Parameter not tested post radiation. 3/ This specification is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4/ IDIS tested under four conditions: A. Initial power reset B. CE = 0.2V C. CE = 3.0 and Function latch bit DB21/DB3 = 01 D. CE = 3.0 and Function latch bit DB21/DB3 = 11. 5/ Digital pins tested with spec levels during digital pin testing (VIH, VIL, VOH, VOL). Relaxed Digital levels applied for device programing during other testing (VIL = 0.2, VIH = 3.0, VOH > 1.6 with CMOS output, VOL < 0.8). 6/ P = 64/65, R = 50, A = 468, 48, fPFD = 200kHz, REF = 10 MHz ASD0016548 Rev. A | Page 6 of 21 ADF4108S Figure 3 – Block Diagram. ASD0016548 Rev. A | Page 7 of 21 ADF4108S TABLE IIA – ELECTRICAL TEST REQUIREMENTS: Table IIA Test Requirements Interim Electrical Parameters Final Electrical Parameters Group A Test Requirements Group C end-point electrical parameters Group D end-point electrical parameters Group E end-point electrical parameters Subgroups (in accordance with MIL-PRF-38535, Table III) 1 1, 2, 3, 4, 5, 6 ,9,10,11 1/ 2/ 3/ 1, 2, 3, 4, 5, 6 ,9,10,11 1, 2, 3, 4, 5, 6 ,9,10,11 2/ 1, 2, 3, 4, 5, 6 ,9,10,11 1, 4, 9 Table IIA Notes: 1/ PDA apply to subgroup 1 only. Delta's are not excluded from PDA. 2/ See Table IIB for delta parameters. 3/ Parameters marked with note 2/ in Table I are part of device initial characterization which is only repeated after design and process changes or with subsequent wafer lots. TABLE IIB – BURN-IN/GROUP C DELTA LIMITS 1/ Parameters Symbol Condition Delta limits Units IDD Supply Current IDD VDD = 3.6 V, Vcp = 5.5 V +/- 0.4 mA ICP Supply Current ICP VDD = 3.6 V, Vcp = 5.5 V +/- 0.05 mA Rset Vout VRSET VDD = 3.2 V, Vcp = 5.5 V +/- 0.06 V Vcp Current, max level Icp8 VDD = 3.3 V, Vcp = 5.5 V +/- 0.35 mA Vcp Current, min level Icp1 VDD = 3.3 V, Vcp = 5.5 V +/- 0.08 mA 1/ Conditions match Table I unless otherwise noted. ASD0016548 Rev. A | Page 8 of 21 ADF4108S 5.0. BURN-IN, LIFE TEST, AND RADIATION 5.1. Burn-in test circuit, Life Test circuit The test conditions and circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 test condition B & D of MIL-STD-883. HTRB is not applicable for this drawing. 5.2. Radiation exposure circuit The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. Total dose irradiation testing shall be performed in accordance with MIL-STD-883 method 1019, condition A. 6.0. MIL-PRF-38535 QMLV EXCEPTIONS 6.1 Wafer Fabrication Wafer fabrication occurs at MIL-PRF-38535 QML Class Q certified facility. 6.2 Wafer lot Acceptance (WLA). Full WLA per MIL-STD-883 TM 5007 is not available for this product. SEM inspection only is available per MIL-STD-883, TM2018. 7.0. Application Notes THEORY OF OPERATION REFERENCE INPUT STAGE The reference input stage is shown in Figure 4. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. Figure 4. Reference Input Stage ASD0016548 Rev. A | Page 9 of 21 ADF4108S RF INPUT STAGE The RF input stage is shown in Figure 5. It is followed by a two-stage limiting amplifier to generate the CML clock levels needed for the prescaler. Figure 5. Reference Input Stage PRESCALER (P/P + 1) The dual-modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core. A minimum divide ratio is possible for contiguous 2 output frequencies. This minimum is determined by P, the prescaler value, and is given by (P − P). A AND B COUNTERS The A and B CMOS counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 300 MHz or less. Thus, with an RF input frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. Pulse Swallow Function The A and B counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is as follows: fVCO = [(P x B) + A] x fREFIN / R Where: fVCO is the output frequency of external voltage controlled oscillator (VCO). P is the preset modulus of dual-modulus prescaler (8/9, 16/17, and so on.). B is the preset divide ratio of binary 13-bit counter (3 to 8191). A is the preset divide ratio of binary 6-bit swallow counter (0 to 63). fREFIN is the external reference frequency oscillator. Figure 6. A and B Counters ASD0016548 Rev. A | Page 10 of 21 PLL Frequency Synthesizer ADF4108S R COUNTER The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. PHASE FREQUENCY DETECTOR AND CHARGE PUMP The phase frequency detector (PFD) takes inputs from the R counter and N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 7 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the reference counter latch, ABP2 and ABP1, control the width of the pulse (see Figure 10). Use of the minimum antibacklash pulse width is not recommended. Figure 7. PFD Simplified Schematic and Timing (in Lock) MUXOUT AND LOCK DETECT The output multiplexer on the ADF4108 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 11 shows the full truth table. Figure 8 shows the MUXOUT section in block diagram form. Lock Detect MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect. Digital lock detect is active high. When the lock detect precision (LDP) bit in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector (PD) cycles is less than 15 ns. With LDP set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. It stays set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, this output is high with narrow, low going pulses. ASD0016548 Rev.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2013 Analog Devices, Inc. All rights reserved. ADF4108S Figure 8. MUXOUT Circuit INPUT SHIFT REGISTER The ADF4108 digital section includes a 24-bit input shift register, a 14-bit R counter, and a 19-bit N counter, comprising a 6bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the 2 LSBs, DB1 and DB0, as shown in the timing diagram of Figure 2. The truth table for these bits is shown in Table III. Figure 9 shows a summary of how the latches are programmed. Table III. C2 and C1 Truth Table ASD0016548 Rev. A | Page 12 of 21 ADF4108S Figure 9. Latch Summary ASD0016548 Rev. A | Page 13 of 21 ADF4108S Figure 10. Reference Counter Latch Map ASD0016548 Rev. A | Page 14 of 21 ADF4108S Figure 11. AB Counter Latch Map ASD0016548 Rev. A | Page 15 of 21 ADF4108S Figure 12. Function Latch Map ASD0016548 Rev. A | Page 16 of 21 ADF4108S Figure 13. Initialization Latch Map ASD0016548 Rev. A | Page 17 of 21 ADF4108S FUNCTION LATCH The on-chip function latch is programmed with C2 and C1 set to 1 and 0, respectively. Figure 12 shows the input data format for programming the function latch. Counter Reset DB2 (F1) is the counter reset bit. When this bit is 1, the R counter and the AB counters are reset. For normal operation, this bit should be 0. Upon powering up, the F1 bit needs to be disabled (set to 0). Then, the N counter resumes counting in close alignment with the R counter. (The maximum error is one prescaler cycle.) Power-Down DB3 (PD1) and DB21 (PD2) provide programmable power-down modes. They are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of PD2 and PD1. In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into the PD1 bit, with the condition that PD2 has been loaded with a 0. In the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into PD1 (on condition that a 1 has also been loaded to PD2), the device goes into power-down on the occurrence of the next charge pump event. When a power-down is activated (either synchronous or asynchronous mode, including CE pin activated powerdown), the following events occur: • All active dc current paths are removed. • The R, N, and timeout counters are forced to their load state conditions. • The charge pump is forced into three-state mode. • The digital lock detect circuitry is reset. • The RFIN input is debiased. • The reference input buffer circuitry is disabled. • The input register remains active and capable of loading and latching data. MUXOUT Control The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF4108. Figure 12 shows the truth table. Fastlock Enable Bit DB9 of the function latch is the fastlock enable bit. Fastlock is enabled only when this bit is 1. Fastlock Mode Bit DB10 of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, then Fastlock Mode 1 is selected; and if the fastlock mode bit is 1, then Fastlock Mode 2 is selected. Fastlock Mode 1 The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock by having a 0 written to the CP gain bit in the AB counter latch. Fastlock Mode 2 The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock under the control of the timer counter. After the timeout period determined by the value in TC4:TC1, the CP gain bit in the AB counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. See Figure 12 for the timeout periods. Timer Counter Control The user has the option of programming two charge pump currents. The intent is that Current Setting 1 is used when the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic and in a state of change (that is, when a new output frequency is programmed). The normal sequence of events is as follows: The user initially decides what the preferred charge pump currents are going to be. For example, the choice may be 2.5 mA as Current Setting 1 and 5 mA as Current Setting 2. ASD0016548 Rev. A | Page 18 of 21 ADF4108S At the same time, it must be decided how long the secondary current is to stay active before reverting to the primary current. This is controlled by the timer counter control bits, DB14:DB11 (TC4:TC1) in the function latch. The truth table is given in Figure 12. Now, to program a new output frequency, the user simply programs the AB counter latch with new values for A and B. At the same time, the CP gain bit can be set to 1, which sets the charge pump with the value in CPI6:CPI4 for a period of time determined by TC4:TC1. When this time is up, the charge pump current reverts to the value set by CPI3:CPI1. At the same time, the CP gain bit in the AB counter latch is reset to 0 and is now ready for the next time the user wishes to change the frequency. Note that there is an enable feature on the timer counter. It is enabled when Fastlock Mode 2 is chosen by setting the fastlock mode bit (DB10) in the function latch to 1. Charge Pump Currents CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Figure 12. Prescaler Value P2 and P1 in the function latch set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300 MHz. Thus, with an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. PD Polarity This bit sets the phase detector polarity bit. See Figure 12. CP Three-State This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled. INITIALIZATION LATCH The initialization latch is programmed when C2 and C1 are set to 1 and 1. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0). See Figure 13. However, when the initialization latch is programmed, an additional internal reset pulse is applied to the R and AB counters. This pulse ensures that the AB counter is at load point when the AB counter data is latched and the device will begin counting in close phase alignment. If the latch is programmed for synchronous power-down (CE pin is high; PD1 bit is high; PD2 bit is low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained when counting resumes. When the first AB counter data is latched after initialization, the internal reset pulse is again activated. However, successive AB counter loads after this do not trigger the internal reset pulse. Device Programming After Initial Power-Up After initially powering up the device, there are three ways to program the device. Initialization Latch Method 1. Apply VDD. 2. Program the initialization latch (11 in 2 LSBs of input word). Make sure that the F1 bit is programmed to 0. 3. Next, do a function latch load (10 in 2 LSBs of the control word), making sure that the F1 bit is programmed to a 0. 4. Then do an R load (00 in 2 LSBs). 5. Then do an AB load (01 in 2 LSBs). When the initialization latch is loaded, the following occurs: 1. The function latch contents are loaded. 2. An internal pulse resets the R, AB, and timeout counters to load state conditions and also three-states the charge pump. Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. 3. Latching the first AB counter data after the initialization word activates the same internal reset pulse. Successive AB loads do not trigger the internal reset pulse unless there is another initialization. ASD0016548 Rev. A | Page 19 of 21 ADF4108S CE Pin Method 1. Apply VDD. 2. Bring CE low to put the device into power-down. This is an asynchronous power-down in that it happens immediately. 3. Program the function latch (10). 4. Program the R counter latch (00). 5. Program the AB counter latch (01). 6. Bring CE high to take the device out of power-down. The R and AB counters will now resume counting in close alignment. Note that after CE goes high, a duration of 1 μs may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. CE can be used to power the device up and down to check for channel activity. The input register does not need to be repro-grammed each time the device is disabled and enabled as long as it has been programmed at least once after VDD was initially applied. Counter Reset Method 1. Apply VDD. 2. Do a function latch load (10 in 2 LSBs). As part of this, load 1 to the F1 bit. This enables the counter reset. 3. Do an R counter load (00 in 2 LSBs). 4. Do an AB counter load (01 in 2 LSBs). 5. Do a function latch load (10 in 2 LSBs). As part of this, load 0 to the F1 bit. This disables the counter reset. This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down. INTERFACING The ADF4108 has a simple SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table III for the latch truth table. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 μs. This is certainly more than adequate for systems that have typical lock times in hundreds of microseconds. Figure 14 ADuC812 to ADF4108 Interface ADuC812 Interface example Figure 14 shows the interface between the ADF4108 and the ADuC812 MicroConverter®. Because the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4108 needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. On first applying power to the ADF4108, it needs four writes (one each to the initialization latch, function latch, R counter latch, and N counter latch) for the output to become active. I/O port lines on the ADuC812 are also used to control power-down (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 166 kHz. ASD0016548 Rev. A | Page 20 of 21 ADF4108S ORDERING GUIDE Model ADF4108L703F Temperature Range –55°C to +125°C Package Description 16 Lead Bottom Brazed Flat Pack Package Option X 8.0. Revision History Rev A Description of Change Initial Release Date 05/06/2013 © 2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. 05/13 Printed in the U.S.A. ASD0016548 Rev. A | Page 21 of 21