SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Product List
Features
SM5964C25, 25MHz 64KB internal flash MCU
SM5964C40, 40MHz 64KB internal flash MCU
Description
The SM5964 series product is an 8 - bit single chip
micro controller with 64KB flash & 1K byte RAM
embedded. It has In-System Programming (ISP)
function and is a derivative of the 8052 micro
controller family. It has 5-channel SPWM build-in. With
its hardware features and powerful instruction set, it’s
straight forward to make it a versatile and cost
effective controller for those applications which
demand up to 32 I/O pins for PDIP package or up to
36 I/O pins for PLCC/PQFP package, or applications
which need up to 64K byte flash memory either for
program or for data or mixed.
To program the on-chip flash memory, a commercial
writer is available to do it in parallel programming
method. The on-chip flash memory can be
programmed in either parallel or serial interface with
its ISP feature.
Ordering Information
yymmv
SM5964ihhkL
yy: year, mm: month
v: version identifier{ , A, B,…}
i: process identifier {L=3.0V~3.6V,C=4.5V~ 5.5V}
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
L:PB Free identifier
{No text is Non-PB Free，”P”is PB Free}
Postfix
P
J
Q
Package
40L PDIP
44L PLCC
44L PQFP
Pin / Pad Configuration
Page 2
Page 3
Page 4
Working Voltage:4.5V through 5.5V
General 8052 family compatible
12 clocks per machine cycle
64K byte on chip program flash with
in-System Programming(ISP) capability
1024 bytes on chip data RAM
Three 16 bit Timers/Counters
One Watch Dog Timer
Four 8-bit I/O ports for PDIP package
Four 8-bit I/O ports + one 4-bit I/O ports for
PLCC or QFP package
Full duplex serial channel
Bit operation instruction
Industrial Level
8-bit Unsigned Division
8-bit Unsigned Multiply
BCD arithmetic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes: Idle mode and Power
down mode
Code protection function
Low EMI (inhibit ALE)
Reset with address $0000 blank initiate ISP
service program
ISP service program space configurable in
N*512 byte (N=0 to 8) size
Five channel Specific PWM(SPWM) build-in
with P1.3~P1.7
Taiwan
6F, No.10-2 Li- Hsin 1st Road ,
Science-based Industrial Park,
Hsinchu, Taiwan 30078
TEL: 886-3-567-1820
886-3-567-1880
FAX: 886-3-567-1891
886-3-567-1894
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
1
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Pin Configuration
1
40
VDD
T2EX/P1.1
2
39
P0.0/AD0
P1.2
3
38
P0.1/AD1
SPWM0/P1.3
4
37
P0.2/AD2
SPWM1/P1.4
5
36
P0.3/AD3
SPWM2/P1.5
6
35
P0.4/AD4
SPWM3/P1.6
7
34
P0.5/AD5
SPWM4/P1.7
8
33
P0.6/AD6
RESET
9
32
P0.7/AD7
RXD/P3.0
10
31
EA
TXD/P3.1
11
30
ALE
INT0/P3.2
12
29
PSEN
INT1/P3.3
13
28
P2.7/A15
T0/P3.4
14
27
P2.6/A14
T1/P3.5
15
26
P2.5/A13
WR/P3.6
16
25
P2.4/A12
RD/P3.7
17
24
P2.3/A11
XTAL2
18
23
P2.2/A10
XTAL1
19
22
P2.1/A9
VSS
20
21
P2.0/A8
SyncMOS
T2/P1.0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
2
03/2013
SyncMOS Technologies International, Inc.
SM5964
39
38
P0.3/AD3
P2.7/A15
T0/P3.4
P2.6/A14
T1/P3.5
P2.5/A13
18
19
20
21
22
23
24
25
26
27
28
A12/P2.4
37
P0.2/AD2
INT1/P3.3
A11/P2.3
36
P0.1/AD1
PSEN
A10/P2.2
35
P0.0/AD0
INT0/P3.2
A9/P2.1
34
VDD
ALE
A8/P2.0
TXD/P3.1
33
P4.2
P4.1
P4.0
P4.3
32
P1.0/T2
EA
VSS
RXD/P3.0
31
P1.1/T2EX
P0.7/AD7
XTAL1
RESET
30
P1.2
P0.6/AD6
XTAL2
SPWM4/P1.7
SPWM3/P1.6
RD/P3.7
P0.5/AD5
SPWM2/P1.5
WR/P3.6
P0.4/AD4
29
P1.3/SPWM0
40
7
41
8
42
9
43
10
44
11
1
12
2
13
3
14
4
15
5
16
6
17
P1.4/SPWM1
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
3
03/2013
SyncMOS Technologies International, Inc.
SM5964
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
P4.1
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
33
32
31
30
29
28
27
26
25
24
23
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
17
P4.0
T2/P1.0
40
16
VSS
T2EX/P1.1
41
15
XTAL1
P1.2
42
14
XTAL2
SPWM0/P1.3
43
13
P3.7/RD
SPWM1/P1.4
44
12
P3.6/WR
11
39
T1/P3.5
P4.2
10
P2.0/A8
T0/P3.4
18
9
38
INT1/P3.3
VDD
8
P2.1/A9
INT0/P3.2
19
7
37
TXD/P3.1
AD0/P0.0
6
P2.2/A10
P4.3
20
5
36
RXD/P3.0
AD1/P0.1
4
P2.3/A11
RESET
21
3
35
SPWM4/P1.7
AD2/P0.2
2
P2.4/A12
SPWM3/P1.6
22
1
34
SPWM2/P1.5
AD3/P0.3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
4
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Block Diagram
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
5
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Pin Description
40L
PDIP
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
44L PQFP
Pin#
44L
PLCC
Pin#
Symbol
40
41
42
43
44
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
17
28
39
6
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
23
34
1
12
P1.0/T2
P1.1/T2EX
P1.2
P1.3/SPWM0
P1.4/SPWM1
P1.5/SPWM2
P1.6/SPWM3
P1.7/SPWM4
RES
P3.0/RXD
P3.1/TXD
P3.2/#INT0
P3.3/#INT1
P3.4/T0
P3.5/T1
P3.6/#WR
P3.7/#RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
#PSEN
ALE
#EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
P4.0
P4.1
P4.2
P4.3
Active
H
L/L/-
L
L
I/O
Names
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
i
bit 0 of port 1 & timer 2 clock out
bit 1 of port 1 & timer 2 control
bit 2 of port 1
bit 3 of port 1 & SPWM channel 0
bit 4 of port 1 & SPWM channel 1
bit 5 of port 1 & SPWM channel 2
bit 6 of port 1 & SPWM channel 3
bit 7 of port 1 & SPWM channel 4
Reset
bit 0 of port 3 & Receiver data
bit 1 of port 3 & Transmit data
bit 2 of port 3 & low true interrupt 0
bit 3 of port 3 & low true interrupt 1
bit 4 of port 3 & Timer 0
bit 5 of port 3 & Timer 1
bit 6 of port 3 & ext. memory write
bit 7 of port 3 & ext. memory read
Crystal out
Crystal in
Sink Voltage, Ground
bit 0 of port 2 & bit 8 of ext. memory address
bit 1 of port 2 & bit 9 of ext. memory address
bit 2 of port 2 & bit 10 of ext. memory address
bit 3 of port 2 & bit 11 of ext. memory address
bit 4 of port 2 & bit 12 of ext. memory address
bit 5 of port 2 & bit 13 of ext. memory address
bit 6 of port 2 & bit 14 of ext. memory address
bit 7 of port 2 & bit 15 of ext. memory address
program storage enable
address latch enable
external access
bit 7 of port 0 & data/address bit 7 of ext. memory
bit 6 of port 0 & data/address bit 6 of ext. memory
bit 5 of port 0 & data/address bit 5 of ext. memory
bit 4 of port 0 & data/address bit 4 of ext. memory
bit 3 of port 0 & data/address bit 3 of ext. memory
bit 2 of port 0 & data/address bit 2 of ext. memory
bit 1 of port 0 & data/address bit 1 of ext. memory
bit 0 of port 0 & data/address bit 0 of ext. memory
Drive Voltage
bit 0 of Port 4
bit 1 of Port 4
bit 2 of Port 4
bit 3 of port 4
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
o
I
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
6
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Special Function Register (SFR)
The address $80 to $FF can be accessed by direct addressing mode only.
Address $80 to $FF is SFR area.
The following table lists the SFRs which are identical to general 8052 as well as SM5964 Extension SFRs .
Special Function Register (SFR) Memory Map
$F8
$F0
$E8
$E0
$D8
$D0
$C8
$C0
$B8
$B0
$A8
$A0
$98
$90
$88
$80
B
ACC
P4
PSW
T2CON
IP
P3
IE
P2
SCON
P1
TCON
P0
T2MOD
RCAP2L
RCAP2H
ISPFAH
ISPFAL
TL2
TH2
ISPFD
ISPC
SCONF
SBUF
TMOD
SP
SPWMD4
SPWMD0
SPWMC
P1CON
TL0
DPL
TL1
DPH
SPWMD1
TH0
SPWMD2
TH1
RCON
SPWMD3
WDTC
PCON
$FF
$F7
$EF
$E7
$DF
$D7
$CF
$C7
$BF
$B7
$AF
$A7
$9F
$97
$8F
$87
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM5964
Addr
SFR
Reset
85H
RCON
******00
7
6
9BH
P1CON
00000***
SPWM4E
SPWM3E
SPWM2E
9FH
WDTC
0*0**000
WDTE
Reserved**
CLEAR
A3H
SPWMC
******00
A4H
SPWMD0
00H
SPWMD04
SPWMD03
SPWMD02
SPWMD01
A5H
SPWMD1
00H
SPWMD14
SPWMD13
SPWMD12
A6H
SPWMD2
00H
SPWMD24
SPWMD23
SPWMD22
A7H
SPWMD3
00H
SPWMD34
SPWMD33
ACH
SPWMD4
00H
SPWMD44
SPWMD43
BFH
SCONF
0****010
WDR
C9H
T2MOD
******00
*
D8H
P4
****1111
F4H
ISPFAH
00H
FA15
FA14
FA13
F5H
ISPFAL
00H
FA7
FA6
FA5
F6H
ISPFD
00H
FD7
FD6
FD5
F7H
ISPC
0*****00
START
*
5
1
0
RAMS1
RAMS0
PS2
PS1
PS0
PDIV1
PDIV0
SPWMD00
BRM02
BRM01
BRM00
SPWMD11
SPWMD10
BRM12
BRM11
BRM10
SPWMD21
SPWMD20
BRM22
BRM21
BRM20
SPWMD32
SPWMD31
SPWMD30
BRM32
BRM31
BRM30
SPWMD42
SPWMD41
SPWMD40
BRM42
BRM41
BRM40
ISPE
OME
ALEI
*
4
SPWM1E
*
3
2
SPWM0E
*
*
T2OE
DCEN
P4.3
P4.2
P4.1
P4.0
FA12
FA11
FA10
FA9
FA8
FA4
FA3
FA2
FA1
FA0
FD4
FD3
FD2
FD1
FD0
F1
F0
** Keep to “0” when write WDTC (9FH).
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
7
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Extension Function Description
1. Memory Structure
The SM5964 is the general 8052 hardware core to integrate the ISP function as a single chip micro controller. It’s memory
structure follows general 8052 structure.
1.1 Program Memory
The SM5964 has 64K byte on-chip flash memory which used as general program memory, on which include up to 4K byte
specific ISP service program memory space. The address range for the 64K byte is $0000 to $FFFF. The address range
for the ISP service program is $F000 to $FFFF. The ISP service program size can be partitioned as N blocks of 512 byte
(N=0 to 8). When N=0 means no ISP service program space available, total 64K byte memory used as program memory.
When N=1 means memory address $FE00 to $FFFF reserved for ISP service program. When N=2 means memory
address $FC00 to FFFF reserved for ISP service program,...etc. Value N can be set and programmed into SM5964 by
writer.
The feature of FLASH memory is shown as following:
READ:
byte-wise
WRITE: byte-wise within 30us (previously erased by a chip erase).
ERASE:
Full Erase (64K bytes) within 2 sec.
Erased bytes contain FFH
Retention : 10 years
1.1.1 Program Code Security
MOVC instruction executed from external program memory space will not be able to fetch internal codes from on chip
program memory after the chip is protected on the Writer.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
8
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
1.2 Data Memory
The SM5964 has 1K bytes on-chip RAM, 256 bytes of it are the same as general 8052 internal memory structure while the
expanded 768 bytes on-chip RAM can be accessed by external memory addressing method (by instruction MOVX.).
1.2.1 Data Memory - Lower 128 byte ($00 to $7F)
Data Memory $00 to $FF is the same as 8052.
The address $00 to $7F can be accessed by direct and indirect addressing modes.
Address $00 to $1F is register area.
Address $20 to $2F is memory bit area.
Address $30 to $7F is for general memory area.
1.2.2 Data Memory - Higher 128 byte ($80 to $FF)
The address $80 to $FF can be accessed by indirect addressing mode .
Address $80 to $FF is data area.
1.2.3 Data Memory - Expanded 768 bytes ($0000 to $02FF)
From external address $0000 to $02FF is the on-chip expanded RAM area, total 768 bytes. This area can be accessed by
external direct addressing mode (by instruction MOVX).
If the address of instruction MOVX @DPTR is larger than $02FF then SM5964 will generate the external memory control
signal automatically. The bit 1 (OME) of special function register $BF (SCONF) can enable or disable this expanded 768
byte RAM. The default setting of OME bit is 1 (enable).
System Control Register (SCONF, $BF)
bit-7
WDR
Unused
Unused
Unused
DFEN
ISPE
OME
bit-0
ALEI
Read / Write:
R/W
-
-
-
-
R/W
R/W
R/W
Reset value:
0
*
*
*
*
0
1
0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
9
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
WDR: Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1.
ISPE: ISP function enable bit
OME: 768 bytes on-chip RAM enable bit .
ALEI: ALE output inhibit bit, to reduce EMI .
Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin.
The bit 1 (OME) of SCONF can enable or disable the on-chip expanded 768 byte RAM. The default setting of OME bit is 1
(enable).
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User
should check WDR bit whenever un-predicted reset happened.
2. Port 4 for PLCC or QFP package:
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is
located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Port4 (P4, $D8)
Read / Write:
bit-7
Unused
Unused
Unused
Unused
P4.3
P4.2
P4.1
bit-0
P4.0
-
-
-
-
R/W
R/W
R/W
R/W
1
1
Reset value:
*
*
*
*
1
1
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.
3. In-System Programming (ISP) Function
The SM5964 can generate flash control signal by internal hardware circuit. User utilize flash control register, flash address
register and flash data register to perform the ISP function without removing the SM5964 from the system.
The SM5964 provides internal flash control signals which can do flash program/chip erase/page erase/protect functions.
User need to design and use any kind of interface which SM5964 can input data. User then utilize ISP service program to
perform the flash program/chip erase/page erase/protect functions.
3.1 ISP Service Program
The ISP service program is a user developed firmware program which resides in the ISP service program space. After user
developed the ISP service program, user then determine the size of the ISP service program. User need to program the
ISP service program in the SM5964 for the ISP purpose.
The ISP service programs were developed by user so that it should includes any features which relates to the flash
memory programming function as well as communication protocol between SM5964 and host device which output data to
the SM5964. For example, if user utilize UART interface to receive/transmit data between SM5964 and host device, the
ISP service program should include baud rate, checksum or parity check or any error-checking mechanism to avoid data
transmission error.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
10
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
The ISP service program can be initiated under SM5964 active or idle mode. It can not be initiated under power down
mode.
3.2 Lock Bit (N)
The Lock Bit N has two functions: one is for service program size configuration and the other is to lock the ISP service
program space from flash erase function.
The ISP service program space address range from $F000 to $FFFF. It can be divided as blocks of N*512 byte. (N=0 to 8).
When N=0 means no ISP function, all of 64K byte flash memory can be used as program memory. When N=1 means ISP
service program occupies 512 byte while the rest of 63.5K byte flash memory can be used as program memory. The
maximum ISP service program allowed is 4K byte for N=8. Under such configuration, the usable program memory space is
60K byte.
After N determined, SM5964 will reserve the ISP service program space downward from the top of the program address
$FFFF. The start address of the ISP service program located at $Fx00 while x is an even number, depending on the lock
bit N. Please see page 7 program memory diagram for this ISP service program space structure.
The lock bit N function is different from the flash protect function. The flash erase function can erase all of the flash
memory except for the locked ISP service program space. If the flash not been protected, the content of ISP service
program still can be read. If the flash been protected, the overall content of flash program memory space including ISP
service program space can not be read.
3.3 Program the ISP Service Program
After Lock Bit N is set and ISP service program been programmed, the ISP service program memory will be protected
(locked) automatically. The lock bit N has its own program/erase timing. It is different from the flash memory
program/erase timing so the locked ISP service program can not be erased by flash erase function. If user need to erase
the locked ISP service program, he can do it by writer only. User can not change ISP service program when SM5964 was
in system.
3.4 Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and
execute it. There are three ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start address of ISP
service program.
(2) Execute ‘JUMP’ instruction can load the start address of the ISP service program to PC.
User can initiate general 8052 INT function to initiate the ISP service program. After ISP service program executed, user
need to reset the SM5964, either by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware
program.
ISP Registers - ISPFAH, ISPFAL, ISPFD and ISPC
ISP Flash Address-High Register(ISPFAH,$F4)
bit-7
FA15
FA14
FA13
FA12
FA11
FA10
FA9
bit-0
FA8
Read / Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value:
0
0
0
0
0
0
0
0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
11
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
FA15 ~ FA8: flash address-high for ISP function
ISP Flash Address-Low Register(ISPFAL,$F5)
Read / Write:
bit-7
FA7
FA6
FA5
FA4
FA3
FA2
FA1
bit-0
FA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Reset value:
0
0
FA7 ~ FA0: flash address-low for ISP function
The ISPFAH & ISPFAL provide the 16-bit flash memory address for ISP function. The flash memory address should not
include the ISP service program space address. If the flash memory address indicated by ISPFAH & ISPFAL registers
overlay with the ISP service program space address, the flash program/page erase of ISP function executed thereafter will
have no effect.
ISP Flash Data Register (ISPFD, $F6)
Read / Write:
bit-7
FD7
FD6
FD5
FD4
FD3
FD2
FD1
bit-0
FD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Reset value:
0
0
FD7 ~FD0 : flash data for ISP function
The ISPFD provide the 8-bit data for ISP function
ISP Flash Control Register (ISPC, $F7)
bit-7
START
Unused
Unused
Unused
Unused
Unused
ISPF1
bit-0
ISPF0
Read / Write:
R/W
-
-
-
-
-
R/W
R/W
Reset value:
0
*
*
*
*
*
0
0
F[1: 0]: ISP function select bit
START: ISP function start bit
= 1: start ISP function which indicated by bit 1, bit 0 (F1, F0)
= 0: no operation
The START bit is read-only by default, software must write three specific values 55H, AAH and 55H sequentially to the
ISPFD register to enable the START bit write attribute. That is:
MOV ISPFD, #55H
MOV ISPFD, #0AAH
MOV ISPFD, #55H
Any attempt to set START bit will not be allowed without the procedure above.
After START bit set to 1 then the SM5964 hardware circuit will latch address and data bus and hold the program counter
until the START bit reset to 0 when ISP function finished. User does not need to check START bit status by software
method.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
12
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
F[1:0]
00
01
10
11
ISP function
Byte program
Chip protect
Page erase
Chip erase
F[1:0]: ISP function select bit
One page of flash memory is 512 byte.
To perform byte program/page erase ISP function, user need to specify flash address at first. When performing page erase
function, SM5964 will erase entire page which flash address indicated by ISPFAH & ISPFAL registers located within the
page.
e.g. flash address: $XYMN
page erase function will erase from $XY00 to $X(Y+1)FF (Y:even number), or
page erase function will erase from $X(Y-1) 00 to $XYFF (Y:odd number)
To perform the chip erase ISP function, SM5964 will erase all the flash program memory except the ISP service program
space, also, SM5964 will un-protect the flash memory automatically. To perform chip protect ISP function, the SM5964
flash memory content will be read #00H.
e.g. ISP service program to do the byte program - to program #22H to the address $1005H
MOV SCONF,#04H
MOV ISPFAH,#10H
MOV ISPFAL,#05H
MOV ISPFD,#22H
MOV ISPC,#80H
; enable SM5964 ISP function
; set flash address-high, 10H
; set flash address-low, 05H
; set flash data to be programmed, data = 22H
; start to program #22H to the flash address $1005H
; after byte program finished, START bit of ISPC will be reset to 0 automatically
; program counter then point to the next instruction
ISP Registers - System Control Register (SCONF,$BF)
bit-7
WDR
Unused
Unused
Unused
Unused
ISPE
OME
bit-0
ALEI
Read / Write:
R/W
-
-
-
-
R/W
R/W
R/W
Reset value:
0
*
*
*
*
0
1
0
The bit 2 (ISPE) of SCONF is ISP enable bit. User can enable overall SM5964 ISP function by setting ISPE bit to 1, to
disable overall ISP function by set ISPE to 0.
The function of ISPE behaves like a security key. User can disable overall ISP function to prevent software program be
erased accidentally.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
13
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
4. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT
is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover form abnormal software condition. The WDT is
different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically
clearing the WDT counter. User should check WDR bit of SCONF register whenever un-predicted reset happened
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit2~bit0
(PS2~PS0) of Watch Dog Timer Control Register (WDTC) should be set accordingly.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to
count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows. The
WDTE bit will be cleared to 0 automatically when SM5964 been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC. This will clear the content of the 16-bit counter and let
the counter re-start to count from the beginning.
4.1 Watch Dog Timer Registers: WDTC and SCONF
Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
bit-7
WDTE
reserved**
Clear
Unused
Unused
PS2
PS1
bit-0
PS0
Read / Write:
R/W
-
R/W
-
-
R/W
R/W
R/W
Reset value:
0
*
0
*
** Keep to “0” when write WDTC (9FH).
*
0
0
0
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer reset bit
PS[2:0] : Overflow period select bits
PS [2:0]
Divider(OSC in)
Time Period (ms) @ 40 MHZ
000
8
13.12.048
001
16
26.21
010
32
52.42
011
64
104.8
100
128
209.71
101
256
419.43
110
512
838.86
111
1024
1677.72
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
14
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Watch Dog Timer Register - System Control Register (SCONF, $BF)
bit-7
WDR
Unused
Unused
Unused
Unused
ISPE
OME
bit-0
ALEI
Read / Write:
R/W
-
-
-
-
R/W
R/W
R/W
Reset value:
0
*
*
*
*
0
1
0
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow.
User should check WDR bit whenever un-predicted reset happened.
5. Reduce EMI Function
The SM5964 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will
inhibit the clock signal in Fosc/6Hz output to the ALE pin.
6. Specific Pulse Width Modulation (SPWM)
The Specific Pulse Width Modulation (SPWM) module has five 8-bit channels, each channel contains a 8-bit wide SPWM
data register (SPWMD) to decide number of continuous pulses within a SPWM frame cycle.
6.1 SPWM Function Description:
Each 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit binary
rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse length of
the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle frame. The
number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the BRM is to
generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit SPWM clock speed.
The PDIV[1:0] settings of SPWMC ($A3) register are dividend of Fosc to be SPWM clock, Fosc/2^(PDIV[1:0]+1). The
SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is [Fosc/2^(PDIV[1:0]+1)]/32.
6.2 SPWM Registers - P1CON, SPWMC, SPWMR[4:0]
SPWM Registers - Port1 Configuration Register (P1CON, $9B)
bit-7
SPWM4E
SPWM3E
SPWM2E
SPWM1E
SPWM0E
Unused
Unused
bit-0
Unused
Read / Write:
R/W
R/W
R/W
R/W
R/W
-
-
-
Reset value:
0
0
0
0
0
*
*
*
SPWM[4:0]E :When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit reset to
zero, the corresponding SPWM pin is active as I/O pin. Five bits are cleared upon reset.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
15
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
SPWM Registers -SPWM Control Register (SPWMC, $A3)
bit-7
Unused
Unused
Unused
Unused
Unused
Unused
PDIV1
bit-0
PDIV0
Read / Write:
-
-
-
-
-
-
R/W
R/W
Reset value:
*
*
*
*
*
*
0
0
PDIV[1:0] : These two bits is 2’s power parameter to form a frequency divider for input clock.
PDIV1
PDIV0
Divider
SPWM clock, Fosc=20MHz
SPWM clock, Fosc=24MHz
0
0
2
10MHz
12MHz
0
1
4
5MHz
6MHz
1
0
8
2.5MHz
3MHz
1
1
16
1.25MHz
1.5MHz
SPWM Data Register (SPWMD[4:0], $AC, $A7 ~$A4)
Read / Write:
bit-7
SPWMD
[4:0]4
R/W
SPWMD
[4:0]3
R/W
SPWMD
[4:0]2
R/W
SPWMD
[4:0]1
R/W
SPWMD
[4:0]0
R/W
BRM
[2:0]2
R/W
BRM
[2:0]1
R/W
bit-0
BRM
[2:0]0
R/W
Reset value:
0
0
0
0
0
0
0
0
SPWMD[4:0][4:0]: content of SPWM Data Register. It determines duty cycle of SPWM output waveform.
BRM[4:0][2:0]: will insert certain narrow pulses among an 8-SPWM-cycle frame .
N = BRM[4:0][2:0]
Number of SPWM cycles inserted in an 8-cycle frame
XX1
1
X1X
2
1XX
4
Example of SPWM timing diagram:
MOV SPWMD0 , #83H
MOV P1CON , #08H
; SPWMD0[4:0]=10h (=16T high, 16T low), BRM[2:0] = 3
; Enable P1.3 as SPWM output pin
(na
rrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3)
SPWM clock = 1 / T = Fosc / 2^(PDIV +1)
The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(SPFS[1:0]+1)]/32
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
16
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
If user use Fosc=20MHz, SPFS[1:0] of SPWMC=#03H, then
SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz
SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
17
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit.
Remarks
TA
Operating temperature
-40
25
85
℃
Ambient temperature under bias
VCC5
Supply voltage
4.5
5.0
5.5
V
Fosc 25
Oscillator Frequency
3.0
25
25
MHz
For 5V application
Fosc 40
Oscillator Frequency
3.0
40
40
MHz
For 5V application
DC Characteristics
(TA = -40 degree C to 85 degree C, Vcc = 5.5V)
Symbol
Parameter
Valid
VIL1
VIL2
Input Low Voltage
Input Low Voltage
port 0,1,2,3,4,#EA
RES, XTAL1
VIH1
Input High Voltage
port 0,1,2,3,4,#EA
Min.
-0.5
Max.
Test Conditions
Unit
0.8
V
0
0.8
2.0
Vcc+0.5
V
V
70%Vcc
Vcc=5V
VIH2
Input High Voltage
RES, XTAL1
Vcc+0.5
V
VOL1
Output Low Voltage
port 0, ALE, #PSEN
0.45
V
IOL=3.2mA
VOL2
VOH1
Output Low Voltage
Output High Voltage
port 1,2,3,4
port 0
0.45
IOL=1.6mA
2.4
V
V
90%Vcc
V
IOH=-80uA
2.4
90%Vcc
V
V
IOH=-60uA
VOH2
Output High Voltage
port 1,2,3,4,ALE,#PSEN
IOH=-800uA
IOH=-10uA
IIL
Logical 0 Input Current
port 1,2,3,4
-75
uA
Vin=0.45V
ITL
Logical Transition Current
port 1,2,3,4
-650
uA
Vin=2.0V
ILI
Input Leakage Current
port 0, #EA
±10
uA
0.45V<Vin<Vcc
300
Kohm
10
pF
R RES
C IO
I CC
Reset Pull-down
Resistance
Pin Capacitance
Power Supply Current
RES
Vdd
50
Freq=1MHz, Ta=25 ℃
20
mA
Active mode, 16MHz
6.5
mA
Idle mode, 16MHz
50
uA
Power down mode
Note1:Under steady state (non-transient) conditions, IOL must be externally
Limited as follows : Maximum IOL per port pin : 10mA
Maximum IOL per 8-bit port : port 0 :26mA
port 1,2,3
:15mA
Maximum total IOL for all output pins : 71mA
If IOL exceeds the condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
18
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
AC Characteristics
(16/25/40MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=150pF; CL for all Other Output=80pF)
Symbol
Parameter
Valid Cycle
fosc=16MHz
Min. Typ. Max
Variable fosc
Min.
Typ.
Unit
T LHLL
ALE pulse width
RD/WRT
115
2xT - 10
nS
T AVLL
Address Valid to ALE low
RD/WRT
43
T - 20
nS
T LLAX
Address Hold after ALE low
RD/WRT
53
T LLIV
ALE low to Valid Instruction In
RD
T LLPL
ALE low to #PSEN low
RD
53
T PLPH
#PSEN pulse width
RD
173
T PLIV
#PSEN low to Valid Instruction In
RD
T PXIX
Instruction Hold after #PSEN
RD
T PXIZ
Instruction Float after #PSEN
RD
87
T + 25
nS
T AVIV
Address to Valid Instruction In
RD
292
5xT -20
nS
T PLAZ
#PSEN low to Address Float
RD
10
10
nS
T RLRH
#RD pulse width
RD
365
T WLWH
#WR pulse width
WRT
365
T RLDV
#RD low to Valid Data In
RD
T RHDX
Data Hold after #RD
RD
T RHDZ
Data Float after #RD
RD
145
2xT+20
nS
T LLDV
ALE low to Valid Data In
RD
590
8xT - 10
nS
T AVDV
Address to Valid Data In
RD
542
9xT - 20
nS
T LLYL
ALE low to #WR High or #RD low
RD/WRT
3xT+10
nS
T AVYL
Address Valid to #WR or #RD low
RD/WRT
230
4xT-20
nS
T QVWH
Data Valid to #WR High
WRT
403
7xT-35
nS
T QVWX
Data Valid to #WR transition
WRT
38
T - 25
nS
T WHQX
Data hold after #WR
WRT
73
T + 10
T RLAZ
#RD low to Address Float
RD
T YALH
#WR or #RD high to ALE high
RD/WRT
T CHCL
clock fall time
nS
T CLCX
clock low time
nS
T CLCH
clock rise time
nS
T CHCX
clock high time
nS
T, TCLCL
clock period
T - 10
nS
240
4xT-10
T - 10
3xT - 15
nS
3xT-10
0
nS
6xT - 10
nS
302
5xT - 10
0
178
197
53
72
63
nS
nS
6xT - 10
0
nS
nS
177
0
Remarks
Max
nS
nS
3xT-10
nS
T -10
5
nS
T + 10
nS
1/fosc
nS
ISP Test Conditions
(40 MHZ, typical operating conditions, valid for SM5964 series)
Symbol
MAX
Remark
Chip erase
3000ms
Vcc = 5V
Page erase
10ms
“
Program
30us
“
Protect
400us
“
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
19
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Application Reference
Valid for SM5964
X'tal
C1
C2
R
3MHz
30 pF
30 pF
open
6MHz
30 pF
30 pF
open
9MHz
30 pF
30 pF
open
12MHz
30 pF
30 pF
open
X'tal
C1
C2
R
16MHz
30 pF
30 pF
open
25MHz
15 pF
15 pF
62KΩ
33MHz
5 pF
5 pF
6.8KΩ
40MHz
2 pF
2 pF
4.7KΩ
NOTE: Oscillation circuit may differs with different crystal or ceramic
resonator in higher oscillation frequency which was due to
each crystal or ceramic resonator has its own characteristics.
User should check with the crystal or ceramic resonator
manufacture for appropriate value of external components.
Please see SM59264 application note for details.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
20
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Data Memory Read Cycle Timing
Program Memory Read Cycle Timing
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
21
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Data Memory Write Cycle Timing
I/O Ports Timing
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
22
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Timing Critical, Requirement of External Clock
(Vss=0.0V is assumed)
Tm.I External Program Memory Read Cycle
Tm.II External Data Memory Read Cycle
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
23
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Tm.III External Data Memory Write Cycle
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
24
03/2013
SyncMOS Technologies International, Inc.
SM5964
8-Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
MCU writer list
Company
Advantech
7F, No.98, Ming-Chung Rd.,
Shin-Tien City, Taipei, Taiwan,
ROC
Web site:
http://www.aec.com.tw
Contact info
Tel:02-22182325
Fax:02-22182435
E-mail:
[email protected]
Programmer Model Number
Lab Tool - 48XP/UXP
Lab Tool – 848/848XP
Hi-Lo
4F.,No.18,Lane 79,Rueiguang
Rd.,Neihu,Taipei,Taiwan R.O.C.
Web site:
http://www.hilosystems.com.tw
Tel: 02-87923301
Fax:02-87923285
E-mail:
[email protected]
All - 100 series
Leap
6th F1-4, Lane 609,
Chunghsin Rd., Sec. 5, Sanchung,
Taipei , Taiwan, ROC
Web site:
http://www.leap.com.tw
Tel: 886-2-29991860
Fax:02-29990015
E-mail:
[email protected]
Leap-48
Xeltek Electronic Co., Ltd
Bldg 6-31 Meizhiguo garden, #2 Jiangjun
Ave., Jiangning, Nanjing, China
211100
Web site:
http://www.xeltek-cn.com
Tel: + 86-25-52765201,
E-mail:
[email protected]
[email protected]
Superpro 280U
Superpro 580U
Superpro 3000U
Superpro 9000U
Guangzhou Zhiyuan Electronic Co.,Ltd
Floor 2,No.7 building,Huangzhou Industrial
Estate,Chebei Road,Tianhe
district,Guangzhou,China 510660
Web site:
http://www.embedtools.com/
TEL: +86-20-28872449
E-mail:
[email protected]
SmartPRO 5000U/X8
TianJin Weilei technology ltd
Rm 357,Venturetech Center,12 Keyan West
Road Nankai District,Tianjin,P.R.C, 300192
Web site:
http://www.weilei.com.cn/
TEL: + 86-22-87891218#801
E-mail:
[email protected]
[email protected]
VP-890;VP-980;VP-880;VP-680
VP-480;VP-380;VP-280;VP-190
GuangZhou Chang Xingjinggong
Technology Development Co ., Ltd.
Room 102 , No.167 , CuiJing street ,
ChangXing road , TianHe district ,
GuangZhou.
Web site:
http://www.top2048.com/
TEL: + 86-20-61391469
E-mail:
[email protected]
TOP-2007
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M011 Ver:D SM5964
25
03/2013