WDT 功能使用方法
WDT 功能使用方法
1
适用产品：
1.1 SM59R16A2/ SM59R08A2
1.2 SM59R16A5/ SM59R09A5/ SM59R05A5/SM59R16A3/SM59R09A3/SM59R05A3
1.3 SM59R04A2/ SM59R04A1/ SM59R03A1/ SM59R02A1
2
文件说明：SM59R 系列注意 WDT 因架构差异，各型号说明请参考以下相对章节。
3
以下说明适用：SM59R16A5/ SM59R09A5/ SM59R05A5/ SM59R16A3/ SM59R09A3/ SM59R05A3/
SM59R04A2/ SM59R04A1/ SM59R03A1/ SM59R02A1：
3.1 WDT 模块之时钟源为 MCU 内部之 250KHz RC 振荡电路产生。
3.2 WDT 烧录时可设定 WDT 禁能、致能。当于烧录时设定 WDT 禁能，则不论 WDTE(WTC[5])于程
序中设定为 WDT 功能启动，WDT 模块仍然不会动作；当于烧录时设定 WDT 致能，则 WDT 模
块由 WDTE(WTC[5])于程序中设定为 WDT 功能为启动或停止。
3.3 WDT 启动或停止：当于烧录时设定 WDT 致能，由 WDTE(WTC[5])决定，当设定为”1”，WDT 启
动，设定为”0”，WDT 停止；WDTC SFR 之设定需先由 TAKEY SFR 连续写入 0x55H，0xAAH
及 0x55H 才可修改。
3.4 WDT 重置时间：由程序设定 WDTM[3:0]决定，共有 16 组可供选择。
3.5 WDT counter 清除可由外部重置，或由软件执行（写入 0x55 至 SFR WDTK 即可）
3.6 WDTK 须不断的执行清除，以确保 WDT counter 不会溢位
3.7 当 WDT counter 溢位时，WDTF 由硬件设定为”1”，并且重置 MCU，重置后 WDTF 由硬件清除
为”0”
3.8 以下为 WDT reset time 计算方式：
WDTCLK =
250KHz
2 WDTM
Watchdog reset time =
256
WDTCLK
Specifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0190
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Ver. A 2010/08
WDT 功能使用方法
3.9
下表 WDT reset time：
Divider
WDTM [3:0]
(250 KHz RC oscillator in)
Time period @ 250KHz
0000
1
1.02ms
0001
2
2.05ms
0010
4
4.10ms
0011
8
8.19ms
0100
16
16.38ms (default)
0101
32
32.77ms
0110
64
65.54ms
0111
128
131.07ms
1000
256
262.14ms
1001
512
524.29ms
1010
1024
1.05s
1011
2048
2.10s
1100
4096
4.19s
1101
8192
8.39s
1110
16384
16.78s
1111
32768
33.55s
1
2WDTM
Specifications subject to change without notice, contact your sales representatives for the most recent information.
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Ver. A 2010/08
WDT 功能使用方法
Fig. Watchdog timer block diagram
3.10 WDT 相关缓存器：
Mnemoni
c
Description
Bit 7
Direct
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
Watchdog Timer
TAKEY
WDTC
WDTK
Time Access Key
F7h
register
Watchdog timer
TAKEY [7:0]
B6h
control register
Watchdog timer
WDTF
-
WDTE
-
B7h
refresh key
WDTM [3:0]
WDTK[7:0]
Mnemonic: TAKEY
7
00H
6
04H
00H
Address: F7h
5
4
3
2
1
0
TAKEY [7:0]
Reset
00H
Watchdog timer control register (WDTC) is read-only by default; software must write three specific
values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Mnemonic: WDTC
Address: B6h
7
6
5
4
WDTF
-
WDTE
-
3
2
1
WDTM [3:0]
0
Reset
04H
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag
clear by software or external reset or power on reset.
WDTE: Control bit used to enable Watchdog timer.
The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT
can be disabled / enabled by the WDTE bit.
Specifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0190
3
Ver. A 2010/08
WDT 功能使用方法
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if WDTEN is "1". That is, if the WDTEN bit is "1", WDT is
always disabled no matter what the WDTE bit status is. The WDTE bit can be read
and written.
WDTM [3:0]: WDT clock source divider bit. Please see the WDT reset time table to reference the
WDT time-out period.
Mnemonic: WDTK
7
6
Address: B7h
5
4
3
2
1
0
Reset
WDTK[7:0]
00h
WDTK: Watchdog timer refresh key.
A programmer must write 0x55 into WDTK register, and then the watchdog
timer will be cleared to zero.
For example, if enable WDT and select time-out reset period is 262.14ms.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
; enable WDTC write attribute.
MOV WDTC, #28h
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT
; function.
.
.
.
MOV WDTK, #55h
; Clear WDT timer to 0.
Specifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0190
4
Ver. A 2010/08
WDT 功能使用方法
4
SM59R16A2/ SM59R08A2 WDT(Watchdog Timer) 使用说明：
4.1 WDT 必须在烧录 information block 时，设定 WDT 致能(或禁能)及重置时间。
4.2 WDT 禁能和致能：由 WDTENB 决定，WDTENB = ”1”，WDT 致能，WDTENB = ”0”，WDT 禁
能。
4.3 WDT 重置时间：由 WDTM[3:0]决定，共有 16 组可供选择。
4.4 WDTK 须不断的执行清除(写 0x55 至 SFR WDTK 即可)，以确保 WDT counter 不会溢位。
4.5 当 WDT 溢位时，WDTF 旗标由硬件设定为”1”，WDT 重置并不会清除 WDTF；清除方式可由(1)
上电重置(POR) (2)外部重置(Pad Reset) (3)软件直接清除。
4.6 以下为 WDT reset time 计算方式：
WDTCLK =
Fosc
12X 2 WDTM
Watchdog reset time =
256
WDTCLK
4.7 下表为 OSC 使用 22.1184MHz，计算 WDT reset time：
Fosc
WDTENB
WDTM
WDTCLK
WDT reset time
22.1184
1
0
1843200
0.138ms
22.1184
1
1
921600
0.277ms
22.1184
1
2
460800
0.555ms
22.1184
1
3
230400
1.111ms
22.1184
1
4
115200
2.222ms
22.1184
1
5
57600
4.444ms
22.1184
1
6
28800
8.888ms
22.1184
1
7
14400
17.777ms
22.1184
1
8
7200
35.555ms
Specifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0190
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Ver. A 2010/08
WDT 功能使用方法
22.1184
1
9
3600
71.111ms
22.1184
1
10
1800
142.222ms
22.1184
1
11
900
284.444ms
22.1184
1
12
450
568.888ms
22.1184
1
13
225
1.137s
22.1184
1
14
112.5
2.275s
22.1184
1
15
56.25
4.551s
Fig. Watchdog timer block diagram
4.8 WDT 相关缓存器：
Mnemonic
Description
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
-
-
-
-
-
00h
Watchdog Timer
WDTC
WDTK
Watchdog timer
control register
Watchdog timer
refresh key
B6h
B7h
WDTF
-
-
WDTK[7:0]
Specifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0190
6
Ver. A 2010/08
00h
WDT 功能使用方法
Mnemonic: WDTC
Address: B6h
7
6
5
4
3
2
1
0
Reset
WDTF
-
-
-
-
-
-
-
00h
WDTF: Watchdog timer reset flag.
当重置时，WDTF 由硬件设为”1”
须由软件(WDTK)设定，或由外部重置(Reset)，将 WDTF 清除为”0”
Mnemonic: WDTK
7
6
Address: B7h
5
4
3
2
1
WDTK[7:0]
0
Reset
00h
WDTK: Watchdog timer refresh key.
当 WDTK 写入 0x55 时，WDTC 即可清除为”0”
4.9 WDT 应用的范例程序
1. 烧录时先于芯片组态中设定 WDT 致能及选择 WDTM 重置时间
Description
2. 当执行 user code 时，WDTK 须不断的执行清除
3. 量测 P2，若为 0x00 表示正确；若 P2 不断的 Hi-Low 变化，表示 WDT counter 溢位
Main program
//====================================================================
//
//
SYNCMOS
TECHNOLOGY
//
//====================================================================
#include "..\h\SM59R16A2.h"
void WDT_Clear()
{
/*WDTK: Watchdog timer refresh key. A programmer must write 0x55
into WDTK register, then the watchdog timer will be cleared to zero.*/
Specifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0190
7
Ver. A 2010/08
WDT 功能使用方法
WDTK = 0x55;
}
void main()
{
P2 = 0;
while(1)
{
//if WDTK has clear, P2 always low
//if WDTK no clear, P2 Hi-low switch(P2 default 0xFF)
WDT_Clear();
}
}
Specifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0190
8
Ver. A 2010/08