SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Description .......................................................................................................................................................................... 3
Features .............................................................................................................................................................................. 3
Pin Configuration ................................................................................................................................................................ 4
Block Diagram................................................................................................................................................................... 10
Pin Description .................................................................................................................................................................. 11
Special Function Register (SFR) ...................................................................................................................................... 13
Function Description ......................................................................................................................................................... 16
1.
General Features ..................................................................................................................................................... 16
1.1.
Embedded Flash ......................................................................................................................................... 16
1.2.
IO Pads ....................................................................................................................................................... 16
1.3.
2T/1T Selection ........................................................................................................................................... 16
1.4.
RESET ........................................................................................................................................................ 17
1.4.1.
Hardware RESET function ............................................................................................................. 17
1.4.2.
Software RESET function .............................................................................................................. 17
1.4.3.
Time Access Key register (TAKEY)................................................................................................ 17
1.4.4.
Software Reset register (SWRES) ................................................................................................. 17
1.4.5.
Reset Status Flag(RSTS) ............................................................................................................... 18
1.4.6.
Example of software reset ............................................................................................................. 18
1.5.
Clocks ......................................................................................................................................................... 18
2.
Instruction Set .......................................................................................................................................................... 19
3.
Memory Structure ..................................................................................................................................................... 23
3.1.
Program Memory ........................................................................................................................................ 23
3.2.
Data Memory............................................................................................................................................... 24
3.2.1.
Data memory - lower 128 byte (00h to 7Fh) .................................................................................. 24
3.2.2.
Data memory - higher 128 byte (80h to FFh) ................................................................................ 24
4.
CPU Engine ............................................................................................................................................................. 25
4.1.
Accumulator ................................................................................................................................................ 25
4.2.
B Register ................................................................................................................................................... 25
4.3.
Program Status Word .................................................................................................................................. 26
4.4.
Stack Pointer ............................................................................................................................................... 26
4.5.
Data Pointer ................................................................................................................................................ 26
4.6.
Data Pointer 1 ............................................................................................................................................. 27
4.7.
Interface control register ............................................................................................................................. 27
5.
GPIO ........................................................................................................................................................................ 28
6.
Timer 0 and Timer 1 ................................................................................................................................................. 30
6.1.
Timer/counter mode control register (TMOD) ............................................................................................. 30
6.2.
Timer/counter control register (TCON) ....................................................................................................... 31
6.3.
Peripheral Frequency control register(PFCON) .......................................................................................... 31
6.4.
Mode 0 (13-bit Counter/Timer) .................................................................................................................... 32
6.5.
Mode 1 (16-bit Counter/Timer) .................................................................................................................... 32
6.6.
Mode 2 (8-bit auto-reload Counter/Timer) .................................................................................................. 33
6.7.
Mode 3 (Timer 0 acts as two independent 8 bit Timers / Counters) ........................................................... 33
7.
Timer 2 and Capture/Compare Unit ......................................................................................................................... 34
7.1.
Timer 2 function........................................................................................................................................... 36
7.1.1.
Timer mode .................................................................................................................................... 36
7.1.2.
Event counter mode ....................................................................................................................... 36
7.1.3.
Gated timer mode .......................................................................................................................... 36
7.1.4.
Reload of Timer 2 ........................................................................................................................... 36
7.2.
Compare function ........................................................................................................................................ 36
7.2.1.
Compare Mode 0 ........................................................................................................................... 37
7.2.2.
Compare Mode 1 ........................................................................................................................... 37
7.3.
Capture function .......................................................................................................................................... 38
7.3.1.
Capture Mode 0 ............................................................................................................................. 38
7.3.2.
Capture Mode 1 ............................................................................................................................. 38
8.
Serial interface 0 ...................................................................................................................................................... 39
8.1.
Serial interface 0 ......................................................................................................................................... 40
8.1.1.
Mode 0 ........................................................................................................................................... 40
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
1
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
8.1.2.
Mode 1 ........................................................................................................................................... 41
8.1.3.
Mode 2 ........................................................................................................................................... 41
8.1.4.
Mode 3 ........................................................................................................................................... 41
8.2.
Multiprocessor communication of Serial Interface 0 ................................................................................... 42
8.3.
Baud rate generator .................................................................................................................................... 42
8.3.1.
Serial interface 0 modes 1 and 3 ................................................................................................... 42
9.
Watchdog timer ........................................................................................................................................................ 43
10.
Interrupt ........................................................................................................................................................... 46
11.
Power Management Unit ................................................................................................................................. 50
11.1. Idle mode .................................................................................................................................................... 50
11.2. Stop mode ................................................................................................................................................... 50
12.
Low Voltage Control ........................................................................................................................................ 51
13.
In-System Programming (Internal ISP) ........................................................................................................... 52
13.1.
ISP service program ............................................................................................................................... 52
13.2.
Lock Bit (N) ............................................................................................................................................. 52
13.3.
Program the ISP Service Program ......................................................................................................... 52
13.4.
Initiate ISP Service Program................................................................................................................... 53
13.5.
ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC .................................................... 53
Operating Conditions ........................................................................................................................................................ 56
DC Characteristics ............................................................................................................................................................ 56
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
2
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Product List
Features
SM59R02G1W28KP, SM59R02G1W28SP,
SM59R02G1W40PP, SM59R02G1W44JP,
SM59R02G1W44QP, SM59R02G1W44UP,
SM59R02G1W48VP
Description
The SM59R02G1 is a 1T (one machine cycle per clock)
single-chip 8-bit microcontroller. It has 8K-byte
embedded Flash for program, and executes all ASM51
instructions fully compatible with MCS-51.
SM59R02G1 contains 256B on-chip RAM, more than 42
GPIOs (PLCC 44, QFP 44 and LQFP 48), various serial
interfaces and many peripheral functions as described
below. It can be programmed via writers. Its on-chip ICE
is convenient for users in verification during development
stage. The high performance of SM59R02G1 can
achieve complicated manipulation within short time.
About one third of the instructions are pure 1T, and the
average speed is 8 times of traditional 8051, the fastest
one among all the 1T 51-series.Its excellent EMI and
ESD characteristics are advantageous for many different
applications.
Ordering Information
SM59R02G1ihhkL YWW
i: process identifier {W = 2.7V ~ 5.5V}
hh: Pin Count
k: package type postfix {as table below }
L:PB Free identifier
{No text is Non-PB free，”P” is PB free}
Y: Year Code
WW: Week Code (01-52)
Postfix
K
S
P
J
Q
V
Package
28L PDIP
28L SOP
40L PDIP
44L PLCC
44L PQFP
48L LQFP
Operating Voltage: 2.7V ~ 5.5V
High speed architecture of 1 clock/machine cycle
(1T), runs up to 25MHz
1T/2T can be switched on the fly
Instruction-set compatible with MCS-51
8K Bytes on-chip program memory.
External RAM addresses up to 64K bytes.
Standard 12T interface for external RAM access.
256 bytes RAM as standard 8052
Dual 16-bit Data Pointers (DPTR0 & DPTR1)
One serial peripheral interfaces in full duplex mode
(UART0),
Additional Baud Rate Generator for Serial 0.
Three 16-bit Timers/Counters. (Timer 0 , 1, 2)
38 GPIOs(PDIP 40), 42 GPIOs(PLCC 44/PQFP
44/LQFP 48),GPIOs can select four
Type(quasi-bidirectional, push-pull, open drain,
input-only), default is quasi-bidirectional(pull-up)
External interrupt 0,1 with four priority levels
Programmable watchdog timer (WDT)
4-channel 16-bit compare /capture /load functions
22.1184MHz Internal RC oscillator, with programmable
clock divider
Configurable Oscillator pin
ISP/IAP functions.
ISP service program space configurable in N*256 byte
(N=0 to 4) size.
EEPROM function
ALE output select.
LVR (LVR deglitch 500ns)
Enhanced user code protection
Power management unit for idle and power down
modes
Pin / Pad Configuration
Page 4
Page 5
Page 6
Page 7
Page 8
Page 9
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
3
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Pin Configuration
28
VDD
CC1/T2EX/P1.1
2
27
P0.0/AD0
RXD0/P1.2
3
26
P0.1/AD1
CC2/TXD0/P1.3
P4.7/RESET(default)
4
25
P0.2/AD2
24
P0.3/AD3
23
P0.4/AD4
22
P0.5/AD5
21
P0.6/AD6
20
P0.7/AD7
19
P2.4/A12
18
P2.3/A11/CC3
17
P2.2/A10/CC2
5
SyncMOS
1
SM59R02G1ihhKP
YWW
(28L PDIP Top View)
CC0/T2/P1.0
RXD0/P3.0
6
TXD0/P3.1
7
INT0/P3.2
8
INT1/P3.3
T0/P3.4
9
10
T1/P3.5
11
XTAL2/P5.4
12
OSC/XTAL1/P5.5
13
16
P2.1/A9/CC1
VSS
14
15
P2.0/A8/CC0
Notes：
The pin Reset/P4.7 factory default is Reset, user must keep this pin at low during power-up. User can configure it to
GPIO (P4.7) by a flash programmer.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
4
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
28
VDD
CC1/T2EX/P1.1
2
27
P0.0/AD0
RXD0/P1.2
3
26
P0.1/AD1
CC2/TXD0/P1.3
P4.7/RESET(default)
4
25
P0.2/AD2
24
P0.3/AD3
23
P0.4/AD4
22
P0.5/AD5
21
P0.6/AD6
20
P0.7/AD7
19
P2.4/A12
18
P2.3/A11/CC3
17
P2.2/A10/CC2
5
SyncMOS
1
SM59R02G1ihhSP
YWW
(28L SOP Top View)
CC0/T2/P1.0
RXD0/P3.0
6
TXD0/P3.1
7
INT0/P3.2
8
INT1/P3.3
T0/P3.4
9
10
T1/P3.5
11
XTAL2/P5.4
12
OSC/XTAL1/P5.5
13
16
P2.1/A9/CC1
VSS
14
15
P2.0/A8/CC0
Notes：
The pin Reset/P4.7 factory default is Reset, user must keep this pin at low during power-up. User can configure it to
GPIO (P4.7) by a flash programmer.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
5
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
40
VDD
CC1/T2EX/P1.1
2
39
P0.0/AD0
RXD0/P1.2
3
38
P0.1/AD1
CC2/TXD0/P1.3
4
37
P0.2/AD2
CC3/P1.4
5
36
P0.3/AD3
P1.5
6
35
P0.4/AD4
P1.6
7
34
P0.5/AD5
P1.7
8
33
P0.6/AD6
P4.7/RESET(default)
9
32
P0.7/AD7
RXD0/P3.0
10
31
P4.6
TXD0/P3.1
11
30
ALE/P4.5
INT0/P3.2
12
29
P4.4
INT1/P3.3
13
28
P2.7/A15
T0/P3.4
14
27
P2.6/A14
T1/P3.5
15
26
P2.5/A13
WR/P3.6
16
25
P2.4/A12
RD/P3.7
17
24
P2.3/A11/CC3
XTAL2/P5.4
18
23
P2.2/A10/CC2
OSC/XTAL1/P5.5
19
22
P2.1/A9/CC1
VSS
20
21
P2.0/A8/CC0
SyncMOS
1
SM59R02G1ihhPP
YWW
(40L PDIP Top View)
CC0/T2/P1.0
Notes：
1. The pin Reset/P4.7 factory default is Reset, user must keep this pin at low during power-up. User can configure it to
GPIO (P4.7) by a flash programmer.
2. To avoid accidentally entering ISP-Mode(refer to section 13.4), care must be taken not asserting pulse signal at P3.0
during power-up while P2.6, P2.7, P4.3 are set to high.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
6
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
18
19
20
21
22
23
24
25
26
27
28
CC1/KBI1/A9/P2.1
CC2/A10/P2.2
CC3/A11/P2.3
A12/P2.4
39
16
T1/P3.5
CC0/A8/P2.0
15
T0/P3.4
CC0/P4.0
14
INT1/P3.3
VSS
13
INT0/P3.2
XTAL1/OSC/P5.5
12
TXD0/P3.1
XTAL2/P5.4
11
CC3/P4.3
SM59R02G1
ihhJP
YWW
(44L PLCC Top View)
RD/P3.7
10
RXD0/P3.0
WR/P3.6
9
P4.7/RESET(default)
38
SyncMOS
P0.4/AD4
P0.5/AD5
37
P0.3/AD3
40
P0.6/AD6
36
P0.2/AD2
41
P0.7/AD7
35
P0.1/AD1
42
P4.6
34
P0.0/AD0
43
P4.1
33
VDD
44
1
ALE/P4.5
32
P1.0/T2/CC0
P4.2/CC2
2
P4.4
31
P1.1/T2EX/CC1
3
P2.7/A15
30
P1.2/RXD0
4
P2.6/A14
29
P1.3//CC2/TXD0
5
7
P1.7
17
P1.6
6
8
P1.5
P1.4/CC3
8KB with ISP Flash
& 256B RAM embedded
P2.5/A13
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
7
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
P4.6
P4.1/CC1
ALE/P4.5
P4.4
P2.7/A15
P2.6/A14
P2.5/A13
32
31
30
29
28
27
26
25
24
23
11
44
T1/P3.5
CC3/P1.4
10
43
T0/P3.4
TXD0/CC2/P1.3
9
42
INT1/P3.3
RXD0/P1.2
8
41
INT0/P3.2
CC1/T2EX/P1.1
7
40
TXD0/P3.1
CC0/T2/P1.0
SM59R02G1
ihhQ(U)P
YWW
(44L PQFP/LQFP
Top View)
6
39
CC3/P4.3
CC2/P4.2
5
38
RXD0/P3.0
VDD
4
37
P4.7/RESET(default)
AD0/P0.0
SyncMOS
3
36
P1.7
AD1/P0.1
2
35
P1.6
AD2/P0.2
1
34
P1.5
AD3/P0.3
33
8KB with ISP Flash
& 256B RAM embedded
22
P2.4/A12
21
P2.3/A11/CC3
20
P2.2/A10/CC2
19
P2.1/A9/CC1
18
P2.0/A8/CC0
17
P4.0/CC0
16
VSS
15
OSC/XTAL1/P5.5
14
XTAL2/P5.4
13
P3.7/RD
12
P3.6/WR
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
8
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
P4.6
P4.1/CC1
ALE/P4.5
P4.4
P2.7/A15
P2.6/A14
P2.5/A13
N.C.
35
34
33
32
31
30
29
28
27
26
25
12
48
T1/P3.5
N.C.
11
47
T0/P3.4
CC3/P1.4
10
46
INT1/P3.3
TXD0/CC2/P1.3
9
45
INT0/P3.2
RXD0/P1.2
8
44
TXD0/P3.1
CC1/T2EX/P1.1
7
43
CC3/P4.3
CC0/T2/P1.0
SM59R02G1
IhhVP
YWW
(48L LQFP Top View)
6
42
RXD0/P3.0
CC2/P4.2
5
41
P4.7/RESET(default)
VDD
4
40
P1.7
AD0/P0.0
SyncMOS
3
39
P1.6
AD1/P0.1
2
38
P1.5
AD2/P0.2
1
37
N.C.
AD3/P0.3
36
8KB with ISP Flash
& 256B RAM embedded
24
N.C.
23
P2.4/A12
22
P2.3/A11/CC3
21
P2.2/A10/CC2
20
P2.1/A9/CC1
19
P2.0/A8/CC0
18
P4.0/CC0
17
VSS
16
OSC/XTAL1/P5.5
15
XTAL2/P5.4
14
P3.7/RD
13
P3.6/WR
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
9
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
RXD0
TXD0
Block Diagram
RESET
MAX810
UART 0
SRAM
256Bytes
XTAL2
XTAL1
Flash 8KBytes
CPU
Port 0
Port 0
Port 1
Port 1
Port 2
Port 2
Port 3
Port 3
Port 4
Port 4
Port 5
Port 5
Timer 0/1
T0
T1
Watchdog
Interrupt
ALE
WR
RD
Timer2
& CCU
CC0~CC3
T2
T2EX
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
10
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Pin Description
28L
40L
PDIP
44L
PLCC
1
44L
QFP
39
48L
LQFP
42
Symbol
I/O
P4.2/CC2
I/O
Description
1
1
2
40
43
P1.0/T2/CC0
I/O
2
2
3
41
44
P1.1/T2EX/CC1
I/O
3
3
4
42
45
P1.2/RXD0
I/O
4
4
5
43
46
P1.3/TXD0/CC2
I/O
5
6
44
7
8
9
1
2
3
I/O
I/O
I/O
Bit 5 of port 1
Bit 6 of port 1
Bit 7 of port 1
5
9
10
4
5
P1.4/CC3
NC
NC
P1.5
P1.6
P1.7
RESET(default)/P
4.7
I/O
6
7
8
47
48
1
2
3
4
Bit 2 of port 4 & Timer 2 compare/capture Channel 2
Bit 0 of port 1 & Timer 2 external input clock & Timer 2
compare/capture Channel 0
Bit 1 of port 1 & Timer 2 capture trigger & Timer 2
compare/capture Channel 1
Bit 2 of port 1 & Serial interface channel 0 receive data
Bit 3 of port 1 & Serial interface channel 0 transmit data &
Timer 2 compare/capture Channel 2
Bit 4 of port 1 & Timer 2 compare/capture Channel 3
I/O
Reset pin(default)& Bit 7 of port 4
6
10
11
5
6
P3.0/RXD0
I/O
12
6
7
P4.3/CC3
I/O
7
11
13
7
8
P3.1/TXD0
I/O
8
9
10
11
12
13
14
12
13
14
15
16
17
18
19
20
14
15
16
17
18
19
20
21
22
23
8
9
10
11
12
13
14
15
16
17
9
10
11
12
13
14
15
16
17
18
P3.2/#INT0
P3.3/#INT1
P3.4/T0
P3.5/T1
P3.6/#WR
P3.7/#RD
XTAL2/P5.4
XTAL1/OSC/P5.5
VSS
P4.0/CC0
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I/O
15
21
24
18
19
P2.0 /A8/CC0
I/O
16
22
25
19
20
P2.1 /A9/CC1
I/O
17
23
26
20
21
P2.2 /A10/CC2
I/O
18
24
27
21
22
P2.3 /A11/CC3
I/O
19
25
28
22
29
30
31
32
33
34
35
36
23
24
25
26
27
28
29
30
P2.4 /A12
NC
NC
P2.5 /A13
P2.6 /A14
P2.7 /A15
P4.4
ALE/P4.5
P4.1CC1
P4.6
P0.7/AD7
I/O
26
27
28
29
30
23
24
25
26
27
28
29
30
31
32
33
Bit 0 of port 3 & Serial interface channel 0 receive/transmit
data
Bit 3 of port 4 & Timer 2 compare/capture Channel 3
Bit 1 of port 3 & Serial interface channel 0 transmit data or
receive clock in mode 0
Bit 2 of port 3 & External interrupt 0
Bit 3 of port 3 & External interrupt 1
Bit 4 of port 3 & Timer 0 external input
Bit 5 of port 3 & Timer 1 external input
Bit 6 of port 3 & external memory write signal
Bit 7 of port 3 & external memory read signal
Crystal output & bit4 of port 5
Crystal input& Oscillator input& bit5 of port 5
Ground line
Bit 0 of port 4 & Timer 2 compare/capture Channel 0
Bit 0 of port 2 & Bit 8 of external memory address& Timer 2
compare/capture Channel 0
Bit 1 of port 2 & Bit 9 of external memory address& Timer 2
compare/capture Channel 1
Bit 2 of port 2 & Bit 10 of external memory address & Timer
2 compare/capture Channel 2
Bit 3 of port 2 & Bit 11 of external memory address & Timer 2
compare/capture Channel 3
Bit 4 of port 2 & Bit 12 of external memory address
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Bit 5 of port 2 & Bit 13 of external memory address
Bit 6 of port 2 & Bit 14 of external memory address
Bit 7 of port 2 & Bit 15 of external memory address
Bit 4 of port 4
Address latch enable & Bit 5 of port 4
Bit 1 of port 4 & Timer 2 compare/capture Channel 1
Bit 6 of port 4
Bit 7 of port 0 & Bit 7 of external memory address/ data
20
31
32
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
11
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
28L
21
22
23
24
25
26
27
28
40L
PDIP
33
34
35
36
37
38
39
40
44L
PLCC
37
38
39
40
41
42
43
44
44L
QFP
31
32
33
34
35
36
37
38
48L
LQFP
34
35
36
37
38
39
40
41
Symbol
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
Bit 6 of port 0 & Bit 6 of external memory address/ data
Bit 5 of port 0 & Bit 5 of external memory address/ data
Bit 4 of port 0 & Bit 4 of external memory address/ data
Bit 3 of port 0 & Bit 3 of external memory address/ data
Bit 2 of port 0 & Bit 2 of external memory address/ data
Bit 1 of port 0 & Bit 1 of external memory address/ data
Bit 0 of port 0 & Bit 0 of external memory address/ data
Power supply
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
12
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Special Function Register (SFR)
A map of the Special Function Registers is shown as below:
Hex\Bin
X000
X001
X010
X011
X100
X101
F8
X110
X111
Bin/Hex
-
-
FF
F0
B
-
TAKEY
F7
E8
E0
P4
ACC
ISPFAH
ISPFAL
ISPFD
ISPFC
-
LVC
SWRES
EF
E7
D8
P5
PFCON
P3M0
P3M1
P4M0
P4M1
P5M0
P5M1
DF
D0
PSW
CCEN2
P0M0
P0M1
P1M0
P1M1
P2M0
P2M1
D7
C8
C0
T2CON
IRCON
CCCON
CCEN
CRCL
CCL1
CRCH
CCH1
TL2
CCL2
TH2
CCH2
CCL3
CCH3
CF
C7
B8
IEN1
IP1
S0RELH
-
-
-
-
-
BF
B0
P3
-
-
-
-
-
WDTC
WDTK
B7
A8
A0
IEN0
P2
IP0
RSTS
S0RELL
-
-
-
-
-
-
AF
A7
98
S0CON
S0BUF
IEN2
-
-
-
-
-
9F
-
IRCON2
97
X110
IFCON
PCON
X111
8F
87
Bin/Hex
90
P1
AUX
AUX2
-
-
-
88
80
Hex\Bin
TCON
P0
X000
TMOD
SP
X001
TL0
DPL
X010
TL1
DPH
X011
TH0
DPL1
X100
TH1
DPH1
X101
Note: Special Function Registers reset values and description for SM59R02G1
Register
Location
Reset value
Description
P0
SP
80h
81h
FFh
07h
Port 0
Stack Pointer
DPL
DPH
DPL1
DPH1
82h
83h
84h
85h
00h
00h
00h
00h
Data Pointer 0 low byte
Data Pointer 0 high byte
Data Pointer 1 low byte
Data Pointer 1 high byte
PCON
TCON
TMOD
TL0
87h
88h
89h
8Ah
40h
00h
00h
00h
Power Control
Timer/Counter Control
Timer Mode Control
Timer 0, low byte
TL1
TH0
TH1
IFCON
8Bh
8Ch
8Dh
8Fh
00h
00h
00h
00h
Timer 1, low byte
Timer 0, high byte
Timer 1, high byte
Interface control register
P1
90h
FFh
Port 1
AUX
91h
00h
Auxiliary register
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
13
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Register
Location
Reset value
Description
AUX2
92h
00h
Auxiliary 2 register
IRCON2
97H
00h
Interrupt Request Control Register
S0CON
98h
00h
Serial Port 0, Control Register
S0BUF
99h
00h
Serial Port 0, Data Buffer
IEN2
9Ah
00h
Interrupt Enable Register 2
P2
A0h
FFh
Port 2
RSTS
A1h
00h
Reset Status Flag Register
IEN0
A8h
00h
Interrupt Enable Register 0
IP0
A9h
00h
Interrupt Priority Register 0
S0RELL
AAh
00h
Serial Port 0, Reload Register, low byte
P3
B0h
FFh
Port 3
WDTC
B6h
04h
Watchdog timer control register
WDTK
B7h
00h
Watchdog timer refresh key.
IEN1
B8h
00h
Interrupt Enable Register 1
IP1
B9h
00h
Interrupt Priority Register 1
S0RELH
BAh
00h
Serial Port 0, Reload Register, high byte
IRCON
C0h
00h
Interrupt Request Control Register
CCEN
C1h
00h
Compare/Capture Enable Register
CCL1
C2h
00h
Compare/Capture Register 1, low byte
CCH1
C3h
00h
Compare/Capture Register 1, high byte
CCL2
C4h
00h
Compare/Capture Register 2, low byte
CCH2
C5h
00h
Compare/Capture Register 2, high byte
CCL3
C6h
00h
Compare/Capture Register 3, low byte
CCH3
C7h
00h
Compare/Capture Register 3, high byte
T2CON
C8h
00h
Timer 2 Control
CCCON
C9h
00h
Compare/Capture Control
CRCL
CAh
00h
Compare/Reload/Capture Register, low byte
CRCH
CBh
00h
Compare/Reload/Capture Register, high byte
TL2
CCh
00h
Timer 2, low byte
TH2
CDh
00h
Timer 2, high byte
PSW
D0h
00h
Program Status Word
CCEN2
D1h
00h
Compare/Capture Enable 2 register
P0M0
D2h
00h
Port 0 output mode 0
P0M1
D3h
00h
Port 0 output mode 1
P1M0
D4h
00h
Port 1 output mode 0
P1M1
D5h
00h
Port 1 output mode 1
P2M0
D6h
00h
Port 2 output mode 0
P2M1
D7h
00h
Port 2 output mode 1
P5
D8h
FFh
Port 5
PFCON
D9h
00h
Peripheral Frequency control register
P3M0
DAh
00h
Port 3 output mode 0
P3M1
DBh
00h
Port 3 output mode 1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
14
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Register
Location
Reset value
Description
P4M0
DCh
00h
Port 4 output mode 0
P4M1
DDh
00h
Port 4 output mode 1
P5M0
DEh
00h
Port 5 output mode 0
P5M1
DFh
00h
Port 5 output mode 1
ACC
E0h
00h
Accumulator
ISPFAH
E1h
FFh
ISP Flash Address-High register
ISPFAL
E2h
FFh
ISP Flash Address-Low register
ISPFD
E3h
FFh
ISP Flash Data register
ISPFC
E4h
00h
ISP Flash control register
LVC
E6h
20h
Low voltage control register
SWRES
E7h
00h
Software Reset register
P4
E8h
FFh
Port 4
B
F0h
00h
B Register
TAKEY
F7h
00h
Time Access Key register
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
15
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Function Description
1. General Features
SM59R02G1 is an 8-bit micro-controller。All of its functions and the detailed meanings of SFR will be given in the following
sections.
1.1.
Embedded Flash
The program can be loaded into the embedded 8KB Flash memory via its writer or In-System Programming (ISP).
1.2.
IO Pads
The SM59R02G1 has six I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5. Ports 0, 1, 2, 3, 4 are 8-bit ports and
Port 5 is a 2-bit port (Only Bit 4 and Bit 5). These are: quasi-bidirectional (standard 8051 port outputs), push-pull, open
drain, and input-only. As description in section 5.
The XTAL2 and XTAL1 can define as P5.4 and P5.5 by writer or ISP. When user use external OSC as system clock and
input into XTAL1, Only XTAL2 can be defined as P5.4.
All the pads for P0 ~ P5 are with slew rate to reduce EMI. The other way to reduce EMI is to disable the ALE output if
unused. This is selected by its SFR. The IO pads can withstand 4KV ESD in human body mode guaranteeing the
SM59R02G1’s quality in high electro-static environments.
1.3.
2T/1T Selection
The conventional 52-series MCUs are 12T, i.e., 12 oscillator clocks per machine cycle. SM59R02G1 is a 2T or 1T MCU,
i.e., its machine cycle is two-clock or one-clock. In the other words, it can execute one instruction within two clocks or
only one clock. The difference between 2T mode and 1T mode are given in the example in Fig. 1-1.
Fig. 1-1(a): The waveform of internal instruction signal in 2T mode
Fig. 1-1(b): The waveform of internal instruction signal in 1T mode
The default is in 2T mode, and it can be changed to 1T mode if IFCON [7] (at address 8Fh) is set to high any time. Not
every instruction can be executed with one machine cycle. The exact machine cycle number for all the instructions are
given in the next section.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
16
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
1.4.
1.4.1.
RESET
Hardware RESET function
SM59R02G1 provides Internal reset circuit inside，the Internal reset time can set by writer or ISP。
Internal Reset time
25ms (default)
200ms
100ms
50ms
16ms
8ms
4ms
1.4.2.
Software RESET function
SM59R02G1 provides one software reset mechanism to reset whole chip. To perform a software reset, the firmware must
write three specific values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the Software Reset register
(SWRES) write attribute. After SWRES register obtain the write authority, the firmware can write FFh to the SWRES
register. The hardware will decode a reset signal that “OR” with the other hardware reset. The SWRES register is
self-reset at the end of the software reset procedure.
Mnemonic
TAKEY
SWRES
RSTS
1.4.3.
Description
Time Access Key
register
Software Reset
register
Reset Status Flag
register
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Software Reset function
Bit 3
Bit 2
Bit 1
Bit 0
RESET
F7h
TAKEY [7:0]
00H
E7h
SWRES [7:0]
00H
A1h
-
-
-
PDRF
WDTF
SWRF
LVRF
2
1
Address: F7H
0
Reset
00H
PORF
00H
Time Access Key register (TAKEY)
Mnemonic: TAKEY
7
6
5
4
3
TAKEY [7:0]
Software reset register (SWRES) is read-only by default; software must write three specific values
55h, AAh and 5Ah sequentially to the TAKEY register to enable the SWRES register write attribute. That
is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
1.4.4.
Software Reset register (SWRES)
Mnemonic: SWRES
7
6
5
4
3
SWRES [7:0]
2
1
Address: E7H
0
Reset
00H
SWRES [7:0]: Software reset register bit. These 8-bit is self-reset at the end of the reset procedure.
SWRES [7:0] = FFh, software reset.
SWRES [7:0] = 00h ~ FEh, MCU no action.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
17
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
1.4.5.
Reset Status Flag(RSTS)
Mnemonic: RSTS
7
6
-
5
-
4
PDRF
3
WDTF
2
SWRF
1
LVRF
Address: A1H
0
Reset
PORF
00H
PDRF: Pad reset flag.
When MCU is reset by reset pad, PDRF flag will be set to one by hardware. This flag clear by
software.
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag clear by
software.
SWRF: Software reset flag.
When MCU is reset by software, SWRF flag will be set to one by hardware. This flag clear by
software.
LVRF: Low voltage reset flag.
When MCU is reset by LVR, LVRF flag will be set to one by hardware. This flag clear by software.
PORF: Power on reset flag.
When MCU is reset by POR, PORF flag will be set to one by hardware. This flag clear by
software.
1.4.6.
Example of software reset
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah ; enable SWRES write attribute
MOV SWRES, #FFh ; software reset MCU
1.5.
Clocks
The default clock is the 22.1184MHz Internal OSC. This clock is used during the initialization stage. The major work of the
initialization stage is to determine the clock source used in normal operation.
The internal clock sources are from the internal OSC with difference frequency division as given in
source can set by writer。
table 1-1, the clock
Table 1-1: Selection of clock source
Clock source
external crystal
External OSC into Xtal1
22.1184 MHz from internal OSC(default)
11.0592MHz from internal OSC
5.5296MHz from internal OSC
2.7648MHz from internal OSC
1.3824MHz from internal OSC
The internal OSC have ±2％ variance at room temperature.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
18
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
2. Instruction Set
All SM59R02G1 instructions are binary code compatible and perform the same functions as they do with the industry
standard 8051. The following tables give a summary of the instruction set cycles of the SM59R02G1 Microcontroller core.
Mnemonic
ADD A,Rn
Table 2-1: Arithmetic operations
Description
Add register to accumulator
Code
28-2F
ADD A,direct
Add direct byte to accumulator
ADD A,@Ri
ADD A,#data
ADDC A,Rn
Bytes
1
Cycles
1
25
2
2
Add indirect RAM to accumulator
26-27
1
2
Add immediate data to accumulator
Add register to accumulator with carry flag
24
38-3F
2
1
2
1
ADDC A,direct
Add direct byte to A with carry flag
35
2
2
ADDC A,@Ri
Add indirect RAM to A with carry flag
36-37
1
2
ADDC A,#data
SUBB A,Rn
Add immediate data to A with carry flag
Subtract register from A with borrow
34
98-9F
2
1
2
1
SUBB A,direct
Subtract direct byte from A with borrow
95
2
2
SUBB A,@Ri
Subtract indirect RAM from A with borrow
96-97
1
2
SUBB A,#data
INC A
INC Rn
Subtract immediate data from A with borrow
Increment accumulator
Increment register
94
04
08-0F
2
1
1
2
1
2
INC direct
Increment direct byte
05
2
3
INC @Ri
Increment indirect RAM
06-07
1
3
INC DPTR
DEC A
Increment data pointer
Decrement accumulator
A3
14
1
1
1
1
DEC Rn
Decrement register
18-1F
1
2
DEC direct
Decrement direct byte
15
2
3
DEC @Ri
MUL AB
Decrement indirect RAM
Multiply A and B
16-17
A4
1
1
3
5
DIV
Divide A by B
84
1
5
DA A
Decimal adjust accumulator
D4
1
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
19
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Mnemonic
ANL A,Rn
Table 2-2: Logic operations
Description
AND register to accumulator
Code
58-5F
ANL A,direct
AND direct byte to accumulator
ANL A,@Ri
ANL A,#data
ANL direct,A
Bytes
1
Cycles
1
55
2
2
AND indirect RAM to accumulator
56-57
1
2
AND immediate data to accumulator
AND accumulator to direct byte
54
52
2
2
2
3
ANL direct,#data
AND immediate data to direct byte
53
3
4
ORL A,Rn
OR register to accumulator
48-4F
1
1
ORL A,direct
ORL A,@Ri
OR direct byte to accumulator
OR indirect RAM to accumulator
45
46-47
2
1
2
2
ORL A,#data
OR immediate data to accumulator
44
2
2
ORL direct,A
OR accumulator to direct byte
42
2
3
ORL direct,#data
XRL A,Rn
OR immediate data to direct byte
Exclusive OR register to accumulator
43
68-6F
3
1
4
1
XRL A,direct
Exclusive OR direct byte to accumulator
65
2
2
XRL A,@Ri
Exclusive OR indirect RAM to accumulator
66-67
1
2
XRL A,#data
Exclusive OR immediate data to accumulator
64
2
2
XRL direct,A
XRL direct,#data
Exclusive OR accumulator to direct byte
Exclusive OR immediate data to direct byte
62
63
2
3
3
4
CLR A
Clear accumulator
E4
1
1
CPL A
Complement accumulator
F4
1
1
RL A
RLC A
Rotate accumulator left
Rotate accumulator left through carry
23
33
1
1
1
1
RR A
Rotate accumulator right
03
1
1
RRC A
Rotate accumulator right through carry
13
1
1
SWAP A
Swap nibbles within the accumulator
C4
1
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
20
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Mnemonic
MOV A,Rn
MOV A,direct
Table 2-3: Data transfer
Description
Move register to accumulator
Move direct byte to accumulator
Code
E8-EF
E5
Bytes
1
2
Cycles
1
2
MOV A,@Ri
MOV A,#data
MOV Rn,A
MOV Rn,direct
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
Move direct byte to register
E6-E7
74
F8-FF
A8-AF
1
2
1
2
2
2
2
4
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct1,direct2
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
78-7F
F5
88-8F
85
2
2
2
3
2
3
3
4
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
MOV @Ri,direct
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move direct byte to indirect RAM
86-87
75
F6-F7
A6-A7
2
3
1
2
4
3
3
5
MOV @Ri,#data
Move immediate data to indirect RAM
76-77
2
3
MOV DPTR,#data16
Load data pointer with a 16-bit constant
90
3
3
MOVC A,@A+DPTR
Move code byte relative to DPTR to accumulator
93
1
3
MOVC A,@A+PC
MOVX A,@Ri
Move code byte relative to PC to accumulator
Move external RAM (8-bit addr.) to A
83
E2-E3
1
1
3
3
MOVX A,@DPTR
MOVX @Ri,A
MOVX @DPTR,A
PUSH direct
Move external RAM (16-bit addr.) to A
Move A to external RAM (8-bit addr.)
Move A to external RAM (16-bit addr.)
Push direct byte onto stack
E0
F2-F3
F0
C0
1
1
1
2
3
4
4
4
POP direct
XCH A,Rn
XCH A,direct
XCH A,@Ri
XCHD A,@Ri
Pop direct byte from stack
Exchange register with accumulator
Exchange direct byte with accumulator
Exchange indirect RAM with accumulator
Exchange low-order nibble indir. RAM with A
D0
C8-CF
C5
C6-C7
D6-D7
2
1
2
1
1
3
2
3
3
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
21
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Mnemonic
ACALL addr11
Table 2-4: Program branches
Description
Absolute subroutine call
Code
xxx11
LCALL addr16
Long subroutine call
RET
RETI
AJMP addr11
Bytes
2
Cycles
6
12
3
6
from subroutine
22
1
4
from interrupt
Absolute jump
32
xxx01
1
2
4
3
LJMP addr16
Long iump
02
3
4
SJMP rel
Short jump (relative addr.)
80
2
3
JMP @A+DPTR
JZ rel
Jump indirect relative to the DPTR
Jump if accumulator is zero
73
60
1
2
2
3
JNZ rel
Jump if accumulator is not zero
70
2
3
JC rel
Jump if carry flag is set
40
2
3
JNC
JB bit,rel
Jump if carry flag is not set
Jump if direct bit is set
50
20
2
3
3
4
JNB bit,rel
Jump if direct bit is not set
30
3
4
JBC bit,direct rel
Jump if direct bit is set and clear bit
10
3
4
CJNE A,direct rel
Compare direct byte to A and jump if not equal
B5
3
4
CJNE A,#data rel
CJNE Rn,#data rel
Compare immediate to A and jump if not equal
Compare immed. to reg. and jump if not equal
B4
B8-BF
3
3
4
4
CJNE @Ri,#data rel
Compare immed. to ind. and jump if not equal
B6-B7
3
4
DJNZ Rn,rel
Decrement register and jump if not zero
D8-DF
2
3
DJNZ direct,rel
NOP
Decrement direct byte and jump if not zero
No operation
D5
00
3
1
4
1
Mnemonic
CLR C
Table 2-5: Boolean manipulation
Description
Clear carry flag
Code
C3
CLR bit
Clear direct bit
C2
Bytes
1
Cycles
1
2
3
SETB C
Set carry flag
D3
1
1
SETB bit
CPL C
Set direct bit
Complement carry flag
D2
B3
2
1
3
1
CPL bit
Complement direct bit
B2
2
3
ANL C,bit
AND direct bit to carry flag
82
2
2
ANL C,/bit
ORL C,bit
AND complement of direct bit to carry
OR direct bit to carry flag
B0
72
2
2
2
2
ORL C,/bit
OR complement of direct bit to carry
A0
2
2
MOV C,bit
Move direct bit to carry flag
A2
2
2
MOV bit,C
Move carry flag to direct bit
92
2
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
22
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
3. Memory Structure
The SM59R02G1 memory structure follows general 8052 structure. It is 8KB program memory.
3.1.
Program Memory
The SM59R02G1 has 8KB on-chip flash memory which can be used as general program memory or EEPROM, on which
include up to 1K byte specific ISP service program memory space. The address range for the 8K byte is $0000 to $1FFF.
The address range for the ISP service program is $1C00 to $1FFF. The ISP service program size can be partitioned as N
blocks of 256 byte (N=0 to 4). When N=0 means no ISP service program space available, total 8K byte memory used as
program memory. When N=1 means address $1F00 to $1FFF reserved for ISP service program. When N=2 means
memory address $1E00 to $1FFF reserved for ISP service program…etc. Value N can be set and programmed into
SM59R02G1 information block by writer. It can be used to record any data as EEPROM. The procedure of this EEPROM
application function is described in the section 13 on internal ISP.
1FFF
N=0
N=1
1F00
ISP service
Program space,
Up to 1K
1E00
N=2
1D00
1C00
N=3
N=4
8K Program
Memory space
0000
Fig. 3-1: SM59R02G1 programmable Flash
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
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Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
3.2. Data Memory
The SM59R02G1 has 256Bytes on-chip SRAM, 256 Bytes are the same as general 8052 internal memory structure.
Fig 3-2 (a)：External memory access as read
Fig 3-2 (b)：External memory access as write
FF
FF
Higher 128 Bytes (Accessed by
indirect addressing mode only)
SFR (Accessed by direct addressing
mode only)
80
80
7F
Lower 128 Bytes (Accessed by direct
& indirect addressing mode )
00
Fig. 3-3: RAM architecture
3.2.1.
Data memory - lower 128 byte (00h to 7Fh)
Data memory 00h to FFh is the same as 8052.
The address 00h to 7Fh can be accessed by direct and indirect addressing modes.
Address 00h to 1Fh is register area.
Address 20h to 2Fh is memory bit area.
Address 30h to 7Fh is for general memory area.
3.2.2.
Data memory - higher 128 byte (80h to FFh)
The address 80h to FFh can be accessed by indirect addressing mode.
Address 80h to FFh is data area.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
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Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
4. CPU Engine
The SM59R02G1 engine is composed of four components:
a. Control unit
b. Arithmetic – logic unit
c. Memory control unit
d. RAM and SFR control unit
The SM59R02G1 engine allows to fetch instruction from program memory and to execute using RAM or SFR. The
following paragraphs describe the main engine registers.
Mnemonic
Description
Direct
Bit 7
ACC
B
Accumulator
B register
Program status
word
Stack Pointer
Data pointer low 0
Data pointer high
0
Data pointer low 1
Data pointer high
1
Auxiliary register
Interface control
register
E0h
F0h
ACC.7
B.7
D0h
CY
PSW
SP
DPL
DPH
DPL1
DPH1
AUX
IFCON
4.1.
Bit 6
Bit 5
8051 Core
ACC.6 ACC.5
B.6
B.5
AC
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
ACC.4
B.4
ACC.3
B.3
ACC.2
B.2
ACC.1
B.1
ACC.0
B.0
00H
00H
OV
PSW.1
P
00H
F0
RS[1:0]
81h
82h
SP[7:0]
DPL[7:0]
07H
00H
83h
DPH[7:0]
00H
84h
DPL1[7:0]
00H
85h
DPH1[7:0]
00H
91h
BRGS
-
-
P1UR
8Fh
ITS
CDPR
-
-
-
-
-
DPS
00H
ALEC[1:0]
-
ISPE
00H
Accumulator
ACC is the Accumulator register. Most instructions use the accumulator to store the operand.
Mnemonic: ACC
7
6
ACC.7 ACC.6
5
ACC05
4
ACC.4
3
ACC.3
2
ACC.2
1
ACC.1
Address: E0h
0
Reset
ACC.0
00h
ACC[7:0]: The A (or ACC) register is the standard 8052 accumulator.
4.2.
B Register
The B register is used during multiply and divide instructions. It can also be used as a scratch pad register to store
temporary data.
Mnemonic: B
7
6
B.7
B.6
5
B.5
4
B.4
3
B.3
2
B.2
1
B.1
Address: F0h
0
Reset
B.0
00h
B[7:0]: The B register is the standard 8052 register that serves as a second accumulator.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
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Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
4.3.
Program Status Word
Mnemonic: PSW
7
6
CY
AC
5
F0
4
3
RS [1:0]
2
OV
1
F1
Address: D0h
0
Reset
P
00h
CY: Carry flag.
AC: Auxiliary Carry flag for BCD operations.
F0: General purpose Flag 0 available for user.
RS[1:0]: Register bank select, used to select working register bank.
RS[1:0]
Bank Selected
Location
00
Bank 0
00h – 07h
01
Bank 1
08h – 0Fh
10
Bank 2
10h – 17h
11
Bank 3
18h – 1Fh
OV: Overflow flag.
F1: General purpose Flag 1 available for user.
P: Parity flag, affected by hardware to indicate odd/even number of “one” bits in the
Accumulator, i.e. even parity.
4.4.
Stack Pointer
The stack pointer is a 1-byte register initialized to 07h after reset.
instructions, causing the stack to start from location 08h.
Mnemonic: SP
7
6
5
4
3
This register is incremented before PUSH and CALL
2
1
SP [7:0]
Address: 81h
0
Reset
07h
SP[7:0]: The Stack Pointer stores the scratchpad RAM address where the stack begins. In other
words, it always points to the top of the stack.
4.5.
Data Pointer
The data pointer (DPTR) is 2-bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-byte
register (e.g. MOV DPTR, #data16) or as two separate registers (e.g. MOV DPL,#data8). It is generally used to access
the external code or data space (e.g. MOVC A, @A+DPTR or MOVX A, @DPTR respectively).
Mnemonic: DPL
7
6
5
3
DPL [7:0]
2
1
Address: 82h
0
Reset
00h
4
3
DPH [7:0]
2
1
Address: 83h
0
Reset
00h
4
DPL[7:0]: Data pointer Low 0
Mnemonic: DPH
7
6
5
DPH [7:0]: Data pointer High 0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
26
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
4.6.
Data Pointer 1
The Dual Data Pointer accelerates the moves of data block. The standard DPTR is a 16-bit register that is used to
address external memory or peripherals. In the SM59R02G1 core the standard data pointer is called DPTR, the second
data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located
in LSB of AUX register (DPS).
The user switches between pointers by toggling the LSB of AUX register. All DPTR-related instructions use the currently
selected DPTR for any activity.
Mnemonic: DPL1
7
6
5
4
3
DPL1 [7:0]
2
1
Address: 84h
0
Reset
00h
4
3
DPH1 [7:0]
2
1
Address: 85h
0
Reset
00h
2
-
1
-
Address: 91h
0
Reset
DPS
00H
3
2
ALEC[1:0]
1
-
Address: 8Fh
0
Reset
ISPE
00h
DPL1[7:0]: Data pointer Low 1
Mnemonic: DPH1
7
6
5
DPH1[7:0]: Data pointer High 1
Mnemonic: AUX
7
6
BRGS
-
5
-
4
P1UR
3
-
DPS: Data Pointer selects register.
DPS = 1 is selected DPTR1.
4.7.
Interface control register
Mnemonic: IFCON
7
6
ITS
CDPR
5
-
4
-
ITS: Instruction timing select. (default is 2T)
ITS = 0, 2T instruction mode.
ITS = 1, 1T instruction mode.
CDPR: code protect (Read Only)
ALEC[1:0]: ALE output control register.
ALEC[1:0]
ALE Output
00
Always output
01
No ALE output
10
Only Read or Write have ALE output
11
reserved
ISPE: ISP function enable bit
ISPE = 1, enable ISP function
ISPE = 0, disable ISP function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
27
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
5. GPIO
The SM59R02G1 has six I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5. Ports 0, 1, 2, 3, 4 are 8-bit ports and
Port 5 is a 2-bit port (Only Bit 4 and Bit 5). These are: quasi-bidirectional (standard 8051 port outputs), push-pull, open
drain, and input-only. Two configuration registers for each port select the output type for each port pin. All I/O port pins on
the SM59R02G1 may be configured by software to one of four types on a pin-by-pin basis, shown as below:
Mnemonic
P0M0
P0M1
P1M0
P1M1
P2M0
P2M1
P3M0
P3M1
P4M0
P4M1
P5M0
P5M1
Description
Direct
Port 0 output mode 0
Port 0 output mode 1
Port 1 output mode 0
Port 1 output mode 1
Port 2 output mode 0
Port 2 output mode 1
Port 3 output mode 0
Port 3 output mode 1
Port 4 output mode 0
Port 4 output mode 1
Port 5 output mode 0
Port 5 output mode 1
PxM1.y
0
0
1
1
PxM0.y
0
1
0
1
D2h
D3h
D4h
D5h
D6h
D7h
DAh
DBh
DCh
DDh
DEh
DFh
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
I/O port function register
P0M0 [7:0]
P0M1[7:0]
P1M0[7:0]
P1M1[7:0]
P2M0[7:0]
P2M1[7:0]
P3M0[7:0]
P3M1[7:0]
P4M0[7:0]
P4M1[7:0]
P5M0[5:4]
P5M1[5:4]
-
Bit 2
-
Bit 1
-
Bit 0
RESET
-
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Port output mode
Quasi-bidirectional (standard 8051 port outputs) (pull-up)
Push-pull
Input only (high-impedance)
Open drain
The XTAL2 and XTAL1 can define as P5.4 and P5.5 by writer or ISP. When user use external OSC as system clock and
input into XTAL1, only XTAL2 can be defined as P5.4.
For general-purpose applications, every pin can be assigned to either high or low independently as given below:
Mnemonic
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Description
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Direct
Bit 7
Bit 6
D8h
E8h
B0h
A0h
90h
80h
P4.7
P3.7
P2.7
P1.7
P0.7
P4.6
P3.6
P2.6
P1.6
P0.6
Mnemonic: P0
7
6
P0.7
P0.6
5
P0.5
4
P0.4
Bit 5
Ports
P5.5
P4.5
P3.5
P2.5
P1.5
P0.5
3
P0.3
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
P5.4
P4.4
P3.4
P2.4
P1.4
P0.4
P4.3
P3.3
P2.3
P1.3
P0.3
P4.2
P3.2
P2.2
P1.2
P0.2
P4.1
P3.1
P2.1
P1.1
P0.1
P4.0
P3.0
P2.0
P1.0
P0.0
FFh
FFh
FFh
FFh
FFh
FFh
2
P0.2
1
P0.1
Address: 80h
0
Reset
P0.0
FFh
P0.7~ 0: Port0 [7] ~ Port0 [0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
28
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Mnemonic: P1
7
6
P1.7
P1.6
5
P1.5
4
P1.4
3
P1.3
2
P1.2
1
P1.1
Address: 90h
0
Reset
P1.0
FFh
4
P2.4
3
P2.3
2
P2.2
1
P2.1
Address: A0h
0
Reset
P2.0
FFh
4
P3.4
3
P3.3
2
P3.2
1
P3.1
Address: B0h
0
Reset
P3.0
FFh
4
P4.4
3
P4.3
2
P4.2
1
P4.1
Address: E8h
0
Reset
P4.0
FFh
4
P5.4
3
-
2
-
1
-
Address: D8h
0
Reset
FFh
P1.7~ 0: Port1 [7] ~ Port1 [0]
Mnemonic: P2
7
6
P2.7
P2.6
5
P2.5
P2.7~ 0: Port2 [7] ~ Port2 [0]
Mnemonic: P3
7
6
P3.7
P3.6
5
P3.5
P3.7~ 0: Port3 [7] ~ Port3 [0]
Mnemonic: P4
7
6
P4.7
P4.6
5
P4.5
P4.7~ 0: Port4 [7] ~ Port4 [0]
Mnemonic: P5
7
6
-
5
P5.5
P5.5~ 4: Port5 [5] ~ Port5 [4]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
29
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
6. Timer 0 and Timer 1
The SM59R02G1 has three 16-bit timer/counter registers: Timer 0, Timer 1 and Timer 2. All can be configured for counter
or timer operations.
In timer mode, the Timer 0 register or Timer 1 register is incremented every 1/12/96 machine cycles, which means that it
counts up after every 1/12/96 periods of the clk signal. It’s dependent on SFR(PFCON).
In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin T0or T1.
Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator
frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input
should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function registers (TMOD and TCON) are
used to select the appropriate mode.
Mnemonic
Description
Direct
TL0
Timer 0 , low byte
Timer 0 , high
byte
Timer 1 , low byte
Timer 1 , high
byte
Timer Mode
Control
Timer/Counter
Control
Peripheral
Frequency control
register
8Ah
TL0[7:0]
00h
8Ch
TH0[7:0]
00h
8Bh
TL1[7:0]
00h
8Dh
TH1[7:0]
00h
TH0
TL1
TH1
TMOD
TCON
PFCON
6.1.
Bit 7
Bit 6
Bit 5
Timer 0 and 1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
89h
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00h
88h
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00h
D9h
S0RELPS[1:0]
T1PS[1:0]
T0PS[1:0]
Timer/counter mode control register (TMOD)
Mnemonic: TMOD
7
6
5
GATE
C/T
M1
Timer 1
4
M0
3
GATE
2
1
C/T
M1
Timer 0
Address: 89h
0
Reset
M0
00h
GATE: If set, enables external gate control (pin INT0 or INT1 for Counter 0 or 1,
respectively). When INT0 or INT1 is high, and TRx bit is set (see TCON
register), a counter is incremented every falling edge on T0 or T1 input pin
C/T: Selects Timer or Counter operation. When set to 1, a counter operation is
performed, when cleared to 0, the corresponding register will function as a
timer.
M[1:0]: Selects mode for Timer/Counter 0 or Timer/Counter 1.
M1
M0
Mode
Function
0
0
Mode0
13-bit counter/timer, with 5 lower bits in TL0 or
TL1 register and 8 bits in TH0 or TH1 register
(for Timer 0 and Timer 1, respectively). The 3
high order bits of TL0 and TL1 are hold at zero.
0
1
Mode1
16-bit counter/timer.
1
0
Mode2
8 -bit auto-reload counter/timer. The reload
value is kept in TH0 or TH1, while TL0 or TL1 is
incremented every machine cycle. When TLx
overflows, a value from THx is copied to TLx.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
30
Ver.G SM59R02G1 09/2015
00H
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
1
6.2.
1
Mode3
If Timer 1 M1 and M0 bits are set to 1, Timer 1
stops. If Timer 0 M1 and M0 bits are set to 1,
Timer 0 acts as two independent 8 bit timers /
counters.
Timer/counter control register (TCON)
Mnemonic: TCON
7
6
5
TF1
TR1
TF0
4
TR0
3
IE1
2
IT1
1
IE0
Address: 88h
0
Reset
IT0
00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR1: Timer 1 Run control bit. If cleared, Timer 1 stops.
TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR0: Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin INT1
is observed. Cleared when interrupt is processed.
IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin INT0
is observed. Cleared when interrupt is processed.
IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
6.3.
Peripheral Frequency control register(PFCON)
Mnemonic: PFCON
7
6
5
4
S0RELPS[1:0]
T1PS[1:0]: Timer1 Prescaler select
T1PS[1:0]
00
01
10
11
T0PS[1:0]: Timer0 Prescaler select
T0PS[1:0]
00
01
10
11
3
2
T1PS[1:0]
Address: D9h
1
0
Reset
T0PS[1:0]
00H
Prescaler
Fosc/12
Fosc
Fosc/96
reserved
Prescaler
Fosc/12
Fosc
Fosc/96
reserved
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
31
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
6.4.
Mode 0 (13-bit Counter/Timer)
÷12
OSC
00
01
÷96
10
C/T = 1
T1PS[1:0]
T1 pin
TR1
GATE1
ET1
C/T = 0
TL1
TH1
(5 Bits) (8 Bits)
EA
0
1
1
Control
If not higher priority
Interrupt Processing
AND
NOT
TF1
0
Jump
001BH
OR
INT1 pin
D0D1D2D3D4
D5D6D7
D0D1D2D3D4D5D6D7
TL1
6.5.
TF1
TH1
Mode 1 (16-bit Counter/Timer)
÷12
OSC
00
01
÷96
10
C/T = 1
T1PS[1:0]
T1 pin
TR1
GATE1
ET1
C/T = 0
TL1
TH1
(8 Bits) (8 Bits)
EA
0
1
1
Control
If not higher priority
Interrupt Processing
AND
NOT
TF1
0
Jump
001BH
OR
INT1 pin
D0D1D2D3D4D5D6D7
D0D1D2D3D4D5D6D7
TL1
TH1
TF1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
32
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
6.6.
Mode 2 (8-bit auto-reload Counter/Timer)
÷12
OSC
00
01
÷96
10
C/T = 1
T1PS[1:0]
T1 pin
TR1
GATE1
ET1
C/T = 0
TL1
(8 Bits)
Auto
Reload
OR
1
1
If not higher priority
Interrupt Processing
TH1
(8 Bits)
INT1 pin
6.7.
EA
0
Control
AND
NOT
TF1
0
Jump
001BH
Mode 3 (Timer 0 acts as two independent 8 bit Timers / Counters)
÷12
00
TH0
(8 Bits)
TF1
Interrupt
Request
(001BH)
TL0
(8 Bits)
TF0
Interrupt
Request
(000BH)
TR1
OSC
01
÷96
C/T = 0
10
C/T = 1
T0PS[1:0]
T1 pin
TR1
GATE1
Control
AND
NOT
OR
INT1 pin
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
33
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
7. Timer 2 and Capture/Compare Unit
Timer 2 is not only a 16-bit timer, also a 4-channel unit with compare, capture and reload functions.
the programmable counter array (PCA) in some other MCUs except pulse width modulation (PWM).
Mnemonic
Description
Direct
AUX2
T2CON
Auxiliary register2
Timer 2 control
Compare/Capture
Control
Compare/Capture
Enable register
Compare/Capture
Enable 2 register
Timer 2, low byte
Timer 2, high byte
Compare/Reload/
Capture register,
low byte
Compare/Reload/
Capture register,
high byte
Compare/Capture
register 1, low
byte
Compare/Capture
register 1, high
byte
Compare/Capture
register 2, low
byte
Compare/Capture
register 2, high
byte
Compare/Capture
register 3, low
byte
Compare/Capture
register 3, high
byte
CCCON
CCEN
CCEN2
TL2
TH2
CRCL
CRCH
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
It is very similar to
Bit 2
92h
C8h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Timer 2 and Capture Compare Unit
T2PS[2:0]
T2R[1:0]
C9h
CCI3
CCF2
C1h
-
COCAM1[2:0]
-
COCAM0[2:0]
00h
D1h
-
COCAM3[2:0]
-
COCAM2[2:0]
00h
CCI2
CCI1
CCI0
CCF3
-
Bit 1
Bit 0
P42CC[1:0]
T2I[1:0]
CCF1
CCF0
RESET
00h
00h
00H
CCh
CDh
TL2[7:0]
TH2[7:0]
00h
00h
CAh
CRCL[7:0]
00h
CBh
CRCH[7:0]
00h
C2h
CCL1[7:0]
00h
C3h
CCH1[7:0]
00h
C4h
CCL2[7:0]
00h
C5h
CCH2[7:0]
00h
C6h
CCL3[7:0]
00h
C7h
CCH3[7:0]
00h
Mnemonic: AUX2
7
6
-
5
-
4
-
3
-
2
-
Address: 92h
1
0
Reset
P42CC[1: 0]
00H
P42CC[1: 0] 00: Capture/Compare function on Port1.
01: Capture/Compare function on Port2
10: Capture/Compare function on Port4
11: reserved
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
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Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Mnemonic: T2CON
7
6
5
T2PS[2:0]
4
3
T2R[1:0]
2
-
1
Address: C8h
0
Reset
T2I[1:0]
00H
T2PS[2:0]: Prescaler select bit:
T2PS = 000 – timer 2 is clocked with the oscillator frequency.
T2PS = 001 – timer 2 is clocked with 1/2 of the oscillator frequency.
T2PS = 010 – timer 2 is clocked with 1/4 of the oscillator frequency.
T2PS = 011 – timer 2 is clocked with 1/6 of the oscillator frequency.
T2PS = 100 – timer 2 is clocked with 1/8 of the oscillator frequency.
T2PS = 101 – timer 2 is clocked with 1/12 of the oscillator frequency.
T2PS = 110 – timer 2 is clocked with 1/24 of the oscillator frequency.
T2R[1:0]: Timer 2 reload mode selection
T2R[1:0] = 0X – Reload disabled
T2R[1:0] = 10 – Mode 0
T2R[1:0] = 11 – Mode 1
T2I[1:0]: Timer 2 input selection
T2I[1:0] = 00 – Timer 2 stop
T2I[1:0] = 01 – Input frequency from prescaler (T2PS[2:0])
T2I[1:0] = 10 – Timer 2 is incremented by external signal at pin T2
T2I[1:0] = 11 – internal clock input is gated to the Timer 2
Mnemonic: CCCON
7
6
5
CCI3
CCI2
CCI1
4
CCI0
3
CCF3
2
CCF2
1
CCF1
Address: C9h
0
Reset
CCF0
00H
CCI3: Compare/Capture 3 interrupt control bit.
“1” is enable.
CCI2: Compare/Capture 2 interrupt control bit.
“1” is enable.
CCI1: Compare/Capture 1 interrupt control bit.
“1” is enable.
CCI0: Compare/Capture 0 interrupt control bit.
“1” is enable.
CCF3: Compare/Capture 3 flag set by hardware. This flag can be cleared by software.
CCF2: Compare/Capture 2 flag set by hardware. This flag can be cleared by software.
CCF1: Compare/Capture 1 flag set by hardware. This flag can be cleared by software.
CCF0: Compare/Capture 0 flag set by hardware. This flag can be cleared by software.
Compare/Capture interrupt share T2 interrupt vector.
Mnemonic: CCEN
7
6
5
4
COCAM1[2:0]
3
-
2
Address: C1h
1
0
Reset
COCAM0[2:0]
00H
COCAM1[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC1
101: Capture on falling edge at pin CC1
110: Capture on both rising and falling edge at pin CC1
111: Capture on write operation into register CC1
COCAM0[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
35
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
100: Capture on rising edge at pin CC0
101: Capture on falling edge at pin CC0
110: Capture on both rising and falling edge at pin CC0
111: Capture on write operation into register CC0
Mnemonic: CCEN2
7
6
5
4
COCAM3[2:0]
3
-
2
Address: D1h
1
0
Reset
COCAM2[2:0]
00H
COCAM3[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC3
101: Capture on falling edge at pin CC3
110: Capture on both rising and falling edge at pin CC3
111: Capture on write operation into register CC3
COCAM2[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC2
101: Capture on falling edge at pin CC2
110: Capture on both rising and falling edge at pin CC2
111: Capture on write operation into register CC2
7.1.
Timer 2 function
Timer 2 can operate as timer, event counter, or gated timer as explained later.
7.1.1.
Timer mode
In this mode Timer 2 can by incremented in various frequency that depending on the prescaler. The prescaler is selected
by bit T2PS[2:0] in register T2CON.
7.1.2.
Event counter mode
In this mode, the timer is incremented when external signal T2 change value from 1 to 0. The T2 input is sampled in every
cycle. Timer 2 is incremented in the cycle following the one in which the transition was detected.
7.1.3.
Gated timer mode
In this mode, the internal clock which incremented timer 2 is gated by external signal T2.
7.1.4.
Reload of Timer 2
Reload (16-bit reload from the crc register) can be executed in the following two modes:
Mode 0: Reload signal is generate by a Timer 2 overflows - auto reload
Mode 1: Reload signal is generate by a negative transition at the corresponding input pin T2EX.
7.2.
Compare function
In the four independent comparators, the value stored in any compare/capture register is compared with the contents of
the timer register. The compare modes 0 and 1 are selected by bit T2CM. In both compare modes, the results of
comparison arrives at Port 1 within the same machine cycle in which the internal compare signal is activated.
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ISSFD-M061
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Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
7.2.1.
Compare Mode 0
In mode 0, when the value in Timer 2 equals the value of the compare register, the output signal changes from low to high.
It goes back to a low level on timer overflow. In this mode, writing to the port will have no effect, because the input line
from the internal bus and the write-to-latch line are disconnected. The following figure illustrates the function of compare
mode 0.
Fig. 7-1: Compare mode 0 function
Contents of
Timer 2
CRC or CCx
Reload value
CCx Output
Timer 2 = CCx value
7.2.2.
Timer 2 overflow
Compare Mode 1
In compare mode 1, the transition of the output signal can be determined by software. A timer 2 overflow causes no
output change. In this mode, both transitions of a signal can be controlled. Fig. 7-2 shows a functional diagram of a
register/port configuration in compare Mode 1. In compare Mode 1, the value is written first to the “Shadow Register”,
when compare signal is active, this value is transferred to the output register.
Fig. 7-2: Compare mode 1 function
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ISSFD-M061
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Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Contents of
Timer 2
CRC or CCx
Reload value
CCx Output
Output register
Shadow register
CCx Output
Timer 2 = CCx value
7.3.
Capture function
Actual timer/counter contents can be saved into registers CCx or CRC upon an external event (mode 0) or a software
write operation (mode 1).
7.3.1.
Capture Mode 0
In mode 0, value capture of Timer 2 is executed when:
(a) Rising edge on input CC0-CC3
(b) Falling edge on input CC0-CC3
(c) Both rising and falling edge on input CC0-CC3
The contents of Timer 2 will be latched into the appropriate capture register.
7.3.2.
Capture Mode 1
In mode 1, value capture of timer 2 is caused by writing any value into the low-order byte of the dedicated capture register.
The value written to the capture register is irrelevant to this function. The contents of Timer 2 will be latched into the
appropriate capture register.
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ISSFD-M061
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Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
8. Serial interface 0
As the conventional UART, the communication speed can be selected by configuring the baud rate in SFRs.
These two serial buffers consists of two separate registers, a transmit buffer and a receive buffer. Writing data to the
SFR S0BUF sets this data in serial output buffer and starts the transmission. Reading from the S0BUF reads data from
the serial receive buffer. The serial port can simultaneously transmit and receive data. It can also buffer 1 byte at
receive, which prevents the receive data from being lost if the CPU reads the second byte before the transmission of the
first byte is completed.
Mnemonic
PCON
AUX
S0CON
S0RELL
S0RELH
S0BUF
PFCON
Description
Power control
Auxiliary
register
Serial Port 0
control register
Serial Port 0
reload register
low byte
Serial Port 0
reload register
high byte
Serial Port 0
data buffer
Peripheral
Frequency
control register
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Serial interface 0
-
Bit 3
Bit 2
Bit 1
Bit 0
RESET
87h
SMOD
-
-
STOP
IDLE
40h
91h
BRGS
-
-
P1UR
-
-
-
DPS
00H
98h
SM0
SM1
SM20
REN0
TB80
RB80
TI0
RI0
00h
AAh
S0REL
.7
S0REL
.6
S0REL
.5
S0REL
.4
S0REL
.3
S0REL
.2
S0REL
.1
S0REL
.0
00h
BAh
-
-
-
-
-
-
S0REL
.9
S0REL
.8
00h
99h
S0BUF[7:0]
D9H
Mnemonic: AUX
7
6
BRGS
-
S0RELPS[1:0]
5
-
4
P1UR
3
-
2
-
00h
T1PS[1:0]
1
-
T0PS[1:0]
Address: 91h
0
Reset
DPS
00H
BRGS: Baud rate generator.
BRGS = 0 - baud rate generator from Timer 1.
BRGS = 1 - baud rate generator by S0REL.
P1UR: P1UR = 0 – Serial interface function on P3.
P1UR = 1 – Serial interface function on P1.
Mnemonic: S0CON
7
6
5
SM0
SM1
SM20
4
REN0
3
TB80
2
RB80
1
TI0
Address: 98h
0
Reset
RI0
00h
SM0,SM1: Serial Port 0 mode selection.
SM0 SM1
Mode
0
0
0
0
1
1
1
0
2
1
1
3
The 4 modes in UART0, Mode 0 ~ 3, are explained later.
SM20: Enables multiprocessor communication feature
REN0: If set, enables serial reception. Cleared by software to disable reception.
th
TB80: The 9 transmitted data bit in modes 2 and 3. Set or cleared by the CPU
depending on the function it performs such as parity check, multiprocessor
communication etc.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
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Ver.G SM59R02G1 09/2015
00H
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
th
RB80: In modes 2 and 3, it is the 9 data bit received. In mode 1, if SM20 is 0, RB80
is the stop bit. In mode 0, this bit is not used. Must be cleared by software.
TI0: Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
RI0: Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
Mnemonic: PFCON
7
6
5
4
S0RELPS[1:0]
3
2
T1PS[1:0]
Address: D9H
1
0
Reset
T0PS[1:0]
00H
S0RELPS[1:0]: S0REL Prescaler select
S0RELPS[1:0] Prescaler
00
Fosc/64
01
Fosc/32
T1PS[1:0]: Timer 1 Prescaler select
T1PS[1:0]
Prescaler
00
Fosc/12
01
Fosc
10
Fosc/96
11
reserved
8.1.
Serial interface 0
The Serial Interface 0 can operate in the following 4 modes:
SM0
0
0
1
1
SM1
0
1
0
1
Mode
0
1
2
3
Description
Shift register
8-bit UART
9-bit UART
9-bit UART
Board Rate
Fosc/12
Variable
Fosc/32 or Fosc/64
Variable
Here Fosc is the crystal or oscillator frequency.
8.1.1.
Mode 0
Pin RXD0 serves as input and output. TXD0 outputs the shift clock. 8 bits are transmitted with LSB first. The baud
rate is fixed at 1/12 of the crystal frequency. Reception is initialized in Mode 0 by setting the flags in S0CON as follows:
RI0 = 0 and REN0 = 1. In the other modes, a start bit when REN0 = 1 starts receiving serial data.
Fig. 8-1: Transmit mode 0 for Serial 0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
40
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Fig. 8-2: Receive mode 0 for Serial 0
8.1.2.
Mode 1
Here Pin RXD0 serves as input, and TXD0 serves as serial output. No external shift clock is used, 10 bits are
transmitted: a start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes
the transmission, 8 data bits are available by reading S0BUF, and a stop bit sets the flag RB80 in the SFR S0CON. In
mode 1, either internal baud rate generator or timer 1 can be use to specify the desired baud rate.
Fig. 8-3: Transmit mode 1 for Serial 0
Fig. 8-4: Receive mode 1 for Serial 0
8.1.3.
Mode 2
This mode is similar to Mode 1, but with two differences. The baud rate is fixed at 1/32 (SMOD=1) or 1/64(SMOD=0) of
oscillator frequency, and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable Bit 9,
and a stop bit (1). Bit 9 can be used to control the parity of the serial interface: at transmission, bit TB80 in S0CON is
output as Bit 9, and at receive, Bit 9 affects RB80 in SFR S0CON.
8.1.4.
Mode 3
The only difference between Mode 2 and Mode 3 is that: in Mode 3, either internal baud rate generator or timer 1 can be
use to specify baud rate.
Fig. 8-5: Transmit modes 2 and 3 for Serial 0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
41
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Fig. 8-6: Receive modes 2 and 3 for Serial 0
8.2.
Multiprocessor communication of Serial Interface 0
The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface 0 can be used for multiprocessor communication. In
this case, the slave processors have bit SM20 in S0CON set to 1. When the master processor outputs slave’s address, it
sets the Bit 9 to 1, causing a serial port receive interrupt in all the slaves. The slave processors compare the received byte
with their network address. If matched, the addressed slave will clear SM20 and receive the rest of the message, while
other slaves will leave SM20 bit unaffected and ignore this message. After addressing the slave, the host will output the
rest of the message with the Bit 9 set to 0, so no serial port receive interrupt will be generated in unselected slaves.
8.3.
8.3.1.
Baud rate generator
Serial interface 0 modes 1 and 3
(a) When BRGS = 0 (in SFR AUX):
T1PS[1:0] = 00
Baud Rate =
2SMOD × FOSC
32 × 12 × ( 256 − TH1)
Baud Rate =
2SMOD × FOSC
32 × ( 256 − TH1)
Baud Rate =
2SMOD × FOSC
32 × 96 × ( 256 − TH1)
T1PS[1:0] = 01
T1PS[1:0] = 10
(b) When BRGS = 1 (in SFR AUX):
S0RELPS[1:0] = 00
2SMOD × FOSC
Baud Rate =
64 × ( 210 − S0REL )
S0RELPS[1:0] = 01
Baud Rate =
2SMOD × FOSC
32 × ( 210 − S0REL )
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
42
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
9. Watchdog timer
The Watch Dog Timer (WDT) is an 8-bit free-running counter that generate reset signal if the counter overflows. The WDT
is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software
dead loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is
different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically
clearing the WDT counter. User should check WDTF bit of WDTC register whenever un-predicted reset happened. After
an external reset the watchdog timer is disabled and all registers are set to zeros.
The watchdog timer has a free running on-chip RC oscillator (250KHz). The WDT will keep on running even after the
system clock has been turned off (for example, in sleep mode). During normal operation or sleep mode, a WDT time-out
(if enabled) will cause the MCU to reset. The WDT can be enabled or disabled any time during the normal mode. Please
refer the WDTE bit of WDTC register. The default WDT time-out period is approximately 16.38ms (WDTM [3:0] = 0100b).
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit3 ~ bit0
(WDTM [3:0]) of Watch Dog Timer Control Register (WDTC) should be set accordingly.
250KHz
2 WDTM
256
Watchdog reset time =
WDTCLK
WDTCLK =
WDTM [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 9.1 WDT time-out period
Divider
Time period @ 250KHz
(250 KHz RC oscillator in)
1
1.02ms
2
2.05ms
4
4.10ms
8
8.19ms
16
16.38ms (default)
32
32.77ms
64
65.54ms
128
131.07ms
256
262.14ms
512
524.29ms
1024
1.05s
2048
2.10s
4096
4.19s
8192
8.39s
16384
16.78s
32768
33.55s
When MCU is reset, the MCU will be read WDTEN control bit status. When WDTEN bit is set to 1, the watchdog function
will be disabled no matter what the WDTE bit status is. When WDTEN bit is clear to 0, the watchdog function will be
enabled if WDTE bit is set to 1 by program. User can to set WDTEN on the writer or ISP.
The program can enable the WDT function by programming 1 to the WDTE bit premise that WDTEN control bit is clear to
0. After WDTE set to 1, the 8 bit-counter starts to count with the selected time base source clock which set by WDTM [3:0].
It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when MCU been reset,
either hardware reset or WDT reset.
Once the watchdog is started it cannot be stopped. User can refreshed the watchdog timer to zero by writing 0x55 to
Watch Dog Timer refresh Key (WDTK) register. This will clear the content of the 8-bit counter and let the counter re-start
to count from the beginning. The watchdog timer must be refreshed regularly to prevent reset request signal from
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ISSFD-M061
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Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
becoming active.
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The WDTF flag can be
clear by software or external reset or power on reset.
Clear
WDTF = 0
1. Power on reset
2. External reset
3. Software write “0”
250KHz RC
oscillator
WDTF
Set WDTF = 1
CWDTR = 0
WDTCLK
1
TAKEY
(55, AA, 5A)
2WDTM
WDTM[3:0]
Enable/Disable
WDT
WDT time-out
reset
WDT
time-out
select
WDT
Counter
CWDTR = 1
Refresh
WDT Counter
WDT time-out
Interrupt
WDTC
Enable WDTC
write attribute
WDTK
(0x55)
WDTEN
Fig. 9-1: Watchdog timer block diagram
Mnemonic
TAKEY
WDTC
WDTK
RSTS
Description
Time Access Key
register
Watchdog timer
control register
Watchdog timer
refresh key
Reset Status Flag
register
Direct
Bit 7
Bit 6
Bit 5
Watchdog Timer
Bit 4
F7h
Bit 3
Bit 2
Bit 1
Bit 0
TAKEY [7:0]
B6h
-
CWDTR
WDTE
-
B7h
00H
WDTM [3:0]
04H
WDTK[7:0]
A1h
-
Mnemonic: TAKEY
7
6
5
-
-
4
3
TAKEY [7:0]
PDRF
2
WDTF
1
RESET
00H
SWRF
LVRF
PORF
00H
Address: F7h
0
Reset
00H
Watchdog timer control register (WDTC) is read-only by default; software must write three specific
values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Mnemonic: WDTC
7
6
CWDTR
5
WDTE
4
-
3
2
1
WDTM [3:0]
Address: B6h
0
Reset
04H
CWDTR: 0: watchdog reset
1: watchdog interrupt
WDTE: Control bit used to enable Watchdog timer.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
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Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT
can be disabled / enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if WDTEN is "1". That is, if the WDTEN bit is "1", WDT is
always disabled no matter what the WDTE bit status is. The WDTE bit can be read and
written.
WDTM [3:0]: WDT clock source divider bit. Please see table 7.8.1 to reference the WDT time-out
period.
Mnemonic: WDTK
7
6
Address: B7h
4
3
2
1
0
Reset
WDTK[7:0]
00h
WDTK: Watchdog timer refresh key.
A programmer must write 0x55 into WDTK register, and then the watchdog
timer will be cleared to zero.
5
For example, if enable WDT and select time-out reset period is 327.68ms.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
; enable WDTC write attribute.
MOV WDTC, #28h
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT
; function.
.
.
MOV WDTK, #55h
; Clear WDT timer to 0.
Mnemonic: RSTS
Address: B6h
7
6
5
4
3
2
1
0
Reset
PDRF WDTF SWRF LVRF
PORF
00H
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware.
This flag clear by software or external reset or power on reset.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
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Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
10. Interrupt
The SM59R02G1 provides 7 interrupt sources with four priority levels. Each source has its own request flag(s) located in
a special function register. Each interrupt requested by the corresponding flag could individually be enabled or disabled
by the enable bits in SFR’s IEN0, IEN1 and IEN2.
When the interrupt occurs, the engine will vector to the predetermined address as shown in Table 10.1. Once interrupt
service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return
from instruction RETI. When an RETI is performed, the processor will return to the instruction that would have been next
when interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of
whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, and then samples are
polled by hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then interrupt request flag is
set. On the next instruction cycle the interrupt will be acknowledged by hardware forcing an LCALL to appropriate vector
address.
Interrupt response will require a varying amount of time depending on the state of microcontroller when the interrupt
occurs. If microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be
invoked. In other cases, the response time depends on current instruction. The fastest possible response to an interrupt is
7 machine cycles. This includes one machine cycle for detecting the interrupt and six cycles for perform the LCALL.
Table 10-1: Interrupt vectors
Interrupt Vector
Interrupt Request Flags
Address
IE0 – External interrupt 0
0003h
Interrupt Number
*(use Keil C Tool)
0
TF0 – Timer 0 interrupt
000Bh
1
IE1 – External interrupt 1
0013h
2
TF1 – Timer 1 interrupt
001Bh
3
RI0/TI0 – Serial channel 0 interrupt
0023h
4
TF2/EXF2 – Timer 2 interrupt
002Bh
5
WDT interrupt
008Bh
17
*See Keil C about C51 User’s Guide about Interrupt Function description
Mnemonic
IEN0
IEN1
IRCON
IEN2
IRCON2
IP0
IP1
Description
Interrupt Enable
0 register
Interrupt Enable
1 register
Interrupt request
register
Interrupt Enable
2 register
Interrupt request
register 2
Interrupt priority
level 0
Interrupt priority
level 1
Direct
Bit 7
Bit 6
Bit 5
Interrupt
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
A8h
EA
-
ET2
ES0
ET1
EX1
ET0
EX0
00h
B8h
EXEN
2
-
-
-
-
-
-
-
00h
C0H
EXF2
TF2
-
-
-
-
-
-
00h
9AH
-
-
-
-
-
-
-
00h
97H
-
-
-
-
-
-
-
00h
A9h
-
-
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
00h
B9h
-
-
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
00h
IEWD
T
WDTI
F
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
46
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Interrupt Enable 0 register(IEN0)
Mnemonic: IEN0
7
6
EA
-
5
ET2
4
ES0
3
ET1
2
EX1
1
ET0
Address: A8h
0
Reset
EX0
00h
EA: EA=0 – Disable all interrupt.
EA=1 – Enable all interrupt.
ET2: ET2=0 – Disable Timer 2 overflow or external reload interrupt.
ET2=1 – Enable Timer 2 overflow or external reload interrupt.
ES0: ES0=0 – Disable Serial channel 0 interrupt.
ES0=1 – Enable Serial channel 0 interrupt.
ET1: ET1=0 – Disable Timer 1 overflow interrupt.
ET1=1 – Enable Timer 1 overflow interrupt.
EX1: EX1=0 – Disable external interrupt 1.
EX1=1 – Enable external interrupt 1.
ET0: ET0=0 – Disable Timer 0 overflow interrupt.
ET0=1 – Enable Timer 0 overflow interrupt.
EX0: EX0=0 – Disable external interrupt 0.
EX0=1 – Enable external interrupt 0.
Interrupt Enable 1 register(IEN1)
Mnemonic: IEN1
7
6
EXEN2
-
5
-
4
-
3
-
1
-
Address: B8h
0
Reset
00h
1
IEWDT
Address: 9Ah
0
Reset
00h
2
-
EXEN2: Timer 2 reload interrupt enable.
EXEN2 = 0 – Disable Timer 2 external reload interrupt.
EXEN2 = 1 – Enable Timer 2 external reload interrupt.
Interrupt Enable 2 register(IEN2)
Mnemonic: IEN2
7
6
-
5
-
4
-
3
-
2
-
IEWDT: WDT interrupt enable..
IEWDT = 0 – Disable WDT interrupt.
IEWDT = 1 – Enable WDT interrupt.
Interrupt request register(IRCON)
Mnemonic: IRCON
7
6
5
EXF2
TF2
-
4
-
3
-
2
-
1
-
Address: C0h
0
Reset
00H
EXF2: Timer 2 external reloads flag. Must be cleared by software.
TF2: Timer 2 overflows flag. Must be cleared by software.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
47
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Interrupt request register 2(IRCON2)
Mnemonic: IRCON2
7
6
5
-
4
-
3
-
2
-
1
WDTIF
Address: 97h
0
Reset
00H
WDTIF: WDT interrupt flag.
Priority level structure
All interrupt sources are combined in groups:
Table 10-2: Priority level groups
Groups
External interrupt 0
Timer 0 interrupt
External interrupt 1
WDT interrupt
Timer 1 interrupt
Serial channel 0 interrupt
Timer 2 interrupt
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit
in the special function register IP0 and one in IP1. If requests of the same priority level will be received simultaneously, an
internal polling sequence determines which request is serviced first.
Mnemonic: IP0
7
6
-
5
IP0.5
4
IP0.4
3
IP0.3
2
IP0.2
1
IP0.1
Address: A9h
0
Reset
IP0.0
00h
Mnemonic: IP1
7
6
-
5
IP1.5
4
IP1.4
3
IP1.3
2
IP1.2
1
IP1.1
Address: B9h
0
Reset
IP1.0
00h
Table 10-3: Priority levels
IP1.x
IP0.x
Priority Level
0
0
1
1
Bit
IP1.0, IP0.0
IP1.1, IP0.1
IP1.2, IP0.2
IP1.3, IP0.3
IP1.4, IP0.4
IP1.5, IP0.5
0
1
0
1
Level0 (lowest)
Level1
Level2
Level3 (highest)
Table 10-4: Groups of priority
Group
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
Timer 2 interrupt
WDT interrupt
-
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
48
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Table 10-5: Polling sequence
Interrupt source
Timer 0 interrupt
WDT interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
Polling sequence
External interrupt 0
Sequence
Timer 2 interrupt
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
49
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
11. Power Management Unit
Power management unit serves two power management modes, IDLE and STOP, for the users to do power saving
function.
Mnemonic: PCON
7
6
SMOD
-
5
-
4
-
3
-
2
-
1
STOP
Address: 87h
0
Reset
IDLE
40h
STOP: Stop mode control bit. Setting this bit turning on the Stop Mode.
Stop bit is always read as 0
IDLE: Idle mode control bit. Setting this bit turning on the Idle Mode.
Idle bit is always read as 0
11.1. Idle mode
Setting the IDLE bit of PCON register invokes the IDLE mode. The IDLE mode leaves internal clocks and peripherals
running. Power consumption drops because the CPU is not active. The CPU can exit the IDLE state with any interrupts or
a reset.
11.2. Stop mode
Setting the STOP bit of PCON register invokes the STOP mode. All internal clocking in this mode is turn off. The CPU will
exit this state from a no-clocked interrupt (external INT0/1) or WDT Interrupt or a reset (WDT, LVR) condition. Internally
generated interrupts (timer, serial port ...) have no effect on stop mode since they require clocking activity.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
50
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
12. Low Voltage Control
Mnemonic: LVC
7
6
5
LVREN
4
-
3
-
2
-
1
-
Address: E6h
0
Reset
00H
LVREN: External low voltage reset function enable bit.
LVREN = 0 : disable external low voltage reset function.
LVREN = 1 : enable external low voltage reset function.
LVR-level：
Symbol
VLVR
Parameter
Low Voltage Reset Voltage Level
Min
1.9
Typ
2.1
Max
2.3
Units
V
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
51
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
13. In-System Programming (Internal ISP)
The SM59R02G1 can generate flash control signal by internal hardware circuit. Users utilize flash control register, flash
address register and flash data register to perform the ISP function without removing the SM59R02G1 from the system.
The SM59R02G1 provides internal flash control signals which can do flash program/chip erase/page erase/protect
functions. User need to design and use any kind of interface which SM59R02G1 can input data. User then utilize ISP
service program to perform the flash program/chip erase/page erase/protect functions.
13.1. ISP service program
The ISP service program is a user developed firmware program which resides in the ISP service program space.
After user developed the ISP service program, user then determine the size of the ISP service program. User need
to program the ISP service program in the SM59R02G1 for the ISP purpose.
The ISP service programs were developed by user so that it should includes any features which relates to the flash
memory programming function as well as communication protocol between SM59R02G1 and host device which
output data to the SM59R02G1. For example, if user utilize UART interface to receive/transmit data between
SM59R02G1 and host device, the ISP service program should include baud rate, checksum or parity check or any
error-checking mechanism to avoid data transmission error.
The ISP service program can be initiated under SM59R02G1 active or idle mode. It can not be initiated under power
down mode.
13.2. Lock Bit (N)
The Lock Bit N has two functions: one is for service program size configuration and the other is to lock the ISP
service program space from flash erase function.
The ISP service program space address range $1C00 to $1FFF. It can be divided as blocks of N*256 byte. (N=0 to
4). When N=0 means no ISP function, all of 8K byte flash memory can be used as program memory. When N=1
means ISP service program occupies 256 byte while the rest of 7.75K byte flash memory can be used as program
memory. The maximum ISP service program allowed is 1K byte when N=4. Under such configuration, the usable
program memory space is 7K byte.
After N determined, SM59R02G1 will reserve the ISP service program space downward from the top of the program
address $1FFF. The start address of the ISP service program located at $1x00 while x is depending on the lock bit N.
As shown in Table 13-1.
The lock bit N function is different from the flash protect function. The flash erase function can erase all of the flash
memory except for the locked ISP service program space. If the flash not has been protected, the content of ISP
service program still can be read. If the flash has been protected, the overall content of flash program memory space
including ISP service program space can not be read.
Table 13.1 ISP code area.
N
ISP service program address
0
No ISP service program
1
256 bytes ($1F00h ~ $1FFFh)
2
512 bytes ($1E00h ~ $1FFFh)
3
768 bytes ($1D00h ~ $1FFFh)
4
1.0 K bytes ($1C00h ~ $1FFFh)
ISP service program configurable in N*256 byte (N= 0 ~ 4)
13.3. Program the ISP Service Program
After Lock Bit N is set and ISP service program been programmed, the ISP service program memory will be
protected (locked) automatically. The lock bit N has its own program/erase timing. It is different from the flash
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
52
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
memory program/erase timing so the locked ISP service program can not be erased by flash erase function. If user
needs to erase the locked ISP service program, he can do it by writer only. User can not change ISP service program
when SM59R02G1 was in system.
13.4. Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and
execute it. There are four ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start
address of ISP service program. The hardware reset includes Internal (power on reset) and external
pad reset.
(2) Execute jump instruction can load the start address of the ISP service program to PC.
(3) Enters ISP service program by hardware setting. User can force SM59R02G1 enter ISP service
program by setting P2.6, P2.7 “active low” or P4.3 “ active low” during hardware reset period. The
hardware reset includes Internal (power on reset) and external pad reset. In application system
design, user should take care of the setting of P2.6, P2.7 or P4.3 at reset period to prevent
SM59R02G1 from entering ISP service program.
(4) Enter’s ISP service program by hardware setting, the port3.0 will be detected the two clock signals
during hardware reset period. The hardware reset includes Internal (power on reset) and external
pad reset. And detect 2 clock signals after hardware reset.
During hardware reset period, the hardware will detect the status of P2.6/P2.7/P4.3/P3.0. If they meet one of above
conditions, chip will switch to ISP mode automatically. After ISP service program executed, user need to reset the
SM59R02G1, either by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware program.
There are 8 kinds of entry mechanisms for user different applications. This entry method will select on the writer or
ISP.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
First Address Blank. i.e. $0000 = 0xFF. And triggered by Internal reset signal.
First Address Blank. i.e. $0000 = 0xFF. And triggered by PAD reset signal.
P2.6 = 0 & P2.7 = 0. And triggered by Internal reset signal.
P2.6 = 0 & P2.7 = 0. And triggered by PAD reset signal.
P4.3 = 0. And triggered by Internal reset signal.
P4.3 = 0. And triggered by PAD reset signal.
P3.0 input 2 clocks. And triggered by Internal reset signal.
P3.0 input 2 clocks. And triggered by PAD reset signal.
13.5. ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC
Mnemonic
TAKEY
IFCON
ISPFAH
ISPFAL
ISPFD
ISPFC
Description
Time Access Key
register
Interface Control
register
ISP Flash
Address - High
register
ISP Flash
Address - Low
register
ISP Flash Data
register
ISP Flash Control
register
Direct
Bit 7
Bit 6
Bit 5
ISP function
F7h
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
TAKEY [7:0]
8Fh
ITS
CDPR
-
E1h
-
-
-
-
00H
ALEC[1:0]
-
ISPE
ISPFAH [4:0]
00H
FFH
E2h
ISPFAL [7:0]
FFH
E3h
ISPFD [7:0]
FFH
E4h
EMF1
EMF2
EMF3
EMF4
-
ISPF.2
ISPF.1
ISPF.0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
53
Ver.G SM59R02G1 09/2015
00H
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Mnemonic: TAKEY
7
6
5
4
3
TAKEY [7:0]
2
Address: F7H
0
Reset
00H
1
ISP enable bit (ISPE) is read-only by default, software must write three specific values 55h, AAh and 5Ah
sequentially to the TAKEY register to enable the ISPE bit write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Mnemonic: IFCON
7
6
ITS
CDPR
5
-
4
-
3
2
ALEC[1:0]
Address: 8FH
0
Reset
ISPE
00H
1
-
The bit 0 (ISPE) of IFCON is ISP enable bit. User can enable overall SM59R02G1 ISP function by setting ISPE
bit to 1, to disable overall ISP function by set ISPE to 0. The function of ISPE behaves like a security key. User
can disable overall ISP function to prevent software program be erased accidentally. ISP registers ISPFAH,
ISPFAL, ISPFD and ISPFC are read-only by default. Software must be set ISPE bit to 1 to enable these 4
registers write attribute.
Mnemonic: ISPFAH
7
6
-
5
-
Address: E1H
4
3
2
1
0
Reset
ISPFAH4 ISPFAH3 ISPFAH2 ISPFAH1 ISPFAH0
FFH
ISPFAH [4:0]: Flash address-high for ISP function
Mnemonic: ISPFAL
7
6
ISPFAL7 ISPFAL6
5
ISPFAL5
4
ISPFAL4
3
ISPFAL3
2
ISPFAL2
1
ISPFAL1
Address: E2H
0
Reset
ISPFAL0
FFH
ISPFAL [7:0]: Flash address-Low for ISP function
The ISPFAH & ISPFAL provide the 13-bit flash memory address for ISP function. The flash memory address
should not include the ISP service program space address. If the flash memory address indicated by ISPFAH
& ISPFAL registers overlay with the ISP service program space address, the flash program/page erase of ISP
function executed thereafter will have no effect.
Mnemonic: ISPFD
7
6
ISPFD7
ISPFD6
5
ISPFD5
4
ISPFD4
3
ISPFD3
2
ISPFD2
1
ISPFD1
Address: E3H
0
Reset
ISPFD0
FFH
ISPFD [7:0]: Flash data for ISP function.
The ISPFD provide the 8-bit data register for ISP function.
Mnemonic: ISPFC
7
6
5
EMF1
EMF2
EMF3
4
EMF4
3
-
2
ISPF[2]
1
ISPF[1]
Address: E4H
0
Reset
ISPF[0]
00H
EMF1: Entry mechanism (1) flag, clear by reset. (Read only)
EMF2: Entry mechanism (2) flag, clear by reset. (Read only)
EMF3: Entry mechanism (3) flag, clear by reset. (Read only)
EMF4: Entry mechanism (4) flag, clear by reset. (Read only)
ISPF [2:0]: ISP function select bit.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
54
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
ISPF[2:0]
ISP function
000
Byte program
001
Chip protect
010
Page erase
011
Chip erase
100
Write option
101
Read option
110
Erase option
111
Finish Flag
One page of flash memory is 256 byte
The Option function can access the Internal reset time select(description in section
1.4.1)、clock source select(description in section 1.5)、P4[4:7] pins function
select(description in section 5)、WDTEN control bit(description in section 9)、or ISP
entry mechanisms select(description in section 13).
When chip protected or no ISP service, option can only read.
The choice ISP function will start to execute once the software write data to ISPFC register.
To perform byte program/page erases ISP function, user need to specify flash address at first. When
performing page erase function, SM59R02G1 will erase entire page which flash address indicated by ISPFAH
& ISPFAL registers located within the page.
e.g. flash address: $XYMN
page erase function will erase from $XY00 to $XYFF
To perform the chip erase ISP function, SM59R02G1 will erase all the flash program memory except the ISP
service program space. To perform chip protect ISP function, the SM59R02G1 flash memory content will be
read #00H.
e.g. ISP service program to do the byte program - to program #22H to the address $1005H
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
MOV IFCON, #01H
MOV ISPFAH, #10H
MOV ISPFAL, #05H
MOV ISPFD, #22H
MOV ISPFC, #00H
; enable ISPE write attribute
; enable SM59R02G1 ISP function
; set flash address-high, 10H
; set flash address-low, 05H
; set flash data to be programmed, data = 22H
; start to program #22H to the flash address $1005H
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
55
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit.
Remarks
TA
Operating temperature
-40
25
85
℃
Ambient temperature under bias
VDD
Supply voltage
2.7
5.5
V
DC Characteristics
TA = -40℃ to 85℃, VCC = 5.0V
Symbol
Parameter
Valid
VIL1
Input Low-voltage
Port 0,1,2,3,4,5
VIL2
Input Low-voltage
RES, XTAL1
VIH1
Input High-voltage
Port 0,1,2,3,4,5
VIH2
Input High-voltage
RES, XTAL1
VOL
Output Low-voltage
Port 0,1,2,3,4,5
Output High-voltage
(1) Port 0,1,2,3,4,5
using Strong Pull-up
VOH1
VOH2
IIL
ITL
ILI
RRST
CIO
ICC
Notes：
Output High-voltage
(2)
using Weak Pull-up
Logic 0 Input Current
Logical Transition
Current
Input Leakage Current
Reset Pull-down
Resistor
Pin Capacitance
Port 0,1,2,3,4,5
Min
Max
Units
-0.5
0.8
V
0
0.8
V
2.0
VCC + 0.5
V
70%Vcc VCC + 0.5
V
0.4
Conditions
Vcc=5V
V
IOL=4.9mA
90% VCC
V
IOH= -4.6mA
2.4
V
IOH= -250uA
75% VCC
V
IOH= -162uA
90% VCC
V
IOH= -73uA
Port 0,1,2,3,4,5
-75
uA
Vin= 0.45V
Port 0,1,2,3,4,5
-650
uA
Vin= 2.0V
Port 0,1,2,3,4,5
±10
uA
0.45V<Vin<Vcc
300
kΩ
10
pF
12
mA
11
mA
5
uA
RES
Power Supply Current VDD
50
Vcc=5V
Freq= 1MHz, Ta= 25℃
Active mode, 12MHz VCC =5V
25 ℃
Idle mode, 12MHz VCC =5V
25 ℃
Power down mode VCC =5V
25 ℃
1. Port in Push-Pull Output Mode
2. Port in Quasi-Bidirectional Mode
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
56
Ver.G SM59R02G1 09/2015
SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
TA = -40℃ to 85℃, VCC = 3.0V
Symbol
Parameter
Valid
VIL1
Input Low-voltage
Port 0,1,2,3,4,5
VIL2
Input Low-voltage
RES, XTAL1
VIH1
Input High-voltage
Port 0,1,2,3,4,5
VIH2
Input High-voltage
RES, XTAL1
VOL
Output Low-voltage
Port 0,1,2,3,4,5
Output High-voltage
(1) Port 0,1,2,3,4,5
using Strong Pull-up
VOH1
VOH2
IIL
ITL
ILI
RRST
CIO
ICC
Notes：
Output High-voltage
(2)
using Weak Pull-up
Logic 0 Input Current
Logical Transition
Current
Input Leakage Current
Reset Pull-down
Resistor
Pin Capacitance
Min
Max
Units
-0.5
0.8
V
0
0.8
V
2.0
VCC + 0.5
V
70%Vcc VCC + 0.5
V
0.4
Conditions
Vcc=3.0V
V
IOL=3.2mA
90% VCC
V
IOH= -2.3mA
2.4
V
IOH= -77uA
90% VCC
V
IOH= -33uA
Vcc=3.0V
Port 0,1,2,3,4,5
Port 0,1,2,3,4,5
-75
uA
Vin= 0.45V
Port 0,1,2,3,4,5
-650
uA
Vin=1.5V
Port 0,1,2,3,4,5
±10
uA
0.45V<Vin<Vcc
300
kΩ
10
pF
11
mA
10
mA
4
uA
RES
Power Supply Current VDD
50
Freq= 1MHz, Ta= 25℃
Active mode ,12MHz VCC =
3.0 V 25 ℃
Idle mode, 12MHz VCC =3.0V
25 ℃
Power down mode VCC =3.0V
25 ℃
1. Port in Push-Pull Output Mode
2. Port in Quasi-Bidirectional Mode
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
57
Ver.G SM59R02G1 09/2015