SM894051 with SM39R4051 APN SM894051 SM39R4051 SM39R4051 SM39R4051 SM894051 SM894051 SM39R4051 Feature (V) IDD(Power Down) System clock(MHz) MCU SM39R4051 3.0~5.5 20uA at VDD=5.5V 5uA at VDD=3.6V 2.7~5.5 12T up to 25 4K 128 GPIO 15 Interrupt 5 16-bit Dual DPTR Timer UART EEPROM ICP/ISP/IAP IIC interface 1) SM894051 RC Program Flash ( byte) RAM( byte) WDT ( (max 262.14 msec) 3.5uA at VDD=5.0V 1T up to 20 (1T~8T can change on fly) ( 24MHz) 4K 256 18 (When Use internal RC and Internal Reset) 7 (max 33.5 sec) 2 1 2 1 ( ) Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 1 Ver. A 2010/07 SM894051 with SM39R4051 APN SM894051 SM39R4051 SyncMOS SM39R4051ihhNP yymmv (20L PDIP Top View) RESET 1 20 VDD RXD/P3.0 2 19 P1.7 TXD/P3.1 3 18 P1.6 XTAL2 4 17 P1.5 XTAL1 5 16 P1.4 INT0/P3.2 6 15 P1.3 INT1/P3.3 7 14 P1.2 T0/P3.4 8 13 P1.1/AIN1 T1/P3.5 9 12 P1.0/AIN0 VSS 10 11 P3.7 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 2 Ver. A 2010/07 SM894051 with SM39R4051 APN SM894051( Hex\Bin F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 ) X000 X010 X011 X100 X101 X110 X111 Bin/Hex FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 B ACC PSW SCONF IP P3 IE SCON WDTC SBUF LEDENP1 P1 TCON SM39R4051( Hex\Bin F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 X001 TMOD SP TL0 DPL TL1 DPH LEDENP3 TH0 WDTKEY TH1 PCON 3) X000 X001 X010 X011 X100 X101 IICS IICCTL IICA1 IICA2 IICRWD IICEBT X110 B P4 ACC X111 TAKEY ISPFAH ISPFAL ISPFD ISPFC P3M0 P3M1 P4M0 P4M1 P1M0 P1M1 PSW LVC SWRES WDTC WDTK IRCON IEN1 IP1 S0RELH P3 IEN0 IP0 S0CON S0BUF P1 TCON AUX TMOD SP S0RELL TL0 DPL P1WE P31WE REV REV REV TL1 DPH TH0 DPL1 TH1 DPH1 CKCON IFCON PCON Bin/Hex FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 3 Ver. A 2010/07 SM894051 with SM39R4051 APN SM894051 1. Addr. SM39R4051 Addr. WDTKEY 97H TAKEY F7H WDTC 9FH WDTC B6H WDTK B7H 1. WDTC[2:0] 8 2. 3. 250KHz Period = 2.048 m sec ~ 262.14 m sec 2. 4. WDTKEY WDTC[3:0] 1~32768 16 WDTC Period = 1.02 m sec ~ 33.55 sec 5. KEY(TAKEY) WDTC WDTK 5 2 8 WDT 0x55 4 IE A8H IEN0 A8H IP B8H IEN1 B8H IP A9H IP1 B9H Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 4 Ver. A 2010/07 SM894051 with SM39R4051 APN 1. SM39R4051 SM894051 SM39R4051 16 1.02 m sec ~ 33.55 sec 2. SM39R4051 SM894051 8 2.048 m sec~262.14 m sec W77E58 SM39R4051 SM894051 WDTC (0xB6H) WDTK (0xB7H) WDTC (0x9FH) WDTC (0x9FH) WDTKEY (0x97H) 0x1EH 0xE1H WDTC 0xE1H 0x1EH WDTC TAKEY (0xF7H) 0x55H 0xAAH 0x5AH 3. SM39R4051 SM894051 a. SM39R4051 Mnemonic: WDTC 7 6 5 WDTF WDTE 4 - 3 2 1 WDTM [3:0] Address: B6h 0 Reset 04H WDTF: Watchdog timer reset flag. When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag clear by software or external reset or power on reset. WDTE: Control bit used to enable Watchdog timer. The WDTE bit can be used only if WDTEN is “0”. If the WDTEN bit is “0”, then WDT can be disabled / enabled by the WDTE bit. 0: Disable WDT. 1: Enable WDT. The WDTE bit is not used if WDTEN is “1”. That is, if the WDTEN bit is “1”, WDT is always disabled no matter what the WDTE bit status is. The WDTE bit can be read and written. WDTM [3:0]: WDT clock source divider bit. Please see below table to reference the WDT time-out period. Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 5 Ver. A 2010/07 SM894051 with SM39R4051 APN Mnemonic: WDTK 7 6 5 4 3 WDTK[7:0] 2 1 Address: B7h 0 Reset 00h WDTK: Watchdog timer refresh key. A programmer must write 0x55 into WDTK register, and then the watchdog timer will be cleared to zero. Mnemonic: TAKEY 7 6 5 4 3 TAKEY [7:0] ISP 2 Address: F7h 0 Reset 00H 1 ICP MOV TAKEY, #55h MOV TAKEY, #0AAh MOV TAKEY, #5Ah ; MOV WDTC, #28h ; WDTC . 262.14 . . . MOV WDTK, #55h WDTM [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ; Divider (250 KHz RC oscillator in) 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 . Time period @ 250KHz 1.02ms 2.05ms 4.10ms 8.19ms 16.38ms (default) 32.77ms 65.54ms 131.07ms 262.14ms 524.29ms 1.05s 2.10s 4.19s 8.39s 16.78s 33.55s Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 6 Ver. A 2010/07 SM894051 with SM39R4051 APN b. SM894051 Mnemonic: WDTKEY 7 6 WDT KEY7 WDT KEY6 5 4 3 2 1 WDT KEY5 WDT KEY4 WDT KEY3 WDT KEY2 WDT KEY1 Address: 97h Reset WDT KEY0 00H 0 By default, the WDTC is read only. User needs to write values 1EH, 0E1H sequentially to the WDTKEY (97H) register to enable the WDTC write attribute, which is MOV WDTKEY, # 01EH MOV WDTKEY, # 0E1H When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY (97H) register to disable the WDTC write attribute, That is MOV WDTKEY, # 0E1H MOV WDTKEY, # 01EH Mnemonic: WDTC 7 6 5 WDTE CLEAR 4 3 2 PS2 1 PS1 Address: 9Fh 0 Reset PS0 04H WDTE: Watch Dog Timer enable bit CLEAR: Watch Dog Timer reset bit If CLEAR bit set to1, Watch Dog Timer will be reset. User don’t reset value to 0 PS[2:0]: Overflow period select bits PS [2:0] 000 001 010 011 100 101 110 111 Overflow Period (ms) 2.048 4.096 8.192 16.384 32.768 65.536 131.072 262.14 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 7 Ver. A 2010/07 SM894051 with SM39R4051 APN 1. SM39R4051 SM894051 SM39R4051 7 SM894051 4 SM894051 IE0 – External interrupt 0 TF0 – Timer 0 interrupt IE1 – External interrupt 1 5 2 SM39R4051 0x03H 0x0BH 0x13H SM894051 0x03H 0x0BH 0x13H 0x1BH 0x23H 0x63H 0x6BH 0x1BH 0x23H TF1 – Timer 1 interrupt RI0/TI0 – Serial channel 0 interrupt LVIIF – Low Voltage Interrupt IICIF – IIC interrupt 2. SM39R4051 SM894051 SM39R4051 0 1 IEN0 (0xA8H) IEN1 (0xB8H) IP0 (0xA9H) IP1 (0xB9H) 0 1 3. SM39R4051 SM894051 IE (0xA8H) IP (0xB8H) SM894051 a. SM39R4051 Mnemonic: IEN0 7 6 EA - 5 - 4 ES0 3 ET1 2 EX1 1 ET0 Address: A8h 0 Reset EX0 00h EA: EA=0 – Disable all interrupt. EA=1 – Enable all interrupt. ES0: ES0=0 – Disable Serial channel 0 interrupt. ES0=1 – Enable Serial channel 0 interrupt. ET1: ET1=0 – Disable Timer 1 overflow interrupt. ET1=1 – Enable Timer 1 overflow interrupt. EX1: EX1=0 – Disable external interrupt 1. EX1=1 – Enable external interrupt 1. ET0: ET0=0 – Disable Timer 0 overflow interrupt. ET0=1 – Enable Timer 0 overflow interrupt. EX0: EX0=0 – Disable external interrupt 0. Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 8 Ver. A 2010/07 SM894051 with SM39R4051 APN EX0=1 – Enable external interrupt 0. Mnemonic: IEN1 7 6 EXEN2 5 IEIIC 4 IELVI 3 - 2 - 1 - Address: B8h 0 Reset 00h EXEN2: Timer 2 reload interrupt enable. EXEN2 = 0 – Disable Timer 2 external reload interrupt. EXEN2 = 1 – Enable Timer 2 external reload interrupt. IEIIC: IIC interrupt enable. IEIICS = 0 – Disable IIC interrupt. IEIICS = 1 – Enable IIC interrupt. IELVI: LVI interrupt enable. IELVI = 0 – Disable LVI interrupt. IELVI = 1 – Enable LVI interrupt. Mnemonic: IP0 7 6 - 5 IP0.5 4 IP0.4 3 IP0.3 2 IP0.2 1 IP0.1 Address: A9h 0 Reset IP0.0 00h Mnemonic: IP1 7 6 - 5 IP1.5 4 IP1.4 3 IP1.3 2 IP1.2 1 IP1.1 Address: B9h 0 Reset IP1.0 00h SM39R4051 Priority levels IP1.x IP0.x Priority Level 0 0 1 1 0 1 0 1 Level0 (lowest) Level1 Level2 Level3 (highest) SM39R4051 Groups of priority Bit IP1.0, IP0.0 IP1.1, IP0.1 IP1.2, IP0.2 IP1.3, IP0.3 IP1.4, IP0.4 IP1.5, IP0.5 Group External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt LVI interrupt IIC interrupt Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 9 Ver. A 2010/07 SM894051 with SM39R4051 APN SM39R4051 Polling sequence Interrupt source Sequence Polling sequence External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt LVI interrupt IIC interrupt b. SM894051 Mnemonic: IE 7 6 EA - 5 - 4 ES0 3 ET1 2 EX1 1 ET0 Address: A8h 0 Reset EX0 00h 2 PX1 1 PT0 Address: B8h 0 Reset PX0 00h EA: EA=0 – Disable all interrupt. EA=1 – Enable all interrupt. ES0: ES0=0 – Disable Serial channel 0 interrupt. ES0=1 – Enable Serial channel 0 interrupt. ET1: ET1=0 – Disable Timer 1 overflow interrupt. ET1=1 – Enable Timer 1 overflow interrupt. EX1: EX1=0 – Disable external interrupt 1. EX1=1 – Enable external interrupt 1. ET0: ET0=0 – Disable Timer 0 overflow interrupt. ET0=1 – Enable Timer 0 overflow interrupt. EX0: EX0=0 – Disable external interrupt 0. EX0=1 – Enable external interrupt 0. Mnemonic: IP 7 6 - 5 - 4 PS0 3 PT1 PS0: This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level. PT1: This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level. PX1: This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level. PT0: This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level. PX0: This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level. Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 10 Ver. A 2010/07 SM894051 with SM39R4051 APN SM894051 Priority structure of interrupts Source Flag Priority Level External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Port IE0 TF0 IE1 TF1 RI+TI 1(Highest) 2 3 4 5 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 11 Ver. A 2010/07 SM894051 with SM39R4051 APN SM39R4051 1. GPIO Mnemonic: AUX 7 6 BRS - 5 - PINTS [1:0] 0x00 0x01 0x10 0x11 4 3 PTS[1:0] SM39R4051 INT0 and INT1 pins INT0 INT1 P3.2 P3.3 P3.0 P3.1 P1.4 P1.5 P3.2 P3.3 SM39R4051 T0 and T1 pins PTS [1:0] T0 0x00 P3.4 0x01 P3.0 0x10 P1.4 0x11 P1.2 Reset RC GPIO 4 Address: 91h 0 Reset DPS 00H 2 1 PINTS[1:0] RESET Pin XTAL2 T1 P3.5 P3.1 P1.5 P1.3 P3.6 XTAL1 pin P4.0 P4.1 quasi-bidirectional (standard 8051 port outputs) push-pull open drain and input-only 2. Reset a. Reset on-chip hardware RESET duration 25ms (default) 200ms 100ms 50ms 16ms 8ms 4ms 2ms Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 12 Ver. A 2010/07 SM894051 with SM39R4051 APN b. Reset Mnemonic: TAKEY 7 6 5 4 3 TAKEY [7:0] 2 Address: F7H 0 Reset 00H 1 Software reset register (SWRES) is read-only by default; software must write three specific values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the SWRES register write attribute. That is: MOV TAKEY, #55h MOV TAKEY, #0AAh MOV TAKEY, #5Ah Mnemonic: SWRES 7 6 5 4 3 SWRES [7:0] 2 Address: E7H 0 Reset 00H 1 SWRES [7:0]: Software reset register bit. These 8-bit is self-reset at the end of the reset procedure. SWRES [7:0] = FFh, software reset. SWRES [7:0] = 00h ~ FEh, MCU no action. 3. Crystal RC Clock source external crystal (use XTAL1 and XTAL2 pins ) external crystal (only use XTAL1, the XTAL2 define as I/O) 24MHz from on-chip RC-Oscillator 20MHz from on-chip RC-Oscillator 16MHz from on-chip RC-Oscillator 12MHz from on-chip RC-Oscillator 8MHz from on-chip RC-Oscillator 4MHz from on-chip RC-Oscillator 2MHz from on-chip RC-Oscillator 1MHz from on-chip RC-Oscillator 4. Mnemonic: DPL1 7 6 5 4 3 DPL1 [7:0] 2 1 Address: 84h 0 Reset 00h 4 3 DPH1 [7:0] 2 1 Address: 85h 0 Reset 00h DPL1[7:0]: Data pointer Low 1 Mnemonic: DPH1 7 6 5 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 13 Ver. A 2010/07 SM894051 with SM39R4051 APN DPH1[7:0]: Data pointer High 1 Mnemonic: AUX 7 BRS 6 - Address: 91h 5 - 4 3 PTS[1:0] 2 1 PINTS[1:0] 0 DPS Reset 00H DPS: Data Pointer selects register. DPS = 1 is selected DPTR1. 5. ISP/IAP/ICP Mnemonic: IFCON 7 6 CDPR EEPROM 5 - 4 F2K 3 - 2 - Address: 8FH 0 Reset ISPE 00H 1 - Software must be set ISPE bit to 1 to enable Below 4 registers write attribute. Mnemonic: ISPFAH 7 6 - 5 - Mnemonic: ISPFAL 7 6 ISPFAL7 ISPFAL6 5 ISPFAL5 4 ISPFAL4 3 ISPFAL3 2 ISPFAL2 1 ISPFAL1 Address: E2H 0 Reset ISPFAL0 FFH Mnemonic: ISPFD 7 6 ISPFD7 ISPFD6 5 ISPFD5 4 ISPFD4 3 ISPFD3 2 ISPFD2 1 ISPFD1 Address: E3H 0 Reset ISPFD0 FFH Mnemonic: ISPFC 7 6 5 EMF1 EMF2 EMF3 6. 4 - 4 EMF4 Address: E1H 3 2 1 0 Reset ISPFAH3 ISPFAH2 ISPFAH1 ISPFAH0 FFH 3 - 2 ISPF[2] 1 ISPF[1] Address: E4H 0 Reset ISPF[0] 00H IIC Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0xxx 14 Ver. A 2010/07