issfd-m079_d_sm39r16..

SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Product List ......................................................................................................................................................................... 3
Description .......................................................................................................................................................................... 3
Ordering Information ........................................................................................................................................................... 3
Features .............................................................................................................................................................................. 3
Pin Configuration ................................................................................................................................................................ 4
Block Diagram..................................................................................................................................................................... 6
Special Function Register (SFR) ........................................................................................................................................ 8
Function Description ......................................................................................................................................................... 14
1.
General Features ................................................................................................................................................. 14
1.1
Embedded Flash ......................................................................................................................................... 14
1.2
IO Pads ....................................................................................................................................................... 14
1.3
Instruction timing Selection ......................................................................................................................... 14
1.4
Clock Out Selection..................................................................................................................................... 15
1.5
RESET ........................................................................................................................................................ 15
1.5.1
Hardware RESET function ................................................................................................................. 15
1.5.2
Software RESET function ................................................................................................................... 15
1.5.3
Reset status ........................................................................................................................................ 16
1.5.4
Time Access Key register (TAKEY) .................................................................................................... 16
1.5.5
Software Reset register (SWRES) ..................................................................................................... 17
1.5.6
Example of software reset .................................................................................................................. 17
1.6
Clocks ......................................................................................................................................................... 17
2.
Instruction Set ...................................................................................................................................................... 18
3.
Memory Structure ................................................................................................................................................ 22
3.1
Program Memory ........................................................................................................................................ 22
3.2
Data Memory............................................................................................................................................... 23
3.3
Data memory - lower 128 byte (00h to 7Fh) ............................................................................................... 23
3.4
Data memory - higher 128 byte (80h to FFh).............................................................................................. 23
3.5
Data memory - Expanded 1K Bytes ( 0000h ~ 03FFh)............................................................................... 23
4.
CPU Engine ......................................................................................................................................................... 24
4.1
Accumulator ................................................................................................................................................ 24
4.2
B Register ................................................................................................................................................... 24
4.3
Program Status Word .................................................................................................................................. 25
4.4
Stack Pointer ............................................................................................................................................... 25
4.5
Data Pointer ................................................................................................................................................ 25
4.6
Data Pointer 1 ............................................................................................................................................. 26
4.7
Clock control register .................................................................................................................................. 26
4.8
Interface control register ............................................................................................................................. 27
4.9
PAGESEL (Page Select) ............................................................................................................................. 27
5.
GPIO .................................................................................................................................................................... 29
5.1
SFR Setting Method .................................................................................................................................... 29
5.2
Software of Writer Setting Method .............................................................................................................. 30
6.
Multiplication Division unit.................................................................................................................................... 31
6.1
Operating registers of the MDU .................................................................................................................. 31
6.2
Operation of the MDU ................................................................................................................................. 32
6.2.1
First phase: Loading the MDx registers. ............................................................................................ 32
6.2.2
Second phase: Executing calculation. ............................................................................................... 32
6.2.3
Third phase: Reading the result from the MDx registers. .................................................................. 33
6.3
Normalizing ................................................................................................................................................. 33
6.4
Shifting ........................................................................................................................................................ 33
7.
Timer 0 and Timer 1 ............................................................................................................................................. 34
7.1
Timer/Counter mode control register (TMOD) ............................................................................................ 34
7.2
Timer/counter control register (TCON) ....................................................................................................... 35
7.3
Enhance Interrupt Trigger SFR(ENHIT) ...................................................................................................... 36
7.4
Peripheral Frequency control register ......................................................................................................... 36
7.5
Mode 0 (13-bit Counter/Timer) .................................................................................................................... 37
7.6
Mode 1 (16-bit Counter/Timer) .................................................................................................................... 38
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
-1-
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
7.7
7.8
Mode 2 (8-bit auto-reload Counter/Timer) .................................................................................................. 38
Mode 3 (Timer 0 acts as two independent 8 bit Timers / Counters) ........................................................... 39
8.
Timer 2 and Capture Compare Unit ..................................................................................................................... 40
8.1
Timer 2 function........................................................................................................................................... 43
8.1.1
Timer mode ........................................................................................................................................ 43
8.1.2
Event counter mode ........................................................................................................................... 43
8.1.3
Gated timer mode ............................................................................................................................... 43
8.1.4
Reload of Timer 2 ............................................................................................................................... 44
8.2
Compare function ........................................................................................................................................ 45
8.2.1
Compare Mode 0 ................................................................................................................................ 45
8.2.2
Compare Mode 1 ................................................................................................................................ 45
8.3
Capture function .......................................................................................................................................... 47
8.3.1
Capture Mode 0 (by Hardware) .......................................................................................................... 47
8.3.2
Capture Mode 1(by Software) ............................................................................................................ 47
9.
Serial interface ..................................................................................................................................................... 48
9.1
Serial interface ............................................................................................................................................ 49
9.1.1
Mode 0................................................................................................................................................ 49
9.1.2
Mode 1................................................................................................................................................ 50
9.1.3
Mode 2................................................................................................................................................ 50
9.1.4
Mode 3................................................................................................................................................ 50
9.2
Multiprocessor Communication of Serial Interface ..................................................................................... 51
9.3
Peripheral Frequency control register ......................................................................................................... 51
9.4
Baud rate generator .................................................................................................................................... 52
9.4.1
Serial interface modes 1 and 3........................................................................................................... 52
10.
Watchdog timer .................................................................................................................................................... 53
11.
Interrupt................................................................................................................................................................ 57
11.1
Priority level structure.................................................................................................................................. 60
12.
Power Management Unit ..................................................................................................................................... 62
12.1
Idle mode .................................................................................................................................................... 62
12.2
Stop mode ................................................................................................................................................... 62
13.
Pulse Width Modulation (PWM) ........................................................................................................................... 63
14.
IIC function ........................................................................................................................................................... 68
15.
SPI Function - Serial Peripheral Interface ........................................................................................................... 73
16.
LVI & LVR – Low Voltage Interrupt and Low Voltage Reset ................................................................................ 78
17.
10-bit Analog-to-Digital Converter (ADC) ............................................................................................................ 80
18.
In-System Programming (Internal ISP) ................................................................................................................ 84
18.1
ISP service program .................................................................................................................................... 84
18.2
Lock Bit (N) ................................................................................................................................................. 84
18.3
Program the ISP Service Program .............................................................................................................. 85
18.4
Initiate ISP Service Program ....................................................................................................................... 85
18.5
ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC ........................................................ 86
Operating Conditions ........................................................................................................................................................ 89
DC Characteristics ............................................................................................................................................................ 89
LVI& LVR Characteristics .................................................................................................................................................. 91
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
-2-
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Product List
Features
SM39R16A6U24,
SM39R16A6U28,
SM39R16A6U32,



Description

The SM39R16A6 is a 1T (one machine cycle per clock)
single-chip 8-bit microcontroller. It has 16K-byte
embedded Flash for program, and executes all ASM51
instructions fully compatible with MCS-51


SM39R16A6 contains 1K+256B on-chip RAM, up to 30
GPIOs (32L package), various serial interfaces and
many peripheral functions as described below. It can be
programmed via writers. Its on-chip ICE is convenient for
users in verification during development stage.
The high performance of SM39R16A6 can achieve
complicated manipulation within short time. About one
third of the instructions are pure 1T, and the average
speed is 8 times of traditional 8051, the fastest one
among all the 1T 51-series.Its excellent EMI and ESD
characteristics are advantageous for many different
applications.
Ordering Information
SM39R16A6ihhkL
YWW
i: process identifier { U = 1.8V ~ 5.5V}
hh: pin count
k: package type postfix {as table below }
L:PB Free identifier
{No text is Non-PB free，”P” is PB free}
Y: year
WW: week
Postfix
S
V
Package
SOP (300 mil)
LQFP














Main Flash ROM 16KB , 128B/page
Working voltage 1.8V~5.5V
High speed architecture of 1 clock/machine cycle
runs up to 25MHz.
256 bytes SRAM as standard 8052, plus 1K bytes
on-chip expandable SRAM.
Dual 16-bit Data Pointers (DPTR0 & DPTR1).
One serial peripheral interfaces in full duplex mode
(UART).
- Synchronous mode, fixed baud rate.
- 8-bit UART mode, variable baud rate.
- 9-bit UART mode, fixed baud rate.
- 9-bit UART mode, variable baud rate.
Additional Baud Rate Generator for Serial port.
Three 16-bit Timer/Counters. (Timer 0, 1, 2).
Programmable watchdog timer.
One IIC interface. (Master/Slave mode).
One SPI interface. (Master/Slave mode)
4-channel 14-bit PWM for motor control
4-channel 16-bit compare / capture / load functions.
- Comparator out can be CCU input source
internally.
- Noise filter with CCU input with sample
frequency select.
ISP/IAP/ICP functions.
EEPROM function.
On-Chip in-circuit emulator (ICE) functions with OnChip Debugger (OCD).
Fast multiplication-division unit (MDU): 16*16,
32/16, 16/16, 32-bit L/R shifting and 32-bit
normalization.
LVI/LVR (LVR deglitch 500ns).
Enhance user code protection.
Power management unit for IDLE and power down
modes.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
-3-
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Pin Configuration
24 Pin SOP
P1.6/ADC6/MISO/INT0
OCI_SDA/IIC_SDA/TRIGADC/P3.2
2
23
P1.5/ADC5/MOSI
OCI_SCL/IIC_SCL/P3.3
RESET/P3.4
3
22
21
P1.4/ADC4/SS/CC3
P1.3/ADC3/T2EX
CLKOUT/XTAL2/P3.5
5
20
P1.2/ADC2/T2/CC1
XTAL1/P3.6
6
19
P1.1/ADC1/TXD/CC0
VSS
7
18
P1.0/ADC0/RXD
CC0/P2.0
8
17
CC1/P2.1
9
16
VDD
P0.4/PWM4
CC2/P2.2
10
15
P0.5/PWM5
CC3/P2.3
11
14
P0.6/INT1/PWM6
P2.6
12
13
P0.7/T1/PWM7
RXD/P3.0
1
28
TXD/P3.1
OCI_SDA/IIC_SDA/TRIGADC/P3.2
2
27
3
26
P1.7/ADC7/SPI_CLK/T0
P1.6/ADC6/MISO/INT0
P1.5/ADC5/MOSI
OCI_SCL/IIC_SCL/P3.3
4
25
P1.4/ADC4/SS/CC3
RESET/P3.4
5
24
P1.3/ADC3/T2EX/CC2
CLKOUT/XTAL2/P3.5
6
23
P1.2/ADC2/T2/CC1
XTAL1/P3.6
7
22
P1.1/ADC1/TXD/CC0
VSS
8
21
P1.0/ADC0/RXD
CC0/P2.0
9
20
VDD
CC1/P2.1
10
19
P0.4/PWM4
CC2/P2.2
11
18
P0.5/PWM5
CC3/P2.3
P2.4
12
17
P0.6/INT1/PWM6
13
16
P2.5
14
15
P0.7/T1/PWM7
P2.6
4
SyncMOS
24
SM39R16A6U24SP
1
YWW
(24 Pin Top View)
T0/SPI_CLK/ADC7/P1.7
28 Pin SOP
SyncMOS
SM39R16A6U28SP
YWW
(28 Pin Top View)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
-4-
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
P0.4/PWM4
P0.5/PWM5
P0.6/INT1/PWM6
P0.7/T1/PWM7
P2.6
P2.5
P2.4
P2.3/CC3
24
23
22
21
20
19
18
17
32 Pin LQFP
P0.3
25
16
P2.2/CC2
P0.2
26
15
P2.1/CC1
P0.1
27
14
P2.0/CC0
P0.0
28
13
VSS
VDD
29
12
P3.6/XTAL1
RXD/ADC0/P1.0
30
11
P3.5/XTAL2/CLKOUT
CC0/TXD/ADC1/P1.1
31
10
P3.4/RESET
CC1/T2/ADC2/P1.2
32
9
P3.3/OCI_SCL/IIC_SCL
SM39R16A6U32VP
YWW
1
2
3
4
5
6
7
8
CC2/T2EX/ADC3/P1.3
CC3/SS/ADC4/P1.4
MOSI/ADC5/P1.5
INT0/MISO/ADC6/P1.6
T0/SPI_CLK/ADC7/P1.7
RXD/P3.0
TXD/P3.1
OCI_SDA/IIC_SDA/TRIGADC/P3.2
(32 LQFP Top View)
Notes：
(1) The pin Reset/P3.4 factory default is GPIO (P3.4). User can configure it to reset by a flash programmer.
(2) To avoid accidentally entering ISP-Mode(refer to section 18.4), care must be taken not asserting pulse signal at
RXD P3.0 during power-up while P1.2, P1.3 or P1.4 are set to high.
(3) To apply ICP function, OCI_SDA/P3.2 and OCI_SCL/P3.3 are ICP pins during reset period. When reset finish,
they are GPIO.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
-5-
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
XTAL2
XTAL1
ADC
IIC
PWM
SRAM
1KBytes
SRAM
256Bytes
Flash 16KBytes
CPU
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_SS
PWM[7:4]
UART
IIC_SCL
IIC_SDA
MAX810
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
RESET
TXD
RXD
Block Diagram
SPI
Port 0
Port 0
Port 1
Port 1
Port 2
Port 2
Port 3
Port 3
Timer 0/1
T0
T1
MDU
Watchdog
Interrupt
ICP
ICE
OCI_SCL
CC0~CC3
T2
T2EX
OCI_SDA
Interface control
Timer2
& CCU
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
-6-
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Pin Description
32L
LQFP
28L
SOP
24L
SOP
1
24
21
2
25
22
3
26
23
4
27
24
5
28
1
6
1
P1.6/ADC6/MISO/
INT0
P1.7/ADC7/SPI_
CLK/T0
P3.0/RXD
7
2
P3.1/TXD
8
3
2
9
4
3
10
5
4
11
6
5
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
7
8
9
10
11
12
13
14
15
16
17
18
19
6
7
8
9
10
11
20
17
P3.2/TRIGADC/II
C_SDA/OCI_SDA
P3.3/IIC_SCL/OC
I_SCL
P3.4/RESET
P3.5/XTAL2/CLK
OUT
P3.6/XTAL1
VSS
P2.0/CC0
P2.1/CC1
P2.2/CC2
P2.3/CC3
P2.4
P2.5
P2.6
P0.7/PWM7/T1
P0.6/PWM6/INT1
P0.5/PWM5
P0.4/PWM4
P0.3
P0.2
P0.1
P0.0
VDD
30
21
18
P1.0/ADC0/RXD
I/O
31
22
19
P1.1/ADC1/TXD/
CC0
I/O
32
23
20
P1.2/ADC2/T2/C
C1
I/O
12
13
14
15
16
Symbol
P1.3/ADC3/T2EX/
CC2
P1.4/ADC4/SS/C
C3
P1.5/ADC5/MOSI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
Bit 3 of port 1 & ADC input channel 3 & Timer 2 capture
trigger & Timer 2 compare/capture Channel 2
Bit 4 of port 1 & ADC input channel 4 & SPI interface Slave
Select pin & Timer 2 compare/capture Channel 3
Bit 5 of port 1 & ADC input channel 5 & SPI interface Serial
Data Master Output or Slave Input pin
Bit 6 of port 1 & ADC input channel 6 & SPI interface Serial
Data Master Input or Slave Output pin & External interrupt 0
Bit 7 of port 1 & ADC input channel 7 & SPI interface Clock
pin & Timer 0 external input
Bit 0 of port 3 & Serial interface channel Receive data
Bit 1 of port 3 & Serial interface channel Transmit data or
receive clock in mode 0
Bit 2 of port 3 & external pin to trigger ADC & IIC SDA pin &
On-Chip Instrumentation SDA
I/O
Bit 3 of port 3 & IIC SCL pin & On-Chip Instrumentation SCL
I/O
Bit 4 of port 3 & Reset pin
I/O
Bit 5 of port 3 & Crystal output & clock out
I/O
Bit 6 of port 3 & Crystal input
Ground
Bit 0 of port 2 & Timer 2 compare/capture Channel 0
Bit 1 of port 2 & Timer 2 compare/capture Channel 1
Bit 2 of port 2 & Timer 2 compare/capture Channel 2
Bit 3 of port 2 & Timer 2 compare/capture Channel 3
Bit 4 of port 2
Bit 5 of port 2
Bit 6 of port 2
Bit 7 of port 0 & PWM Channel 7 & Timer 1 external input
Bit 6 of port 0 & PWM Channel 6 & External interrupt 1
Bit 5 of port 0 & PWM Channel 5
Bit 4 of port 0 & PWM Channel 4
Bit 3 of port 0
Bit 2 of port 0
Bit 1 of port 0
Bit 0 of port 0
Power supply
Bit 0 of port 1 & ADC input channel 0 & Serial interface
channel receive data
Bit 1 of port 1 & ADC input channel 1 & Serial interface
channel Transmit data & Timer 2 compare/capture Channel
0
Bit 2 of port 1 & ADC input channel 2 & Timer 2 external input
clock & Timer 2 compare/capture Channel 1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
-7-
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Special Function Register (SFR)
A map of the Special Function Registers is shown as below:
In-direct access Mode
Hex\Bin
X000
X001
X010
X011
X100
X101
F8
IICS
IICCTL
IICA1
IICA2
IICRWD
IICEBT
F0
B
SPIC1
SPIC2
SPITXD
SPIRXD
SPIS
E8
E0
ACC
D8
D0
PSW
MD0
ISPFAH
MD1
ISPFAL
MD2
ISPFD
PFCON
P3M0
P3M1
CCEN2
P0M0
P0M1
C8
C0
T2CON
IRCON
CCCON
CCEN
CRCL
CCL1
B8
IEN1
IP1
SRELH
B0
P3
A8
IEN0
IP0
A0
P2
RSTS
98
SCON
SBUF
90
P1
AUX
88
80
Hex\Bin
TCON
P0
X000
TMOD
SP
X001
SRELL
PWM
ADDR
IEN2
TL0
DPL
X010
CRCH
CCH1
ADCC1
PWM
DATA
MD3
ISPFC
MD4
X110
X111
Bin/Hex
FF
MD5
LVC
TAKEY
F7
ARCON
SWRES
EF
E7
DF
P1M0
TL2
CCL2
ADCC2
P1M1
TH2
CCH2
ADCDH
P2M0
P2M1
D7
CCH3
CF
C7
CCL3
PAGESE
L
WDTC
WDTK
B7
ADCDL
ADCCS
AF
BF
A7
9F
TL1
DPH
X011
TH0
DPL1
X100
TH1
DPH1
X101
CKCON
RCON
X110
IRCON2
97
IFCON
PCON
X111
8F
87
Bin/Hex
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
-8-
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Page Mode: page0
Hex\Bin
X000
X001
X010
X011
X100
X101
F8
IICS
IICCTL
IICA1
IICA2
IICRWD
IICEBT
F0
B
SPIC1
SPIC2
SPITXD
SPIRXD
SPIS
MD1
ISPFAL
MD2
ISPFD
MD3
ISPFC
MD4
ACC
MD0
ISPFAH
PFCON
P3M0
P3M1
E8
E0
D8
X110
MD5
LVC
TAKEY
F7
ARCON
SWRES
EF
E7
DF
PSW
CCEN2
P0M0
P0M1
P1M0
P1M1
P2M0
C8
T2CON
CCCON
CRCL
CRCH
TL2
TH2
OpPin2
C0
IRCON
CCEN
CCL1
CCH1
CCL2
CCH2
B8
IEN1
IP1
SRELH
B0
P3
CCL3
PAGESE
L
WDTC
A8
A0
IEN0
P2
IP0
RSTS
SRELL
98
SCON
SBUF
IEN2
90
P1
AUX
88
80
Hex\Bin
TCON
P0
X000
TMOD
SP
X001
TL0
DPL
X010
Bin/Hex
FF
D0
ADCC1
X111
ADCC2
ADCDH
ADCDL
P2M1
Cmp2CO
N
CCH3
D7
CF
C7
BF
WDTK
B7
ADCCS
AF
A7
9F
TL1
DPH
X011
TH0
DPL1
X100
IRCON2
97
TH1
DPH1
X101
CKCON
RCON
X110
IFCON
PCON
X111
8F
87
Bin/Hex
X101
X110
X111
Bin/Hex
Page Mode: page1
Hex\Bin
X000
F8
F0
B
X001
PWMTBC
0
PERIODL
X010
PWMTBC
1
PERIODH
X011
PWMOP
MOD
X100
FF
PWMEN
PWMTB
POST
SCALE
LVC
E8
E0
ACC
D8
ISPFAH
ISPFAL
ISPFD
ISPFC
PWMPOL
ARITY
DUTY2L
PFCON
D0
PSW
C8
C0
T2CON
IRCON
DUTY3H
B8
IEN1
IP1
B0
P3
A8
A0
IEN0
P2
IP0
SRELL
98
SCON
SBUF
IEN2
90
P1
AUX
88
80
Hex\Bin
TCON
P0
X000
TMOD
SP
X001
TL2
TL0
DPL
X010
ADCC1
ADCC2
SWRES
E7
DF
DUTY2H
DUTY3L
D7
CF
C7
BF
PAGESEL
ADCDH
F7
EF
TH2
PWMINT
F
SRELH
TAKEY
WDTC
WDTK
B7
ADCDL
ADCCS
AF
A7
9F
TL1
DPH
X011
TH0
DPL1
X100
TH1
DPH1
X101
CKCON
RCON
X110
IRCON2
97
IFCON
PCON
X111
8F
87
Bin/Hex
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
-9-
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Note: Special Function Registers reset values and description for SM39R16A6.
Register
Location: 80h ~ 8Fh
Method 2 Method 2
Method 1
Page 0
Page 1
Reset
value
Description
SYSTEM
SP
81h
81h
81h
07h
Stack Pointer
ACC
E0h
E0h
E0h
00h
Accumulator
PSW
D0h
D0h
D0h
00h
Program Status Word
B
F0h
F0h
F0h
00h
B Register
DPL
DPH
DPL1
DPH1
82h
83h
84h
85h
82h
83h
84h
85h
82h
83h
84h
85h
00h
00h
00h
00h
Data Pointer 0 low byte
Data Pointer 0 high byte
Data Pointer 1 low byte
Data Pointer 1 high byte
AUX
91h
91h
91h
00h
Auxiliary register
PCON
87h
87h
87h
40h
Power Control
CKCON
8Eh
8Eh
8Eh
10h
Clock control register
PAGESEL
BEh
BEh
BEh
00h
Page select
INTERRUPT & PRIORITY
IRCON
C0h
C0h
C0h
00h
Interrupt Request Control Register
IRCON2
97h
97h
97h
00h
Interrupt Request Control Register 2
IEN0
A8h
A8h
A8h
00h
Interrupt Enable Register 0
IEN1
B8h
B8h
B8h
00h
Interrupt Enable Register 1
IEN2
9Ah
9Ah
9Ah
00h
Interrupt Enable Register 2
IP0
A9h
A9h
A9h
00h
Interrupt Priority Register 0
IP1
B9h
B9h
B9h
00h
Interrupt Priority Register 1
UART
PCON
87h
87h
87h
40h
Power Control
AUX
91h
91h
91h
00h
Auxiliary register
SCON
98h
98h
98h
00h
Serial Port, Control Register
SBUF
99h
99h
99h
00h
Serial Port, Data Buffer
SRELL
AAh
AAh
AAh
00h
Serial Port, Reload Register, low byte
SRELH
BAh
BAh
BAh
00h
Serial Port, Reload Register, high byte
PFCON
D9h
D9h
D9h
00h
Peripheral Frequency control register
ADC
ADCC1
ABh
ABh
ABh
00h
ADC Control 1 Register
ADCC2
ACh
ACh
ACh
08h
ADC Control 2 Register
ADCDH
ADh
ADh
ADh
00h
ADC data high byte
ADCDL
AEh
AEh
AEh
00h
ADC data low byte
ADCCS
AFh
AFh
AFh
00h
ADC clock select
00h
Reset status register
04h
Watchdog timer control register
WDT
RSTS
A1h
A1h
WDTC
B6h
B6h
B6h
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 10 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Register
WDTK
TAKEY
Location: 80h ~ 8Fh
Method 2 Method 2
Method 1
Page 0
Page 1
B7h
B7h
B7h
F7h
F7h
Reset
value
F7h
Description
00h
Watchdog timer refresh key.
00h
Time Access Key register
00h
PWM Time Base Control 0 Reg.
PWM
PWMTBC0
F9h
PWMTBC1
FAh
10h
PWM Time Base Control 1 Reg.
PWMOPMOD
FBh
00h
PWM Output Pair Mode Reg.
PERIODL
F1h
FFh
PWM Period (Low) Reg.
PERIODH
F2h
3Fh
PWM Period (High) Reg.
PWMEN
PWMTBPOST
SCALE
PWMINTF
F5h
00h
PWM Output Enable Reg.
EEh
00h
PWM Time Base Post Scale Reg.
BCh
00h
PWM INT Flag Reg.
PWMPOLARITY
DDh
FFh
PWM Polarity Reg.
DUTY2L
D5h
00h
PWM 2 Duty Low byte Reg.
DUTY2H
D6h
00h
PWM 2 Duty High byte Reg.
DUTY3L
D7h
00h
PWM 3 Duty Low byte Reg.
DUTY3H
C9h
00h
PWM 3 Duty High byte Reg.
PWMADDR
A2h
00h
PWM Address Register
PWMDATA
A3h
00h
PWM Data Register
TIMER0/TIMER1
TCON
88h
88h
88h
00h
Timer/Counter Control
TMOD
89h
89h
89h
00h
Timer Mode Control
TL0
8Ah
8Ah
8Ah
00h
Timer 0, low byte
TL1
8Bh
8Bh
8Bh
00h
Timer 1, low byte
TH0
8Ch
8Ch
8Ch
00h
Timer 0, high byte
TH1
8Dh
8Dh
8Dh
00h
Timer 1, high byte
PFCON
D9h
D9h
D9h
00h
Peripheral Frequency control register
PCA(TIMER2)
CCEN
C1h
C1h
00h
Compare/Capture Enable Register
CCL1
C2h
C2h
00h
CCH1
C3h
C3h
00h
CCL2
C4h
C4h
00h
CCH2
C5h
C5h
00h
CCL3
C6h
C6h
00h
CCH3
C7h
C7h
00h
Compare/Capture Register 1, low byte
Compare/Capture Register 1, high
byte
Compare/Capture Register 2, low byte
Compare/Capture Register 2, high
byte
Compare/Capture Register 3, low byte
Compare/Capture Register 3, high
byte
Timer 2 Control
T2CON
C8h
C8h
CCCON
C9h
C9h
C8h
00h
00h
CRCL
CAh
CAh
00h
Compare/Capture Control
Compare/Reload/Capture Register,
low byte
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 11 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Register
Location: 80h ~ 8Fh
Method 2 Method 2
Method 1
Page 0
Page 1
Reset
value
Description
CRCH
CBh
CBh
TL2
CCh
CCh
CCh
00h
Compare/Reload/Capture Register,
high byte
Timer 2, low byte
TH2
CDh
CDh
CDh
00h
Timer 2, high byte
CCEN2
D1h
D1h
00h
Compare/Capture Enable 2 register
00h
GPIO
P0
80h
80h
80h
P1
90h
90h
90h
User
define
FFh
P2
A0h
A0h
A0h
7Fh
Port 2
P3
B0h
B0h
B0h
Port 3
P0M0
D2h
D2h
P0M1
D3h
D3h
7Fh
User
define
00h
P1M0
D4h
D4h
00h
Port 1 output mode 0
P1M1
D5h
D5h
00h
Port 1 output mode 1
P2M0
D6h
D6h
00h
Port 2 output mode 0
Port 0
Port 1
Port 0 output mode 0
Port 0 output mode 1
P2M1
D7h
D7h
00h
Port 2 output mode 1
P3M0
DAh
DAh
00h
Port 3 output mode 0
P3M1
DBh
DBh
00h
Port 3 output mode 1
ISP/IAP/EEPROM
IFCON
8Fh
8Fh
8Fh
00h
Interface control register
ISPFAH
E1h
E1h
E1h
FFh
ISP Flash Address-High register
ISPFAL
E2h
E2h
E2h
FFh
ISP Flash Address-Low register
ISPFD
E3h
E3h
E3h
FFh
ISP Flash Data register
ISPFC
E4h
E4h
E4h
00h
ISP Flash control register
TAKEY
F7h
F7h
F7h
00h
Time Access Key register
LVI/LVR/SOFTRESET
RSTS
A1h
A1h
00h
Reset status register
LVC
E6h
E6h
E6h
20h
Low voltage control register
SWRES
E7h
E7h
E7h
00h
Software Reset register
TAKEY
F7h
F7h
F7h
00h
Time Access Key register
SPI
SPIC1
F1h
F1h
08h
SPI control register 1
SPIC2
F2h
F2h
00h
SPI control register 2
SPITXD
F3h
F3h
00h
SPI Transmit data buffer
SPIRXD
F4h
F4h
00h
SPI receive data buffer
SPIS
F5h
F5h
40h
SPI status register
IIC
IICS
F8h
F8h
00h
IIC status register
IICCTL
F9h
F9h
04h
IIC control register
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 12 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Register
IICA1
IICA2
Location: 80h ~ 8Fh
Method 2 Method 2
Method 1
Page 0
Page 1
FAh
FAh
FBh
FBh
Reset
value
Description
A0h
IIC channel 1 Address 1 register
60h
IIC channel 1 Address 2 register
IICRWD
FCh
FCh
00h
IIC channel 1 Read / Write Data buffer
IICEBT
FDh
FDh
00h
IIC Enable Bus Transaction register
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 13 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Function Description
1.
General Features
SM39R16A6 is an 8-bit micro-controller. All of its functions and the detailed meanings of SFR will be given in the
following sections.
1.1
Embedded Flash
The program can be loaded into the embedded 16KB Flash memory via its writer or In-System Programming (ISP).
The high-quality Flash suitable for re-programming and data recording as EEPROM.
1.2
IO Pads
The SM39R16A6 has Four I/O ports: Port 0, Port 1, Port 2 and Port 3. Ports 0, 1 are 8-bit ports and Port 2, 3 are 7-bit
ports. These are: quasi-bidirectional (standard 8051 port outputs), push-pull, open drain, and input-only. As description
in section 5.
All the pads for P0, P1, P2 and P3 are with slew rate to reduce EMI. The IO pads can withstand 4KV ESD in human
body mode guaranteeing the SM39R16A6’s quality in high electro-static environments.
The RESET Pin can define as General I/O P3.4 when user use Internal RESET.
The XTAL2 and XTAL1 can define as P3.5 and P3.6 by writer or ISP when user use internal OSC as system clock.
When user use external OSC as system clock and input into XTAL1, only XTAL2 can be defined as P3.5.
1.3
Instruction timing Selection
The conventional 52-series MCUs are 12T, i.e., 12 oscillator clocks per machine cycle. SM39R16A6 is a 1T to 8T MCU,
i.e., its machine cycle is one-clock to eight-clock. In the other words, it can execute one instruction within one clock to
only eight clocks.
Mnemonic: CKCON
7
6
5
ITS[2:0]
4
3
-
2
-
Address: 8Eh
1
0
Reset
CLKOUT[1:0]
10H
ITS: Instruction timing select.
ITS [2:0]
Instruction timing
000
1T mode
001
2T mode (default)
010
3T mode
011
4T mode
100
5T mode
101
6T mode
110
7T mode
111
8T mode
The default is in 2T mode, and it can be changed to another Instruction timing mode if CKCON [6:4] (at address 8Eh) is
change any time. Not every instruction can be executed with one machine cycle. The exact machine cycle number for
all the instructions are given in the next section.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 14 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
1.4
Clock Out Selection
The SM39R16A6 can generate a clock out signal at P3.5 when user use Oscillator (XTAL1 as clock input) or internal
OSC as system clock. The CKCON [1:0] (at address 8Eh) can change any time.
CLKOUT: Clock output select.
CKCON [1:0]
00
01
10
11
1.5
Mode.
GPIO(default)
Fosc
Fosc/2
Fosc/4
RESET
1.5.1
Hardware RESET function
SM39R16A6 provides Internal reset circuit inside, the Internal reset time can set by writer or ISP.
Internal Reset time
25ms (default)
200ms
100ms
50ms
16ms
8ms
4ms
1.5.2
Software RESET function
SM39R16A6 provides one software reset mechanism to reset whole chip. To perform a software reset, the firmware
must write three specific values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the Software Reset
register (SWRES) write attribute. After SWRES register obtain the write authority, the firmware can write FFh to the
SWRES register. The hardware will decode a reset signal that “OR” with the other hardware reset. The SWRES
register is self-reset at the end of the software reset procedure.
Mnemonic
RSTS
TAKEY
SWRES
Description
Reset status
register
Time Access
Key register
Software Reset
register
Dir.
Bit 7
A1h
-
Bit 6
Bit 5
Bit 4
Software Reset function
LVRLP LVRLP
PDRF
INTF
F
Bit 3
Bit 2
Bit 1
Bit 0
RST
WDTF
SWRF
LVRF
PORF
00H
F7h
TAKEY [7:0]
00H
E7h
SWRES [7:0]
00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 15 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
1.5.3
Reset status
Mnemonic: RSTS
7
6
LVRLP
INTF
5
4
3
2
1
LVRLPF
PDRF
WDTF
SWRF
LVRF
Address: A1h
0
Reset
PORF
00H
LVRLPINTF: “Internal” Low voltage reset flag.
When MCU is reset by LVR_LP_INT, LVRLPINTF flag will be set to one by hardware. This flag
clear by software.
LVRLPF: Low voltage reset (Low Power) flag.
When MCU is reset by LVR (Low Power), LVRLPF flag will be set to one by hardware. This flag
clear by software.
PDRF: Pad reset flag.
When MCU is reset by reset pad, PDRF flag will be set to one by hardware. This flag clear by
software.
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag clear by
software.
SWRF: Software reset flag.
When MCU is reset by software, SWRF flag will be set to one by hardware. This flag clear by
software.
LVRF: Low voltage reset flag.
When MCU is reset by LVR, LVRF flag will be set to one by hardware. This flag clear by
software.
PORF: Power on reset flag.
When MCU is reset by POR, PORF flag will be set to one by hardware. This flag clear by
software.
1.5.4
Time Access Key register (TAKEY)
Mnemonic: TAKEY
7
6
5
4
3
TAKEY [7:0]
2
1
Address:F7H
0
Reset
00H
Software reset register (SWRES) is read-only by default, software must write three specific values 55h, AAh and
5Ah sequentially to the TAKEY register to enable the SWRES register write attribute.
That is:
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 16 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
1.5.5
Software Reset register (SWRES)
Mnemonic: SWRES
7
6
SWRES [7:0]:
5
4
3
SWRES [7:0]
2
1
0
Address:E7H
Reset
00H
Software reset register bit. These 8-bit is self-reset at the end of the reset procedure.
SWRES [7:0] = FFh, software reset.
SWRES [7:0] = 00h ~ FEh, MCU no action.
1.5.6
Example of software reset
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah ; enable SWRES write attribute
MOV SWRES, #0FFh ; software reset MCU
1.6
Clocks
The default clock is the 22.1184MHz Internal OSC. This clock is used during the initialization stage. The major work of
the initialization stage is to determine the clock source used in normal operation.
The internal clock sources are from the internal OSC with difference frequency division As shown in Table 1-1, the
clock source can set by writer.
Table 1-1: Selection of clock source
Clock source
external crystal (use XTAL1 and XTAL2 pins )
external crystal (only use XTAL1, the XTAL2 define as I/O)
22.1184MHz from internal OSC
11.0592MHz from internal OSC
5.5296MHz from internal OSC
2.7648MHz from internal OSC
1.3824MHz from internal OSC
There may be having a little variance in the frequency from the internal OSC. The max variance as giving in Table 1-2.
Table 1-2: Temperature with variance
Temperature Max Variance
25℃
±2%
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 17 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
2. Instruction Set
All SM39R16A6 instructions are binary code compatible and perform the same functions as they do with the industry
standard 8051. The following tables give a summary of the instruction set cycles of the SM39R16A6 Microcontroller
core.
Mnemonic
ADD A,Rn
Table 2-1: Arithmetic operations
Description
Add register to accumulator
Code
28-2F
Bytes
1
Cycles
1
ADD A,direct
Add direct byte to accumulator
25
2
2
ADD A,@Ri
Add indirect RAM to accumulator
26-27
1
2
ADD A,#data
ADDC A,Rn
Add immediate data to accumulator
Add register to accumulator with carry flag
24
38-3F
2
1
2
1
ADDC A,direct
Add direct byte to A with carry flag
35
2
2
ADDC A,@Ri
Add indirect RAM to A with carry flag
36-37
1
2
ADDC A,#data
SUBB A,Rn
Add immediate data to A with carry flag
Subtract register from A with borrow
34
98-9F
2
1
2
1
SUBB A,direct
Subtract direct byte from A with borrow
95
2
2
SUBB A,@Ri
Subtract indirect RAM from A with borrow
96-97
1
2
SUBB A,#data
INC A
INC Rn
Subtract immediate data from A with borrow
Increment accumulator
Increment register
94
04
08-0F
2
1
1
2
1
2
INC direct
Increment direct byte
05
2
3
INC @Ri
Increment indirect RAM
06-07
1
3
INC DPTR
DEC A
Increment data pointer
Decrement accumulator
A3
14
1
1
1
1
DEC Rn
Decrement register
18-1F
1
2
DEC direct
Decrement direct byte
15
2
3
DEC @Ri
MUL AB
Decrement indirect RAM
Multiply A and B
16-17
A4
1
1
3
5
DIV
Divide A by B
84
1
5
DA A
Decimal adjust accumulator
D4
1
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 18 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Mnemonic
ANL A,Rn
Table 2-2: Logic operations
Description
AND register to accumulator
Code
58-5F
Bytes
1
Cycles
1
ANL A,direct
AND direct byte to accumulator
55
2
2
ANL A,@Ri
AND indirect RAM to accumulator
56-57
1
2
ANL A,#data
ANL direct,A
AND immediate data to accumulator
AND accumulator to direct byte
54
52
2
2
2
3
ANL direct,#data
AND immediate data to direct byte
53
3
4
ORL A,Rn
OR register to accumulator
48-4F
1
1
ORL A,direct
ORL A,@Ri
OR direct byte to accumulator
OR indirect RAM to accumulator
45
46-47
2
1
2
2
ORL A,#data
OR immediate data to accumulator
44
2
2
ORL direct,A
OR accumulator to direct byte
42
2
3
ORL direct,#data
XRL A,Rn
OR immediate data to direct byte
Exclusive OR register to accumulator
43
68-6F
3
1
4
1
XRL A,direct
Exclusive OR direct byte to accumulator
65
2
2
XRL A,@Ri
Exclusive OR indirect RAM to accumulator
66-67
1
2
XRL A,#data
Exclusive OR immediate data to accumulator
64
2
2
XRL direct,A
XRL direct,#data
Exclusive OR accumulator to direct byte
Exclusive OR immediate data to direct byte
62
63
2
3
3
4
CLR A
Clear accumulator
E4
1
1
CPL A
Complement accumulator
F4
1
1
RL A
RLC A
Rotate accumulator left
Rotate accumulator left through carry
23
33
1
1
1
1
RR A
Rotate accumulator right
03
1
1
RRC A
Rotate accumulator right through carry
13
1
1
SWAP A
Swap nibbles within the accumulator
C4
1
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 19 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Mnemonic
MOV A,Rn
MOV A,direct
Table 2-3: Data transfer
Description
Move register to accumulator
Move direct byte to accumulator
Code
E8-EF
E5
Bytes
1
2
Cycles
1
2
MOV A,@Ri
MOV A,#data
MOV Rn,A
MOV Rn,direct
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
Move direct byte to register
E6-E7
74
F8-FF
A8-AF
1
2
1
2
2
2
2
4
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct1,direct2
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
78-7F
F5
88-8F
85
2
2
2
3
2
3
3
4
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
MOV @Ri,direct
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move direct byte to indirect RAM
86-87
75
F6-F7
A6-A7
2
3
1
2
4
3
3
5
MOV @Ri,#data
Move immediate data to indirect RAM
76-77
2
3
MOV DPTR,#data16
Load data pointer with a 16-bit constant
90
3
3
MOVC A,@A+DPTR
Move code byte relative to DPTR to accumulator
93
1
3
MOVC A,@A+PC
MOVX A,@Ri
Move code byte relative to PC to accumulator
Move external RAM (8-bit addr.) to A
83
E2-E3
1
1
3
3
MOVX A,@DPTR
MOVX @Ri,A
MOVX @DPTR,A
PUSH direct
Move external RAM (16-bit addr.) to A
Move A to external RAM (8-bit addr.)
Move A to external RAM (16-bit addr.)
Push direct byte onto stack
E0
F2-F3
F0
C0
1
1
1
2
3
4
4
4
POP direct
XCH A,Rn
XCH A,direct
XCH A,@Ri
XCHD A,@Ri
Pop direct byte from stack
Exchange register with accumulator
Exchange direct byte with accumulator
Exchange indirect RAM with accumulator
Exchange low-order nibble indir. RAM with A
D0
C8-CF
C5
C6-C7
D6-D7
2
1
2
1
1
3
2
3
3
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 20 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Mnemonic
ACALL addr11
Table 2-4: Program branches
Description
Absolute subroutine call
Code
xxx11
Bytes
2
Cycles
6
LCALL addr16
Long subroutine call
12
3
6
RET
from subroutine
22
1
4
RETI
AJMP addr11
from interrupt
Absolute jump
32
xxx01
1
2
4
3
LJMP addr16
Long iump
02
3
4
SJMP rel
Short jump (relative addr.)
80
2
3
JMP @A+DPTR
JZ rel
Jump indirect relative to the DPTR
Jump if accumulator is zero
73
60
1
2
2
3
JNZ rel
Jump if accumulator is not zero
70
2
3
JC rel
Jump if carry flag is set
40
2
3
JNC
JB bit,rel
Jump if carry flag is not set
Jump if direct bit is set
50
20
2
3
3
4
JNB bit,rel
Jump if direct bit is not set
30
3
4
JBC bit,direct rel
Jump if direct bit is set and clear bit
10
3
4
CJNE A,direct rel
Compare direct byte to A and jump if not equal
B5
3
4
CJNE A,#data rel
CJNE Rn,#data rel
Compare immediate to A and jump if not equal
Compare immed. to reg. and jump if not equal
B4
B8-BF
3
3
4
4
CJNE @Ri,#data rel
Compare immed. to ind. and jump if not equal
B6-B7
3
4
DJNZ Rn,rel
Decrement register and jump if not zero
D8-DF
2
3
DJNZ direct,rel
NOP
Decrement direct byte and jump if not zero
No operation
D5
00
3
1
4
1
Mnemonic
CLR C
Table 2-5: Boolean manipulation
Description
Clear carry flag
Code
C3
CLR bit
Clear direct bit
C2
Bytes
1
Cycles
1
2
3
SETB C
Set carry flag
D3
1
1
SETB bit
CPL C
Set direct bit
Complement carry flag
D2
B3
2
1
3
1
CPL bit
Complement direct bit
B2
2
3
ANL C,bit
AND direct bit to carry flag
82
2
2
ANL C,/bit
ORL C,bit
AND complement of direct bit to carry
OR direct bit to carry flag
B0
72
2
2
2
2
ORL C,/bit
OR complement of direct bit to carry
A0
2
2
MOV C,bit
Move direct bit to carry flag
A2
2
2
MOV bit,C
Move carry flag to direct bit
92
2
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 21 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
3. Memory Structure
The SM39R16A6 memory structure follows general 8052 structure. It is integrate the expanded 1KB data memory and
16KB program memory.
3.1
Program Memory
The SM39R16A6 has 16KB on-chip flash memory which can be used as general program memory or EEPROM, on
which include up to 1K byte specific ISP service program memory space. The address range for the 16K byte is $0000
to $3FFF. The address range for the ISP service program is $3C00 to $3FFF. The ISP service program size can be
partitioned as N blocks of 128 byte (N=0 to 8). When N=0 means no ISP service program space available, total 16K
byte memory used as program memory. When N=1 means address $3F80 to $3FFF reserved for ISP service program.
When N=2 means memory address $3F00 to $3FFF reserved for ISP service program…etc. Value N can be set and
programmed into SM39R16A6 information block by writer. As shown in Fig. 3-1
ISP service
Program space,
Up to 1K
3FFF
3F80
3F00
3E80
3E00
3D80
3D00
3C80
3C00
N=0
N=1
N=2
N=3
N=4
N=5
N=6
N=7
N=8
16K Program
Memory space
0000
Fig. 3-1: SM39R16A6 programmable Flash
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 22 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
3.2
Data Memory
The SM39R16A6 has 1K + 256B on-chip SRAM, 256B of it are the same as general 8052 internal memory structure
while the expanded 1K Bytes on-chip SRAM can be accessed by external memory addressing method ( by instruction
MOVX.). As shown in Fig. 3-2
03FF
FF
FF
Higher 128 Bytes (Accessed by
indirect addressing mode only)
SFR (Accessed by direct addressing
mode only)
Expanded 1K Bytes
(Accessed by direct
external addressing mode
by instruction MOVX)
80
80
7F
Lower 128 Bytes (Accessed by
direct & indirect addressing mode )
00
0000
Fig. 3-2: RAM architecture
3.3
Data memory - lower 128 byte (00h to 7Fh)
Data memory 00h to FFh is the same as 8052.
The address 00h to 7Fh can be accessed by direct and indirect addressing modes.
Address 00h to 1Fh is register area.
Address 20h to 2Fh is memory bit area.
Address 30h to 7Fh is for general memory area.
3.4
Data memory - higher 128 byte (80h to FFh)
The address 80h to FFh can be accessed by indirect addressing mode.
Address 80h to FFh is data area.
3.5
Data memory - Expanded 1K Bytes ( 0000h ~ 03FFh)
From external address 0000h to 03FFh is the on-chip expanded SRAM area, total 1K Bytes. This area can be
accessed by external direct addressing mode (by instruction MOVX). The address space of instruction MOVX @Ri, i=0,
1 is determined by RCON [7:0] of special function register $86 RCON (internal RAM control register). The default
setting of RCON [7:0] is 00h (page0). One page of data RAM is 256 bytes.
Note: SM39R16A6 can not access (off-chip) external RAM.
MOVX @Ri, A
0 ≦ RCON[7:0] ≦ 3
MOVX A, @Ri
Addr [15:8] <= RCON[7:0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 23 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
4.
CPU Engine
The SM39R16A6 engine is composed of four components:
(1) Control unit
(2) Arithmetic – logic unit
(3) Memory control unit
(4) RAM and SFR control unit
The SM39R16A6 engine allows to fetch instruction from program memory and to execute using RAM or SFR. The
following chapter describes the main engine register.
Mnemonic
Description
Dir.
Bit 7
ACC
B
Accumulator
B register
Program status
word
Stack Pointer
Data pointer low 0
Data pointer high 0
Data pointer low 1
Data pointer high 1
Auxiliary register
Clock control
register
Interface control
register
E0h
F0h
ACC.7
B.7
D0h
CY
PSW
SP
DPL
DPH
DPL1
DPH1
AUX
CKCON
IFCON
PAGESEL
4.1
Page Select
Bit 6
Bit 5
8051 Core
ACC.6 ACC.5
B.6
B.5
AC
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
ACC.4
B.4
ACC.3
B.3
ACC.2
B.2
ACC.1
B.1
ACC.0
B.0
00H
00H
OV
PSW.1
P
00H
DPS
07H
00H
00H
00H
00H
00H
CLKOUT[1:0]
10H
F0
81h
82h
83h
84h
85h
91h
BRGS
8Eh
-
8Fh
-
CDPR
-
BEh
-
-
-
RS[1:0]
-
P21CC
SP[7:0]
DPL[7:0]
DPH[7:0]
DPL1[7:0]
DPH1[7:0]
P1UR
-
-
-
-
-
-
-
-
ISPE
00H
-
-
-
Page_
num
Page_
mode
00H
ITS[2:0]
-
Accumulator
ACC is the Accumulator register. Most instructions use the accumulator to store the operand.
Mnemonic: ACC
7
6
ACC.7 ACC.6
5
ACC05
4
ACC.4
3
ACC.3
2
ACC.2
1
ACC.1
Address: E0h
0
Reset
ACC.0
00h
ACC[7:0]: The A (or ACC) register is the standard 8052 accumulator.
4.2
B Register
The B register is used during multiply and divide instructions. It can also be used as a scratch pad register to store
temporary data.
Mnemonic: B
7
6
B.7
B.6
5
B.5
4
B.4
3
B.3
2
B.2
1
B.1
Address: F0h
0
Reset
B.0
00h
B[7:0]: The B register is the standard 8052 register that serves as a second accumulator.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 24 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
4.3
Program Status Word
Mnemonic: PSW
7
6
CY
AC
5
F0
4
3
RS [1:0]
2
OV
1
F1
Address: D0h
0
Reset
P
00h
CY: Carry flag.
AC: Auxiliary Carry flag for BCD operations.
F0: General purpose Flag 0 available for user.
RS[1:0]: Register bank select, used to select working register bank.
RS[1:0]
Bank Selected
Location
00
Bank 0
00h – 07h
01
Bank 1
08h – 0Fh
10
Bank 2
10h – 17h
11
Bank 3
18h – 1Fh
OV: Overflow flag.
F1: General purpose Flag 1 available for user.
P: Parity flag, affected by hardware to indicate odd/even number of “one” bits in the
Accumulator, i.e. even parity.
4.4
Stack Pointer
The stack pointer is a 1-byte register initialized to 07h after reset. This register is incremented before PUSH and CALL
instructions, causing the stack to start from location 08h.
Mnemonic: SP
7
6
5
4
3
2
1
SP [7:0]
Address: 81h
0
Reset
07h
SP[7:0]: The Stack Pointer stores the scratchpad RAM address where the stack begins. In other
words, it always points to the top of the stack.
4.5
Data Pointer
The data pointer (DPTR) is 2-bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-byte
register (e.g. MOV DPTR, #data16) or as two separate registers (e.g. MOV DPL,#data8). It is generally used to access
the external code or data space (e.g. MOVC A, @A+DPTR or MOVX A,@DPTR respectively).
Mnemonic: DPL
7
6
5
3
DPL [7:0]
2
1
Address: 82h
0
Reset
00h
4
3
DPH [7:0]
2
1
Address: 83h
0
Reset
00h
4
DPL[7:0]: Data pointer Low 0
Mnemonic: DPH
7
6
5
DPH [7:0]: Data pointer High 0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 25 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
4.6
Data Pointer 1
The Dual Data Pointer accelerates the moves of data block. The standard DPTR is a 16-bit register that is used to
address external memory or peripherals. In the SM39R16A6 core the standard data pointer is called DPTR, the second
data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is
located in LSB of AUX register (DPS).
The user switches between pointers by toggling the LSB of AUX register. All DPTR-related instructions use the
currently selected DPTR for any activity.
Mnemonic: DPL1
7
6
5
4
3
DPL1 [7:0]
2
1
Address: 84h
0
Reset
00h
4
3
DPH1 [7:0]
2
1
Address: 85h
0
Reset
00h
DPL1[7:0]: Data pointer Low 1
Mnemonic: DPH1
7
6
5
DPH1[7:0]: Data pointer High 1
Mnemonic: AUX
7
6
BRGS P21CC
5
-
4
P1UR
3
-
4
3
-
2
-
1
-
Address: 91h
0
Reset
DPS
00H
DPS: Data Pointer select register.
DPS = 1 is selected DPTR1.
4.7
Clock control register
Mnemonic: CKCON
7
6
5
ITS[2:0]
2
-
Address: 8Eh
1
0
Reset
CLKOUT[1:0]
10H
ITS[2:0]: Instruction timing select.
ITS [2:0]
Mode
000
1T mode
001
2T mode (default)
010
3T mode
011
4T mode
100
5T mode
101
6T mode
110
7T mode
111
8T mode
CLKOUT[1:0]: Clock output select.
CLKOUT[1:0]
Mode
00
GPIO(default)
01
Fosc
10
Fosc/2
11
Fosc/4
It can be used when the system clock is the internal RC oscillator.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 26 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
4.8
Interface control register
Mnemonic: IFCON
7
6
CDPR
5
-
4
-
3
-
2
-
1
-
Address: 8Fh
0
Reset
ISPE
00H
CDPR: Code protect (Read Only)
ISPE: ISP function enable bit
ISPE = 1, enable ISP function
ISPE = 0, disable ISP function
4.9
PAGESEL (Page Select)
The SM39R16A6 provide two different methods to set Special Function Register (SFR) are as follow:

SFR Method 1 (Indirect Mode): This method is only an SFR page. If you want to use
PWM registers of the Method 2, can be used indirectly addressable setting.
Example: Write a data 0x80h to PWMEN Register in Method 1.
PAGESEL = 0x00;
// Method 1.
PWMADDR = 0xF5;


// PWMEN indirect address: 0xF5 (Indirect mode)
// (Refer Page1 Table of the Method 2)
PWMDATA = 0x80;
// Write data 0x80 to PWMEN.
SFR Method 2 (Page Mode): This method provides two SFR page to set the registers.
Example: Write a data 0x80 to PWMEN Register in Method 2, Page 1.
PAGESEL = 0x03;
// Method 2, Page 1 (Page mode)
PWMEN = 0x80;
// Write data 0x80 to PWMEN.
SFR Page Mode Table:
7
-
Page_mode
Page_num
SFR Select
0
0
SFR Method 1
0
1
SFR Method 1
1
0
SFR Method 2, Page 0
1
1
SFR Method 2, Page 1
Mnemonic: PAGESEL
6
5
-
-
4
3
2
-
-
-
1
Page_
num
Address: BEh
0
Reset
Page_
00H
mode
Page_num: This flag is used only in the SFR method 2
0 = page 0 mode.
1 = page 1 mode.
Page_mode: This flag is used to select SFR register table.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 27 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
0 : SFR Method 1 (indirect mode).
1 : SFR Method 2 (page mode).
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 28 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
5. GPIO
5.1
SFR Setting Method
The SM39R16A6 has four I/O ports: Port 0, Port 1, Port 2, Port 3. Ports 0, 1, 2 are 8-bit ports and Ports 2, 3 are 7-bit
ports. These are: quasi-bidirectional (standard 8051 port outputs), push-pull, open drain, and input-only. Two
configuration registers for each port select the output type for each port pin. All I/O port pins on the SM39R16A6 may
be configured by software to one fo four types on a pin-by-pin basis, shown as below:
Mnemonic
P0M0
P0M1
P1M0
P1M1
P2M0
P2M1
P3M0
P3M1
Description
Port 0 output
mode 0
Port 0 output
mode 1
Port 1 output
mode 0
Port 1 output
mode 1
Port 2 output
mode 0
Port 2 output
mode 1
Port 3 output
mode 0
Port 3 output
mode 1
Direct
Bit 7
Bit 6
Bit 5
Bit 4
I/O port function register
Bit 3
Bit 2
Bit 1
Bit 0
RESET
D2h
P0M0 [7:0]
~OP18
D3h
P0M1[7:0]
00H
D4h
P1M0[7:0]
00H
D5h
P1M1[7:0]
00H
D6h
-
P2M0[6:0]
00H
D7h
-
P2M1[6:0]
00H
DAh
-
P3M0[6:0]
00H
DBh
-
P3M1[6:0]
00H
*OP18 by writer programming set.
PxM1.y
0
0
1
1
PxM0.y
0
1
0
1
Port output mode
Quasi-bidirectional (standard 8051 port outputs) (pull-up)
Push-pull
Input only (high-impedance)
Open drain
The RESET Pin can define as General I/O P3.4 when user use Internal RESET.
The XTAL2 and XTAL1 can define as P3.5 and P3.6 by writer when user use internal OSC as system clock. When
user use external OSC as system clock and input into XTAL1, only XTAL2 can be defined as P3.5.
For general-purpose applications, every pin can be assigned to either high or low independently. As shown below:
Mnemonic
Description
Dir.
Bit 7
Bit 6
Port 3
Port 2
Port 1
Port 0
Port 3
Port 2
Port 1
Port 0
B0h
A0h
90h
80h
P1.7
P0.7
P3.6
P2.6
P1.6
P0.6
Bit 5
Ports
P3.5
P2.5
P1.5
P0.5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
P3.4
P2.4
P1.4
P0.4
P3.3
P2.3
P1.3
P0.3
P3.2
P2.2
P1.2
P0.2
P3.1
P2.1
P1.1
P0.1
P3.0
P2.0
P1.0
P0.0
7Fh
7Fh
FFh
OP19
*OP19 by writer programming set.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 29 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Mnemonic: P0
7
6
P0.7
P0.6
5
P0.5
4
P0.4
3
P0.3
2
P0.2
1
P0.1
Address: 80h
0
Reset
P0.0
OP19
4
P1.4
3
P1.3
2
P1.2
1
P1.1
Address: 90h
0
Reset
P1.0
FFh
4
P2.4
3
P2.3
2
P2.2
1
P2.1
Address: A0h
0
Reset
P2.0
7Fh
4
P3.4
3
P3.3
2
P3.2
1
P3.1
Address: B0h
0
Reset
P3.0
7Fh
P0.7~ 0: Port0 [7] ~ Port0[0]
Mnemonic: P1
7
6
P1.7
P1.6
5
P1.5
P1.7~ 0: Port1 [7] ~ Port1 [0]
Mnemonic: P2
7
6
P2.6
5
P2.5
P2.6~ 0: Port2 [6] ~ Port2 [0]
Mnemonic: P3
7
6
P3.6
5
P3.5
P3.6~ 0: Port3 [6] ~ Port3 [0]
5.2 Software of Writer Setting Method
Please Setting the “IO Output Mode" item in the "Configuration" window, it can change the I/O mode of
P1~P3 to the “Quasi-bidirectional (standard 8051 port outputs) (pull-up)” or Input only (high-impedance) mode,
When MCU after reset and initial. It is supported the version D of MCU after.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 30 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
6. Multiplication Division unit
This on-chip arithmetic unit provides 32-bit division, 16-bit multiplication, shift and normalize features. All operations are
unsigned integer operation.
Mnemonic
Description
Direct
PCON
Power control
Arithmetic Control
register
Multiplication/Divi
sion Register 0
Multiplication/Divi
sion Register 1
Multiplication/Divi
sion Register 2
Multiplication/Divi
sion Register 3
Multiplication/Divi
sion Register 4
Multiplication/Divi
sion Register 5
87H
Bit 6
Bit 5
Bit 4
Multiplication Division Unit
SMOD MDUF
-
EFh
MDEF
ARCON
MD0
MD1
MD2
MD3
MD4
MD5
6.1
Bit 7
MDOV
Bit 3
Bit 2
Bit 1
Bit 0
RESET
-
-
STOP
IDLE
40H
SLR
SC[4:0]
00H
E9h
MD0[7:0]
00H
EAh
MD1[7:0]
00H
EBh
MD2[7:0]
00H
ECh
MD3[7:0]
00H
EDh
MD4[7:0]
00H
EEh
MD5[7:0]
00H
Operating registers of the MDU
The MDU is handled by eight registers, which are memory mapped as special function registers. The arithmetic unit
allows operations concurrently to and independent of the CPU’s activity. Operands and results registers are MD0 to
MD5. Control register is ARCON. Any calculation of the MDU overwrites its operands.
Mnemonic: ARCON
7
6
5
MDEF MDOV
SLR
4
3
2
SC[4:0]
1
Address: EFh
0
Reset
00H
MDEF- Multiplocation Division Errot Flag.
The MDEF is an error flag. The error flag is read only. The error flag indicates an improperly performed
operation (when one of the arithmetic operations has been restarted or interrupted by a new operation).
The error flag mechanism is automatically enabled with the first write to MD0 and disabled with the
final read instruction from MD3 multiplication or shift/normalizing) or MD5 (division) in phase three.
The error flag is set when:
1. Phase two in process and write access to MDx registers (restart or interrupt calculations)
The error flag is reset only if:
The second phase two finished (arithmetic operation successful completed) and read access to MDx
registers.
MDOV - Multiplication Division Overflow flag. The overflow flag is read only.
The overflow flag is set when:
1. Division by Zero
2. Multiplication with a result greater then 0000FFFFh
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 31 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
3. Start of normalizing if the most significant bit of MD3 is set(MD3.7 = 1)
The overflow flag is reset when:
Write access to MD0 register (Start Phase one)
SLR - Shift direction bit.
SLR = 0 – shift left operation.
SLR = 1 – shift right operation.
SC[4:0] - Shift counter.
When preset with 00000b, normalizing is selected. After normalize sc.0 – sc.4 contains the
number of normalizing shifts performed. When sc.4 – sc.0 ≠ 0, shift- operation is started. The
number of shifts performed is determined by the count written to sc.4 to sc.0. sc.4 – MSB ...
sc.0 – LSB
6.2
Operation of the MDU
Operations of the MDU consist of three phases:
6.2.1
First phase: Loading the MDx registers.
The type of calculation the MDU has to perform is selected following the order in which the mdx registers are written to.
Operation
First write
Last write
32bit/16bit
MD0 Dividend Low
MD1 Dividend
MD2 Dividend
MD3 Dividend High
MD4 Divisor Low
MD5 Divisor High
Table 6-1 MDU registers write sequence
16bit/16bit
16bit x 16bit
MD0 Dividend Low
MD0 Multiplicand Low
MD1 Dividend High
MD4 Multiplicator Low
MD1 Multiplicand High
MD4 Divisor Low
MD5 Divisor High
MD5 Multiplicator High
shift/normalizing
MD0 LSB
MD1
MD2
MD3 MSB
ARCON start conversion
A write to MD0 is the first transfer to be done in any case. Next writes must be done as shown in Table 6-1 to
determine MDU operation. Last write finally starts selected operation.
6.2.2
Second phase: Executing calculation.
During executing operation, the MDU works on its own parallel to the CPU. When MDU is finished, the MDUF register
will be set to one by hardware and the flag will clear at next calculation.
Mnemonic: PCON
7
6
SMOD MDUF
5
4
3
2
1
STOP
Address: 87h
0
Reset
IDLE
40H
MDUF: MDU finish flag.
When MDU is finished, the MDUF will be set by hardware and the bit will clear by hardware at
next calculation.
Operation
Division 32bit/16bit
Division 16bit/16bit
Multiplication
Table 6-2 MDU execution times
Number of Tclk
17 clock cycles
9 clock cycles
11 clock cycles
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SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Shift
Normalize
6.2.3
min 3 clock cycles , max 18 clock cycles
min 4 clock cycles , max 19 clock cycles
Third phase: Reading the result from the MDx registers.
Read out sequence of the first MDx registers is not critical but the last read (from MD5 - division and MD3 multiplication, shift and normalizing) determines the end of a whole calculation (end of phase three).
Table 6-3 MDU registers read sequence
Operation
First read
Last read
6.3
32Bit/16Bit
MD0 Quotient Low
MD1 Quotient
MD2 Quotient
MD3 Quotient High
MD4 Remainder L
MD5 Remainder H
16Bit/16Bit
MD0 Quotien Low
MD1 Quotien High
MD4 Remainder Low
MD5 Remainder High
16Bit x 16Bit
MD0 Product Low
MD1 Product
MD2 Product
shift/normalizing
MD0 LSB
MD1
MD2
MD3 Product High
MD3 MSB
Normalizing
All reading zeroes of integers variables in registers MD0 to MD3 are removed by shift left operations. The whole
operation is completed when the MSB (most significant bit) of MD3 register contains a ’1’. After normalizing, bits
ARCON.4 (MSB) to ARCON.0 (LSB) contain the number of shift left operations, which were done.
6.4
Shifting
SLR bit (ARCON.5) has to contain the shift direction, and ARCON.4 to ARCON.0 the shift count (which must not be 0).
During shift, zeroes come into the left or right end of the registers MD0 or MD3, respectively.
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SM39R16A6
8-Bit Micro-controller
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& 1K+256B RAM embedded
7. Timer 0 and Timer 1
The SM39R16A6 has three 16-bit timer/counter registers: Timer 0, Timer 1 and Timer 2. All can be configured for
counter or timer operations.
In timer mode, the Timer 0 register or Timer 1 register is incremented every 1/12/96 machine cycles, which means that
it counts up after every 1/12/96 periods of the clk signal. It’s dependent on SFR(PFCON).
In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin T0 or T1.
Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator
frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input
should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function registers (TMOD and TCON) are
used to select the appropriate mode.
Mnemonic
Description
Dir.
TL0
TH0
TL1
TH1
TMOD
Timer 0 , low byte
Timer 0 , high byte
Timer 1 , low byte
Timer 1 , high byte
Timer Mode Control
Timer/Counter
Control
Peripheral
Frequency control
register
8Ah
8Ch
8Bh
8Dh
89h
GATE
C/T
88h
TF1
TR1
D9h
-
-
TCON
PFCON
7.1
Bit 7
Bit 6
Bit 5
Timer 0 and 1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
M1
TL0[7:0]
TH0[7:0]
TL1[7:0]
TH1[7:0]
M0
GATE
C/T
M1
M0
00H
00H
00H
00H
00H
TF0
TR0
IT1
IE0
IT0
00H
SRELPS[1:0]
IE1
T1PS[1:0]
T0PS[1:0]
00H
Timer/Counter mode control register (TMOD)
Mnemonic: TMOD
7
6
5
GATE
C/T
M1
Timer 1
4
M0
3
GATE
2
1
C/T
M1
Timer 0
Address: 89h
0
Reset
M0
00h
GATE: If set, enables external gate control (pin INT0 or INT1 for Counter 0 or 1,
respectively). When INT0 or INT1 is high, and TRx bit is set (see TCON
register), a counter is incremented every falling edge on T0 or T1 input pin.
C/T: Selects Timer or Counter operation. When set to 1, a counter operation is
performed, when cleared to 0, the corresponding register will function as a
timer.
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8-Bit Micro-controller
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7.2
M1
0
M0
0
Mode
Mode0
0
1
1
0
Mode1
Mode2
1
1
Mode3
Function
13-bit counter/timer, with 5 lower bits in TL0 or
TL1 register and 8 bits in TH0 or TH1 register
(for Timer 0 and Timer 1, respectively). The 3
high order bits of TL0 and TL1 are hold at
zero.
16-bit counter/timer.
8-bit auto-reload counter/timer. The reload
value is kept in TH0 or TH1, while TL0 or TL1
is incremented every machine cycle. When
TLx overflows, a value from THx is copied to
TLx.
If Timer 1 M1 and M0 bits are set to 1, Timer 1
stops. If Timer 0 M1 and M0 bits are set to 1,
Timer 0 acts as two independent 8 bit timers /
counters.
Timer/counter control register (TCON)
Mnemonic: TCON
7
6
5
TF1
TR1
TF0
4
TR0
3
IE1
2
IT1
1
IE0
Address: 88h
0
Reset
IT0
00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR1: Timer 1 Run control bit. If cleared, Timer 1 stops.
TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR0: Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin
INT1 is observed. Cleared when interrupt is processed.
IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to
cause interrupt. IT1=1, interrupt 1 select falling edge trigger. IT1=0, interrupt1
select low level trigger.
IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin
INT0 is observed. Cleared when interrupt is processed.
IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to
cause interrupt. IT0=1, interrupt 0 select falling edge trigger. IT0=0, interrupt
0 select low level trigger.
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SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
7.3
Enhance Interrupt Trigger SFR(ENHIT)
Address: E5h
Mnemonic: ENHIT
7
6
5
ENHIT1
-
4
ENHIT0
3
-
2
-
1
-
0
-
Reset
07H
Note: It is supported the version D of MCU after.
ENHIT1: Interrupt 1 edge trigger control bit.
When ENHIT1 is set to 0 and IT1 is set to 1, The method of edge trigger is falling
edge trigger.
When ENHIT1 and IT1 both are set to 1, The method of edge trigger is rising edge
trigger.
ENHIT1=0
ENHIT1=1
IT1=0
INT1 low level trigger
INT1 low level trigger
IT1=1
INT1 failing edge trigger
INT1 rising edge trigger
ENHIT0: Interrupt 0 edge trigger control bit.
When ENHIT0 is set to 0 and IT0 is set to 1, The method of edge trigger is falling
edge trigger.
When ENHIT0 and IT0 both are set to 1, The method of edge trigger is rising edge
trigger.
7.4
ENHIT0=0
ENHIT0=1
IT0=0
INT0 low level trigger
INT0 low level trigger
IT0=1
INT0 failing edge trigger
INT0 rising edge trigger
Peripheral Frequency control register
Mnemonic: PFCON
7
6
-
5
4
SRELPS[1:0]
T1PS[1:0]: Timer1 Prescaler select
T0PS[1:0]
00
01
10
11
3
2
T1PS[1:0]
1
Address: D9h
0
Reset
T0PS[1:0]
00H
Prescaler
Fosc/12
Fosc
Fosc/96
reserved
T0PS[1:0]: Timer0 Prescaler select
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8-Bit Micro-controller
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T0PS[1:0]
00
01
10
11
7.5
Prescaler
Fosc/12
Fosc
Fosc/96
reserved
Mode 0 (13-bit Counter/Timer)
÷12
OSC
00
01
÷96
10
C/T = 1
T1PS[1:0]
T1 pin
TR1
GATE1
ET1
C/T = 0
TL1
TH1
(5 Bits) (8 Bits)
EA
0
1
1
Control
If not higher priority
Interrupt Processing
AND
NOT
TF1
0
Jump
001BH
OR
INT1 pin
D0D1D2D3D4
TL1
D5D6D7
D0D1D2D3D4D5D6D7
TF1
TH1
Fig. 7-1: Mode 0 -13 bit Timer / Counter operation
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SM39R16A6
8-Bit Micro-controller
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7.6
Mode 1 (16-bit Counter/Timer)
÷12
OSC
00
01
÷96
10
C/T = 1
T1PS[1:0]
T1 pin
TR1
GATE1
ET1
C/T = 0
TL1
TH1
(8 Bits) (8 Bits)
0
1
1
Control
Jump
001BH
If not higher priority
Interrupt Processing
AND
NOT
0
TF1
EA
OR
INT1 pin
D0D1D2D3D4D5D6D7
D0D1D2D3D4D5D6D7
TL1
TH1
TF1
Fig. 7-2: Mode 1 16 bit Counter/Timer operation
7.7
Mode 2 (8-bit auto-reload Counter/Timer)
÷12
OSC
00
01
÷96
10
C/T = 1
T1PS[1:0]
T1 pin
TR1
GATE1
INT1 pin
ET1
C/T = 0
TL1
(8 Bits)
OR
EA
0
1
1
Control
Auto
Reload
AND
NOT
TF1
0
TH1
(8 Bits)
If not higher priority
Interrupt Processing
Jump
001BH
Fig. 7-3: Mode 2 8-bit auto-reload Counter/Timer operation.
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SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
7.8
Mode 3 (Timer 0 acts as two independent 8 bit Timers / Counters)
÷12
00
TH0
(8 Bits)
TF1
Interrupt
Request
(001BH)
TL0
(8 Bits)
TF0
Interrupt
Request
(000BH)
TR1
OSC
01
÷96
C/T = 0
10
C/T = 1
T0PS[1:0]
T0 pin
TR0
GATE0
Control
AND
NOT
OR
/INT0 pin
Fig. 7-4: Mode 3 Timer 0 acts as two independent 8 bit Timers / Counters operatin
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Ver D SM39R16A6 06/30/2015
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SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
8. Timer 2 and Capture Compare Unit
Timer 2 is not only a 16-bit timer, also a 4-channel unit with compare, capture and reload functions. It is very similar to
the programmable counter array (PCA) in some other MCUs except pulse width modulation (PWM).
Mnemonic
Description
Dir.
AUX
T2CON
Auxiliary register
Timer 2 control
Compare/Capture
Control
Compare/Capture
Enable register
Compare/Capture
Enable 2 register
Timer 2, low byte
Timer 2, high byte
Compare/Reload/
Capture register,
low byte
Compare/Reload/
Capture register,
high byte
Compare/Capture
register 1, low byte
Compare/Capture
register 1, high byte
Compare/Capture
register 2, low byte
Compare/Capture
register 2, high byte
Compare/Capture
register 3, low byte
Compare/Capture
register 3, high byte
CCCON
CCEN
CCEN2
TL2
TH2
CRCL
CRCH
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
Bit 2
Bit 1
91h
C8h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Timer 2 and Capture Compare Unit
BRGS P21CC
P1UR
T2PS[2:0]
T2R[1:0]
-
-
C9h
CCI3
CCF2
CCF1
C1h
-
COCAM1[2:0]
-
COCAM0[2:0]
00H
D1h
-
COCAM3[2:0]
-
COCAM2[2:0]
00H
CCI2
CCI1
CCI0
CCF3
Bit 0
RST
DPS
T2I[1:0]
00H
00H
CCF0
00H
CCh
CDh
TL2[7:0]
TH2[7:0]
00H
00H
CAh
CRCL[7:0]
00H
CBh
CRCH[7:0]
00H
C2h
CCL1[7:0]
00H
C3h
CCH1[7:0]
00H
C4h
CCL2[7:0]
00H
C5h
CCH2[7:0]
00H
C6h
CCL3[7:0]
00H
C7h
CCH3[7:0]
00H
Mnemonic: AUX
7
6
BRGS
P21CC
5
-
4
P1UR
3
-
2
-
Address: 91h
0
Reset
DPS
00H
1
-
P21CC : P21CC = 0 – Capture/Compare function on P1.
P21CC = 1 – Capture/Compare function on P2.
Mnemonic: T2CON
7
6
5
T2PS[2:0]
4
3
T2R[1:0]
2
-
1
Address: C8h
0
Reset
T2I[1:0]
00H
T2PS[2:0]: Prescaler select bit:
T2PS = 000 – timer 2 is clocked with the oscillator frequency.
T2PS = 001 – timer 2 is clocked with 1/2 of the oscillator frequency.
T2PS = 010 – timer 2 is clocked with 1/4 of the oscillator frequency.
T2PS = 011 – timer 2 is clocked with 1/6 of the oscillator frequency.
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8-Bit Micro-controller
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T2PS = 100 – timer 2 is clocked with 1/8 of the oscillator frequency.
T2PS = 101 – timer 2 is clocked with 1/12 of the oscillator frequency.
T2PS = 110 – timer 2 is clocked with 1/24 of the oscillator frequency.
T2R[1:0]: Timer 2 reload mode selection
T2R[1:0] = 0X – Reload disabled.
T2R[1:0] = 10 – Mode 0: Auto Reload.
T2R[1:0] = 11 – Mode 1: T2EX Falling Edge Reload.
T2I[1:0]: Timer 2 input selection
T2I[1:0] = 00 – Timer 2 stop.
T2I[1:0] = 01 – Input frequency from prescaler (T2PS[2:0]).
T2I[1:0] = 10 – Timer 2 is incremented by external signal at pin T2.
T2I[1:0] = 11 – internal clock input is gated to the Timer 2.
Mnemonic: CCCON
7
6
5
CCI3
CCI2
CCI1
4
CCI0
3
CCF3
2
CCF2
1
CCF1
Address: C9h
0
Reset
CCF0
00H
CCI3: Compare/Capture 3 interrupt control bit.
CCI3 = 1 is enable.
CCI2: Compare/Capture 2 interrupt control bit.
CCI3 = 1 is enable.
CCI1: Compare/Capture 1 interrupt control bit.
CCI3 = 1 is enable.
CCI0: Compare/Capture 0 interrupt control bit.
CCI3 = 1 is enable.
CCF3: Compare/Capture 3 flag set by hardware. This flag can be cleared by software.
CCF2: Compare/Capture 2 flag set by hardware. This flag can be cleared by software.
CCF1: Compare/Capture 1 flag set by hardware. This flag can be cleared by software.
CCF0: Compare/Capture 0 flag set by hardware. This flag can be cleared by software.
Compare/Capture interrupt share T2 interrupt vector.
Mnemonic: CCEN
7
6
5
4
COCAM1[2:0]
3
-
2
Address: C1h
1
0
Reset
COCAM0[2:0]
00H
COCAM1[2:0] 000 - Compare/Capture disable.
001 - Compare enable but no output on Pin.
010 - Compare mode 0.
011 - Compare mode 1.
100 - Capture on rising edge at pin CC1.
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8-Bit Micro-controller
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101 - Capture on falling edge at pin CC1.
110 - Capture on both rising and falling edge at pin CC1.
111 - Capture on write operation into register CC1.
COCAM0[2:0] 000 - Compare/Capture disable.
001 - Compare enable but no output on Pin.
010 - Compare mode 0.
011 - Compare mode 1.
100 - Capture on rising edge at pin CC0.
101 - Capture on falling edge at pin CC0.
110 - Capture on both rising and falling edge at pin CC0.
111 - Capture on write operation into register CC0.
Mnemonic: CCEN2
7
6
5
4
COCAM3[2:0]
3
-
2
Address: D1h
1
0
Reset
COCAM2[2:0]
00H
COCAM3[2:0] 000 - Compare/Capture disable.
001 - Compare enable but no output on Pin.
010 - Compare mode 0.
011 - Compare mode 1.
100 - Capture on rising edge at pin CC3.
101 - Capture on falling edge at pin CC3.
110 - Capture on both rising and falling edge at pin CC3.
111 - Capture on write operation into register CC3.
COCAM2[2:0] 000 - Compare/Capture disable.
001 - Compare enable but no output on Pin.
010 - Compare mode 0.
011 - Compare mode 1.
100 - Capture on rising edge at pin CC2.
101 - Capture on falling edge at pin CC2.
110 - Capture on both rising and falling edge at pin CC2.
111 - Capture on write operation into register CC2.
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Ver D SM39R16A6 06/30/2015
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SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
8.1
Timer 2 function
Timer 2 can operate as timer, event counter, or gated timer as explained later.
8.1.1
Timer mode
In this mode Timer 2 can by incremented in various frequency that depending on the prescaler. The prescaler is
selected by bit T2PS[2:0] in register T2CON. As shown in Fig. 8-1
Fig. 8-1: Timer mode and Reload mode function
8.1.2
Event counter mode
In this mode, the timer is incremented when external signal T2 change value from 1 to 0. The T2 input is sampled in
every cycle. Timer 2 is incremented in the cycle following the one in which the transition was detected. As shown in Fig.
8-2.
Fig. 8-2: Event counter mode function
8.1.3
Gated timer mode
In this mode, the internal clock which incremented timer 2 is gated by external signal T2. As shown in Fig. 8-3
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SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Fig. 8-3: Gated timer mode function
8.1.4
Reload of Timer 2
Reload (16-bit reload from the crc register) can be executed in the following two modes:
Mode 0: Reload signal is generate by a Timer 2 overflows – autoreload.
Mode 1: Reload signal is generate by a negative transition at the corresponding input pin T2EX.
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SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
8.2
Compare function
In the four independent comparators, the value stored in any compare/capture register is compared with the contents
of the timer register. The compare modes 0 and 1 are selected by bits C0CAMx. In both compare modes, the results
of comparison arrives at Port 1 within the same machine cycle in which the internal compare signal is activated.
8.2.1
Compare Mode 0
In mode 0, when the value in Timer 2 equals the value of the compare register, the output signal changes from low to
high. It goes back to a low level on timer overflow. In this mode, writing to the port will have no effect, because the
input line from the internal bus and the write-to-latch line are disconnected. As shown in Fig. 8-4 illustrates the function
of compare mode 0.
Contents of
Timer 2
CRC or CCx
Reload value
CCx Output
Timer 2 = CCx value
Timer 2 overflow
Fig. 8-4: Compare mode 0 function
8.2.2
Compare Mode 1
In compare mode 1, the transition of the output signal can be determined by software. A timer 2 overflow causes no
output change. In this mode, both transitions of a signal can be controlled. As shown in Fig. 8-5 and Fig. 8-6 a
functional diagram of a register/port configuration in compare Mode 1. In compare Mode 1, the value is written first to
the “Shadow Register”, when compare signal is active, this value is transferred to the output register.
Fig. 8-5: Mode 1 Register/Port Function
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SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
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Contents of
Timer 2
CRC or CCx
Reload value
CCx Shadow Register
CCx Output
Timer 2 = CCx value
Timer 2 = CCx value
Fig. 8-6: Compare mode 1 function
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8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
8.3
Capture function
Actual timer/counter contents can be saved into registers CCx or CRC upon an external event (mode 0) or a software
write operation (mode 1).
8.3.1
Capture Mode 0 (by Hardware)
In mode 0, value capture of Timer 2 is executed when:
(1) Rising edge on input CC0-CC3
(2) Falling edge on input CC0-CC3
(3) Both rising and falling edge on input CC0-CC3
The contents of Timer 2 will be latched into the appropriate capture register. As shown in Fig. 8-7
Fig. 8-7: Capture mode 0 function
8.3.2
Capture Mode 1(by Software)
In mode 1, value capture of timer 2 is caused by writing any value into the low-order byte of the dedicated capture
register. The value written to the capture register is irrelevant to this function. The contents of Timer 2 will be latched
into the appropriate capture register. As shown in Fig. 8-8
Fig. 8-8: Capture mode 1 function
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9. Serial interface
The serial buffer consists of two separate registers, a transmit buffer and a receive buffer.
Writing data to the Special Function Register SBUF sets this data in serial output buffer and starts the transmission.
Reading from the SBUF reads data from the serial receive buffer. The serial port can simultaneously Transmit and
receive data. It can also buffer 1 byte at receive, which prevents the receive data from being lost if the CPU reads the
first byte before transmission of the second byte is completed.
Mnemonic
PCON
AUX
SCON
SRELL
SRELH
SBUF
PFCON
Description
Dir.
Bit 7
Power control
87H
SMOD
Auxiliary register
91h
BRGS
98H
SM0
SM1
AAH
SREL.
7
BAH
-
Serial Port control
register
Serial Port reload
register low byte
Serial Port reload
register high byte
Serial Port data
buffer
Peripheral
Frequency control
register
Bit 6
Bit 5
Serial interface
MDUF
P21C
C
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
-
-
-
STOP
IDLE
40H
P1UR
-
-
-
DPS
00H
SM2
REN
TB8
RB8
TI
RI
00H
SREL.
6
SREL.
5
SREL.
4
SREL.
3
SREL.
2
-
-
-
-
-
SREL.
1
SREL.
9
SREL.
0
SREL.
8
99H
SBUF[7:0]
D9h
Mnemonic: AUX
7
6
BRGS P21CC
-
5
-
4
P1UR
SRELPS[1:0]
3
1
-
2
RB8
1
TI
00H
00H
T1PS[1:0]
2
-
00H
T0PS[1:0]
00H
Address: 91h
0
Reset
DPS
00H
BRGS: Baud rate generator.
BRGS = 0 - baud rate generator from Timer 1.
BRGS = 1 - baud rate generator by SREL.
P1UR: P1UR = 0 - Serial interface function on P3.
P1UR = 1 - Serial interface function on P1.
Mnemonic: SCON
7
6
5
SM0
SM1
SM2
4
REN
3
TB8
Address: 98h
0
Reset
RI
00H
SM0, SM1: Serial Port 0 mode selection.
SM0
SM1 Mode
0
0
0
0
1
1
1
0
2
1
1
3
The 4 modes in UART, Mode 0 ~ 3, are explained later.
SM2: Enables multiprocessor communication feature.
REN: If set, enables serial reception. Cleared by software to disable reception.
TB8: The 9th transmitted data bit in modes 2 and 3. Set or cleared by the CPU depending on
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the function it performs such as parity check, multiprocessor communication etc.
RB8: In modes 2 and 3, it is the 9th data bit received. In mode 1, if SM2 is 0, RB8 is the stop
bit. In mode 0, this bit is not used. Must be cleared by software.
TI: Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be
cleared by software.
Receive interrupt flag, set by hardware after completion of a serial reception. Must be
RI:
cleared by software.
9.1
Serial interface
The Serial Interface can operate in the following 4 modes:
SM0
0
0
1
1
SM1
0
1
0
1
Mode
0
1
2
3
Description
Shift register
8-bit UART
9-bit UART
9-bit UART
Board Rate
Fosc/12
Variable
Fosc/32 or Fosc/64
Variable
Here Fosc is the crystal or oscillator frequency.
9.1.1
Mode 0
Pin RXD serves as input and output. TXD outputs the shift clock. 8 bits are transmitted with LSB first. The baud rate is
fixed at 1/12 of the crystal frequency. Reception is initialized in Mode 0 by setting the flags in SCON as follows: RI = 0
and REN = 1. In other modes, a start bit when REN = 1 starts receiving serial data. As shown in Fig. 9-1 and Fig. 9-2
Fig. 9-1: Transmit mode 0
Fig. 9-2: Receive mode 0
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SM39R16A6
8-Bit Micro-controller
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9.1.2
Mode 1
Pin RXD serves as input, and TXD serves as serial output. No external shift clock is used, 10 bits are transmitted: a
start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes the
transmission, 8 data bits are available by reading SBUF, and stop bit sets the flag RB8 in the Special Function Register
SCON. In mode 1 either internal baud rate generator or timer 1 can be use to specify baud rate. As shown in Fig. 9-3
and Fig. 9-4
Fig. 9-3: Transmit mode 1
Fig. 9-4: Receive mode 1
9.1.3
Mode 2
This mode is similar to Mode 1, with two differences. The baud rate is fixed at 1/32 (SMOD=1) or 1/64(SMOD=0) of
oscillator frequency and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable 9th
bit, and a stop bit (1). The 9th bit can be used to control the parity of the serial interface: at transmission, bit TB8 in
SCON is output as the 9th bit, and at receive, the 9th bit affects RB8 in Special Function Register SCON.
9.1.4
Mode 3
The only difference between Mode 2 and Mode 3 is that in Mode 3 either internal baud rate generator or timer 1 can be
use to specify baud rate. As shown in Fig. 9-5 and Fig. 9-6.
Fig. 9-5: Transmit modes 2 and 3
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Fig. 9-6: Receive modes 2 and 3
9.2
Multiprocessor Communication of Serial Interface
The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface can be used for multiprocessor communication. In
this case, the slave processors have bit SM2 in SCON set to 1. When the master processor outputs slave’s address, it
sets the 9th bit to 1, causing a serial port receive interrupt in all the slaves. The slave processors compare the received
byte with their network address. If there is a match, the addressed slave will clear SM2 and receive the rest of the
message, while other slaves will leave SM2 bit unaffected and ignore this message. After addressing the slave, the
host will output the rest of the message with the 9th bit set to 0, so no serial port receive interrupt will be generated in
unselected slaves.
9.3
Peripheral Frequency control register
Mnemonic: PFCON
7
6
5
4
SRELPS[1:0]
3
2
T1PS[1:0]
Address: D9h
1
0
Reset
T0PS[1:0]
00H
SRELPS[1:0]: SREL Prescaler select
SRELPS[1:0]
00
01
Prescaler
Fosc/64
Fosc /32
T1PS[1:0]: Timer1 Prescaler select
T1PS[1:0]
00
01
10
11
Prescaler
Fosc/12
Fosc
Fosc/96
reserved
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8-Bit Micro-controller
16KB with ISP Flash
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9.4
Baud rate generator
9.4.1
Serial interface modes 1 and 3
9.4.1.1
When BRGS = 0 (in Special Function Register AUX).
(1) T1PS[1:0] is 00
Baud Rate =
2 SMOD × Fosc
32 × 12 × (256 − TH1)
(2) T1PS[1:0] is 01
Baud Rate =
2 SMOD × Fosc
32 × (256 − TH1)
(3) T1PS[1:0] is 10
Baud Rate =
9.4.1.2
2 SMOD × Fosc
32 × 96 × (256 − TH1)
When BRGS = 1 (in Special Function Register AUX).
(1) SRELPS[1:0] is 00
2 SMOD × Fosc
Baud Rate =
64 × 210 − SREL
(
)
(2) SRELPS[1:0] is 01
2 SMOD × Fosc
Baud Rate =
32 × 210 − SREL
(
)
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SM39R16A6
8-Bit Micro-controller
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10. Watchdog timer
The Watch Dog Timer (WDT) is an 8-bit free-running counter that generate reset signal if the counter overflows. The
WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing
software dead loop or runaway. The WDT function can help user software recover from abnormal software condition.
The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by
software periodically clearing the WDT counter. User should check WDTF bit of WDTC register whenever un-predicted
reset happened. After an external reset the watchdog timer is disabled and all registers are set to zeros.
The watchdog timer has a free running on-chip RC oscillator (23 KHz). The WDT will keep on running even after the
system clock has been turned off (for example, in sleep mode). During normal operation or sleep mode, a WDT timeout (if enabled) will cause the MCU to reset. The WDT can be enabled or disabled any time during the normal mode.
Please refer the WDTE bit of WDTC register. The default WDT time-out period is approximately 178.0ms (WDTM [3:0]
= 0100b).
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit3 ~
bit0 (WDTM [3:0]) of Watch Dog Timer Control Register (WDTC) should be set accordingly. As shown in Table 10-1.
23KHz
2 WDTM
256
Watchdog reset time =
WDTCLK
WDTCLK =
Table 10-1: WDT time-out period
Divider
Time period @ 23KHz
WDTM [3:0]
(23 KHz RC oscillator in)
0000
1
11.1ms
0001
2
22.2ms
0010
4
44.5ms
0011
8
89.0ms
0100
16
178.0ms (default)
0101
32
356.1ms
0110
64
712.3ms
0111
128
1.4246s
1000
256
2.8493s
1001
512
5.6987s
1010
1024
11.397s
1011
2048
22.795s
1100
4096
45.590s
1101
8192
91.180s
1110
16384
182.36s
1111
32768
364.72s
Note: RC oscillator (23 KHz), about ± 20% of variation
When MCU is reset, the MCU will be read WDTEN control bit status. When WDTEN bit is set to 1, the watchdog
function will be disabled no matter what the WDTE bit status is. When WDTEN bit is clear to 0, the watchdog function
will be enabled if WDTE bit is set to 1 by program. User can to set WDTEN on the writer or ISP.
The program can enable the WDT function by programming 1 to the WDTE bit premise that WDTEN control bit is clear
to 0. After WDTE set to 1, the 8 bit-counter starts to count with the selected time base source clock which set by
WDTM [3:0]. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when MCU
been reset, either hardware reset or WDT reset. As shown in Fig. 10-1.
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Once the watchdog is started it cannot be stopped. User can refreshed the watchdog timer to zero by writing 0x55 to
Watch Dog Timer refresh Key (WDTK) register. This will clear the content of the 8-bit counter and let the counter restart to count from the beginning. The watchdog timer must be refreshed regularly to prevent reset request signal from
becoming active.
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The WDTF flag can be
clear by software or external reset or power on reset.
Clear
WDTF = 0
1. Power on reset
2. External reset
3. Software write “0”
23KHz RC
oscillator
Set WDTF = 1
CWDTR = 0
WDTCLK
1
TAKEY
(55, AA, 5A)
WDTF
2WDTM
WDTM[3:0]
Enable/Disable
WDT
WDT time-out
reset
WDT
time-out
select
WDT
Counter
CWDTR = 1
Refresh
WDT Counter
WDT time-out
Interrupt
WDTC
Enable WDTC
write attribute
WDTK
(0x55)
WDTEN
Fig. 10-1: Watchdog timer block diagram
Mnemonic
TAKEY
WDTC
WDTK
RSTS
Description
Time Access
Key register
Watchdog timer
control register
Watchdog timer
refresh key
Reset status
register
Dir.
Bit 7
Bit 6
Bit 5
Watchdog Timer
Bit 4
F7h
Bit 3
Bit 2
Bit 1
Bit 0
TAKEY [7:0]
B6h
-
CWDTR
WDTE
-
B7h
00H
WDTM [3:0]
04H
WDTK[7:0]
A1h
-
Mnemonic: TAKEY
7
6
5
LVRLP
INTF
LVRLP
F
4
3
TAKEY [7:0]
PDRF
2
WDTF
1
RST
00H
SWRF
LVRF
PORF
00H
Address: F7h
0
Reset
00H
Watchdog timer control register (WDTC) is read-only by default; software must write three specific values 55h, AAh and
5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
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SM39R16A6
8-Bit Micro-controller
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Mnemonic: WDTC
7
6
CWDTR
5
WDTE
4
-
3
2
1
WDTM [3:0]
Address: B6h
0
Reset
04H
CWDTR: Watch dog states select bit(Support stop mode wakeup)
CWDTR = 0 - Enable watch dog reset.
CWDTR = 1 - Enable watch dog interrupt.
WDTE: Control bit used to enable Watchdog timer.
The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT
can be disabled / enabled by the WDTE bit.
WDTE = 0 - Disable WDT.
WDTE = 1 - Enable WDT.
The WDTE bit is not used if WDTEN is "1". That is, if the WDTEN bit is "1", WDT is
always disabled no matter what the WDTE bit status is. The WDTE bit can be read
and written.
WDTM [3:0]: WDT clock source divider bit. As seen in Fig. 10-1 to reference the WDT time-out
period.
Mnemonic: RSTS
7
6
5
LVRLP LVRLP
INTF
F
4
3
2
1
PDRF
WDTF
SWRF
LVRF
Address: A1h
0
Reset
PORF
00h
WDTF: Watchdog timer reset flag. When MCU is reset by watchdog, WDTF flag will be set to
one by hardware. This flag clear by software
Mnemonic: WDTK
7
6
5
4
3
WDTK[7:0]
2
1
Address: B7h
0
Reset
00h
WDTK: Watchdog timer refresh key.
A programmer must write 0x55 into WDTK register, and then the watchdog
timer will be cleared to zero.
For example 1, if enable WDT and select time-out reset period is 2.8493s.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
; enable WDTC write attribute.
MOV WDTC, #28h
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT function.
.
.
.
MOV WDTK, #55h
; Clear WDT timer to 0.
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8-Bit Micro-controller
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For example 2, if enable WDT and select time-out Interrupt period is 178.0ms.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
; enable WDTC write attribute.
MOV WDTC, #64h
;Set WDTM [3:0] = 0100b. ;Set WDTE =1 to enable WDT function
; and Set CWDTR =1 to enable period interrupt function
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11. Interrupt
The SM39R16A6 provides 12 interrupt sources with four priority levels. Each source has its own request flag(s) located
in a special function register. Each interrupt requested by the corresponding flag could individually be enabled or
disabled by the enable bits in SFR’s IEN0, IEN1.
When the interrupt occurs, the engine will vector to the predetermined address as given in Table 11-1. Once interrupt
service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a
return from instruction RETI. When an RETI is performed, the processor will return to the instruction that would have
been next when interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless
of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, and then
samples are polled by hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then
interrupt request flag is set. On the next instruction cycle the interrupt will be acknowledged by hardware forcing an
LCALL to appropriate vector address.
Interrupt response will require a varying amount of time depending on the state of microcontroller when the interrupt
occurs. If microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be
invoked. In other cases, the response time depends on current instruction. The fastest possible response to an
interrupt is 7 machine cycles. This includes one machine cycle for detecting the interrupt and six cycles for perform the
LCALL.
1
Table 11-1: Interrupt vectors
Interrupt Vector
Interrupt Request Flags
Address
IE0 – External interrupt 0
0003h
2
TF0 – Timer 0 interrupt
000Bh
1
3
IE1 – External interrupt 1
0013h
2
4
TF1 – Timer 1 interrupt
001Bh
3
5
RI/TI – Serial channel interrupt
0023h
4
6
TF2/EXF2 – Timer 2 interrupt
002Bh
5
7
PWMIF – PWM interrupt
0043h
8
8
SPIIF – SPI interrupt
004Bh
9
9
ADCIF – A/D converter interrupt
0053h
10
10
LVIIF – Low Voltage Interrupt
0063h
12
11
IICIF – IIC interrupt
006Bh
13
12
WDT – Watchdog interrupt
008Bh
17
Interrupt Number
*(use Keil C Tool)
0
*See Keil C about C51 User’s Guide about Interrupt Function description
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Mnemonic
IEN0
IEN1
IEN2
IRCON
IRCON2
IP0
IP1
Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
ET2
ES
ET1
EX1
ET0
EX0
00H
-
IEIIC
IELVI
-
IEADC
IESPI
-
00H
-
-
-
-
-
-
EWDT
-
00H
C0H
EXF2
TF2
IICIF
LVIIF
-
ADCIF
SPIIF
-
00H
97H
-
-
-
-
-
-
WDTIF
-
00H
A9H
-
-
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
00H
B9H
-
-
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
00H
Mnemonic: IEN0
7
6
EA
-
5
ET2
4
ES
Interrupt Enable
0 register
Interrupt Enable
1 register
Interrupt Enable
2 register
Interrupt request
register
Interrupt request
register 2
Interrupt priority
level 0
Interrupt priority
level 1
Dir.
Bit 7
Bit 6
A8H
EA
-
B8H
EXEN2
9AH
Bit 5
Interrupt
3
ET1
2
EX1
1
ET0
Address: A8h
0
Reset
EX0
00h
EA: EA=0 – Disable all interrupt.
EA=1 – Enable all interrupt.
ET2: ET2=0 – Disable Timer 2 overflow or external reload interrupt.
ET2=1 – Enable Timer 2 overflow or external reload interrupt.
ES: ES=0 – Disable Serial channel interrupt.
ES=1 – Enable Serial channel interrupt.
ET1: ET1=0 – Disable Timer 1 overflow interrupt.
ET1=1 – Enable Timer 1 overflow interrupt.
EX1: EX1=0 – Disable external interrupt 1.
EX1=1 – Enable external interrupt 1.
ET0: ET0=0 – Disable Timer 0 overflow interrupt.
ET0=1 – Enable Timer 0 overflow interrupt.
EX0: EX0=0 – Disable external interrupt 0.
EX0=1 – Enable external interrupt 0.
Mnemonic: IEN1
7
6
EXEN2
-
5
IEIIC
4
IELVI
3
-
2
IEADC
1
IESPI
Address: B8h
0
Reset
00H
EXEN2: Timer 2 reload interrupt enable.
EXEN2 = 0 – Disable Timer 2 external reload interrupt.
EXEN2 = 1 – Enable Timer 2 external reload interrupt.
IEIIC: IIC interrupt enable.
IEIICS = 0 – Disable IIC interrupt.
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8-Bit Micro-controller
16KB with ISP Flash
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IEIICS = 1 – Enable IIC interrupt.
IELVI: LVI interrupt enable.
IELVI = 0 – Disable LVI interrupt.
IELVI = 1 – Enable LVI interrupt.
IEADC: A/D converter interrupt enable
IEADC = 0 – Disable ADC interrupt.
IEADC = 1 – Enable ADC interrupt.
IESPI: SPI interrupt enable.
IESPI = 0 – Disable SPI interrupt.
IESPI = 1 – Enable SPI interrupt.
Mnemonic: IEN2
7
6
-
5
-
4
-
3
-
2
-
1
EWDT
Address: 9Ah
0
Reset
00H
EWDT: Enable Watch dog interrupt.
EWDT = 0 – Disable Watch dog interrupt.
EWDT = 1 – Enable Watch dog interrupt.
Mnemonic: IRCON
7
6
5
EXF2
TF2
IICIF
4
LVIIF
3
-
2
ADCIF
1
SPIIF
Address: C0h
0
Reset
00H
EXF2: Timer 2 external reload flag. Must be cleared by software.
TF2: Timer 2 overflow flag. Must be cleared by software.
IICIF: IIC interrupt flag. Hardware will clear this flag automatically when enter interrupt vector.
LVIIF: LVI interrupt flag. Hardware will clear this flag automatically when enter interrupt vector.
ADCIF: A/D converter end interrupt flag. Hardware will clear this flag automatically when enter
interrupt vector.
SPIIF: SPI interrupt flag. Hardware will clear this flag automatically when enter interrupt vector.
Mnemonic:IRCON2
7
6
-
5
-
4
-
3
-
2
-
1
WDTIF
Address: 97h
0
Reset
00H
WDTIF: Watch dog interrupt flag. Hardware will clear this flag automatically when enter interrupt
vector.
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SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
11.1 Priority level structure
All interrupt sources are combined in groups, As given in Table 11-2.
Table 11-2: Priority level groups
Groups
Watchdog interrupt
-
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel interrupt
Timer 2 interrupt
PWM interrupt
SPI interrupt
ADC interrupt
LVI interrupt
IIC interrupt
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one
bit in the special function register IP0 and one in IP1. If requests of the same priority level will be received
simultaneously, an internal polling sequence determines which request is serviced first. As given in Table 11-3 and
Table 11-4 and Table 11-5.
Mnemonic: IP0
7
6
-
5
IP0.5
4
IP0.4
3
IP0.3
2
IP0.2
1
IP0.1
Address: A9h
0
Reset
IP0.0
00h
Mnemonic: IP1
7
6
-
5
IP1.5
4
IP1.4
3
IP1.3
2
IP1.2
1
IP1.1
Address: B9h
0
Reset
IP1.0
00h
Table 11-3: Priority levels
IP1.x
IP0.x
Priority Level
0
0
1
1
Bit
IP1.0, IP0.0
IP1.1, IP0.1
IP1.2, IP0.2
IP1.3, IP0.3
IP1.4, IP0.4
IP1.5, IP0.5
0
1
0
1
Level0 (lowest)
Level1
Level2
Level3 (highest)
Table 11-4: Groups of priority
Group
External interrupt 0
Timer 0 interrupt
Watchdog interrupt
External interrupt 1
Timer 1 interrupt
Serial channel interrupt
Timer 2 interrupt
-
PWM interrupt
SPI interrupt
ADC interrupt
LVI interrupt
IIC interrupt
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 60 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Table 11-5: Polling sequence
Interrupt source
Sequence
External interrupt 0
PWM interrupt
Timer 0 interrupt
SPI interrupt
External interrupt 1
ADC interrupt
Timer 1 interrupt
Serial channel interrupt
Polling sequence
Watchdog interrupt
LVI interrupt
Timer 2 interrupt
IIC interrupt
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 61 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
12. Power Management Unit
Power management unit serves two power management modes, IDLE and STOP, for the users to do power saving
function.
Mnemonic: PCON
7
6
SMOD MDUF
5
-
4
-
3
-
2
-
1
STOP
Address: 87h
0
Reset
IDLE
40h
STOP: Stop mode control bit. Setting this bit turning on the Stop Mode.
Stop bit is always read as 0
IDLE: Idle mode control bit. Setting this bit turning on the Idle Mode.
Idle bit is always read as 0
12.1 Idle mode
Setting the IDLE bit of PCON register invokes the IDLE mode. The IDLE mode leaves internal clocks and peripherals
running. Power consumption drops because the CPU is not active. The CPU can exit the IDLE state with any interrupts
or a reset.
12.2 Stop mode
Setting the STOP bit of PCON register invokes the STOP mode. All internal clocking in this mode is turn off. The CPU
will exit this state from a no-clocked interrupt (external INT0/1, LVI and Watchdog interrupt) or a reset (WDT and LVR)
condition. Internally generated interrupts (timer, serial port ...) have no effect on stop mode since they require clocking
activity.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 62 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
13. Pulse Width Modulation (PWM)
PWM module features:

Four-channel (tow-pair) PWM output pins.

14-bit resolution.
The interrupt vector is 43h.
Mnemonic
Description
Dir.
Bit 7
Bit 6
PWMTBC0
PWM Time Base
Control 0 Reg.
F9h
-
-
-
-
PWMTBC1
PWM Time Base
Control 1 Reg.
FAh
PWM
TBEN
-
-
PWM
Protec
tDIS
-
-
-
PWMP
IE
10H
PWMOP
MOD
PWM Output Pair
Mode Reg.
FBh
-
-
-
-
PWM
OP3
MOD
PWMO
P2
MOD
-
-
00H
PERIODL
PERIODH
PWMEN
PWMTB
POST
SCALE
PWMINTF
PWMPOLA
RITY
DUTY2L
DUTY2H
DUTY3L
DUTY3H
PWM Period
(Low) Reg.
PWM Period
(High) Reg.
PWM Output
Enable Reg.
PWM Time Base
Post Scale Reg.
PWM INT Flag
Reg.
PWM Polarity
Reg.
PWM 2 Duty Low
byte Reg.
PWM 2 Duty
High byte Reg.
PWM 3 Duty Low
byte Reg.
PWM 3 Duty
High byte Reg.
Bit 5
PWM
F1h
Bit 4
Bit 3
Bit 2
PWMTBPRE
[1:0]
Bit 1
Bit 0
RST
PWMTBMOD
[1:0]
00H
PWM Period Low 8 bit
F2h
-
-
F5h
PWM7
EN
PWM6
EN
FFH
PWM Period High 6 bit
PWM5
EN
EEh
PWM4
EN
-
-
3FH
-
-
PWMTBPOST[7:0]
00H
00H
BCh
PWM
TBDIR
-
-
-
-
-
-
PWMP
IF
00H
DDh
Polarity
7
Polarity
6
Polarity
5
Polarity
4
-
-
-
-
FFH
D5h
D6h
PWM2 Duty Low 8 bit
-
-
D7h
C9h
PWM2 Duty High 6 bit
PWM3 Duty Low 8 bit
-
-
PWM3 Duty High 6 bit
00H
00H
00H
00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 63 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Mnemonic: PWMTBC0
(PWM Time Base Control 0)
7
6
5
-
Address: F9h
4
-
3
2
PWMTBPRE[1:0]
1
0
PWMTBMOD[1:0]
Reset
00H
PWMTBPRE[1:0]: PWM Time Base PreScale.
PWMTBPRE
[1:0]
00
01
10
11
Mode
Fosc
Fosc/4
Fosc/16
Fosc/64
PWMTBMOD: PWM Time Base Mode.
PWMTBMOD [1:0] = 00 - Free Running mode (Edge-align).
PWMTBMOD [1:0] = 01 - Single-shot mode (Edge-align).
PWMTBMOD [1:0] = 10 - Continuous up/down counting mode (Center-align).
( TBCOUNTER = PERIOD generate an interrupt)
PWMTBMOD [1:0] = 11 - Continuous up/down counting with interrupt for double PWM
updates (Center-align). (TBCOUNTER = PERIOD and TBCOUNTER = 0 generate an
interrupt)
Freq = 24MHz, Period = 14 bit
PWM Frequency Edge-align
PWM Frequency Center-align
1500 Hz
750 Hz
375 Hz
188 Hz
94 Hz
47 Hz
23 Hz
12 Hz
Prescale
1:1
1:4
1:16
1:64
Mnemonic: PWMTBC1
(PWM Time Base Control 1)
7
6
5
PWMTB
EN
Address: FAh
4
PWMPro
tectDIS
3
2
1
0
Reset
-
-
-
PWMPIE
10H
PWMTBEN: PWM Time Base Enable
0 = PWM Time Base Disable.
1 = PWM Time Base Enable.
WMProtectDIS: PWM Protect Set (fool proof circuit)
0 = Enable. (Aaply to complementary mode)
1 = Disable.
PWM4/PWM5, PWM6/PWM7, Protect enable/disable.
PWMPIE: PWM Period Interrupt Enable
PWMPIE = 0 - PWM Period Interrupt Diable.
PWMPIE = 1 - PWM Period Interrupt Enable.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 64 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Fig. 13-1: Opertion of the PWM Protect Mode
Mnemonic: PWMOPMOD
(PWM Output Pair Mode)
7
6
-
-
Address: FBh
5
4
-
-
3
PWMOP3
MOD
2
PWMOP2
MOD
1
0
Reset
-
-
00H
PWMOP3MOD: PWM Output Pair 3 Mode.
0 = (PWM6, PWM7) is complementary mode.
1 = (PWM6, PWM7) is independent mode.
PWMOP2MOD: PWM Output Pair 2 Mode.
0 = (PWM4, PWM5) is complementary mode.
1 = (PWM4, PWM5) is independent mode.
Mnemonic: PWMEN
7
6
PWM7EN PWM6EN
5
PWM5EN
4
PWM4EN
3
-
2
-
1
-
Address: F5h
0
Reset
00H
PWM7EN: PWM 7 Enable.
PWM7EN = 0 - PWM7 Output Disable.
PWM7EN = 1 - PWM7 Output Enable.
PWM6EN: PWM 6 Enable.
PWM6EN = 0 - PWM6 Output Disable.
PWM6EN = 1 - PWM6 Output Enable.
PWM5EN: PWM 5 Enable.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 65 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
PWM5EN = 0 - PWM5 Output Disable.
PWM5EN = 1 - PWM5 Output Enable.
PWM4EN: PWM 4 Enable.
PWM4EN = 0 - PWM4 Output Disable.
PWM4EN = 1 - PWM4 Output Enable.
Mnemonic: PWMTBPOSTSCALE
7
6
5
4
3
PWMTBPOST [7:0]
2
1
0
Address: EEh
Reset
00H
PWMTBPOST[7:0] PWM Time Base Post Scale. (How many PWM period happen will a triger need)
0000_0000 = 1: 1 Postscale
0000_0001 = 1: 2 Postscale
:
:
0000_1111 = 1: 16 Postscale
0001_0000 = 1: 17 Postscale
:
:
1111_1111 = 1: 256 Postscale
Mnemonic: PWMINTF
(PWM Interrupt Flag)
7
6
PWMTB
DIR
Address: BCh
5
4
3
2
1
-
-
-
-
-
0
PWMP
IF
Reset
00H
PWMTBDIR: PWM Time Base Count Direction Status.(Read only)
0 = counts up.
1 = counts down.
PWMPIF: PWM Period Interrupt Flag. Must be cleared by software.
Mnemonic: PWMPOLARITY
7
6
5
POLARITY POLARITY POLARITY
7
6
5
4
POLARITY
4
3
2
1
Address: DDh
0
Reset
-
-
-
-
FFH
POLARITY7: PWM Polarity 7
POLARITY7 = 0 - PWM7 Polarity active low.
POLARITY7 = 1 - PWM7 Polarity active high.
POLARITY6: PWM Polarity 6
POLARITY6 = 0 - PWM6 Polarity active low.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 66 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
POLARITY6 = 1 - PWM6 Polarity active high.
POLARITY5: PWM Polarity 5
POLARITY5 = 0 - PWM5 Polarity active low.
POLARITY5 = 1 - PWM5 Polarity active high.
POLARITY4: PWM Polarity 4
POLARITY4 = 0 - PWM4 Polarity active low.
POLARITY4 = 1 - PWM4 Polarity active high.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 67 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
14. IIC function
The IIC module uses the SCL (clock) and the SDA (data) line to communicate with external IIC interface. Its speed can
be selected to 400Kbps (maximum) by software setting the IICBR [2:0] control bit. The IIC module provided 2 interrupts
(RXIF, TXIF). It will generate START, repeated START and STOP signals automatically in master mode and can
detects START, repeated START and STOP signals in slave mode. The maximum communication length and the
number of devices that can be connected are limited by a maximum bus capacitance of 400pF.
Mnemonic
Description
Dir.
The interrupt vector is 6Bh.
Bit 7
Bit 6
Bit 5
Bit 4
IIC function
AB_E
IICEN
MSS
MAS
N
Bit 3
IIC control
register
F9h
IICS
IIC status register
F8h
IICA1
IIC Address 1
register
FAh
IICA1[7:1]
IICA2
IIC Address 2
register
FBh
IICA2[7:1]
IICCTL
IICRWD
IICEBT
IIC Read/Write
register
IIC Enaable Bus
Transaction
-
MPIF
LAIF
FDh
BF_EN
RXIF
FCh
Bit 2
TXIF
Bit 1
Bit 0
IICBR[2:0]
RXAK
TXAK
04H
RW or
BB
MATC
H1or
RW1
MATC
H2 or
RW2
IICRWD[7:0]
FU_EN
Mnemonic: IICCTL
7
6
5
IICEN
MSS
MAS
4
AB_EN
-
3
BF_EN
-
2
-
1
IICBR[2:0]
RST
00H
A0H
60H
00H
-
-
-
00H
Address: F9h
0
Reset
04h
IICEN: Enable IIC module
IICEN = 1 is Enable.
IICEN = 0 is Disable.
MSS: Master or slave mode select.
MSS = 1 is master mode.
MSS = 0 is slave mode.
*The software must set this bit before setting others register.
MAS: Master address select (master mode only)
MAS = 0 is to use IICA1.
MAS = 1 is to use IICA2.
AB_EN: Arbitration lost enable bit. (Master mode only)
If set AB_EN bit, the hardware will check arbitration lost. Once arbitration lost occurred,
hardware will return to IDLE state. If this bit is cleared, hardware will not care arbitration lost
condition. Set this bit when multi-master and slave connection. Clear this bit when single
master to single slave.
BF_EN: Bus busy enable bit. (Master mode only)
If set BF_EN bit, hardware will not generate a start condition to bus until BF=0. Clear this bit
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 68 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
will always generate a start condition to bus when MStart is set. Set this bit when multi-master
and slave connection. Clear this bit when single master to single slave.
IICBR[2:0]: Baud rate selection (master mode only), where Fosc is the external crystal or oscillator
frequency. The default is Fosc/512 for users’ convenience.
IICBR[2:0]
000
001
010
011
100
101
110
111
Mnemonic: IICS
7
6
MPIF
5
LAIF
Baud rate
Fosc/32
Fosc/64
Fosc/128
Fosc/256
Fosc/512
Fosc/1024
Fosc/2048
Fosc/4096
4
RXIF
3
TXIF
2
RXAK
1
TxAK
Address: F8H
0
Reset
RW or BB
00H
MPIF: The Stop condition Interrupt Flag
The stop condition occurred and this bit will be set. Software need to clear this bit
LAIF: Arbitration lost bit. (Master mode only)
The Arbitration Interrupt Flag, the bus arbitration lost occurred and this bit will be set. Software need
to clear this bit
RxIF: The data Receive Interrupt Flag (RXIF) is set after the IICRWD (IIC Read Write Data Buffer) is
loaded with a newly receive data.
TxIF: The data Transmit Interrupt Flag (TXIF) is set when the data of the IICRWD (IIC Read Write Data
Buffer) is downloaded to the shift register.
RxAK: The Acknowledge Status indicate bit. When clear, it means an acknowledge signal has been
received after the complete 8 bits data Transmit on the bus.
TxAK: The Acknowledge status Transmit bit. When received complete 8 bits data, this bit will set (NoAck)
or clear (Ack) and Transmit to master to indicate the receive status.
RW or BB: Master Mode:
BB : Bus busy bit
If detect scl=0 or sda=0 or bus start, this bit will be set. If detect stop,this bit will be cleared. This bit
can be cleared by software to return ready state.
Slave Mode:
RW:The slave mode read (received) or wrote (Transmit) on the IIC bus. When this bit is clear, the
slave module received data on the IIC bus (SDA).(Slave mode only).
As shown in Fig. 14-1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 69 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Fig. 14-1: Acknowledgement bit in the 9th bit of a byte transmission
Mnemonic: IICA1
7
6
5
4
IICA1[7:1]
R/W
3
2
1
Address: FA
0
Reset
Match1 or RW1 A0H
R or R/W
Slave mode:
IICA1[7:1]: IIC Address registers
This is the first 7-bit address for this slave module. It will be checked when an address (from
master) is received
Match1: When IICA1 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets first data, this bit will clear.
Master mode:
IICA1[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW1: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit.
It appears at the 8th bit after the IIC address as below figure. It is used to tell the salve the
direction of the following communication. If it is 1, the module is in master receive mode. If 0,
the module is in master Transmit mode. As shown in Fig. 14-2
RW1=1, master receive mode
RW1=0, master Transmit mode
Fig. 14-2: RW bit in the 8th bit after IIC address
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 70 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Mnemonic: IICA2
7
6
5
4
IICA2[7:1]
3
2
Address: FB
0
Reset
Match2 or RW2 60H
1
R/W
R or R/W
Slave mode:
IICA2[7:1]: IIC Address registers
This is the second 7-bit address for this slave module.
It will be checked when an address (from master) is received
Match2: When IICA2 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets first data, this bit will clear.
Master mode:
IICA2[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW2: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit.
It is used to tell the salve the direction of the following communication. If it is 1, the module is
in master receive mode. If 0, the module is in master Transmit mode.
RW2=1, master receive mode
RW2=0, master Transmit mode
Mnemonic: IICRWD
7
6
5
4
3
IICRWD[7:0]
2
1
Address: FCh
0
Reset
00h
IICRWD[7:0]: IIC read write data buffer.
In receiving (read) mode, the received byte is stored here.
In Transmitting mode, the byte to be shifted out through SDA stays here.
Mnemonic: IICEBT
7
6
FU_EN
5
-
4
-
3
-
2
-
1
-
0
-
Address: FDH
Reset
00H
Master Mode：
00: reserved
01: IIC bus module will enable read/write data transfer on SDA and SCL.
10: IIC bus module generate a start condition on the SDA/SCL, then send out address which is
stored in the IICA1/IICA2(selected by MAS control bit)
11: IIC bus module generates a stop condition on the SDA/SCL.
FU_EN[7:6] will be auto-clear by hardware, so setting FU_EN[7:6] repeatedly is necessary.
Slave mode:
01: FU_EN[7:6] should be set as 01 only. The other value is inhibited.
Notice:
FU_EN[7:6] should be set as 01 before read/write data transfer for bus release; otherwise,
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 71 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
SCL will be locked(pull low).
FU_EN[7:6] should be set as 01 after read/write data transfer for receiving a stop condition
from bus master.
In Transmit data mode (slave mode), the output data should be filled into IICRWD before
setting FU_EN[7:6] as 01.
FU_EN[7:6] will be auto-clear by hardware, so setting FU_EN[7:6] repeatedly is necessary.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 72 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
15. SPI Function - Serial Peripheral Interface
Serial Peripheral Interface (SPI) is a synchronous protocol that allows a master device to initiate communication with
slave devices.
The interrupt vector is 4Bh.
There are 4 signals used in SPI, they are
SPI_MOSI: data output in the master mode, data input in the slave mode,
SPI_MISO: data input in the master mode, data output in the slave mode,
SPI_SCK: clock output from the master, the above data are synchronous to this signal.
SPI_SS: input in the slave mode.
This slave device detects this signal to judge if it is selected by the master. As shown in Fig. 15-1
In the master mode, it can select the desired slave device by any IO with value = 0. As below figure is an example
showing the relation of the 4 signals between master and slaves.
Master
Slave 2
Slave 1
MOSI
MISO
CLK
IO
IO
MOSI
MISO
CLK
MOSI
MISO
CLK
SS
SS
Fig. 15-1: SPI signals between master and slave devices
There is only one channel SPI interface. The SPI SFRs are shown as below:
Mnemonic
SPIC1
SPIC2
SPIS
SPITXD
SPIRXD
Description
SPI control
register 1
SPI control
register 2
SPI status
register
SPI Transmit
data buffer
SPI receive
data buffer
Dir.
Bit 7
F1h
SPIEN
F2h
SPIFD
F5h
SPIRF
Bit 6
Bit 5
Bit 4
SPI function
SPIMS SPISS SPICK
S
P
P
Bit 3
SPIML
S
SPICK
E
SPIRS
T
SPITD
R
TBC[2:0]
SPIOV
SPITXI
F
Bit 2
SPIRXI
F
Bit 1
Bit 0
RST
SPIBR[2:0]
08H
RBC[2:0]
00H
SPIRD
R
SPIRS
40H
F3h
SPITXD[7:0]
00H
F4h
SPIRXD[7:0]
00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 73 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Mnemonic:SPIC1
7
6
SPIEN
SPIMSS
5
SPISSP
4
SPICKP
3
SPICKE
2
1
SPIBR[2:0]
Address:F1H
0
Reset
08H
SPIEN: Enable SPI module.
SPIEN = 1 - is Enable.
SPIEN = 0 - is Disable.
SPIMSS: Master or Slave mode Select
SPIMSS = 1 - is Master mode.
SPIMSS = 0 - is Slave mode.
SPISSP: SS or CS active polarity.(Slave mode used only)
SPISSP = 1 - high active.
SPISSP = 0 - low active.
SPICKP: Clock idle polarity select.
SPICKP = 1 - SCK will idle high. Ex :
SPICKP = 0 - SCK will idle low. Ex :
SPICKE: Clock sample edge select.
SPICKE = 1 - rising edge latch data.
SPICKE = 0 - falling edge latch data.
* To ensure the data latch stability, SM39R16A6 generate the output data As shown in the
following example, the other side can latch the stable data no matter in rising or falling edge.
sufficient set-up time
sufficient hold time
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 74 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
SPIBR[2:0]: SPI baud rate select. (Master mode used only)
SPIBR[2:0]
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Baud rate
Fosc/4
Fosc /8
Fosc /16
Fosc /32
Fosc /64
Fosc /128
Fosc /256
Fosc /512
Mnemonic: SPIC2
7
6
5
SPIFD
TBC[2:0]
4
3
SPIRST
2
1
RBC[2:0]
Address: F2H
0
Reset
00H
SPIFD: Full-duplex mode enable.
SPIFD = 1 is enable full-duplex mode.
SPIFD = 0 is disable full-duplex mode.
When it is set, the TBC[2:0] and RBC[2:0] will be reset and keep to zero. When the Master device
Transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to
the Master device via the MISO line. This implies full-duplex transmission with both data out and data
in synchronized with the same clock. As shown in Fig 15-2.
Input Shift register
SPIRXD
Output Shift register
SPITXD
Clock Generator
SyncMos Master
MISO
MISO
MOSI
MOSI
SCK
SCK
Output Shift register
SPITXD
Input Shift register
SPIRXD
SyncMos Slave
Fig. 15-2: SPI Mater and slave transfer method
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 75 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
SPIRST: SPI Re-start (Slave mode used only)
SPIRST = 0 - Re-start function disable.SPI Transmit/receive data when SS active.
In SPITXD/SPIRXD buffer, data got from previous SS active period will not be removed (i.e. it's valid).
SPIRST = 1 - Re-start function enable.SPI Transmit/receive new data when SS re-active;
In SPITXD/SPIRXD buffer, data got from previous SS active period will be removed (i.e. It's invalid).
TBC[2:0]: SPI Transmitter bit counter.
TBC[2:0]
Bit counter
0:0:0
8 bits output
0:0:1
1 bit output
0:1:0
2 bits output
0:1:1
3 bits output
1:0:0
4 bits output
1:0:1
5 bits output
1:1:0
6 bits output
1:1:1
7 bits output
RBC[2:0]: SPI receiver bit counter.
RBC[2:0]
Bit counter
0:0:0
8 bits input
0:0:1
1 bit input
0:1:0
2 bits input
0:1:1
3 bits input
1:0:0
4 bits input
1:0:1
5 bits input
1:1:0
6 bits input
1:1:1
7 bits input
Mnemonic: SPIS
7
6
SPIRF
SPIMLS
5
SPIOV
4
SPITXIF
3
SPITDR
2
SPIRXIF
1
SPIRDR
Address:F5H
0
Reset
SPIRS
40H
SPIRF: SPI SS pin Release Flag.
This bit is set when SS pin release & SPIRST as ‘1’.
SPIMLS: MSB or LSB first output /input Select.
SPIMLS = 1 is MSB first output/input.
SPIMLS = 0 is LSB first output/input.
SPIOV: Overflow flag.
When SPIRDR is set and next data already into shift register, this flag will be set.
It is clear by hardware, when SPIRDR is cleared.
SPITXIF: Transmit Interrupt Flag.
This bit is set when the data of the SPITXD register is downloaded to the shift register.
SPITDR: Transmit Data Ready.
When MCU finish writing data to SPITXD register, the MCU needs to set this bit to ‘1’ to
inform the SPI module to send the data. After SPI module finishes sending the data
from SPITXD, this bit will be cleared automatically.
SPIRXIF: Receive Interrupt Flag.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 76 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
This bit is set after the SPIRXD is loaded with a newly receive data.
SPIRDR: Receive Data Ready.
The MCU must clear this bit after it gets the data from SPIRXD register. The SPI
module is able to write new data into SPIRXD only when this bit is cleared.
SPIRS: Receive Start.
This bit set to “1” to inform the SPI module to receive the data into SPIRXD register.
Mnemonic: SPITXD
7
6
5
4
3
SPITXD[7:0]
2
1
Address: F3H
0
Reset
00H
4
3
SPIRXD[7:0]
2
1
Address: F4H
0
Reset
00H
SPITXD[7:0]: Transmit data buffer.
Mnemonic: SPIRXD
7
6
5
SPIRXD[7:0]: Receive data buffer.
P.S. MISO pin must be float when SS or CS no-active in slave mode.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 77 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
16. LVI & LVR – Low Voltage Interrupt and Low Voltage Reset
Mnemonic
RSTS
LVC
Description
Reset status
register
Low voltage
control register
Mnemonic: RSTS
7
-
6
LVRLP
INTF
Dir.
Bit 7
A1h
-
E6h
LVI_E
N
The interrupt vector 63h
Bit 6
Bit 5
Bit 4
Watchdog Timer
LVRLP
LVRLP
PDRF
INTF
F
LVRLPE
LVRE
LVIF
Bit 3
Bit 2
Bit 1
Bit 0
RST
WDTF
SWRF
LVRF
PORF
00H
LVRLP
INTE
-
LVIS[1:0]
Address: A1h
Reset
5
4
3
2
1
0
LVRLPF
PDRF
WDTF
SWRF
LVRF
PORF
20H
00H
LVRLPINTF: “Internal” Low voltage reset flag.
When MCU is reset by LVR_LP_INT, LVRLPINTF flag will be set to one by hardware.
This flag clear by software.
LVRLPF: “External” Low voltage reset flag.
When MCU is reset by LVR(External Low Power), LVRLPF flag will be set to one by
hardware. This flag clear by software.
PDRF: Pad reset flag.
When MCU is reset by reset pad, PDRF flag will be set to one by hardware. This flag
clear by software.
LVRF: Low voltage reset flag.
When MCU is reset by LVR, LVRF flag will be set to one by hardware. This flag clear
by software.
PORF: Power on reset flag.
When MCU is reset by POR, PORF flag will be set to one by hardware. This flag clear
by software.
Mnemonic: LVC
7
6
LVR
LVI_EN
LPE
5
4
LVRE
LVIF
3
LVRLP
INTE
2
-
Address: E6h
1
0
LVIS[1:0]
Reset
20H
LVI_EN: Low voltage interrupt function enable bit.
LVI_EN = 0 - disable low voltage detect function.
LVI_EN = 1 - enable low voltage detect function.
LVRLPE: External low voltage reset function (Low Power)enable bit.
LVRLPE = 0 - enable external low voltage reset(Low Power) function.
LVRLPE = 1 - disable external low voltage reset(Low Power) function.
LVRE: External low voltage reset function enable bit.
LVRXE = 0 - disable external low voltage reset function.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 78 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
LVRXE = 1 - enable external low voltage reset function.
Note: LVR = 1.50 V
LVIF: Low Voltage interrupt Flag(i.e., Low Voltage Interrupt Status Flag)
LVRLPINTE: LVR_LP_INT(“Internal” low voltage reset) function enable bit.
LVRLPINTE = 0 - disable internal low voltage reset function.
LVRLPINTE = 1 - enable internal low voltage reset function.
LVIS[1:0]: LVI level select:
00: 1.65V
01: 2.60V
10: 3.20V
11: 4.00V
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 79 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
17. 10-bit Analog-to-Digital Converter (ADC)
The SM39R16A6 provides 8 channels 10-bit ADC. The Digital output DATA [9:0] were put into ADCD [9:0]. The ADC
the block diagram show in Fig. 17-1
The ADC interrupt vector is 53H.
ADCC1[7:0]
VDD
ADCCH[2:0]
Start
ADC0
AVDD
…
…
…
…
ADCD[9:0]
MUX
ADC6
High Speed
10 Bits
ADC Module
ADC7
ADC
Clock
Divider
Fosc
ADC_ISR
AVSS
ADCCS[4:0]
VSS
Fig. 17-1: ADC Analog to Digital converter operation set
The ADC SFR show as below:
Mnemonic
Description
Dir.
Bit 7
ADCC1
ADC Control
register 1
ABh
ADC7
EN
ADCC2
ADC Control
register 2
ACh
Start
ADCDH
ADCDL
ADCCS
ADC data high
byte
ADC data low
byte
ADC clock select
Mnemonic: ADCC1
7
6
ADC7EN
ADC6EN
Bit 6
Bit 5
ADC
ADC6
ADC5
EN
EN
ADJU
ST
-
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
ADC4
EN
EXT
Trigger
EN
ADC3
EN
ADC2
EN
ADC1
EN
ADC0
EN
00H
ADCM
ODE
ADCCH[2:0]
08H
ADh
ADCDH [7:0]
00H
AEh
ADCDL [7:0]
00H
AFh
5
ADC5EN
-
-
4
ADC4EN
-
3
ADC3EN
ADCCS[4:0]
2
ADC2EN
1
ADC1EN
00H
Address: ABh
0
Reset
ADC0EN
00H
ADC7EN: ADC channels 7 enable.
ADC7EN = 1 - Enable ADC channel 7
ADC6EN: ADC channels 6 enable.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 80 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
ADC6EN = 1 - Enable ADC channel 6
ADC5EN: ADC channels 5 enable.
ADC5EN = 1 - Enable ADC channel 5
ADC4EN: ADC channels 4 enable.
ADC4EN = 1 - Enable ADC channel 4
ADC3EN: ADC channels 3 enable.
ADC3EN = 1 - Enable ADC channel 3
ADC2EN: ADC channels 2 enable.
ADC2EN = 1 - Enable ADC channel 2
ADC1EN: ADC channels 1 enable.
ADC1EN = 1 - Enable ADC channel 1
ADC0EN: ADC channels 0 enable.
ADC0EN = 1 - Enable ADC channel 0
Mnemonic: ADCC2
7
6
Start
ADJUST
5
-
4
EXTTrigg
erEN
3
ADCMO
DE
2
1
ADCCH[2:0]
Address: ACh
0
Reset
08H
Start: When this bit is set, the ADC will be start conversion.
(SW trigger conversion)
ADJUST: Adjust the format of ADC conversion DATA.
ADJUST = 0 - (default value)
ADC data high byte ADCD [9:2] = ADCDH [7:0].
ADC data low byte ADCD [1:0] = ADCDL [1:0].
ADJUST = 1- ADC data high byte ADCD [9:8] = ADCDH [1:0].
ADC data low byte ADCD [7:0] = ADCDL [7:0].
EXTTriggerEN: External Pin trigger ADC to start conversion.
(HW external trigger conversion)
0 = disable.
1 = enable.
ADCMODE: 0 = continuous mode.
1 = single-shot mode.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 81 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
ADCCH[2:0] ADC channel select.
ADCCH [2:0]
000
001
010
011
100
101
110
111
Channel
0
1
2
3
4
5
6
7
ADJUST = 0:
Mnemonic: ADCDH
7
6
ADCD[9]
ADCD[8]
Mnemonic: ADCDL
7
6
-
5
ADCD[7]
4
ADCD[6]
3
ADCD[5]
2
ADCD[4]
1
ADCD[3]
Address: ADh
0
Reset
ADCD[2]
00H
5
-
4
-
3
-
2
-
1
ADCD[1]
Address: AEh
0
Reset
ADCD[0]
00H
ADJUST = 1:
Address: ADh
Mnemonic: ADCDH
7
6
Mnemonic: ADCDL
7
6
ADCD[7]
ADCD[6]
5
-
4
-
3
-
2
-
1
ADCD[9]
0
ADCD[8]
Reset
00H
5
ADCD[5]
4
ADCD[4]
3
ADCD[3]
2
ADCD[2]
1
ADCD[1]
Address: AEh
0
Reset
ADCD[0]
00H
4
ADCCS[4]
3
ADCCS[3]
2
ADCCS[2]
1
ADCCS[1]
Address: AFh
0
Reset
ADCCS[0]
00H
ADCD[9:0]: ADC data register.
Mnemonic: ADCCS
7
6
-
5
-
ADCCS[4:0]: ADC clock select.
*The ADC clock maximum 12.5MHz.
*The ADC Conversion rate maximum 961 KHz.
ADCCS[4:0]
ADC Clock(Hz)
Clocks for ADC Conversion
00000
Fosc /2
26
00001
Fosc /4
52
00010
Fosc /6
78
00011
Fosc /8
104
00100
Fosc /10
130
00101
Fosc /12
156
00110
Fosc /14
182
00111
Fosc /16
208
01000
Fosc /18
234
01001
Fosc /20
260
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 82 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Fosc /22
Fosc /24
Fosc /26
Fosc /28
Fosc /30
Fosc /32
Fosc /34
Fosc /36
Fosc /38
Fosc /40
Fosc /42
Fosc /44
Fosc /46
Fosc /48
Fosc /50
Fosc /52
Fosc /54
Fosc /56
Fosc /58
Fosc /60
Fosc /62
Fosc /64
286
312
338
364
390
416
442
468
494
520
546
572
598
624
650
676
702
728
754
780
806
832
Fosc
2 × ( ADCCS + 1)
ADC_Clock
ADC _ Conversion _ Rate =
13
ADC _ Clock =
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 83 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
18. In-System Programming (Internal ISP)
The SM39R16A6 can generate flash control signal by internal hardware circuit. Users utilize flash control register, flash
address register and flash data register to perform the ISP function without removing the SM39R16A6 from the system.
The SM39R16A6 provides internal flash control signals which can do flash program/chip erase/page erase/protect
functions. User need to design and use any kind of interface which SM39R16A6 can input data. User then utilize ISP
service program to perform the flash program/chip erase/page erase/protect functions.
18.1 ISP service program
The ISP service program is a user developed firmware program which resides in the ISP service program space. After
user developed the ISP service program, user then determine the size of the ISP service program. User need to
program the ISP service program in the SM39R16A6 for the ISP purpose.
The ISP service programs were developed by user so that it should includes any features which relates to the flash
memory programming function as well as communication protocol between SM39R16A6 and host device which output
data to the SM39R16A6. For example, if user utilize UART interface to receive/Transmit data between SM39R16A6
and host device, the ISP service program should include baud rate, checksum or parity check or any error-checking
mechanism to avoid data transmission error.
The ISP service program can be initiated under SM39R16A6 active or idle mode. It can not be initiated under power
down mode.
18.2 Lock Bit (N)
The Lock Bit N has two functions: one is for service program size configuration and the other is to lock the ISP service
program space from flash erase function.
The ISP service program space address range $3C00 to $3FFF. It can be divided as blocks of N*128 byte. (N=0 to 8).
When N=0 means no ISP function, all of 16K byte flash memory can be used as program memory. When N=1 means
ISP service program occupies 128 byte while the rest of 15.875K byte flash memory can be used as program memory.
The maximum ISP service program allowed is 1K byte when N=8. Under such configuration, the usable program
memory space is 15K byte.
After N determined, SM39R16A6 will reserve the ISP service program space downward from the top of the program
address $3FFF. The start address of the ISP service program located at $3x00 while x is depending on the lock bit N.
Please see section 3.1 program memory diagram for this ISP service program space structure.
The lock bit N function is different from the flash protect function. The flash erase function can erase all of the flash
memory except for the locked ISP service program space. If the flash not has been protected, the content of ISP
service program still can be read. If the flash has been protected, the overall content of flash program memory space
including ISP service program space can not be read. As given in Table 18-1.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 84 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
0
1
2
3
4
5
6
7
8
Table 18-1 ISP code area
ISP service program address
No ISP service program
128 bytes ($3F80h ~ $3FFFh)
256 bytes ($3F00h ~ $3FFFh)
384 bytes ($3E80h ~ $3FFFh)
512 bytes ($3E00h ~ $3FFFh)
640 bytes ($3D80h ~ $3FFFh)
768 bytes ($3D00h ~ $3FFFh)
896 bytes ($3C80h ~ $3FFFh)
1.0 K bytes ($3C00h ~ $3FFFh)
ISP service program configurable in N*128 byte (N= 0 ~ 8)
18.3 Program the ISP Service Program
After Lock Bit N is set and ISP service program been programmed, the ISP service program memory will be protected
(locked) automatically. The lock bit N has its own program/erase timing. It is different from the flash memory
program/erase timing so the locked ISP service program can not be erased by flash erase function. If user needs to
erase the locked ISP service program, he can do it by writer only. User can not change ISP service program when
SM39R16A6 was in system.
18.4 Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and
execute it. There are four ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start address of
ISP service program. The hardware reset includes MAX810 (power on reset) and external pad reset. The
hardware will issue a strobe window about 256us after hardware reset.
(2) Execute jump instruction can load the start address of the ISP service program to PC.
(3) Enter’s ISP service program by hardware setting. User can force SM39R16A6 enter ISP service program by
setting P1.2, P1.3 “active low” or P1.4 “ active low” during hardware reset period. The hardware reset
includes MAX810 (power on reset) and external pad reset. The hardware will issue after hardware reset. In
application system design, user should take care of the setting of P1.2,P1.3 or P1.4 at reset period to
prevent SM39R16A6 from entering ISP service program.
(4) Enter’s ISP service program by hardware setting, the P3.0(RXD) will be detected the two clock signals during
hardware reset period. The hardware reset includes MAX810 (power on reset) and external pad reset. The
hardware will issue to detect 2 clock signals after hardware reset.
During the strobe window, the hardware will detect the status of P1.2, P1.3 (or P1.4)/P1.0. If they meet one of above
conditions, chip will switch to ISP mode automatically. After ISP service program executed, user need to reset the
SM39R16A6, either by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware program.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 85 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
There are 6 kinds of entry mechanisms for user different applications. This entry method will select on the writer or ISP.
(1) First Address Blank. i.e. $0000 = 0xFF. And triggered by Internal reset signal. ( Entry mechanism 1 )
(2) First Address Blank. i.e. $0000 = 0xFF. And triggered by PAD reset signal. ( Entry mechanism 1 )
(3) P1.2 = 0 & P1.3 = 0. And triggered by Internal reset signal. ( Entry mechanism 2 )
(4) P1.2 = 0 & P1.3 = 0. And triggered by PAD reset signal. ( Entry mechanism 2 )
(5) P1.4 = 0. And triggered by Internal reset signal. ( Entry mechanism 3 )
(6) P1.4 = 0. And triggered by PAD reset signal. ( Entry mechanism 3 )
(7) P3.0 input 2 clocks. And triggered by Internal reset signal. ( Entry mechanism 4 )
(8) P3.0 input 2 clocks. And triggered by PAD reset signal. ( Entry mechanism 4 )
18.5 ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC
Mnemonic
TAKEY
IFCON
ISPFAH
ISPFAL
ISPFD
ISPFC
Description
Time Access Key
register
Interface Control
register
ISP Flash
Address – High
register
ISP Flash
Address - Low
register
ISP Flash Data
register
ISP Flash Control
register
Dir.
Bit 7
Bit 6
Bit 5
ISP function
Bit 4
F7h
8Fh
Bit 3
Bit 2
Bit 1
Bit 0
TAKEY [7:0]
-
CDPR
-
-
RST
00H
-
-
-
ISPE
00H
E1h
ISPFAH [7:0]
FFH
E2h
ISPFAL [7:0]
FFH
E3h
ISPFD [7:0]
FFH
E4h
Mnemonic: TAKEY
7
6
5
EMF1
EMF2
EMF3
EMF4
4
3
TAKEY [7:0]
-
2
ISPF.2
1
ISPF.1
ISPF.0
00H
Address: F7H
0
Reset
00H
ISP enable bit (ISPE) is read-only by default, software must write three specific values 55h, AAh and 5Ah
sequentially to the TAKEY register to enable the ISPE bit write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
Mnemonic: IFCON
7
6
CDPR
5
-
4
-
3
-
2
-
1
-
Address: 8FH
0
Reset
ISPE
00H
The bit 0 (ISPE) of IFCON is ISP enable bit. User can enable overall SM39R16A6 ISP function by setting ISPE
bit to 1, to disable overall ISP function by set ISPE to 0. The function of ISPE behaves like a security key. User
can disable overall ISP function to prevent software program be erased accidentally. ISP registers ISPFAH,
ISPFAL, ISPFD and ISPFC are read-only by default. Software must be set ISPE bit to 1 to enable these 4
registers write attribute.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 86 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Mnemonic: ISPFAH
7
6
ISPFAH7 ISPFAH6
5
ISPFAH5
4
ISPFAH4
3
ISPFAH3
2
ISPFAH2
1
ISPFAH1
Address: E1H
0
Reset
ISPFAH0
FFH
2
ISPFAL2
1
ISPFAL1
Address: E2H
0
Reset
ISPFAL0
FFH
ISPFAH [7:0]: Flash address-high for ISP function
Mnemonic: ISPFAL
7
6
ISPFAL7 ISPFAL6
5
ISPFAL5
4
ISPFAL4
3
ISPFAL3
ISPFAL [7:0]: Flash address-Low for ISP function
The ISPFAH & ISPFAL provide the 16-bit flash memory address for ISP function. The flash memory address
should not include the ISP service program space address. If the flash memory address indicated by ISPFAH &
ISPFAL registers overlay with the ISP service program space address, the flash program/page erase of ISP
function executed thereafter will have no effect.
Mnemonic: ISPFD
7
6
ISPFD7
ISPFD6
5
ISPFD5
4
ISPFD4
3
ISPFD3
2
ISPFD2
1
ISPFD1
Address: E3H
0
Reset
ISPFD0
FFH
ISPFD [7:0]: Flash data for ISP function.
The ISPFD provide the 8-bit data register for ISP function.
Mnemonic: ISPFC
7
6
EMF1
EMF2
5
EMF3
4
EMF4
3
-
2
ISPF[2]
1
ISPF[1]
Address: E4H
0
Reset
ISPF[0]
00H
EMF1: Entry mechanism (1) flag, clear by reset. (Read only)
EMF2: Entry mechanism (2) flag, clear by reset. (Read only)
EMF3: Entry mechanism (3) flag, clear by reset. (Read only)
EMF4: Entry mechanism (4) flag, clear by reset. (Read only)
ISPF [2:0]: ISP function select bit.
ISPF[2:0]
ISP function
000
Byte program
001
Chip protect
010
Page erase
011
Chip erase
100
Write option
101
Read option
110
Erase option
111
reserved
One page of flash memory is 128byte
The Option function can access the XTAL1 and XTAL2 swap to I/O pins
select(description in section 1.2)、Internal reset time select(description in section
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 87 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
1.4.1)、clock source select(description in section 1.5)、Reset swap to I/O pins
function select(description in section 5)、WDTEN control bit(description in section
10)、or ISP entry mechanisms select(description in section 18).
When chip protected or no ISP service, option can only read.
The choice ISP function will start to execute once the software write data to ISPFC register.
To perform byte program/page erases ISP function, user need to specify flash address at first. When performing
page erase function, SM39R16A6 will erase entire page which flash address indicated by ISPFAH & ISPFAL
registers located within the page.
e.g. flash address: $ XY00
page erase function will erase from $XY00 to $XY7F
To perform the chip erase ISP function, SM39R16A6 will erase all the flash program memory except the ISP
service program space. To perform chip protect ISP function, the SM39R16A6 flash memory content will be read
#00H.
e.g. ISP service program to do the byte program - to program #22H to the address $1005H
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
; enable ISPE write attribute
ORL IFCON, #01H
; enable SM39R16A6 ISP function
MOV ISPFAH, #10H ; set flash address-high, 10H
MOV ISPFAL, #05H
; set flash address-low, 05H
MOV ISPFD, #22H
; set flash data to be programmed, data = 22H
MOV ISPFC, #00H
; start to program #22H to the flash address $1005H
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
; enable ISPE write attribute
ANL IFCON, #0FEH
; disable SM39R16A6 ISP function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 88 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Operating Conditions
Symbol
Min.
Typ.
Max.
Unit.
Operating temperature
-40
25
85
℃
VDD
Supply voltage
1.8
5.5
V
Vref
Internal reference voltage
1.1
1.3
V
TA
Description
1.2
Remarks
Ambient temperature under bias
DC Characteristics
TA = -40℃ to 85℃, VCC = 5.0V
Symbol
Parameter
Valid
Min
Typical
Max
Units
Conditions
VIL1
Input Low-voltage
Port 0,1,2,3
-0.5
-
0.8
V
VIL2
Input Low-voltage
RES, XTAL1
0
-
V
-
VIH1
Input High-voltage
Port 0,1,2,3
2.0
V
-
VIH2
Input High-voltage
RES, XTAL1
70%Vcc
V
-
VOL
Output Low-voltage
V
IOL=40mA
Vcc=5V
Vcc=5V
VOH1
VOH2
IIL
ITL
ILI
RRST
CIO
ICC
Port 0 (3.)
-
-
0.8
VCC +
0.5
VCC +
0.5
0.45
Port 1,2,3 (4.)
-
-
0.45
V
IOL=20mA
4.6
-
-
V
IOH= -12mA
4.6
-
-
V
IOH= -7mA
-
V
IOH= -350uA
-75
uA
Vin= 0.45V
-650
uA
Vin= 2.0V
±10
uA
0.45V<Vin<Vcc
300
kΩ
Freq= 1MHz, Ta= 25℃
Active
mode ,IRC=22.1184MHz
Active mode, 12MHz
VCC=5V 25 ℃
Idle mode, 12MHz
VCC =5V 25 ℃
Power down mode
VCC =5V 25 ℃
Output High-voltage
Port 0
using Strong PullPort 1,2,3
up(1)
Output High-voltage
Port 0,1,2,3
using Weak Pull-up(2)
Logic 0 Input Current Port 0,1,2,3
Logical Transition
Port 0,1,2,3
Current
Input Leakage Current Port 0,1,2,3
Reset Pull-down
RES
Resistor
Pin Capacitance
-
Power Supply Current
Vcc=5V
VDD
2.6
50
-
-
-
-
10
pF
-
3.19
4.78
mA
-
5.5
8.25
mA
-
4.5
7.25
mA
-
3
7
uA
Notes:
(1) Port in Push-Pull Output Mode
(2) Port in Quasi-Bidirectional Mode
(3) Maximum IOL per port0 pin : 40mA
(4) Maximum IOL per port1,2,3 pin : 20mA
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 89 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
TA = -40℃ to 85℃, VCC = 3.0V
Symbol
VIL1
Parameter
Input Low-voltage
Valid
Port 0,1,2,3
Min
Typical
Max
Units
-0.5
-
0.8
V
-
V
-
V
-
V
-
VIL2
Input Low-voltage
RES, XTAL1
0
VIH1
Input High-voltage
Port 0,1,2,3
2.0
VIH2
Input High-voltage
RES, XTAL1
70%Vcc
VOL
Output Low-voltage
VOH1
VOH2
IIL
ITL
ILI
RRST
CIO
ICC
Port 0 (3.)
-
-
0.8
VCC +
0.5
VCC +
0.5
0.45
Port 1,2,3 (4.)
-
-
2.6
2.6
Output High-voltage
Port 0
using Strong PullPort 1,2,3
up(1)
Output High-voltage
Port 0,1,2,3
using Weak Pull-up(2)
Logic 0 Input Current Port 0,1,2,3
Logical Transitio
Port 0,1,2,3
n Current
Input Leakage Current Port 0,1,2,3
Reset Pull-down
RES
Resistor
Pin Capacitance
Power Supply Current VDD
2.4
50
-
Conditions
Vcc=3.0V
V
IOL=20mA
Vcc=3V
0.45
V
IOL=12mA
Vcc=3V
-
-
V
IOH=- 9mA
-
-
V
IOH= -5mA
-
V
IOH= -70uA
-75
uA
Vin= 0.45V
-650
uA
Vin=1.5V
±10
uA
0.45V<Vin<Vcc
300
kΩ
Freq= 1MHz, Ta= 25℃
Active
mode ,IRC=22.1184MHz
Active mode ,12MHz
VCC = 3.0 V 25 ℃
Idle mode, 12MHz
VCC =3.0V 25 ℃
Power down mode
VCC=3.0V 25 ℃
-
-
-
10
pF
-
3.15
4.73
mA
-
2.77
4.16
mA
-
1.77
3.16
mA
-
1
5
uA
Notes:
(1) Port in Push-Pull Output Mode
(2) Port in Quasi-Bidirectional Mode
(3) Maximum IOL per port0 pin : 20mA
(4) Maximum IOL per port1,2,3 pin : 12mA
SYMBOL
Maximum sourced
current
Maximum sink
current
Tj
PARAMETER
An I/O pin
Total I/O pins
An I/O pin
Total I/O pins
Max. Junction
Temperature
Absolute Maximum Ratings
MAX
N/A
150
N/A
150
UNIT
mA
mA
mA
mA
150
℃
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 90 -
SM39R16A6
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
LVI& LVR Characteristics
1.8V ~ 5.5V
Min
VIL=1.42V
(VIH=1.62V)
LVIS[1:0] = 00
LVIS[1:0] = 01
LVIS[1:0] = 10
LVIS[1:0] = 11
Min
VIL=1.57V
(VIH=1.77V)
VIL=2.47V
(VIH=2.67V)
VIL=3.04V
(VIH=3.24V)
VIL=3.80V
(VIH=4.00V)
LVR
Typical
VIL=1.50V
(VIH=1.70V)
LVI
Typical
VIL=1.65V
(VIH=1.85V)
VIL=2.60V
(VIH=2.80V)
VIL=3.20V
(VIH=3.40V)
VIL=4.00V
(VIH=4.20V)
Max
VIL=1.57V
(VIH=1.77V)
Max
VIL=1.73V
(VIH=1.93V)
VIL=2.73V
(VIH=2.93V)
VIL=3.36V
(VIH=3.56V)
VIL=4.20V
(VIH=4.40V)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M079
Ver D SM39R16A6 06/30/2015
- 91 -