Single-chip Type with Built-in FET Switching Regulator Series Output 1.5A or Less High Efficiency Step-down Switching Regulator with Built-in Power MOSFET BD9152MUV No.10027ECT14 ●Description ROHM’s high efficiency dual step-down switching regulator BD9152MUV is a power supply designed to produce a low voltage including 3.3,0.8 volts from 5.5/4.5 volts power supply line. Offers high efficiency with our original pulse skip control technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load. ●Features 1) Offers fast transient response with current mode PWM control system. 2) Offers highly efficiency for all load range with synchronous rectifier (Pch/Nch FET) TM and SLLM (Simple Light Load Mode) 3) Incorporates soft-start function. 4) Incorporates thermal protection and ULVO functions. 5) Incorporates short-current protection circuit with time delay function. 6) Incorporates shutdown function Icc=0μA(Typ.) 7) Employs small surface mount package : VQFN020V4040 ●Application Power supply for LSI including DSP, Micro computer and ASIC ●Absolute Maximum Rating (Ta=25℃) Parameter Vcc Voltage EN Voltage SW Voltage Power Dissipation Operating Temperature Range Storage Temperature Range Maximum Junction Temperature *1 *2 *3 *4 *5 Symbol VCC VEN1 VEN2 VSW1 VSW2 Pd1 Pd2 Pd3 Pd4 Topr Tstg Tjmax Limit -0.3～+7 *1 -0.3～+7 -0.3～+7 -0.3～+7 -0.3～+7 2 0.34* 0.70 *3 1.21 *4 3.56*5 -40～+85 -55～+150 +150 Unit V V V V V W W W W ℃ ℃ ℃ Pd should not be exceeded. IC only 1-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2 4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2 , in each layers 4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 5505mm2, in each layers ●Operating Conditions (Ta=-40～+105℃) Parameter Vcc Voltage EN Voltage Output Voltage range SW Average Output Current *6 Symbol Min. 4.5 0 0 0.8 - VCC VEN1 VEN2 VOUT2 ISW1 ISW2 Limit Typ. 5.0 - Max. 5.5 5.5 5.5 2.5 1.5*6 1.5*6 Unit V V V V A A Pd and ASO should not be exceeded. www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ 1/16 2010.04 - Rev.C Technical Note BD9152MUV ●Electrical Characteristics ◎(Ta=25℃ VCC=5V, EN1=EN2=VCC ,unless otherwise specified.) Parameter Symbol Min. Limit Typ. Max. Unit Condition Standby Current ISTB - 0 10 μA Bias Current ICC - 500 800 μA EN Low Voltage VENL - GND 0.8 V Standby Mode EN High Voltage VENH 2 Vcc - V Active Mode EN Input Current IEN - 1 10 μA EN1=EN2=2V FOSC 0.8 1.0 1.2 MHz RONP1 - 0.17 0.3 Ω Vcc=5V RONP2 - 0.17 0.3 Ω Vcc=5V RONN1 - 0.13 0.2 Ω Vcc=5V RONN2 - 0.13 0.2 Ω Vcc=5V FB1 3.25 3.3 3.35 V ±1.5% FB2 0.788 0.8 0.812 V ±1.5% UVLO Threshold Voltage1 VUVLOL1 3.6 3.8 4.0 V Vcc=5→0V UVLO Release Voltage1 VUVLOH1 3.65 3.9 4.2 V Vcc=0→5V UVLO Threshold Voltage2 VUVLOL2 2.4 2.5 2.6 V Vcc=5→0V UVLO Release Voltage2 VUVLOH2 2.425 2.55 2.7 V Vcc=0→5V RFB1 - 20 40 Ω Vcc=5V TSS 0.4 0.8 1.6 ms TLATCH 1.0 2.0 4.0 ms SCP/TSD ON VSCP1 - 1.65 2.4 V FB1=3.3→0V VSCP2 - 0.4 0.56 V FB2=0.8→0V Oscillation Frequency Pch FET ON Resistance Nch FET ON Resistance FB Reference Voltage FB1 Discharge Resistance Soft Start Time Timer Latch Time Output Short circuit Threshold Voltage www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ 2/16 EN1=EN2=0V 2010.04 - Rev.C Technical Note BD9152MUV ●Block Diagram, Application Circuit 【BD9152MUV】 PVCC FB1 Current Comp 4.0±0.1 4.0±0.1 EN1 Current R Gm Amp Q D9152 Slope1 EN1 AGND SW1 + Soft Start1 Driver Logic Lot No. ITH1 1.0Max. Sense/ Protect S PGND1 SCP1 S C0.2 2.1±0.1 16 10 0.5 CLK2 UVLO1 UVLO2 PVCC Current Current Comp R Gm Amp FB2 11 Q S Soft Start2 EN2 (Unit : mm) Driver CLK2 Logic Function PGND2 AGND Fig.2 BD9152MUV Block Diagram Pin No. Pin name 1 PGND2 Ch2 Lowside source pin 11 ITH1 2 3 4 PVcc PVcc PVcc Highside FET source pin Highside FET source pin Highside FET source pin 12 13 14 AGND N.C. AVcc 5 PGND1 Ch1 Lowside source pin 15 ITH2 6 7 8 9 10 PGND1 SW1 SW1 EN1 FB1 Ch1 Lowside source pin Ch1 Pch/Nch FET drain output pin Ch1 Pch/Nch FET drain output pin Ch1 Enable pin(High Active) Ch1 output voltage detect pin 16 17 18 19 20 FB2 EN2 SW2 SW2 PGND2 www.rohm.com SW2 ITH2 Fig.1 BD9152MUV TOP View c 2010 ROHM Co., Ltd. All rights reserved. ○ Sense/ Protect + Slope2 0.25 +0.05 -0.04 ●Pin No. & function table Pin Pin No. name SCP/ TSD SCP2 6 15 OSC 5 20 1.0 VREF 2.1±0.1 0.4±0.1 1 CLK1 0.02 +0.03 -0.02 (0.22) 0.08 S 3/16 Function Ch1 GmAmp output pin/ Connected phase compensation capacitor Ground Non Connection VCC power supply input pin Ch1 GmAmp output pin/Connected phase compensation capacitor Ch2 output voltage detect pin Ch2 Enable pin(High Active） Ch2 Pch/Nch FET drain output pin Ch2 Pch/Nch FET drain output pin Ch2 Lowside source pin 2010.04 - Rev.C Technical Note BD9152MUV ●Characteristics data 3.5 Ta=25℃ Io=1.5A 3.0 OUTPUT VOLTAGE:VOUT[V] OUTPUT VOLTAGE:VOUT[V] 3.0 【VOUT1=3.3V】 2.5 2.0 3.5 【VOUT2=1.2V】 1.5 1.0 0.5 2.5 2.0 【VOUT2=1.2V】 1.5 VCC=5V Ta=25℃ Io=0A 1.0 0.5 0 1 2 3 4 INPUT VOLTAGE:VCC[V] 0 5 1 2 3 4 1.0 0 3.30 VCC=5V Io=0A 3.20 0 20 40 60 TEMPERATURE:Ta[℃] 1.23 1.20 1.18 80 VCC=5V Io=0A 90 【VOUT1=3.3V】 80 【VOUT2=2.5V】 70 60 40 20 -20 0 20 40 60 TEMPERATURE:Ta[℃] 80 0.6 0.4 VCC=5V 200 1 0.9 0.8 Ta=25℃ 60 TEMPERATURE:Ta[℃] Fig.9 Ta- Fosc 4.75 5 5.25 INPUT VOLTAGE:VCC[V] 5.5 125 100 NMOS 75 50 -40 -20 0 20 40 60 80 TEMPERATURE:Ta[℃] 100 600 1.6 1.4 1.2 1.0 0.8 0.6 VCC=5V 0.4 CIRCUIT CURRENT:ICC[μA] 1.8 EN VOLTAGE:VEN[V] 150 Fig.11 Ta – RONN, RONP Fig.10 VCC-Fosc 2.0 PMOS 0 4.5 80 VCC=5V 25 0.7 0.0 10000 Fig.8 Efficiency ON RESISTANCE:RON[mΩ] FREQUENCY:FOSC[MHz] FREQUENCY:FOSC[MHz] 0.8 40 【VOUT2=1.0V 】 100 1000 OUTPUT CURRENT:IOUT[mA] 10 175 1.0 20 VCC=5V Ta=25℃ 10 1.1 0 【VOUT2=1.2V】 30 Fig. 7 Ta-VOUT2 Fig. 6 Ta-VOUT1 -20 【VOUT2=1.5V】 50 0 -40 1.2 4 100 【VOUT2=1.2V】 【VOUT2=1.2V 設定】 1.15 -40 1 2 3 OUTPUT CURRENT:IOUT [A] Fig.5 IOUT - VOUT EFFICIENCY:η[%] OUTPUT VOLTAGE:VOUT[V] 3.35 0.2 VCC=5V Ta=25℃ 0.5 5 1.25 【VOUT1=3.3V】 -20 【VOUT2=1.2V】 1.5 Fig.4 VEN - VOUT 3.40 -40 2.0 EN VOLTAGE:VEN[V] Fig.3 VCC – VOUT1,VOUT2 3.25 【VOUT1=3.3V】 2.5 0.0 0.0 0.0 OUTPUT VOLTAGE:VOUT[V] 3.0 【VOUT1=3.3V】 OUTPUT VOLTAGE:VOUT[V] 3.5 VCC=5V,Ta=25℃ 500 400 EN1=E2 300 VOUT1 200 VCC=5V VOUT2 100 0.2 0 0.0 -40 -20 0 20 40 60 80 TEMPERATURE:Ta[℃] Fig.12 Ta－EN1,EN2 www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ -40 -20 0 20 40 60 80 TEMPERATURE:Ta[℃] Fig.13 Ta－Icc 4/16 Fig.14 Soft start wave form (Io=0mA) 2010.04 - Rev.C Technical Note BD9152MUV ●Characteristics data VCC=5V,Ta=25℃ VCC=5V,Ta=25℃ VCC=5V,Ta=25℃ SW1 SW1 VOUT1 VOUT1 EN1=E2 VOUT1 VOUT2 Fig.15 Soft start wave form (Io=1.5A) Fig.16 SW1 wave form (Io=0mA) VCC=5V,Ta=25℃,VOUT2=1.2V VCC=5V,Ta=25℃,VOUT2=1.2V VOUT1 VOUT2 IOUT1 Fig.19 SW2 wave form (Io=1.5A) VCC=5V,Ta=25℃ www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ VCC=5V,Ta=25℃ SW2 Fig.18 SW2 wave form (Io=0mA) Fig.21 VOUT1 transient responce (Io1.5A→0.5A/ usec) Fig.17 SW1 wave form (Io=1.5A) Fig.20 VOUT1 transient responce (Io0.5A→1.5A / usec) VCC=5V,Ta=25℃,VOUT2=1.2V VCC=5V,Ta=25℃,VOUT2=1.2V VOUT2 VOUT2 IOUT2 IOUT2 Fig.22 VOUT2 transient responce (Io0.5A→1.5A/ usec) 5/16 Fig.23 VOUT2 transient responce (Io1.5A→0.5A/ usec) 2010.04 - Rev.C Technical Note BD9152MUV ●Information on advantages Advantage 1：Offers fast transient response with current mode control system. Conventional product (Load response IO=0.5A→1.5A) BD9152MUV (Load response IO=1.5A→0.5A) VOUT1 VOUT1 IOUT IOUT Fig.24 Transient response Advantage 2： Offers high efficiency for all load range. ・For lighter load: Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load. Achieves efficiency improvement for lighter load. ・For heavier load: Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor. ON resistance of Highside MOS FET : 170mΩ(Typ.) ON resistance of Lowside MOS FET : 130mΩ(Typ.) Efficiency η[%] 100 Achieves efficiency improvement for heavier load. SLLM ② 50 ① PWM ①inprovement by SLLM system ②improvement by synchronous rectifier 0 0.001 Offers high efficiency for all load range with the improvements mentioned above. 0.01 0.1 Output current Io[A] 1 Fig.25 Efficiency Advantage 3：・Supplied in smaller package due to small-sized power MOS FET incorporated. ・Output capacitor Co required for current mode control: 22μF ceramic capacitor ・Inductance L required for the operating frequency of 1 MHz: 2.2μH inductor ・Incorporates FET + Boot strap diode Reduces a mounting area required. VOUT1 L1 FB1 ITH1 RITH1 EN1 SW1 SW1 PGND1 AGND PVcc PVcc AVcc PVcc ITH2 FB2 COUT1 COUT2 CIN1 PGND1 N.C. RITH2 20mm COUT1 CIN1 15mm CIN2 PGND2 EN2 SW2 SW2 PGND2 L1 COUT2 R1 L2 RITH1 RITH2 R2 CITH1 CITH2 VOUT2 L2 R2 R1 www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ Fig.26 Example application 6/16 2010.04 - Rev.C Technical Note BD9152MUV ●Operation BD9152MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load, while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency. ○Synchronous rectifier It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power dissipation of the set is reduced. ○Current mode PWM control Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback. ・PWM (Pulse Width Modulation) control The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a highside MOS FET (while a lowside MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the highside MOS FET (while a lowside MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation. ・SLLM (Simple Light Load Mode) control When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa. Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching dissipation and improves the efficiency. SENSE Current Comp RESET VOUT Level Shift R Q FB SET Gm Amp. ITH IL Driver Logic S VOUT SW Load OSC Fig.27 Diagram of current mode PWM control PVCC Current Comp SENSE PVCC SENSE Current Comp FB FB SET GND SET GND RESET GND RESET GND SW GND SW IL GND IL(AVE) IL 0A VOUT VOUT VOUT(AVE) VOUT(AVE) Not switching Fig.28 PWM switching timing chart www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ Fig.29 SLLM 7/16 TM switching timing chart 2010.04 - Rev.C Technical Note BD9152MUV ●Description of operations ・Soft-start function EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current. ・Shutdown function With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0µF (Typ.). ・UVLO function Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of 50mV (Typ.) is provided to prevent output chattering. Each the outputs have UVLO. It is possible to set output sequence easy. Hysteresis 100mV VCC Hysteresis 50mV EN1,2 VOUT1 TSS discharge ON VOUT2 Natural discharge discharge ON Ch1 Standby mode Ch2 Standby mode Ch1, Ch2 Operating mode UVLO2 UVLO1 Ch1 : standby mode Ch2 : Operating mode UVLO1 TSS Natural discharge TSS Ch1 Standby mode Standby mode Ch1, Ch2 Operating mode UVLO1 UVLO2 discharge ON Natural discharge TSS TSS Ch1, Ch2 Standby mode TSS discharge ON EN Ch1, Ch2 Operating mode EN Ch2 Standby mode UVLO1 UVLO2 Fig.30 Soft start, Shutdown, UVLO timing chart www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ 8/16 2010.04 - Rev.C Technical Note BD9152MUV ・Short-current protection circuit with time delay function Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO. EN1＝EN2 Output Short circuit Threshold Voltage Output OFF Latch VOUT2 IL Limit IL1 t2=TLATCH t1<TLATCH Operating mode Standby mode Standby mode Timer latch EN Operating mode EN Fig.31 Short-current protection circuit with time delay timing chart ●Switching regulator efficiency Efficiency ŋ may be expressed by the equation shown below: η= VOUT×IOUT Vin×Iin ×100[%]= POUT Pin ×100[%]= POUT POUT+PDα ×100[%] Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows: Dissipation factors: 2 1) ON resistance dissipation of inductor and FET：PD(I R) 2) Gate charge/discharge dissipation：PD(Gate) 3) Switching dissipation：PD(SW) 4) ESR dissipation of capacitor：PD(ESR) 5) Operating current dissipation of IC：PD(IC) 2 2 1)PD(I R)=IOUT ×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output current.) 2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[H]：Switching frequency, V[V]：Gate driving voltage of FET) 3)PD(SW)= 2 Vin ×CRSS×IOUT×f IDRIVE (CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.) 2 4)PD(ESR)=IRMS ×ESR (IRMS[A]：Ripple current of capacitor, ESR[Ω]：Equivalent series resistance.) 5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.) www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ 9/16 2010.04 - Rev.C Technical Note BD9152MUV ●Consideration on permissible dissipation and heat generation As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation. 4.5 2 ① 4 layers (copper foil area : 5505mm ) (copper foil in each layers) θj-a=35.1℃/W 2 ② 4 layers (copper foil area : 10.29mm ) (copper foil in each layers) θj-a=103.3℃/W 2 ③ 1 layer (copper foil area : 0mm ) θj-a=178.6℃/W ④IC only θj-a=367.6℃/W 4.0 Power dissipation : Pd [W] ①3.56W 3.0 2 P=IOUT ×RON RON=D×RONP+(1-D)RONN D：ON duty (=VOUT/VCC) RONH：ON resistance of Highside MOS FET RONL：ON resistance of Lowside MOS FET IOUT：Output current 2.0 ②1.21W 1.0 ③0.70W ④0.34W 0 0 25 50 75 100 105 125 150 Ambient temperature :Ta [℃] Fig.32 Thermal derating curve (VQFN020V4040) (Example) VCC=5V, VOUT1=3.3V, VOUT2=1.2V, RONH=170mΩ, RONL=130mΩ IOUT=1.5A, for example, D1=VOUT1/VCC=3.3/5=0.66 D2=VOUT2/VCC=1.2/5=0.24 RON1=0.66×0.170+(1-0.66)×0.130 =0.1122+0.0442 =0.1564[Ω] RON2=0.24×0.170+(1-0.24)×0.130 =0.0408+0.0988 =0.1397[Ω] P=1.52×0.1564+1.52×0.1397=0.666[W] As RONH is greater than RONL in this IC, the dissipation increases as the ON duty becomes greater. With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed. www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ 10/16 2010.04 - Rev.C Technical Note BD9152MUV ●Selection of components externally connected 1. Selection of inductor (L) IL The inductance significantly depends on output ripple current. As seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. (VCC-VOUT)×VOUT [A]・・・(1) ΔIL= L×VCC×f ΔIL VCC IL Appropriate ripple current at output should be 20% more or less of the maximum output current. VOUT L ΔIL=0.2×IOUTmax. [A]・・・(2) Co L= Fig.33 Output ripple current (VCC-VOUT)×VOUT ΔIL×VCC×f [H]・・・(3) (ΔIL: Output ripple current, and f: Switching frequency) ※Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. If VCC=5.0V, VOUT=1.2V, f=1.0MHz, ΔIL=0.3×1.5A=0.45A, for example,(BD9152MUV) (5-1.2)×1.2 L= 0.45×5×1.0M =2.02μ → 2.2[μH] ※Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency. 2. Selection of output capacitor (CO) VCC Output capacitor should be selected with the consideration on the stability region and the equivalent series resistance required to smooth ripple voltage. Output ripple voltage is determined by the equation (4)： VOUT L ESR ΔVOUT=ΔIL×ESR [V]・・・(4) Co (ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor) ※Rating of the capacitor should be determined allowing sufficient margin against output voltage. A 22μF to 100μF ceramic capacitor is recommended. Less ESR allows reduction in output ripple voltage. Fig.34 Output capacitor 3. Selection of input capacitor (Cin) VCC Input capacitor to select must be a low ESR capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. The ripple current IRMS is given by the equation (5): Cin VOUT L Co IRMS=IOUT× √VOUT(VCC-VOUT) VCC [A]・・・(5) < Worst case > IRMS(max.) When Vcc=2×VOUT, IRMS= Fig.35 Input capacitor IOUT 2 If VCC=5.0V, VOUT=1.8V, and IOUTmax.=1.5A, (BD9152MUV) IRMS=2× √1.8(5.0-1.8) =0.48[ARMS] 5.0 A low ESR 22μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency. www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ 11/16 2010.04 - Rev.C Technical Note BD9152MUV 4. Determination of RITH, CITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier. fp(Min.) 1 2π×RO×CO 1 fz(ESR)= 2π×ESR×CO A fp= fp(Max.) Gain [dB] 0 fz(ESR) IOUTMin. Phase [deg] IOUTMax. Pole at power amplifier When the output current decreases, the load resistance Ro increases and the pole frequency lowers. 0 -90 fp(Min.)= 1 [Hz]←with lighter load 2π×ROMax.×CO fp(Max.)= 1 2π×ROMin.×CO Fig.36 Open loop gain characteristics A [Hz] ←with heavier load fz(Amp.) Zero at power amplifier Increasing capacitance of the output capacitor lowers the pole frequency while the zero frequency does not change. (This is because when the capacitance is doubled, the capacitor ESR reduces to half.) Gain [dB] 0 0 Phase [deg] -90 fz(Amp.)= 1 2π×RITH×CITH Fig.37 Error amp phase compensation characteristics VOUT1 L1 FB1 EN1 SW1 SW1 ITH1 RITH1 CITH1 RITH2 CITH2 PGND1 RO1 PGND1 AGND PVcc N.C. PVcc AVcc PVcc ITH2 PGND2 FB2 ESR COUT1 EN2 SW2 SW2 PGND2 CIN1 CIN2 COUT2 VOUT2 L2 R2 RO2 R1 Fig.38 Typical application Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier. fz(Amp.)= fp(Min.) 1 2π×RITH×CITH www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ = 1 2π×ROMax.×CO 12/16 2010.04 - Rev.C Technical Note BD9152MUV 5. Determination of VOUT2 output voltage The output voltage VOUT2 is determined by the equation (6): VOUT2=(R2/R1+1)×VFB2・・・(6) VFB2: Voltage at ADJ terminal (0.8V Typ.) With R1 and R2 adjusted, the output voltage may be determined as required. L2 VOUT2 SW2 FB2 Adjustable output voltage range : 0.8V～2.5V Cout2 R2 R1 Fig.39 Determination of output voltage Use 1 kΩ～100 kΩ resistor for R1. If a resistor of the resistance higher than 100 kΩ is used, check the assembled set carefully for ripple voltage etc. ●BD9152MUV Cautions on PC Board layout VOUT1 L1 FB1 EN1 SW1 SW1 PGND1 ITH1 RITH1 CITH1 RITH2 CITH2 COUT1 PGND1 AGND PVcc N.C. PVcc AVcc PVcc ITH2 PGND2 FB2 EN2 SW2 SW2 PGND2 CIN1 CIN2 COUT2 VOUT2 L2 R2 R1 Fig.40 Layout diagram ① ② Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin PGND. Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring. ※ VQFN020V4040 (BD9152MUV) has thermal PAD on the reverse of the package. The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of PCB. www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ 13/16 2010.04 - Rev.C Technical Note BD9152MUV ●Recommended components Lists on above application Symbol Part Value Manufacturer Series Coil 2.2uH TDK LTF5022-2R2N3R2 CIN1,CIN2 Ceramic capacitor 22uF Murata GRM32EB11A226KE20 Cout1,Cout2 Ceramic capacitor 22uF Murata GRM31CB30J226KE18 CITH1 Ceramic capacitor 680pF Murata GRM18 Series RITH1 Resistance 82kΩ Rohm MCR03 Series L1,2 CITH2 RITH2 Ceramic capacitor Resistance VOUT2=0.8V 680pF Murata GRM18 Series VOUT2=1.0V 680pF Murata GRM18 Series VOUT2=1.2V 680pF Murata GRM18 Series VOUT2=1.5V VOUT2=1.8V VOUT2=2.5V VOUT2=0.8V VOUT2=1.0V VOUT2=1.2V VOUT2=1.5V VOUT2=1.8V VOUT2=2.5V 680pF 680pF 680pF 12kΩ 12kΩ 15kΩ 15kΩ 33kΩ 82kΩ Murata Murata Murata Rohm Rohm Rohm Rohm Rohm Rohm GRM18 Series GRM18 Series GRM18 Series MCR03 Series MCR03 Series MCR03 Series MCR03 Series MCR03 Series MCR03 Series ※The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode or snubber established between the SW and PGND pins. ●I/O equivalence circuit ・EN1,EN2 pin ・SW1,SW2 PVCC PVCC PVCC EN1,EN2 SW1,SW2 ・FB1,FB2 pin ・ITH1,ITH2 pin AVCC FB1,FB2 ITH1,ITH2 Fig.41 I/O equivalence circuit www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ 14/16 2010.04 - Rev.C Technical Note BD9152MUV ●Notes for use 1. Absolute Maximum Ratings While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. Electrical potential at GND GND must be designed to have the lowest electrical potential In any operating conditions. 3. Short-circuiting between terminals, and mismounting When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may also cause breakdown. 4. Thermal shutdown protection circuit Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any operation originally intended. 5. Inspection with the IC set to a pc board If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply before it is connected and removed. 6. Input to IC terminals This is a monolithic IC with P+ isolation between P-substrate and each element as illustrated below. This P-layer and the N-layer of each element form a P-N junction, and various parasitic element are formed. If a resistor is joined to a transistor terminal as shown in Fig 42. ○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and ○if GND>Terminal B (at NPN transistor side), a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode. The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements. Resistor Transistor (NPN) Pin A C Pin B B E Pin A N P+ N P+ P N Parasitic element N P + B N P P substrate Parasitic element GND P C + N E Parasitic element P substrate Parasitic element GND GND GND Other adjacent elements Fig.42 Simplified structure of monorisic IC 7. Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. 8 . Selection of inductor It is recommended to use an inductor with a series resistance element (DCR) 0.15Ω or less. Note that use of a high DCR inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF. When using an inductor over 0.15Ω, be careful to ensure adequate margins for variation between external devices and this IC, including transient as well as static characteristics. www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ 15/16 2010.04 - Rev.C Technical Note BD9152MUV Ordering part number B D 9 Part No. 1 5 2 M Part No. U V - Package MUV: VQFN020V4040 E 2 Packaging and forming specification E2: Embossed tape and reel VQFN020V4040 <Tape and Reel information> 4.0±0.1 4.0±0.1 2.1±0.1 0.5 0.4±0.1 1 6 16 1.0 Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 5 20 10 15 2500pcs (0.22) S C0.2 Embossed carrier tape Quantity 11 2.1±0.1 0.08 S +0.03 0.02 -0.02 1.0MAX 1PIN MARK Tape +0.05 0.25 -0.04 1pin (Unit : mm) www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. ○ Reel 16/16 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2010.04 - Rev.C Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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