tm TE CH T15V4M16B 256K X 16 LOW POWER CMOS STATIC RAM SRAM FEATURES • Single power supply voltage of 2.7V to 3.6V GENERAL DESCRIPTION The T15V4M16B is a very Low Power CMOS • Low Stand-by Current : 35uA • Power down features using CE# Static RAM organized as 262,144 words by 16 bits. • Low power dissipation • Data retention supply voltage: 1.5V to 3.6V to 3.6V power supply, Fabricated using high That operates on a wide voltage range from 2.7V • Direct TTL compatibility for all input and output • Wide operating temperature range: -40°C to 85°C performance CMOS technology, Inputs and • Standby current @ VDD = 3.6 V structures. Data retention is guaranteed at a power three-state outputs are TTL compatible and allow for direct interfacing with common system bus supply voltage as low as 1.5V. PART NUMBER EXAMPLES PART NO. PACKAGE CODE BLOCK DIAGRAM T15V4M16B-70S S = TSOP-II T15V4M16B-70C C = BGA T15V4M16B-85S G = lead free T15V4M16B-85C T15V4M16B-70SG T15V4M16B-70CG T15V4M16B-85SG T15V4M16B-85CG Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 1 Publication Date: FEB. 2007 Revision:A tm TE CH T15V4M16B PIN CONFIGURATIONS 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B DQ8 UB A3 A4 CE DQ0 C DQ9 D Q 10 A5 A6 DQ1 DQ2 D GND D Q 11 A17 A7 DQ3 VDD E VDD D Q 12 NC A16 DQ4 GND F D Q 14 D Q 13 A14 A15 DQ5 DQ6 G D Q 15 NC A12 A13 W E DQ7 H NC A8 A9 A10 A11 NC 48-Ball BGA TOP VIEW (Ball Down) PIN DESCRIPTIONS SYMBOL A0 ~ A17 DESCRIPTIONS Address inputs DQ0~DQ15 Data inputs/outputs SYMBOL DESCRIPTIONS Lower byte (DQ0~7) LB UB Upper byte (DQ8~15) CE Chip enable VDD Power supply WE Write enable input GND Ground OE Output enable input NC No connection Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 2 Publication Date: FEB. 2007 Revision:A tm TE CH T15V4M16B TRUTH TABLE Mode Read Write CE# L L OE# WE# L X H L LB# UB# DQ0~DQ7 DQ8~DQ15 L L DOUT DOUT H L High-Z DOUT L H DOUT High-Z L L DIN DIN H L High-Z DIN L H DIN High-Z High-Z High-Z High-Z High-Z L H H X X L X X H H H X X X X Output Deselect Standby *Note: X = Don’t Care (Must be low or high state), L = Low, H = High ABSOLUTE MAXIMUM RATINGS Supply voltage, VDD -0.3 to +4.6V Input voltages, VIN -0.3 to +4.6V -0.5 to VDD +0.5V Input and output voltages, VI/O Operating temperature, TOPR -40 to +85°C Storage temperature, TSTRG -55 to +150°C Soldering Temperature (10s), TSOLDER 260°C Power dissipation, PD 0.6 W Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 3 Publication Date: FEB. 2007 Revision:A tm TE CH T15V4M16B RECOMMENDED OPERATING CONDITIONS (Ta = -40°C to 85°C**) PARAMETER Supply Voltage SYM VDD GND MIN 2.7 0.0 2.7 -0.3 VIH VIL Input Voltage TYP 3.0 0.0 - MAX 3.6 0.0 VDD+0.3 0.6 UNIT V V V V Note: (1) Overshoot : VDD +2.0V in case of pulse width ≤ 20ns Undershoot : -2.0V in case of pulse width ≤ 20ns OPERATING CHARACTERISTICS (Ta = -40°°C to 85°°C, VDD = 2.7V to 3.6V) Parameter Input low current Symbol IIL Test Conditions IIN = 0V to VDD Min Max Unit -1 1 uA Output low voltage VOL IOL = 2.1 mA - 0.4 V Output high voltage VOH IOH = -1.0 mA VDD - 0.15 − V IDD1 CE# = VIL and − 25 IDD2 Standby current Cycle time = min VDD = 3.6 V IOUT = 0mA Operating current IDDS2 mA Other Input = VIH / VIL CE# ≥ VDD - 0.2V Cycle time = 1us -70/85 VDD = 3.6 V − 5 − 35 CAPACITANCE (f = 1 MHz, Ta = 25°C,) PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL C IN C I/O CONDITION VIN = 0V VIN = VOUT = 0V MAX. 10 10 UNIT pF pF Note: This parameter is guaranteed by device characterization and is not production tested. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 4 Publication Date: FEB. 2007 Revision:A uA tm TE CH T15V4M16B AC Characteristics and Operating Conditions (Ta = -40°°C to 85°°C, VDD = 2.7V to 3.6V) Read Cycle Symbol Parameter -85 -70 Min Max Min Max 85 70 − − tRC tAA Read cycle time Address access time − 85 − 70 tCO1 tOE Chip Enable (CE#) Access Time − 85 − 70 Output enable access time − 45 − 35 tBA tLZ Data Byte Control Access Time − 45 − 35 Chip Enable Low to Output in Low-Z 10 − 10 − tOLZ tBLZ Output enable Low to Output in Low-Z 3 − 3 − Data Byte Control Low to Output in Low-Z 5 − 5 − Chip Enable High to Output in High-Z − 35 − 25 Output Enable High to Output in High-Z − 35 − 25 Data Byte Control High to Output in High-Z − 35 − 25 Output Data Hold Time 0 − 0 − tHZ tOHZ tBHZ tOH Unit ns Write Cycle Symbol tWC tWP tCW tBW tAS tWR tWHZ tOW tDS tDH Parameter -85 -70 Min Max Min Max 85 70 − − Write cycle time Write pulse width 55 − 55 − Chip Enable to end of write 70 − 60 − Data Byte Control to end of Write 70 − 60 − Address setup time 0 − 0 − Write Recovery time 0 − 0 − WE# Low to Output in High-Z − 35 − 30 WE# High to Output in Low-Z 5 − 5 − Data Setup Time 35 − 30 − Data Hold Time 0 − 0 − Unit ns AC Test Condition • Output load : 50pF + one TTL gate • Input pulse level : 0.4V, 2.4V • Timing measurements : 0.5 x VDD • tR, tF : 5ns Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 5 Publication Date: FEB. 2007 Revision:A tm TE CH T15V4M16B TIMING WAVEFORMS Read Cycle(See Note 1) Write Cycle1 (WE# Controlled)(See Note 4) Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 6 Publication Date: FEB. 2007 Revision:A tm TE CH T15V4M16B Write Cycle 2 (CE# Controlled)(See Note 4) Write Cycle3 (UB#, LB# Controlled)(See Note 4) Note: 1. 2. 3. 4. 5. WE# remains HIGH for the read cycle. If CE# goes LOW with or after WE# goes LOW, the outputs will remain at high impedance. If CE# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance. If OE# is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 7 Publication Date: FEB. 2007 Revision:A tm TE CH T15V4M16B Data Retention Characteristics (Ta = -40°°C to 85°°C) Symbol Parameter CE# ≥ VDD - 0.2V, VDR Data Retention Supply Voltage IDR Data Retention Current tSDR Chip Deselect to Data Retention Mode Time tRDR Recovery Time VIN ≥ VDD - 0.2V or VIN ≤ 0.2V VDD = 1.5V, CE# ≥ VDD - 0.2V, ≥ VDD - 0.2V or VIN ≤ 0.2V VIN Min Max Unit 1.5 3.6 V − 35 uA 0 − ns tRC − ns CE# Controlled Data Retention Mode Note: 1. CE# ≥ VDD – 0.2V or UB# = LB# ≥ VDD – 0.2V Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 8 Publication Date: FEB. 2007 Revision:A tm TE CH T15V4M16B PACKAGE DIMENSIONS 44-LEAD TSOP-II D 44 23 E2 E E1 L1 b1 22 INDEX MARK Mirror finish c e b A £c A3 A2 c1 Symbol A A1 A2 A3 b b1 c c1 D e E E1 E2 L L1 θ Dimension in mm Nom Min Max 1.20 0.05 0.1 0.95 1.00 1.05 0.25 0.35(typ) 0.10 0. 15 0.25 0.805 0.10 18.31 18.41 18.51 0.80(typ) 11.56 11.76 11.96 10.03 10.16 10.29 10.76 0.4 0.5 0.6 0.8(typ) 0 8 SEATING PLANE A1 L Dimension in inch Min Nom Max 0.047 0.002 0.004 0.037 0.039 0.041 0.010 0.014(typ) 0.004 0.006 0.010 0.032 0.004 0.721 0.725 0.729 0.031(typ) 0.455 0.463 0.471 0.394 0.400 0.405 0.458 0.016 0.020 0.024 0.032(typ) 0 8 Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 9 Publication Date: FEB. 2007 Revision:A tm TE CH T15V4M16B PACKAGE DIMENSIONS 48-pin BGA (8 row x 6 column) 48 BALL FINE PITCH BGA (0.75mm ball pitch) Units : millimeters B ottom V ie w To p V ie w A 1 IN DE X MA RK B 0 .5 0 B1 0.50 # A1 C C1 C1/2 B /2 A Y E2 D E Symbol A B B1 C C1 D E E1 E2 Y min 5.95 7.95 0.25 0.20 - typ 0.75 6.00 3.75 8.00 5.25 0.30 1.10 0.95 0.25 - max 6.05 8.05 0.35 1.20 0.30 0.08 0.3 0 E1 Notes : 1. Bump counts : 48 (8 row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75) typ. 3. All tolerance are ±0.050 unless otherwise specified. 4. ‘Y’ is coplanarity : 0.08(max) 5. Units : mm Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 10 Publication Date: FEB. 2007 Revision:A