PL133-47 Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC FEATURES DESCRIPTION The PL133-47 is an advanced fanout buffer design for high performance, low-power, small form factor applications. The PL133-47 accepts a reference clock input from DC to 150MHz and provides 4 outputs of the same frequency. 1:4 LVCMOS output fanout buffer for DC to150MHz Low Additive Phase Jitter of 60fs RMS 8mA Output Drive Strength Low power consumption for portable applications Low input-output delay Output-Output skew less than 250ps 2.5V to 3.3V, ±10% operation Operating temperature range from -40°C to 85°C Available in 8-Pin SOP GREEN/RoHS package The PL133-47 is offered in a SOP-8L package and it offers the best phase noise, additive jitter performance, and lowest power consumption of any comparable IC. BLOCK DIAGRAM AND PACKAGE PINOUT CLK0 CLK1 REF CLK2 VDD 1 8 CLK3 VDD 2 7 CLK2 REF 3 6 CLK1 GND 4 5 CLK0 CLK3 SOP-8L 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 02/14/11 Page 1 PL133-47 Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC PIN DESCRIPTIONS Name SOP-8L Type Description REF 3 I Input reference frequency. CLK0 5 O Buffered clock output CLK1 6 O Buffered clock output CLK2 7 O Buffered clock output CLK3 8 O Buffered clock output VDD 1, 2 P VDD connection GND 4 P GND connection LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ). - Design long traces (> 1 inch) as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bouncing back and forth. - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1F for designs using frequencies < 50MHz and 0.01F for designs using frequencies > 50MHz. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 02/14/11 Page 2 PL133-47 Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC ABSOLUTE MAXIMUM CONDITIONS Supply Voltage to Ground Potential ...... –0.5V to 4.6V DC Input Voltage ........................... V SS – 0.5V to 4.6V Storage Temperature ........................ –65°C to 150°C Junction Temperature………………………….. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015)…………..> 2000V OPERATING CONDITIONS Parameter Description Min. Max. Unit V DD Supply Voltage 2.25 3.63 V 0 70 C Industrial Operating Temperature (ambient temperature) -40 85 C Load Capacitance, below 100 MHz ― 30 pF Load Capacitance between 100 MHz and 134 MHz ― 10 pF Load Capacitance, above 134 MHz ― 5 pF C IN Input Capacitance ― 7 pF REF, CLK[1:6] Operating Frequency, Input=Output DC 150 MHz t PU Power-up time for all V DD s to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms TA CL Commercial Operating Temperature (ambient temperature) ELECTRICAL CHARACTERISTICS (Commercial and Industrial Temperature Devices) Parameter Description Test Conditions Min. Max. Unit – 0.8 V 2.0 – V VIL Input LOW Voltage [1] VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V – 50 µA IIH Input HIGH Current VIN = VDD – 100 µA VOL Output LOW Voltage [2] IOL = 8 mA – 0.4 V VOH Output HIGH Voltage [2] IOH = –8 mA 2.4 – V IDD Supply Current 66.67MHz with unloaded outputs – 32 mA [1] 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 02/14/11 Page 3 PL133-47 Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC SWITCHING CHARACTERISTICS (Commercial and Industrial Temperature Devices) [3] Parameter Description Test Conditions Min. Typ. Max. Unit Duty Cycle [2] = t2 ÷ t1 Measured at 1.4V, Input is 50% 40 50 60 % t3 Rise Time [2] Measured between 0.8V and 2.0V – – 1.5 ns t4 Fall Time Measured between 0.8V and 2.0V – – 1.5 ns t5 Output to Output Skew [2] All outputs equally loaded – – 250 ps t6 Propagation Delay, REF Rising Edge to CLKX Rising Edge [2] Measured at VDD/2 1 5 9.2 ns Typ. Max. Unit [2] Notes: 1. REF input has a threshold voltage of V DD /2 2. Parameter is guaranteed by design and characterization. Not 100% tested in produ ction. 3. All parameters are specified with loaded outputs. NOISE CHARACTERISTICS (Commercial and Industrial Temperature Devices) Parameter Description Test Conditions Min. Additive Phase Jitter V DD=3.3V, Frequency=100MHz Offset=12KHz ~ 20MHz 60 fs PL133-47 Additive Phase Jitter: VDD=3.3V, CLK=100MHz, Integration Range 12KHz to 20MHz: 0.059ps typical. REF Input PL133-47 Output 10000 100000 -60 -70 -80 Phase Noise (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 10 100 1000 1000000 10000000 100000000 Offset Frequency (Hz) When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive Phase Jitter is as follows: 2 Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter) 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 2 www.phaselink.com Rev 02/14/11 Page 4 PL133-47 Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC SWITCHING WAVEFORMS Duty Cycle Timing t1 t2 1.4V All Outputs Rise/Fall Time 1.4V 2.0V 2.0V 0.8V OUTPUT 3.3V V 0V 0.8V t3 t4 Output-Output Skew 1.4V OUTPUT 1.4V OUTPUT t5 Input-Output Propagation Delay VDD/2 INPUT VDD/2 OUTPUT t6 TEST CIRCUIT VDD 0.1 F OUTPUTS C LOAD VDD 0.1 F GND CLK GND 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 02/14/11 Page 5 PL133-47 Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC PACKAGE DRAWING (GREEN PACKAGE COMPLIANT) SOP 8L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC E H D A2 A A1 C e 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 b www.phaselink.com L Rev 02/14/11 Page 6 PL133-47 Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC ORDERING INFORMATION For part ordering, please contact our Sales Department: 2880 Zanker Road, San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range Part/Order Number PL133-47SC PL133-47SC-R PL133-47SI PL133-47SI-R Marking Package Option Green (Lead-Free) Package P133-47 8-Pin SOP SC 8-Pin SOP LLLLL P133-47 8-Pin SOP SI 8-Pin SOP LLLLL Tube (Tape and Reel) Tube (Tape and Reel) *Note: LLLLL designates lot number PhaseLink Corporation, reserves the right to make changes in its products or specificat ions, or both at any time without notice. The information fu rnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any lo ss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the e xpress written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 02/14/11 Page 7