PhaseLink Offices www.phaselink.com PhaseLink Corporation, USA US Headquarters 47745 Fremont Boulevard Fremont, CA 94538 + 1.510.492.0990 (phone) + 1.510.492.0991 (fax) [email protected] PhaseLink Company, Ltd., Taiwan Asia Pacific Headquarters 5F-3, No. 94, Pao Chung Road. Hsin Tien, Taipei, Taiwan, R.O.C. + 886.2.2910.0248 (phone) + 886.2.2910.0249 (fax) [email protected] PhaseLink Technology Inc., China No. 2101, Building 3, Caoxi Rd Xuhui Qu, Shanghai, China + 86.21.54261068 (phone) [email protected] Copyright©2007, PhaseLink Corporation PhaseLink, AFM, Pico-PLL, Pico-EMI are trademarks of PhaseLink Corporation 03/07 Product Selector Guide 2007 CHINA ROHS EU ROHS www.phaselink.com Product Contents About PhaseLink Founded in 1999, PhaseLink has established itself as a leading global supplier of high performance Frequency Generation and Signal Conditioning solutions for the communication, storage network, consumer electronics and personal computing markets. Our expertise resides in analog intensive mixed signal integrated circuits for frequency synthesis, multiplication and conditioning. Through our proprietary technology, we provide unequalled performance in frequency multiplication for optical, Gigabit and telecommunication applications as well as the world’s smallest programmable clocks. Our constant efforts for innovation and simplification also deliver affordable clock generation products for the personal electronic, home electronic, portable device, storage network, and wireless system markets. Through our advanced design, manufacturing, and packaging capabilities, coupled with our responsiveness to shifting market trends, we have established a track record of producing highperformance, low-cost products. Our design methodology enables rapid prototyping of both standard and custom solutions, available for sampling in just a few days. Our worldwide manufacturing information system ensures ontime delivery. Furthermore, PhaseLink and its suppliers are ISO 9001-certified. Frequency Generation Voltage Controlled Frequency Source 15 15 16 17 Reference Frequency Clock 14 14 16 17 18 Crystal Oscillator (XO) ICs General Purpose PLL Multiplier Clocks Analog Frequency Multiplier Clocks PhasorV Frequency Multiplier Clocks Multimedia and Network Clocks PicoPLLTM - Programmable Clocks 12-13 Programmable Clocks Clock Distribution 19 Non-PLL Fanout Buffers 19 Zero Delay Buffers 19 Translator Buffers Signal Conditioning 18 EMI Reduction ICs Featured Products 4 5 6-11 2 VCXO ICs VCXO with PLL Multiplier ICs VCXO with Analog Frequency Multiplier IC VCXO with PhasorV Frequency Multiplier IC Analog Frequency Multiplier (AFM) PhasorV Frequency Multiplier Quick Turn Programmable Clocks (QTC) 3 Featured Product Featured Product < 0.4ps Phase Jitter (12KHz-20MHz) < 20ps PK-PK Period Jitter < 0.25ps Phase Jitter (12KHz-20MHz) < 2.5ps RMS Period Jitter < 20ps PK-PK Period Jitter 0 Phase Noise Comparison at 155.52MHz -20 -40 155.52MHz Jitter Comparison -60 -80 -100 PhasorV (blue) =38.88x4 -120 -140 -160 AFM (red) =77.76x2 10 100 1K 10K 100K 1M 10M 100M 8 9 L(f) [dBc/Hz] vs f [Hz] Practically, No Accumulated Jitter PhasorV Long Term Jitter Industry’s first CMOS Non-PLL multiplier utilizing analog multiplication of a high frequency fundamental or 3rd overtone crystal input. Our patent pending AFM technology can generate up to 800MHz in LVPECL, LVDS or CMOS without using a phased lock loop. This is achieved with practically no jitter or phase noise deterioration. See page 16 for detailed product selector guide. RMS Jitter (ps) (Crystal=38.88MHz, Output=155.52MHz) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 6 Interval (us) 7 10 For detail product selector guide, please refer to page 17. 4 5 Featured Product Tiny Package, Big Benefits ! World’s Smallest Programmable Clock Applications Unlimited ! Lowest Power Consumption 1.8V, 2.5V, 3.3V Supply 30~70ps Peak-Peak Jitter Fast Turnaround with Factory Programming Unit: mm 6x5 11.5X 3x3 3.5X 3x3 3.5X 2.2x2.3 2x1.3 2X 1X Device Family PL611s PL612 PL613 PL671 PL672 PL673 PL653 PL657 PhaseLink’s QTC programmable clock family is a general purpose frequency synthesizer with the key features of low jitter, low power and tiny package. This low cost frequency source solution is designed to fit almost any application where high performance, space saving and time to market is crucial. 6 # of PLLs EMI # of Outputs Voltage Package Crystal: 10 - 50 Clock : 0.01-200 up to 8 1.8V, 2.5V, 3.3V DFN, (M)SOP SOT23, SC70, QFN3x3, (T)SSOP Crystal: 10 - 50 Clock : 1-200 up to 10 1.8V, 2.5V, 3.3V SOT23, (M)SOP, QFN3x3, (T)SSOP √ Crystal: 17 - 36 Clock : <200 up to 9 2.5V, 3.3V QFN3x3 (T)SSOP √ Crystal: 17 - 36 Clock : <200 up to 9 2.5V, 3.3V QFN3x3 (T)SSOP VCXO √ (1-3) √ (1-3) √ √ (3) √ (3) √ Input (MHz) Programming Box Available Please Order your sample requests and evaluation board on line at www.phaselink.com 7 Application Examples 1. Line Card for High Speed Serial Links 2. DTV/HDTV PhaseLink offers a variety of high performance timing sources for the most demanding communication applications such as 10Gbps line cards. PL613-01, a three Programmable Frequency Synthesizer, provides all the necessary clocks for common DTV/HDTV requirements. 3. USB Clock PL611s-17, a KHz to MHz Programmable Frequency Synthesizer, can generate an USB clock from a 32.768KHz reference input. 8 9 Application Examples 4. VOIP Phone 6. Bluetooth Headset PL611s-18, a MHz to KHz Programmable Frequency Synthesizer, can generate both MHz and KHz clock outputs from a MHz crystal input. PL611s-28, a low power programmable PLL, is the ideal clocking solution to generate any frequency for handheld and small footprint applications. 5. Printer 7. Digital Video (Set top Box, DTV) PhaseLink’s PL671 PicoEMI Programmable Spread Spectrum Clock Generator (PSSCG) can generate multiple clocks to reduce EMI emission. Using PLL500 VCXO IC and PL611s Pico-PLL programmable clock, users are able to generate multiple VCXO clocks at low cost. 10 11 Programmable Clocks PicoPLL is PhaseLink’s line of programmable, low-cost clock ICs. Accepting a single crystal or reference clock input and producing up to 10 outputs, the PicoPLL family is designed to reduce system cost and fit almost any application where high performance, low-power, space saving, cost sensitivity and time to market are crucial. Part Numer # of PLLs Input (MHz) Xtal Reference Output (MHz) # of Outputs Voltage Programmable I/O Pin Ultra Low Power Other Features Package 1.8V 2.5V 3.3V PDB OE FSEL CLK √ √ √ √ √ √ √ √ √ √ √ √ √ √ Differential CMOS and PECL/LVDS compatible SOP-8, MSOP-8 Fixed FSEL Input pin DFN-6, SC70-6, SOT23-6 MHz to MHz Clocks PL611s-02 PL611s-28 1 10 - 50 1 - 200 ≤ 200 (-02) ≤ 65*1 (-28) ≤2 PL611-01 1 10 - 30 1 - 200 ≤ 200 ≤3 √ √ PL611-30 PL611-31 1 10 - 30 1 - 200 ≤ 400 (-30) ≤ 200 (-31) ≤3 √ (-31) √ PL611s-26 1 - 1 - 200 ≤ 200 1 √ √ √ √ √ √*2 √ PL611s-27 1 - 1 - 200 ≤ 65*1 2 √ √ √ √ √ √ √*3 √ Fixed 2nd Clock output DFN-6, SC70-6, SOT23-6 PL612-01 2 10 - 50 1 - 200 ≤ 200 ≤8 √ √ √ √ √ √ √ √ Individual clock disable option for each output QFN3x3-16, (T)SSOP-16 PL613-01 3 10 - 50 1 - 200 ≤ 200 ≤8 √ √ √ √ √ √ √ √ Individual clock disable option for each output QFN3x3-16, (T)SSOP-16 PL653-01 3 17 - 36 1 - 200 ≤ 200 ≤9 √ √ √ √ √ √ √ VCXO Output SOP-8, QFN, TSSOP ≤3 √ √ √ SS Rate: ±0.125%~±2.0% (C) or -0.25%~-4.0% (D) SOT23-6, MSOP-8, SOP-8 √* SS Rate: ±0.125%~±2.0% (C) or -0.25%~-4.0% (D) SOT23-6 SS Rate: ±0.125%~±2.0% (C) or -0.25%~-4.0% (D) SOT23-6 DFN-6, SC70-6, SOT23-6 √ (-28) SOT23-6, SOP-8, MSOP-8 MHz to MHz Clocks (With EMI Reduction) PL671-01/-25 1 10 - 40 1 - 200 ≤ 200 √ √ √* PL671-21/-22 1 10 - 40 1 - 200 ≤ 200 ≤2 √ √ PL671-05/-06 1 - 10 - 200 10 - 200 1 √ √ PL672-01 2 10 - 50 1 - 200 ≤ 200 ≤ 10 √ √ √ √ √ √ √ SS Rate: ±0.125%~±3.0% (C) or -0.25%~-5.0% (D) QFN3x3-16, (T)SSOP-16/-20 PL673-01 3 10 - 50 1 - 200 ≤ 200 ≤ 10 √ √ √ √ √ √ √ SS Rate: ±0.125%~±3.0% (C) or -0.25%~-5.0% (D) QFN3x3-16, (T)SSOP-16/-20 PL657-01 3 17 - 36 1 - 200 ≤ 200 ≤9 √ √ √ √ √ √ VCXO with EMI reduction . SS Rate: ±0.125%~±3.0% (C) or -0.25%~-5.0% (D) QFN3x3-16, (T)SSOP-16/-20 √ √ √ √ √ 32.768KHz input to MHz output. DFN-6, SC70-6, SOT23-6 √ √ Fixed frequency output, Selectable 12Mhz or 24Mhz DFN-6, SC70-6, SOT23-6 4 4 KHz to MHz Clocks PL611s-17 1 - 0.01 - 200 ≤ 65*1 ≤2 √ √ √ PL611s-52 1 - 32.768KHz 12 or 24 1 √ √ √ MHz to KHz Clocks PL611s-18 1 10 - 50 1 - 200 0.5KHz - 65*1 ≤2 √ √ √ √ √ √ √ √ Can generate 0-ppm 32.768KHz output. DFN-6, SC70-6, SOT23-6 PL611s-19 1 - 1 - 200 0.5KHz - 65*1 2 √ √ √ √ √ √ √ √ Can generate 0-ppm 32.768KHz output. DFN-6, SC70-6, SOT23-6 PL613-18 3 10 - 50 0.01 - 200 ≤ 200 ≤8 √ √ √ √ √ √ √ Can generate 0-ppm 32.768KHz output. QFN3x3-16, (T)SSOP-16 Note *1: Maximum output at 1.8V. *2: Fixed FSEL Input pin. 12 *3: Fixed 2nd Clock output. *4: PDB/CLK1 option (-21), CSEL (-22) 13 Crystal Oscillator (XO) ICs VCXO (Voltage Controlled Crystal Oscillator) ICs PhaseLink’s crystal oscillator ICs provide the best level of negative impedance, lowest jitter, and lowest phase noise up to 200MHz. Our best in class buffer outputs (CMOS, LVDS, LVPECL) make them suitable for all types of applications, including low current, low jitter, low phase noise system clock reference, and ceramic based SMD crystal oscillators. PhaseLink’s integrated low phase noise VCXO products provide cost efficient solutions with high linearity, wide pull-range, and very high temperature stability. They are available in die form or in small form factor packaged chips. Our products meet performance requirements of SONET, ADSL, VDSL, Set top box, and many more applications. Part Number Function Input (MHz) Output (MHz) Output Type Operating Voltage Package Part Number Function Input (MHz) Multiplier Output (MHz) Output Type Voltage Package PL610-01 PL610-02 PL610-03 Programmable Cload, XO, Output Divider 5 - 130 0.1 - 130 CMOS 1.8V - 3.3V DIE SOT23-6 DFN-6 Pull Range (ppm)1 VCXO 16 - 36 N/A +/-200 2.5-3.3V XO 10 - 52 10 - 52 CMOS 1.8V - 3.3V SOT23-6 1 - 4.5 4 - 18 17 - 36 CMOS PL610-27 PLL500-15 PLL500-16 PLL500-17 DIE, SOT23-6 SOP-8 PLL600-27T XO 10 - 52 10 - 52 3 CMOS 1.8V - 3.3V SOP-8 PLL502-51 VCXO 20 - 52 N/A 20 - 52 CMOS +/- 200 3.3V SOP-8 PLL620-20 XO 100 - 200 (or 3rd OT) 100 - 200 PECL/LVDS 3.3V DIE PLL520-20 VCXO 120 - 200 N/A 120 - 200 +/-110 3.3V DIE PLL620-30 XO 65 - 130 (or 3rd OT) 32.5 - 130 PECL/LVDS 3.3v DIE CMOS PECL LVDS PLL520-30 VCXO 65 - 130 N/A 65 - 130 +/-120 3.3V DIE PLL620-38 PLL620-39 XO 65 - 130 (or 3rd OT) 32.5 - 130 PECL (-38) LVDS (-39) 3.3V TSSOP-16 PECL LVDS PLL520-38/39 VCXO 65 - 130 N/A 65 - 130 +/-120 3.3V TSSOP-16 PLL620-80 XO 19 - 65 (or 3rd OT) 9.5 - 65 PECL, LVDS 3.3V DIE PECL LVDS PLL520-80 VCXO 19 - 65 N/A 9.5 - 65 +/-200 2.5-3.3V DIE PLL620-88 PLL620-89 XO 19 - 65 (or 3rd OT) 9.5 - 65 PECL (-88) LVDS (-89) 3.3V TSSOP-16 PECL LVDS PLL520-88/89 VCXO 19 - 65 N/A 9.5 - 65 PECL LVDS +/-200 2.5-3.3V TSSOP-16 PLL521-23 VCXO 100 – 200 N/A 100 – 200 PECL +/-110 2.5-3.3V TSSOP-16 DIE PLL502-00 VCXO+PLL 12-25 1,2,4,8 12 - 200 CMOS +/- 200 3.3V DIE PLL502-02 VCXO+PLL 12-25 2 24 - 50 CMOS +/- 200 3.3V SOP-8 PLL502-03 VCXO+PLL 12-25 4 48 - 100 CMOS +/- 200 3.3V SOP-8 PLL502-04 VCXO+PLL 12-25 8 96 - 200 CMOS +/- 200 3.3V SOP-8 PLL502-30 VCXO+PLL 12-25 /16 to x32 0.75 - 800 CMOS PECL LVDS +/- 200 3.3V DIE PLL502-37 PLL502-35/38 PLL502-39 VCXO+PLL 12-25 /16 to x32 0.75 - 800 CMOS PECL LVDS +/- 200 3.3V QFN3x3-16 TSSOP-16 PLL520-00 PLL520-08 PLL520-09 VCXO+PLL 100-200 1,2,4,8 100 - 800 CMOS PECL LVDS +/- 110 3.3V DIE QFN3x3-16 TSSOP-16 PLL520-10 VCXO+PLL 65-130 1,2,4,8 65 - 800 CMOS PECL LVDS +/- 110 3.3V DIE General Purpose PLL Multiplier Clocks Integrating with the best in class PLL multiplier, this high performance clock family products offer very low jitter output frequency from 750KHz to 800MHz using a low-cost crystal input. Ideas for all types of applications to replace multiple expensive crystals or crystal oscillators. Part Number Function Input (MHz) Multiplier Output (MHz) Output Type Voltage Package PLL602-00 XO+PLL 12 - 25 1,2,4,8 12 - 200 CMOS 3.3V DIE, WAFER PLL602-35 XO+PLL 12 - 25 /16 to x32 0.75 - 800 PECL, Inverted OE 3.3V TSSOP-16, QFN3x3-16 PLL602-37 PLL602-38 PLL602-39 XO+PLL 12 - 25 /16 to x32 0.75 - 800 CMOS (-37) PECL (-38) LVDS (-39) 3.3V TSSOP-16, QFN3x3-16 PLL620-00 XO+PLL 100200 1,2,4 100 - 800 PECL,LVDS CMOS 3.3V DIE, WAFER PLL620-07 PLL620-08 PLL620-09 XO+PLL 100200 1,2,4 100 - 800 CMOS (-07) PECL (-08) LVDS (-09) 3.3V TSSOP-16, QFN3x3-16 14 Note 1: Pull measurement was obtained using a typical crystal within target frequency range. Typical low frequency crystal has C1=16 fF, C0=4 pF (C0/C1=250), High frequency mesa crystal has C1= 6 fF, C0=1.8 pF (C0/C1=300). 15 Analog Frequency (non-PLL) Multiplier (AFMTM) PhasorVTM Frequency Multiplier PhaseLink’s low phase noise and low jitter Analog Frequency Multiplier products provide the most cost efficient clocking solutions for high speed applications. The multiplication of two (X2) or four (X4) times the input crystal frequency significantly lower the cost of expensive crystals to achieve the most stringent performance requirements of telecommunications, storage networking, and high speed networking LAN systems. The PhasorV is a low jitter and low phase noise frequency multiplier, capable of 0.4ps RMS phase jitter and less than 25ps peak to peak period jitter, with practically no Accumulated Jitter. Using a low-cost crystal of 19-40MHz, the PhasorV enables output frequencies of 2X, 4X, 8X, or 16X, up to 640MHz. It supports CMOS, LVDS, and PECL outputs. Jitter(ps) - Typical Part Number Input Range (MHz) Output Range (MHz) Output Type Voltage RMS Period Peak to Peak Period Phase Jitter 12K20MHz Jitter(ps) - Typical Package VCXO ICs (AFM) 75 - 200 300 - 800 (4X) PECL (-08) LVDS (-09) 2.5V, 3.3V 4 25 0.08 @622M DIE, Wafer QFN3x3-16 TSSOP-16 PL560-37 PL560-38 PL560-39 30 - 80 120 - 320 (4X) CMOS (-37) PECL (-38) LVDS (-39) 2.5V, 3.3V 4.7 25 0.25 @155M DIE, Wafer QFN3x3-16 TSSOP-16 PL560-47 PL560-48 PL560-49 30 - 80 60 - 160 (2X) CMOS (-47) PECL (-48) LVDS (-49) 2.5V, 3.3V 2.5 18 0.25 @155M DIE, Wafer QFN3x3-16 TSSOP-16 PL560-68 PL560-69 75 - 200 150 - 400 (2X) PECL (-68) LVDS (-69) 2.5V, 3.3V 2.5 18 0.10 @311M DIE, Wafer QFN3x3-16 TSSOP-16 XO ICs (AFM) 60 - 160 (2X) Input Range (MHz) Output Range (MHz) Output Type # Of Voltage Output RMS Period Peak to Peak Period Phase Jitter 12K20MHz Package VCXO ICs PL560-08 PL560-09 PL663-07 30 - 80 PL663-08 (or 3rd OT) Part Number CMOS (-07) PECL (-08) 2.5V, 3.3V 2.5 PL663-17 CMOS (-17) 75 - 140 150 - 280 PL663-18 PECL (-18) (or 3rd OT) (2X) PL663-19 LVDS (-19) 2.5V, 3.3V 2.5 PL663-28 140 - 160 280 - 320 PL663-29 (or 3rd OT) (2X) 2.5V, 3.3V 2.5 PECL (-28) LVDS (-29) 18 18 18 0.29 @106M DIE, Wafer QFN3x3-16 TSSOP-16 0.14 @212M DIE, Wafer QFN3x3-16 TSSOP-16 0.13 @311M DIE, Wafer QFN3x3-16 TSSOP-16 PL580-30 19 - 40 38 - 640 (2X, 4X, 8X,16 X) CMOS, PECL, LVDS 1 3.3V 3 20 0.4 DIE @155M Wafer PL580-37 PL580-38 PL580-39 19 - 40 38 - 320 (2X, 4X, 8X) CMOS (-37) PECL (-38) LVDS (-39) 1 3.3V 3 20 0.4 QFN3x3-16 @155M TSSOP-16 PL580-68 PL580-69 20 - 40 320 - 640 PECL (-68) (16X) LVDS (-69) 1 3.3V 6 40 0.4 QFN3x3-16 @622M TSSOP-16 PL680-37 PL680-38 PL680-39 19 - 40 38 - 640 CMOS (-37) (2X, 4X, PECL (-38) 8X,16 X) LVDS (-39) 1 2.5V, 3.3V 3 20 0.4 QFN3x3-16 @155M TSSOP-16 PL685-38 19 - 50 50 - 800 PECL 1 2.5V, 3.3V TBD TBD TBD QFN3x3-16 TSSOP-16 PL685-39 19 - 50 50 - 800 LVDS 1 2.5V, 3.3V TBD TBD TBD QFN3x3-16 TSSOP-16 XO ICs Note1: Phase Noise was obtained using Agilent E5500 data. Note2: No Filtering was used in Jitter Calculations. Note1: Phase Noise was obtained using Agilent E5500 data. Note2: No Filtering was used in Jitter Calculations. 16 17 EMI Reduction ICs Clock Distribution PhaseLink’s proprietary Spread Spectrum Timing (SST) technology can efficiently suppress EMI without requiring expensive enclosures or system redesign. These EMI reduction ICs with very low cycle to cycle jitter (100ps Peak-Peak) are suitable for clock generation from a single crystal or a signal reference. PhaseLink’s clock distribution products consist of translator buffers, zero delay buffers and non-PLL fanout buffers. These general purpose buffer products will reproduce a master clock frequency up to 1GHz with low skew between the outputs. Our zero delay buffers use a phase locked loop to ensure zero-delay between the outputs and the master signal. Part Number Translator Buffers PL671 PL672 PL673 PL657 Function Input (MHz) Output (MHz) SST Modulation Magnitude Voltage /Output Package Part Number Function Input/Output (MHz) Output Type Description Voltage Package PLL130-05 Translator to PECL DC to 1000 1 PECL Single ended to PECL, OE (Low) 2.5V, 3.3V QFN3x3-16 Please refer to Page 12-13 for detailed Programmable EMI Clock information. 2.5V, 3.3V SOT23-6, (M)SOP8, QFN3x3-16 (T)SSOP-16 PLL702-01 Fixed Freq. Output + SST 14.318 7 outputs out of 9 freq, <133 -0.5% to -1.25% Down Spread 3.3V SSOP-28 PLL130-07 Translator to CMOS DC to 200 CMOS Singled ended to CMOS 2.5V, 3.3V SOP-8, QFN3x3-16 PLL701-21 1X PLL + SST 24 - 200 Clock input 24 - 200 0.25% to 2.5% Center Spread 3.3V SOP-8 DC to 1000 1 PECL (-08) 1 LVDS (-09) Single ended to PECL (-08), LVDS (-09) 2.5V, 3.3V SOP-8, QFN3x3-16 PLL701-25 1X PLL + SST 33 - 90 Clock input 33 - 90 5 outputs +/- 0.50% Center Spread 3.3V SOP-8 PLL130-08 Translator PLL130-09 to PECL or LVDS PLL701-26 1X PLL + SST 33 - 90 Clock input 33 - 90 5 outputs +/- 1.0% Center Spread 3.3V SOP-8 Zero Delay Buffers Multimedia Clock PhaseLink’s Multimedia Clocks are designed to provide the necessary video or audio clocking requirements. Part Number Input (MHz) [Output Frequencies (MHz)] X number of outputs PL612 PL613 Please refer to Page 12-13 for detailed Programmable Clock Information. Output Type Voltage Package CMOS 1.8V 2.5V 3.3V QFN3x3 (T)SSOP PLL650-03 25 50x4, [25,100]x1, [66.6,75,83.3,100]x1, SST CMOS 3.3V SOP-16 PLL650-04 25 25x1, 50x1, [90,100,125,133,145,150] x5, SST CMOS 3.3V SSOP-20 PLL601-22 27 27x2, 1x Selectable Audio: [8.192, 11.2896, 12.288, 16.9344, 18.432, 22.5792, 8, 24.576] CMOS 3.3V SOP-16 PLL650-04 25 25x1, 50x1, [90,100,125,133,145,150] x5, SST CMOS 3.3V SSOP-20 18 Note: All OE functions are “Logic High” Enabled unless indicated otherwise. Part Number Function Input/Output (MHz) Output Type Description Voltage Package PLL102-03 PLL102-04 PLL102-05 5 outputs 75-180 (-03) 50-120 (-04) 25- 60 (-05) CMOS High Performance Low Skew Buffer 3.3V SOP-8 PLL102-10 3 outputs 15-120 CMOS High Performance Low Skew Buffer 2.5V 3.3V SOT23-6 SOP-8 Non-PLL Fanout Buffers Part Number Function Input/Output (MHz) Output Type Description Voltage Package PLL103-02 12 Differential outputs for DDR SDRAM 66 - 170 Diff. CMOS < 5ps delay < 100ps skew I2C interface 2.5V, 3.3V SSOP-48 PLL600-27T 3 Outputs 10-52 CMOS Low Jitter: 2.5 ps 1.8V, 2.5V, 3.3V SOP-8 PL611-01 3 Outputs DC-200 CMOS Programmable Drive Strength for High fanout 2.5V, 3.3V SOP-8 19