PhaseLink Offices www.phaselink.com PhaseLink Corporation, USA US Headquarters 47745 Fremont Boulevard Fremont, CA 94538 + 1.510.492.0990 (phone) + 1.510.492.0991 (fax) [email protected] PhaseLink Company, Ltd., Taiwan Asia Pacific Headquarters 5F-2, No. 94, Pao Chung Road. Hsin Tien, Taipei, Taiwan, R.O.C. + 886.2.2910.0248 (phone) + 886.2.2910.0249 (fax) [email protected] PhaseLink Corporation, Japan 1-38-7-111 Matsubara Setagaya-ku Tokyo 156-0043 + 81.3.5355.0536, + 81.3.5355.0360 (phone) + 81.3.5355.0553 (fax) [email protected] Product Selector Guide Winter 2004 PhaseLink Technology Inc., China No. 2101, Building 3, Caoxi Rd Xuhui Xu, Shanghai, China + 86.21.54261068 (phone) [email protected] Copyright©2004, PhaseLink Corporation PhaseLink and AFM are trademarks of PhaseLink Corporation www.phaselink.com Product Contents About PhaseLink Founded in 1991, PhaseLink has established itself as a leading global supplier of high performance Frequency Generation and Signal Conditioning solutions for broadband communication, storage network and personal electronic markets. Our expertise resides in analog intensive mixed signal integrated circuits for frequency synthesis, multiplication and conditioning. Through our proprietary technology, we provide unequalled performance in frequency multiplication for optical, Gigabit and telecommunication applications. Our constant efforts for innovation and simplification also deliver affordable clock generation products for the personal electronic, home electronic, portable device, storage network, and wireless system markets. Through our advanced design, manufacturing, and packaging capabilities, coupled with our responsiveness to shifting market trends, we have established a track record of producing highperformance, low-cost products. Our design methodology enables rapid prototyping of both standard and custom solutions, available for sampling in just a few weeks. Our worldwide manufacturing information system ensures ontime delivery. Furthermore, PhaseLink and its suppliers are ISO 9001-certified. Frequency Generation Voltage Controlled Frequency Source 10 11 8 VCXO ICs VCXO with PLL Multiplier ICs VCXO with Analog Frequency Multiplier IC Reference Frequency Clock 6 7 9 12 12 Crystal Oscillator (XO) ICs General Purpose PLL Multiplier Clocks Analog Frequency Multiplier Clocks Network LAN Clocks Multimedia Clocks Quick Turn Programmable Clock 12 Low cost Programmable Clocks Clock Distribution 14 Non-PLL Fanout Buffers 14 Zero Delay Buffers 14 Translator Buffers Signal Conditioning 13 Contact Factory EMI Reduction ICs Jitter Cleaners Featured Products 4 5 15 2 Analog Frequency Multiplier (AFM) Quick Turn Programmable Clocks (QTC) 622.08MHz Phase Noise Comparison 3 Featured Product Analog Frequency Multiplier (AFMTM) Featured Product Featured Product Quick Turn Clock (QTC) Jitter Comparison using PhaseLink’s 520-20 (Fundamental, no multiplier), 560-48 (2X AFM), 560-38 (4X AFM), 502-30 (PLL) Industry’s first CMOS “Balanced Oscillator” utilizing analog multiplication of a high frequency fundamental or 3rd overtone crystal at double or quadruple frequency. Our patent pending AFM technology can generate up to 800MHz in LVPECL, LVDS or CMOS without using a phased lock loop. This is achieved with practically no jitter or phase noise deterioration. See page 8-9 for detailed product selector guide. 4 PL611 is a low cost, general purpose frequency synthesizer, a member of PhaseLink’s factory programmable quick-turn clock family. This low cost clock IC family is designed to fit almost any application where high performance, space saving, cost sensitivity and time to market are crucial. See page 12 for detailed product selector guide. 5 Crystal Oscillator (XO) ICs General Purpose PLL Multiplier Clocks PhaseLink’s crystal oscillator ICs provide the best level of negative impedance, lowest jitter, and lowest phase noise in the frequency ranges, up to the 200MHz range. Our best in class buffer outputs (CMOS, LVDS, LVPECL) make them suitable for all types of applications, including low current clock reference, low jitter, low phase noise system clock reference, and small ceramic based SMD crystal oscillators. Integrating with the best in class PLL multiplier, this high performance clock family products offer very low jitter output frequency from 750KHz to 800MHz using a low-cost crystal input. Ideas for all types of applications to replace multiple expensive crystals and/or crystal oscillators. Part Number Function Input (MHz) Output (MHz) Output Type Operating Voltage Package Part Number Function Input (MHz) Multiplier Output (MHz) Output Type Voltage Package PLL600-27 XO 10 - 52 10 - 52 CMOS Ultra Low Current 1.8V - 3.3V 6 SOT, 8 SOIC PLL602-00 XO+PLL 12 - 25 1,2,4,8 12 - 200 CMOS (Hi Drive) 3.3V 2.5V* Die PLL600-37 XO 10 - 52 10 - 52 Clipped CMOS Ultra Low Current 1.8V - 3.3V 8 SOIC PLL602-01 XO+PLL 12 - 25 2 24 - 50 CMOS 3.3V 8 SOIC/TSSOP PLL600-27T XO 10 - 52 10 - 52 3 CMOS Ultra Low Current 1.8V - 3.3V 8 SOIC PLL602-03 XO+PLL 12 - 25 4 48 - 100 CMOS 3.3V 8 SOIC/TSSOP PLL602-04 XO+PLL 12 - 25 8 96 - 200 CMOS 8 SOIC/TSSOP PLL600-27F XO 10 - 52 10 - 52 5 CMOS Ultra Low Current 1.8V - 3.3V 14 SOIC 3.3V 2.5V* XO+PLL 12 - 25 8 96 - 200 16 SOIC/TSSOP Dual XO 10 - 52 10 - 52 4 CMOS Ultra Low Current 1.8V - 3.3V 14 SOIC PECL (-11) LVDS (-12) 3.3V PLL600-27M PLL602-11 PLL602-12 XO+PLL 12 - 25 16 192 - 400 16 SOIC/TSSOP XO 12 - 27 12 - 27 1 LVDS, 1 CMOS 2.5V, 3.3V 8 SOIC PECL (-13) LVDS (-14) 3.3V PLL602-89 PLL602-13 PLL602-14 PLL602-89C XO 12 - 27 12 - 27 1 LVDS, 2 CMOS 2.5V, 3.3V 8 SOIC PLL602-30 XO+PLL 12 - 25 /16 to x32 0.75 - 800 3.3V 2.5V* Die PLL602-89D XO 12 - 27 12 - 27 2 LVDS 2.5V, 3.3V 8 SOIC CMOS PECL LVDS PLL602-89T XO 12 - 27 12 - 27 3 LVDS, 1 CMOS 2.5V, 3.3V 16 SSOP PLL602-35 XO+PLL 12 - 25 /16 to x32 0.75 - 800 PLL605-27 XO 40 - 44 (3rd OT) 40 - 44 CMOS Ultra Low Current 1.8V - 3.3V 6 SOT, 8 SOIC PECL, Inverted OE 3.3V 2.5V* 16 TSSOP, 3x3 QFN-16 XO+PLL 12 - 25 /16 to x32 0.75 - 800 PLL620-20 XO 100 - 200 (or 3rd OT) 100 - 200 Differential outputs: PECL/LVDS 2.5V, 3.3V Die PLL602-37 PLL602-38 PLL602-39 CMOS (-37) PECL (-38) LVDS (-39) 3.3V 2.5V* 16 TSSOP, 3x3 QFN-16 PLL620-28 PLL620-29 XO 100 - 200 (or 3rd OT) 100 - 200 Differential outputs: PECL (-28) LVDS (-29) 2.5V, 3.3V 16 TSSOP PLL620-00 XO+PLL 100200 1,2,4 100 - 800 CMOS PECL LVDS 3.3V Die PLL620-30 XO 65 - 130 (or 3rd OT) 32.5 - 130 Differential outputs: PECL/LVDS 2.5V, 3.3v Die PLL620-07 PLL620-08 XO+PLL 100200 1,2,4 100 - 800 CMOS (-07) PECL (-08) 3.3V 16 TSSOP, 3x3 QFN-16 PLL620-38 PLL620-39 XO 65 - 130 (or 3rd OT) 32.5 - 130 Differential outputs: PECL (-38) LVDS (-39) (with selectable /2) 2.5V, 3.3V 16 TSSOP PLL620-09 XO+PLL 100200 1,2,4,8 100 - 1GHz LVDS 3.3V 16 TSSOP, 3x3 QFN-16 PLL601-01 XO+PLL 10-27 10 - 160 CMOS 3.3V 16 SOIC/TSSOP PLL620-80 XO 19 - 65 (or 3rd OT) 9.5 - 65 Differential outputs: PECL, LVDS or two CMOS 2.5V, 3.3V Die 1,2,3,4,5, 6,7,8,9, 10,11,12,16 PLL601-02 XO+PLL 10-27 4,8 20-160 CMOS 3.3V 16 SOIC/TSSOP Differential outputs: PECL (-88) LVDS (-89) (with selectable /2) 2.5V, 3.3V PLL601-12 XO+PLL 13 - 31 2.5, 2.75, 3, 4.25, 5, 5.5, 5.75, 6, 6.25, 10, 11, 11.5, 12 32.5 - 312 CMOS 3.3V 16 SOIC/TSSOP PLL620-88 PLL620-89 XO 19 - 65 (or 3rd OT) 9.5 - 65 16 TSSOP *Note: Contact factory for 2.5V low voltage version 6 7 Analog Frequency Multiplier (AFMTM) PhaseLink’s low phase noise and low jitter Analog Frequency Multiplier products provide the most cost efficient solutions with high linearity, wide pull-range, and very high temperature stability. The multiplication of two (X2) or four (X4) times the input crystal frequency significantly lower the cost of expensive crystals to achieve the most stringent performance requirements of telecommunications, Storage networking, and high speed networking LAN systems. The low phase noise and jitter performance of the AFM family of products, combined with their low system implementation cost and small form-factor packaging (TSSOP, SSOP, 3x3 QFN) make them the ideal choice for the above markets. Part Number Input Range (MHz) Multiplier Output Range (MHz) Output Type Phase Noise2 at Frequency Offset From Carrier (dBc/Hz) Voltage 10 Hz 100 Hz 1 KHz 10 KHz 100 KHz 1 MHz 10 MHz Carrier Frequency (MHz) Jitter(ps) - Typical3 RMS Period Peak to Peak Period RMS Accumulated1 Spectral Specifications4 Sub-harmonic Content (dBc) Phase Jitter 12K-20MHz -75% -50% -25% +25% +50% +75% (Fc) (Fc) (Fc) (Fc) (Fc) (Fc) VCXO ICs (AFM) PL560-08 PL560-09 75 - 200 4 300 - 800 PECL (-08) LVDS (-09) 2.5V, 3.3V -55 -85 -110 -130 -137 -148 -150 622.08 4 25 6 0.09 -55 -50 -40 -40 -50 -55 PL560-37 PL560-38 PL560-39 30 - 80 4 120 - 320 CMOS (-37) PECL (-38) LVDS (-39) 2.5V, 3.3V -50 -82 -110 -128 -142 -148 -150 155.52 4.7 24.5 6 0.25 -55 -55 -43 -43 -55 -55 PL560-47 PL560-48 PL560-49 30 - 80 2 60 - 160 CMOS (-47) PECL (-48) LVDS (-49) 2.5V, 3.3V -65 -95 -122 -138 -142 -148 -149 155.52 2.5 18 3 0.25 -55 -55 PL560-68 PL560-69 75 - 200 2 150 - 400 PECL (-68) LVDS (-69) 2.5V, 3.3V -60 -85 -112 -135 -142 -150 -151 311.04 2.5 18 3 0.18 -55 -55 PL660-08 30 - 80 PL660-09 (or 3rd OT) 4 100 - 300 PECL (-08) LVDS (-09) 2.5V, 3.3V -72 -100 -125 -132 -142 -147 -149 155.52 3 21 5 0.3 PL663-07 30 - 80 PL663-08 (or 3rd OT) PL663-09 2 60 - 160 CMOS (-07) PECL (-08) LVDS (-09) 2.5V, 3.3V -75 -105 -130 -140 -145 -150 -150 156.25 2 18 3 0.2 -58 -58 PL663-17 75 - 140 PL663-18 (or 3rd OT) PL663-19 2 150 - 280 CMOS (-17) PECL (-18) LVDS (-19) 2.5V, 3.3V -70 -100 -130 -140 -145 -148 -148 212.5 2.5 18 4 0.2 -58 -58 PL663-28 140 - 160 PL663-29 (or 3rd OT) 2 280 - 320 PECL (-28) LVDS (-29) 2.5V, 3.3V -60 -92 -122 -140 -142 -146 -146 311.04 2.5 18 4 0.2 -58 -58 XO ICs (AFM) -55 -55 -43 -43 -55 -55 Note1: Wavecrest Data 1,000,000 hits. Note2: Phase Noise was obtained using Agilent E5500 data. Note3: No Filtering was used in Jitter Calculations. Note4: Spectral Specifications (Typical) were obtained using Agilent E7401A. 8 9 VCXO (Voltage Controlled Crystal Oscillator) ICs VCXO with PLL Multiplier ICs PhaseLink’s integrated low phase noise VCXO products provide cost efficient solutions with high linearity, wide pull-range, and very high temperature stability. They are available in die form or in small form factor packaged chips. Our products meet performance requirements of the applications such as SONET, ADSL, VDSL, Set top box, etc. This high performance VCXO family of products offers very low jitter and phase noise with integrated PLL multipliers as high as 32X and generates output frequency from 750KHz to 800MHz, using a low-cost crystal input. These VCXO’s high linearity, wide pull range, and high temperature stability make them ideal for Video, SONET, VDSL, ADSL, etc. applications. Part Number Function Input (MHz) Output (MHz) Output Type Pull Range (ppm)1 Operating Voltage Package Part Number Function Input Range (MHz) Multiplier Output Range (MHz) Output Type Pull Range (ppm)2 Voltage Package PLL500-17 PLL500-17B VCXO 17 - 36 17-36 CMOS +/-200 2.5V, 3.3V 6 SOT, 8 SOIC or DIE PLL502-00 VCXO+PLL 12-25 1,2,4,8 12 - 200 CMOS +/- 200 3.3V Die PLL502-02 VCXO+PLL 12-25 2 24 - 50 CMOS +/- 200 3.3V 8 SOIC PLL500-27B VCXO 27 - 65 27 - 65 CMOS +/-200 2.5V, 3.3V 8 SOIC or DIE PLL502-03 VCXO+PLL 12-25 4 48 - 100 CMOS +/- 200 3.3V 8 SOIC PLL500-37B VCXO 65 - 130 65 - 130 CMOS +/-120 2.5V, 3.3V 8 SOIC or DIE PLL502-04 VCXO+PLL 12-25 8 96 - 200 CMOS +/- 200 3.3V 8 SOIC PLL500-47B VCXO 100 - 200 100 - 200 CMOS +/-100 2.5V, 3.3V 8 SOIC or DIE 12-25 8 96 - 200 3.3V 16 TSSOP 12 - 27 12 - 27 CMOS +/- 200 2.5V, 3.3V 8 SOIC or TSSOP PECL (-11) LVDS (-12) +/- 200 VCXO PLL502-11 PLL502-12 VCXO+PLL PLL502-05 PLL502-25 12-25 16 192 - 400 3.3V 16 TSSOP 27 27 + Audio Clock CMOS +/- 250 3.3V 16 SOIC PECL (-13) LVDS (-14) +/- 200 VCXO + Audio PLL PLL502-13 PLL502-14 VCXO+PLL PLL502-26 PLL502-30 VCXO+PLL 12-25 /16 to x32 0.75 - 800 +/- 200 3.3V, 2.5V1 Die PLL502-50 VCXO 20 - 50 2.5 - 50 CMOS +/- 200 2.5V, 3.3V Die CMOS PECL LVDS PLL502-51 VCXO 20 - 52 20 - 52 CMOS +/- 200 2.5V, 3.3V 8 SOIC or TSSOP PLL502-35 VCXO+PLL 12-25 0.75 - 800 VCXO 20 - 40 10 - 20 CMOS +/- 200 2.5V, 3.3V 8 SOIC or TSSOP PECL (~OE) +/- 200 PLL502-52 /16 to x32 3.3V, 2.5V1 3x3 QFN, 16 TSSOP PLL520-20 VCXO 120 - 200 120 - 200 CMOS PECL LVDS +/-110 2.5V, 3.3V Die PLL502-37 PLL502-38 PLL502-39 VCXO+PLL 12-25 /16 to x32 0.75 - 800 CMOS (-37) PECL (-38) LVDS (-39) +/- 200 3.3V, 2.5V1 3x3 QFN, 16 TSSOP PLL520-28 VCXO 120 - 200 120 - 200 PECL +/-110 2.5V, 3.3V 16 TSSOP, 3x3 QFN-16 PLL502-67 VCXO+PLL 4 outputs 12-25 /2 to 8 6 - 200 CMOS +/- 200 3.3V 14 SOIC PLL520-29 VCXO 120 - 200 120 - 200 LVDS +/-110 2.5V, 3.3V 16 TSSOP, 3x3 QFN-16 PLL520-00 VCXO+PLL 100200 1,2,4,8 100 - 1GHz CMOS PECL LVDS +/- 110 3.3V Die PLL520-30 VCXO 65 - 130 65 - 130 PECL LVDS +/-120 2.5V, 3.3V Die PLL520-07 PLL520-08 VCXO+PLL 100200 1,2,4 100 - 800 +/- 110 3.3V 16 TSSOP, 3x3 QFN PLL520-38 VCXO 65 - 130 65 - 130 PECL +/-120 2.5V, 3.3V 16 TSSOP PLL520-09 VCXO+PLL 100 - 1GHz LVDS +/- 110 3.3V VCXO 65 - 130 65 - 130 LVDS +/-120 2.5V, 3.3V 16 TSSOP 100200 1,2,4,8 PLL520-39 16 TSSOP, 3x3 QFN PLL520-40 VCXO 65 - 130 65 - 130 CMOS +/-120 2.5V, 3.3V Die PLL520-10 VCXO+PLL 65-130 1,2,4,8 65 - 800 +/- 110 3.3V Die PLL520-80 VCXO 19 - 65 9.5 - 65 PECL LVDS +/-200 2.5V, 3.3V Die CMOS PECL LVDS PLL520-88 VCXO 19 - 65 9.5 - 65 PECL +/-200 2.5V, 3.3V 16 TSSOP VCXO+PLL 65-130 1,2,4,8 65 - 800 3.3V 16 TSSOP VCXO 19 - 65 9.5 - 65 LVDS +/-200 2.5V, 3.3V 16 TSSOP CMOS (-17) PECL (-18) LVDS (-19) +/- 110 PLL520-89 PLL520-17 PLL520-18 PLL520-19 PLL521-23 VCXO 100 – 200 100 – 200 PECL +/-110 2.5V, 3.3V 16 TSSOP, Die Note 1: Pull measurement was obtained using a typical crystal within target frequency range. Typical Low frequency crystal has C1=16 fF, C0=4 pF (C0/C1=250), High frequency mesa crystal has C1= 6fF, C0=1.8 pF (C0/C1=300). 10 CMOS (-07) PECL (-08) Note 1: Contact factory for 2.5V low voltage version Note 2: Pull measurement was obtained using a typical crystal within target frequency range. Typical Low frequency crystal has C1=16 fF, C0=4 pF (C0/C1=250), High frequency mesa crystal has C1=6 fF, C0=1.8 pF (C0/C1=300). 11 Low Cost Programmable Clocks EMI Reduction ICs Quick-Turn Clock (QTC) is PhaseLink’s line of programmable, Low-cost clock ICs. Accepting a single crystal or reference clock input and producing up to 3 outputs, the QTC family is designed to reduce system cost and fit almost any application where high performance, space saving, cost sensitivity and time to market are crucial. PhaseLink’s proprietary Spread Spectrum Timing (SST) technology can efficiently suppress EMI without requiring expensive enclosures or system redesign. These EMI reduction ICs with very low Cycle to Cycle jitter (Typical meaured at 100ps) are suitable for clock generation from a single crystal or a signal reference. Part Number Input (MHz) Output (MHz) # of Outputs Voltage Other Features Package Part Number Function Input (MHz) Output (MHz) SST Modulation Magnitude Voltage /Output Package PL611-01 10 - 30 or <75 3rd OT <200 up to 3 2.5V, 3.3V Programmable CLOCK/OE/ PDB/FSEL 8 MSOP/SOIC or 6 SOT PLL702-01 Fixed Freq. output + SST 14.318 7 outputs, 9 freq. up to 133 -0.5% to -1.25% Down Spread 3.3V CMOS 28 SSOP PL611-20 10 - 30 or <75 3rd OT <200 Dual +Ref 2.5V, 3.3V Programmable REF/OE/FSEL 8 MSOP/SOIC or 6 SOT PLL702-02 Fixed Freq. output + SST 14.318 or 24.576 0.5% to 1.5% Center Spread 3.3V CMOS 16 SOIC or TSSOP PL611-30 10 - 30 <375 2+ Ref 3.3V Differential outputs 8 MSOP/SOIC 24.576, 25,12, 10 or 8, 27 or 14.318 Note: Most devices in this family accept Reference Clock input of <200MHz. PLL702-05 Fixed Freq. output + SST 14.318 or 24.576 24.576, 25, 27 or 14.318 0.5 and 0.75 Center Spread 3.3V CMOS 8 SOIC LAN and Multimedia Clocks Source PLL701-01 PLL701-02 PLL701-04 PLL701-06 1X (-01) 2X (-02) 4X (-04) 6X (-06) PLL + SST 10 - 30 Crystal or Clock Input 10 - 30 (-01) 20 - 60 (-02) 40 - 120 (-04) 60 - 180 (-06) 0.50% to 3.50% A, C, D Spread* 3.3V CMOS 8 SOIC PLL701-10 (1,2,3,4,5,6, 7,8)X PLL + SST 10 - 30 Crystal or Clock input 10 - 240 0.25% to 3.75% A, C, D Spread* 3.3V CMOS 16 SSOP PLL701-50 (1,2,3,4,5,6, 7,8)X PLL + SST 10 - 30 Crystal or Clock input 10 - 240 0.25% to 3.75% A, C, D Spread* 3.3V CMOS Die PLL701-11 (1,2,4)X PLL + SST 24 - 120 Clock input 24 - 240 0.50% to 2.50% Center Spread* 3.3V CMOS 8 SOIC PLL701-13 (1,2,4)X PLL + SST 24 - 120 Clock input 24 - 240 -0.50% to -3.0% Down Spread* 3.3V CMOS 8 SOIC PLL701-14 6X PLL + SST 10 - 30 Crystal or Clock input 60 - 180 0.25% to 0.75% Center Spread* 3.3V CMOS 8 SOIC PLL701-17 (1,2,4,2.94) X PLL+SST 12 - 60 Crystal or Clock input 12 - 240 0.25% to 1.25% Center Spread* 3.3V CMOS 8 SOIC PLL701-21 1X PLL + SST 24 - 200 Clock input 24 - 200 0.50% to 2.5% Center Spread* 3.3V CMOS 8 SOIC PLL701-25 1X PLL + SST 33 - 90 Clock input 33 - 90 5 outputs +/- 0.50% Center Spread 3.3V CMOS 8 SOIC PLL701-26 1X PLL + SST 33 - 90 Clock input 33 - 90 5 outputs +/- 1.0% Center Spread 3.3V CMOS 8 SOIC PLL701-31 1X PLL + SST 10 - 30 Crystal or Clock input 10 - 30 3.25% to 3.75% A, C, D Spread* 3.0V CMOS 8 SOIC PhaseLink’s LAN Networking Clocks provide the most commonly required frequencies in switches, hubs, and other LAN systems, from a single reference crystal. This permits users to fulfill all timing requirements from a single crystal and IC. PhaseLink’s Multimedia Clocks, on the other hand, are designed to provide the necessary video or audio clocking requirements. Part Number Input (MHz) [Output Frequencies (MHz)] X number of outputs Output Type Operating Voltage Package PLL650-02 25 50x4, [25 or 125]x2, [25 or 100]x1, [66.6 or 75 or 83.3 or 100]x2, Spread Spectrum CMOS 3.3V 24 SSOP PLL650-03 25 50x4, [25 or 100]x1, [66.6 or 75 or 83.3 or 100]x1, Spread Spectrum CMOS 3.3V 16 SOIC PLL650-04 25 25x1, 50x1, [90 or 100 or 125 or 133 or 145 or 150] x5, Spread Spectrum CMOS 3.3V 20 SSOP PLL650-05 25 25x1, 75x1, [83.3 or 105 or 140]x1, 125x1 Spread Spectrum modulation Selectable CMOS 3.3V 16 SOIC PLL650-06 25 25x1, [66.6 or 75]x1 CMOS 3.3V 8 SOIC PLL650-07 25 50x2, 25x2 CMOS 3.3V 14 SOIC PLL650-08 25 100x1, 125x1 CMOS 3.3V 8 SOIC PLL650-09 25 50x4 CMOS 3.3V 16 SOIC PLL650-10 25 125x2 CMOS 3.3V 8 SOIC PLL601-22 27 27x2, 1x Selectable Audio: [8.192, 11.2896, 12.288, 16.9344, 18.432, 22.5792, 8, 24.576] CMOS 3.3V 16 SOIC PLL601-27 27 27x1, 1x Selectable Audio: [8.192, 11.2896, 12.288, 24.576] CMOS 3.3V 8 SOIC PLL603-27 27 27x2, 83.3x1, 12.28x1, 3.38x1, 1.53x1, 48Kx1 CMOS 3.3V 28 SSOP 12 *Note: C: Center Spread. A: Asymmetric Spread. D: Down Spread. General SST spread is at .25% increments. Please refer to the datasheet for more detail. 13 Benchmark Clock Distribution Phase Noise Comparison (622.08Mhz PECL) PhaseLink’s clock distribution products consist of Translator buffers, Zero delay buffers and Non-PLL fanout buffers. These general purpose buffer products will reproduce a master clock frequency up to 1GHz with low skew between the outputs. Our Zero Delay buffers use a Phase Locked Loop to ensure a zero-delay between the outputs and the master signal. PhaseLink makes no compromise when it comes to performance. Achieving the best phase noise performance in an affordable solution is no exception. The chart sown below is the Phase Noise comparison among PhaseLink’s products Translator Buffers Part Number Function Input/Output (MHz) Output Type Description Voltage Package PLL130-05 Translator to PECL DC to 1.0 GHz 1 PECL Single ended to PECL, OE (Low) 2.5V, 3.3V 3x3 QFN-16 PLL130-07 Translator to CMOS DC to 200 CMOS Singled ended to CMOS 2.5V, 3.3V 8 SOIC, 3x3 QFN-16 PLL130-08 Translator PLL130-09 to PECL or LVDS DC to 1.0 GHz 1 PECL (-08) 1 LVDS (-09) Single ended to PECL (-08), LVDS (-09) 2.5V, 3.3V 8 SOIC, 3x3 QFN-16 PLL130-68 Translator PLL130-69 to PECL or LVDS DC to 1.3 GHz 1 PECL (-68) 1 LVDS (-69) Single ended to PECL (-68), LVDS (-69) Selectable OE (Low/Hi) 2.5V, 3.3V 3x3 QFN-16, Die • • • • 4XAFM with high frequency mesa fundamental crystal input (560-08) SAW oscillator (570-00) PLL multiplier (4X) with high frequency mesa fundamental crystal input (520-08) PLL multiplier (32X) with low frequency crystal input (502-38) Note: All OE functions are “Logic High” Enabled unless indicated otherwise. Zero Delay Buffers Part Number Function Input/Output (MHz) Output Type Description Voltage Package PLL102-03 5 outputs 75-180 CMOS High Performance Low Skew Buffer 3.3V 8 SOIC PLL102-04 5 outputs 50-120 CMOS High Performance Low Skew Buffer 3.3V 8 SOIC PLL102-05 5 outputs 25-60 CMOS High Performance Low Skew Buffer 3.3V 8 SOIC Non-PLL Fanout Buffers Part Number Function Input/Output (MHz) Output Type Description Voltage Package PLL103-02 12 Differential outputs for DDR SDRAM 66 - 170 Diff. CMOS < 5ps delay < 100ps skew I2C interface 2.5V, 3.3V 48 SSOP PLL600-27F 5 Outputs 10-52 CMOS Low Jitter: 2.5 ps 1.8V, 2.5V, 3.3V 14 SOIC PLL600-27T 3 Outputs 10-52 CMOS Low Jitter: 2.5 ps 1.8V, 2.5V, 3.3V 8 SOIC 14 15