PL135-47 Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:4 Oscillator Fanout Buffer FEATURES DESCRIPTION Advanced Oscillator Design for Wide Frequency Coverage 4 LVCMOS Outputs with Individual OE Control 8mA Output Drive Strength Input/Output Frequency: o Fundamental Crystal: 10MHz to 40MHz Very Low Jitter and Phase Noise Low Current Consumption Single 1.62V to 3.63V Power Supply Available in QFN-16L and TSSOP-16L GREEN/RoHS Compliant Packages The PL135-47 is an advanced oscillator fanout buffer design for high performance, low-power, small formfactor applications. The PL135-47 accepts a fundamental input crystal of 10MHz to 40MHz and produces four outputs of the same frequency, each with its own Output Enable pin. Offered in a small 3 x 3mm QFN or TSSOP package, the PL135-47 offers the best phase noise and jitter performance and lowest power consumption of any comparable IC. XIN XOUT VDD 11 10 9 14 OE0 16 1 6 2 3 QFN 4 OE1 15 CLK0 VDD 8 7 GND CLK3 12 13 VDD OE3 GND PACKAGE PIN CONFIGURATION 5 CLK2 OE2 GND CLK1 XIN 1 16 XOUT GND 2 15 VDD OE3 3 14 CLK2 CLK3 4 13 OE2 VDD 5 12 GND OE0 6 11 CLK1 CLK0 7 10 OE1 VDD 8 9 GND TSSOP BLOCK DIAGRAM 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 517-1688 www.phaselink.com Rev 02/14/11 Page 1 PL135-47 Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:4 Oscillator Fanout Buffer PACKAGE PIN ASSIGNMENT Name Package Pin # Type Description QFN-16L (T)SSOP-16L CLK0 1 7 O Output clock VDD 2, 9, 15 5, 8, 15 P V DD connection GND 3, 6, 12 2, 9, 12 P GND connection OE1 4 10 I* Output enable (OE) input for CLK1. Internal pull-up. Pull low to tri-state CLK1. CLK1 5 11 O Output clock OE2 7 13 I* Output enable (OE) input for CLK2. Internal pull-up. Pull low to tri-state CLK2. CLK2 8 14 O XOUT 10 16 O XIN 11 1 I OE3 13 3 I* Output enable (OE) input for CLK3. Internal pull-up. Pull low to tri-state CLK3. CLK3 14 4 O Output clock OE0 16 6 I* Output enable (OE) input for CLK0. Internal pull-up. Pull low to tri-state CLK0. Output clock Crystal output. Do not connect when using a reference clock. Crystal input * Note: These pins include an internal 60KΩ pull up. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 517-1688 www.phaselink.com Rev 02/14/11 Page 2 PL135-47 Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:4 Oscillator Fanout Buffer LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Place decoupling capacitors as close as possible to the V DD pin(s) to limit noise from the power supply - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections (looks like ringing). - Design long traces as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bouncing back and forth. - Multiple V DD pins should be decoupled separately for best performance. - Addition of a ferrite bead in series with V DD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical value to use is 0.1F. Crystal Tuning Circuit Series and parallel capacitors used to fine tune the crystal load to the circuit load. Crystal Cst XIN XOUT 1 8 Cpt Cpt CST – Series Capacitor, used to lower circuit load to match crystal load. Raises frequency offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator. CPT – Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers frequency offset. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS V DD -0.5 4.6 V Input Voltage Range VI -0.5 V DD +0.5 V Output Voltage Range VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 C -40 85 C Supply Voltage Range Ambient Operating Temperature* Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 517-1688 www.phaselink.com Rev 02/14/11 Page 3 PL135-47 Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:4 Oscillator Fanout Buffer AC SPECIFICATIONS PARAMETERS CONDITIONS MIN. TYP. 10 MAX. UNITS 40 MHz Crystal Input Frequency Fundamental crystal Settling Time At power-up (V DD > 1.62V) 2 ms Output Enable Time OE Function; Ta=25º C 10 ns V DD Sensitivity Frequency vs. V DD , ±10% 2 ppm Output Rise Time 15pF Load, 10/90% V DD , 3.3V 2 4 ns Output Fall Time 15pF Load, 90/10% V DD , 3.3V 2 4 ns Output to Output Skew Under all conditions 1 ns Duty Cycle Under all conditions -2 45 50 55 % MIN TYP MAX UNITS DC SPECIFICATIONS PARAMETERS SYMBOL Supply Current, Dynamic I DD CONDITIONS V DD = 3.3V, 25MHz, No Load 6.5 mA V DD = 2.5V, 25MHz, No Load 4.4 mA V DD = 1.8V, 25MHz, No Load 3.2 mA Operating Voltage V DD 1.62 Output Low Voltage V OL I OL = +4mA, 3.3V Output High Voltage V OH I OH = -4mA, 3.3V Output Current I OSD V OL = 0.4V, V OH = 2.4V 3.63 V 0.4 V 2.4 V 8 mA CRYSTAL SPECIFICATIONS PARAMETERS Fundamental Crystal Resonator Frequency Crystal Loading Rating SYMBOL MIN. F XIN 10 C L (xtal) Operating Drive Level Metal Can Crystal Small SMD Crystal TYP. ESR Max Shunt Capacitance ESR Max UNITS 40 MHz 15 0.1 Shunt Capacitance MAX. pF 2 mW C0 5.5 pF ESR 40 Ω C0 2.5 pF ESR 60 Ω 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 517-1688 www.phaselink.com Rev 02/14/11 Page 4 PL135-47 Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:4 Oscillator Fanout Buffer PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) QFN 16L A e L D D1 E1 b A3 Pin1 Dot SEATING PLANE A1 A A1 A3 b D E D1 E1 L e Dimension in MM Min. Max. 0.07 0.8 0.05 0.05 0.20 0.18 0.30 3.00 BSC 3.00 BSC -1.70 -1.70 0.30 0.50 0.50 BSC E Symbol TSSOP 16L Symbol A A1 b C D E H L e Dimension in MM Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.20 6.60 0.45 0.75 0.635 BSC E H D A A1 C e B L 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 517-1688 www.phaselink.com Rev 02/14/11 Page 5 PL135-47 Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:4 Oscillator Fanout Buffer ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range Part Number/Order Number Marking PL135-47OC P135-47 OC LLLLL P135 47 LLL PL135-47OC-R PL135-47QC-R Package Option 16-Pin TSSOP (Tube) 16-Pin TSSOP (Tape and Reel) 16-Pin QFN (Tape and Reel) *Note:”LLL” or “LLLLL” designates lot number PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning t he accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 517-1688 www.phaselink.com Rev 02/14/11 Page 6