High Speed Translator Buffer to LVDS VDD REF_IN 2 7 GND GND 3 6 LVDS_BAR LVDS 4 5 VDD 13 GND 14 GND 15 OE^ 16 12 11 10 9 PLL130-09 1 2 3 4 GND GND GND 8 VDD 1 REF_IN The PLL130-09 is a low cost, high performance, high speed, buffer that reproduces any input frequency from 0 to 1.0GHz. It provides a pair of differential LVDS output. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion from sine wave, TTL, CMOS, or PECL to LVDS. GND VDD DESCRIPTION (TOP VIEW) GND Differential LVDS output Single AC coupled input (min. 100mV swing). Input range from 0 to 1.0GHz. 2.5V to 3.3V operation. Available in 8-Pin SOP or 3x3mm QFN GREEN/RoHS compliant packaging. VDD PIN CONFIGURATION GND FEATURES 8 LVDS_BAR 7 VDD 6 LVDS 5 GND Note: ^ denotes internal pull up BLOCK DIAGRAM LVDS_BAR REF_IN Input LVDS 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 6/27/08 Page 1 High Speed Translator Buffer to LVDS PIN DESCRIPTIONS Name Pin Number Type Description SOP-8L QFN-16L GND 1,3,7 1,2,4,5, 9,13,14,15 P Ground. VDD 5,8 7,10,11,12 P Power supply. REF_IN 2 3 I Reference input signal. The frequency of this signal will be reproduced at the output (after translation to LVDS level). LVDS 4 6 O LVDS True output. LVDS_BAR 6 8 O LVDS Complementary output. OE N/A 16 I Output enable (‘1’ for enable). Internal pull-up (default is ‘1’). ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage MIN. MAX. UNITS 4.6 V V DD Input Voltage, dc VI -0.5 V DD +0.5 V Output Voltage, dc VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 C Ambient Operating Temperature* TA -40 85 C Junction Temperature TJ 125 C Lead Temperature (soldering, 10s) 260 C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. 2. General Electrical Specifications PARAMETERS SYMBOL Supply Current, No Load I DD Operating Voltage V DD Output Clock Duty Cycle Short Circuit Current CONDITIONS MIN. Fout = 200MHz, LVDS TYP. MAX. UNITS 25 30 mA 3.63 V 2.25 @ 1.25V (LVDS) ±5% of input % 50 mA 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 06/27/08 Page 2 High Speed Translator Buffer to LVDS 3. AC Specifications PARAMETERS CONDITIONS MIN. Input Frequency TYP. 0 Input signal swing REF_IN input MAX. UNITS 1000 MHz 100 Output Frequency mV 0 1000 MHz 4. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change MIN. TYP. MAX. UNITS V OD 247 355 454 mV V OD -50 50 mV 1.6 V Output High Voltage V OH Output Low Voltage V OL Offset Voltage CONDITIONS 1.4 R L = 100 (see figure) 0.9 1.1 V OS 1.125 1.2 1.375 V Offset Magnitude Change V OS 0 3 25 mV Power-off Leakage I OXD 1 10 uA Output Short Circuit Current I OSD -5.7 -8 mA V out = V DD or GND, V DD = 0V V 5. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit OUT 50? VOD LVDS Transistion Time Waveform VOS OUT 50? 0V (Differential) OUT OUT LVDS Switching Test Circuit OUT 80% VDIFF CL = 10pF 80% 0V 20% VDIFF 20% RL = 100? tR tF CL = 10pF OUT 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 06/27/08 Page 3 High Speed Translator Buffer to LVDS PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) 8 PIN SOP ( dimensions in mm ) SOP-8L Symbol Min. Max. A 1.47 1.73 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 4.95 E 3.80 4.00 H 5.80 6.20 L 0.38 e 1.27 1.27 BSC E H D A A 1 C L B e QFN-16L 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 06/27/08 Page 4 High Speed Translator Buffer to LVDS ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL130-09 X C PART NUMBER TEMPERATURE C=COMMERCIAL (0°C to 70°C) I=INDUSTRAL (-40°C to 85°C) PACKAGE TYPE Q=QFN-16L S=SOP-8L Part/Order Number Marking PLL130-09SC P130 09 P130-09 PLL130-09SC-R P130-09 PLL130-09QC-R Package Option 16-pin QFN-16L - (Tape and Reel) 8-pin SOP-8L - (Tube) 8-pin SOP-8L - (Tape and Reel) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 06/27/08 Page 5