PL133-27 Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC FEATURES DESCRIPTION 2 LVCMOS Outputs Input/Output Frequency: 1MHz to 150MHz Supports LVCMOS or Sine Wave Input Clock Extremely low additive Jitter 8 mA Output Drive Strength Low Current Consumption Single 1.8V, 2.5V, or 3.3V, ±10% Power Supply Operating Temperature Range o 0°C to 70°C (Commercial) o -40C to 85C (Industrial) Available in DFN-6L GREEN/RoHS Compliant Packages The PL133-27 is an advanced fanout buffer design for high performance, low-power, small form-factor applications. The PL133-27 accepts a reference clock input of 1MHz to 150MHz and produces two outputs of the same frequency. Reference clock inputs may be LVCMOS or sine-wave signals (the inputs are internally AC-coupled). PL133-27 is designed to fit in a small 2 x 1.3 x 0.6mm DFN package, and offers the best phase noise and jitter performance and lowest power consumption of any comparable IC. PACKAGE PIN CONFIGURATION BLOCK DIAGRAM 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 04/18/11 Page 1 PL133-27 Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC PACKAGE PIN ASSIGNMENT Name Package Pin # DFN-6L Type Description FIN 1 I Reference clock input CLK1 2 O Clock output GND 3 P GND connection CLK0 4 O Clock output VDD 5 P V DD connection OE 6 I Output enable input LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Place decoupling capacitors as close as possible to the V DD pin(s) to limit noise from the power supply - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections (looks like ringing). - Design long traces as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bouncing back and forth. - Multiple V DD pins should be decoupled separately for best performance. - Addition of a ferrite bead in series with V DD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1F for designs using crystals < 50MHz and 0.01F for designs using crystals > 50MHz. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 04/18/11 Page 2 PL133-27 Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS V DD -0.5 4.6 V Input Voltage Range VI -0.5 V DD +0.5 V Output Voltage Range VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 C -40 85 C Supply Voltage Range Ambient Operating Temperature* Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC SPECIFICATIONS PARAMETERS CONDITIONS Input (FIN) Frequency MIN. TYP. MAX. UNITS 1MHz 150 MHz 0.9 V DD V PP Input (FIN) Signal Amplitude Internally AC coupled Output Rise Time 15pF Load, 10/90%V DD , 3.3V 2 3 ns Output Fall Time 15pF Load, 90/10%V DD , 3.3V 2 3 ns 500 ps Output to Output Skew Duty Cycle Input Duty Cycle is 50% 45 50 55 % MIN TYP MAX UNITS DC SPECIFICATIONS PARAMETERS Supply Current, Dynamic SYMBOL I DD CONDITIONS V DD = 3.3V, 25MHz, No Load 1.8 mA V DD = 2.5V, 25MHz, No Load 1.3 mA V DD = 1.8V, 25MHz, No Load 0.8 mA Operating Voltage V DD 1.62 Output Low Voltage V OL I OL = +4mA, V DD = 3.3V Output High Voltage V OH Output Current I OSD I OH = -4mA, V DD = 3.3V V OL = 0.4V, V OH = 2.4V, V DD = 3.3V 3.63 V 0.4 V 2.4 V 8 mA 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 04/18/11 Page 3 PL133-27 Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC NOISE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS Additive Phase Jitter MIN TYP MAX UNIT V DD=3.3V, Frequency=26MHz Offset=12KHz ~ 5MHz 130 fs V DD=3.3V, Frequency=100MHz Offset=12KHz ~ 20MHz 150 fs PL133-27 Additive Phase Jitter: VDD=3.3V, CLK=26MHz, Integration Range 12KHz to 5MHz: 0.127ps typical. REF Input PL133-27 Output -70 -80 -90 Phase Noise (dBc/Hz) -100 -110 -120 -130 -140 -150 -160 -170 10 100 1000 10000 100000 1000000 10000000 Offset Frequency (Hz) When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive Phase Jitter is as follows: 2 Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter) 2 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 04/18/11 Page 4 PL133-27 Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) DFN-6L D1 Symbol A A1 A3 b e D E D1 E1 L Dimension in MM Min. Max. 0.45 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30 b e D Pin 6 ID Chamfer E E1 L Pin1 Dot A A1 A3 ORDERING INFORMATION (GREEN PACKAGE) For part ordering, please contact our Sales Department: 2880 Zanker Rd., San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range Part/Order Number PL133-27GC-R Marking H27 LLL Package Option 6-Pin DFN (Tape and Reel) *Note: LLL designates lot number PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without t he express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 04/18/11 Page 5