PL133-37 Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC FEATURES DESCRIPTION The PL133-37 is an advanced fanout buffer design for high performance, low-power, small form-factor applications. The PL133-37 accepts a reference clock input of 1MHz to 150MHz and produces three outputs of the same frequency. Reference clock inputs may be LVCMOS or sine-wave signals (the inputs are internally AC-coupled). Offered in a small 3 x 3mm SOT23, the PL133-37 offers the best phase noise and jitter performance and lowest power consumption of any comparable IC. 3 LVCMOS Outputs 12 mA Output Drive Strength Input/Output Frequency: o Reference Clock: 1MHz to 150MHz Supports LVCMOS or Sine Wave Input Clock Very Low Jitter and Phase Noise Low Current Consumption Single 1.8V, 2.5V, or 3.3V, ±10% Power Supply Operating Temperature Range o 0°C to 70°C (Commercial) o -40 C to 85 C (Industrial) Available in SOT23-6L GREEN/RoHS Compliant Packages PACKAGE PIN CONFIGURATION CLK1 1 6 CLK2 GND 2 5 VDD FIN 3 4 CLK0 SOT23-6L BLOCK DIAGRAM CLK0 CLK1 FIN CLK2 2880 Zanker Rd., San Jose, California 95134 Tel (408) 517-1668 Fax (408) 517-1688 www.phaselink.com Rev 03/18/11 Page 1 PL133-37 Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC PIN DESCRIPTION Name Package Pin # SOT23-6L Type Description CLK1 1 O Output clock GND 2 P Ground connection FIN 3 I Reference clock input CLK0 4 O Output clock VDD 5 P Power supply CLK2 6 O Output clock LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Place decoupling capacitors as close as possible to the V DD pin(s) to limit noise from the power supply - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections (looks like ringing). - Design long traces as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bouncing back and forth. - Multiple V DD pins should be decoupled separately for best performance. - Addition of a ferrite bead in series with V DD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical value to use is 0.1 F. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer (Typical buffer impedance 20Ω) To CMOS Input 50Ω line Series Resistor Use value to match output buffer impedance to 50Ω trace. Typical value 30Ω 2880 Zanker Rd., San Jose, California 95134 Tel (408) 517-1668 Fax (408) 517-1688 www.phaselink.com Rev 03/18/11 Page 2 PL133-37 Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS V DD -0.5 4.6 V Input Voltage Range VI -0.5 V DD +0.5 V Output Voltage Range VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 C -40 85 C Supply Voltage Range Ambient Operating Temperature* Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permane nt damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specif ication is not implied. *Operating temperature is guaranteed by design. Parts are tested to commerci al grade only. AC SPECIFICATIONS PARAMETERS Input (FIN) Frequency CONDITIONS MIN. TYP. MAX. UNITS 2.5V and 3.3V operation 1 150 MHz 1.8V operation 1 100 MHz 0.9 V DD V PP 10 ns Input (FIN) Signal Amplitude Internally AC coupled Output Enable Time OE Function; Ta=25º C, 15pF Load Output Rise Time 15pF Load, 10/90%V DD , 3.3V 2 3 ns Output Fall Time 15pF Load, 90/10%V DD , 3.3V 2 3 ns Duty Cycle Input Duty Cycle is 50% 50 55 % Output to Output Skew All outputs equally loaded 250 ps MAX UNITS 45 DC SPECIFICATIONS PARAMETERS Supply Current, Dynamic Supply Current, Standby SYMBOL I DD I DD_SB CONDITIONS TYP V DD = 3.3V, 25MHz, No Load 1.2 mA V DD = 2.5V, 25MHz, No Load 0.9 mA V DD = 1.8V, 25MHz, No Load 0.6 mA OE Pin Pulled Low, V DD = 3.3V 0.3 mA Operating Voltage V DD Output Low Voltage V OL I OL = +12mA, V DD = 3.3V Output High Voltage V OH Output Current I OSD I OH = -12mA, V DD = 3.3V V OL = 0.4V, V OH = 2.4V, V DD = 3.3V 2880 Zanker Rd., San Jose, California 95134 MIN 1.62 Tel (408) 517-1668 Fax (408) 517-1688 3.63 V 0.4 V 2.4 V 12 mA www.phaselink.com Rev 03/18/11 Page 3 PL133-37 Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC NOISE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS Additive Phase Jitter MIN TYP MAX UNIT V DD=3.3V, Frequency=26MHz Offset=12KHz ~ 5MHz 70 fs V DD=3.3V, Frequency=100MHz Offset=12KHz ~ 20MHz 80 fs PL133-37 Additive Phase Jitter: VDD=3.3V, CLK=26MHz, Integration Range 12KHz to 5MHz: 0.072ps typical. REF Input PL133-37 Output -70 -80 -90 Phase Noise (dBc/Hz) -100 -110 -120 -130 -140 -150 -160 -170 10 100 1000 10000 100000 1000000 10000000 Offset Frequency (Hz) When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive Phase Jitter is as follows: 2 Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter) 2880 Zanker Rd., San Jose, California 95134 Tel (408) 517-1668 Fax (408) 517-1688 2 www.phaselink.com Rev 03/18/11 Page 4 PL133-37 Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) SOT23-6L Symbol A A1 A2 b c D E H L e Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.00 0.35 0.55 0.95 BSC Pin1 Dot E H D A2 A A1 C e b L ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department : 2880 Zanker Rd., San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 517-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL133-37 X X - X Part Number None=Tubes R=Tape and Reel Package Type T = SOT23-6L Temperature Range C=Commercial (0°C to 70°C) Part/Order Number Marking H37 LLL PL133-37TC-R Package Option 6-Pin SOT23 (Tape and Reel) *Note: LLL designates lot number PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fu rnished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever n ature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the e xpress written approval of the President of PhaseLin k Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 2880 Zanker Rd., San Jose, California 95134 Tel (408) 517-1668 Fax (408) 517-1688 www.phaselink.com Rev 03/18/11 Page 5