PL611-31 - Phaselink.com

PL611-31
Programmable Quick Turn Clock T M
FEATURES
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PIN CONFIGURATION
Advanced programmable PLL design
Very low Jitter and Phase Noise (< 40ps Pk-Pk typical)
Up to 3 outputs
Output frequency up to 200MHz CMOS.
o Provides complementary LVCMOS outputs to
drive LVCMOS, LVPECL or LVDS inputs.
Input frequencies:
o Fundamental crystal: 10MHz - 30MHz
o Reference Clock: 1MHz - 200MHz
Accepts <1.0V reference signal input voltage
One programmable I/O pin can be configured as
Output Enable (OE) input, Frequency Selection
(FSEL) input or Reference clock output.
Single 2.5V ~ 3.3V ± 10% power supply
Operating temperature range from -40C to 85C
Available in 8-pin MSOP/SOP GREEN/RoHS
compliant packages.
DESCRIPTION
The PL611-31 is a low-cost general purpose frequency synthesizer and a member of PhaseLink’s Factory
Programmable ‘Quick Turn Clock (QTC)’ family. PhaseLink’s PL611-31 product family can generate any output
frequency up to 200 MHz from a fundamental crystal input of 10MHz to 30MHz. In addition, the complementary
LVCMOS outputs can be used to drive differential LVPECL or LVDS inputs at 2.5V or 3.3V
BLOCK DIAGRAM
2880 Zanker Rd., San Jose, California 95134
Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 2/14/11 Page 1
PL611-31
Programmable Quick Turn Clock T M
KEY PROGRAMMING PARAMETERS
CLK[ 0:2 ]
Output Frequency
FOUT= FIN * M / (R * P)
where M=10 bit
R = 8 bit
P = 5 bit
1. CLK[0:1] = VCO / 2 * P
2. CLK0 = ~ CLK1
3. CLK[2]= FIN
Output Drive
Strength
Programmable
Input/Output (pin #7)
Crystal Load
Std: 10mA
(default)
+/- 200ppm tuning
High: 24mA
# of Register
Banks
One output pin can be
configured as
1. CLK2 - output
2. FSEL - input
3. OE - input
2
PIN DESCRIPTION
Name
Pin #
(M)SOP-8L
Type
Description
XIN, FIN
1
I
Crystal or Reference input pin
GND
2
P
GND connection
CLK[0:1]
3,4
O
Programmable Clock Output [note:CLK0=CLK1]
VDD
5
P
VDD connection (2.25~3.63V)
DNC
6
-
Do No Connect
This programmable I/O pin can be configured as Output
Enable (OE) input, Frequency Selection (FSEL) input or
CLK2 (F IN or F IN /2) output. This pin has an internal 60KΩ
pull up resistor.
OE, FSEL, CLK2
7
B
State
0
1 (default)
XOUT
8
2880 Zanker Rd., San Jose, California 95134
O
OE
Tristate
CLK[0:1]
Normal
mode
FSEL
Bank 0
Bank 1
Crystal output pin
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Rev 2/14/11 Page 2
PL611-31
Programmable Quick Turn Clock T M
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
V DD
-0.5
4.6
V
Input Voltage Range
VI
-0.5
V DD +0.5
V
Output Voltage Range
VO
-0.5
V DD +0.5
V
Supply Voltage Range
Data Retention @ 85º C
10
Years
Soldering Temperature (Green Package)
Storage Temperature
TS
Ambient Operating Temperature*
260
C
-65
150
C
-40
+85
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency
CONDITIONS
MIN.
Fundamental Crystal
TYP.
10
Input (F IN ) Frequency
Input (F IN ) Signal Amplitude
Internally AC coupled
Settling Time
At power-up (V DD < 1.62V)
VDD Sensitivity
Frequency vs. V DD +/-10%
Output Rise Time
Output Fall Time
0.9
-2
MAX.
UNITS
30
MHz
200
MHz
V DD
Vpp
10
ms
2
ppm
15pF Load, 10/90%V DD , Standard drive
2.5
3.5
ns
15pF Load, 10/90%V DD , High drive
1.0
1.5
ns
15pF Load, 90/10%V DD , Standard drive
2.5
3.5
ns
15pF Load, 90/10%V DD , High drive
1.0
1.5
ns
50
55
%
200
ps
Duty Cycle
At V DD /2
45
Max. output skew between
same frequency clocks
Equal loading (15 pF). Equal frequency &
drive strength
Period Jitter, peak-to-peak*
(10,000 samples measured)
With capacitive decoupling between V DD and
GND. CLK0 & CLK1 active
40
ps
* Note: Jitter performance depends on the programming parameters.
2880 Zanker Rd., San Jose, California 95134
Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 2/14/11 Page 3
PL611-31
Programmable Quick Turn Clock T M
DC SPECIFICATIONS
PARAMETERS
SYMBOL
Supply Current, Dynamic,
with Loaded Outputs
I DD
Operating Voltage
V DD
Output Low Voltage
V OL
I OL = +4mA (Standard Drive)
Output High Voltage
V OH
I OH = -4mA (Standard Drive)
I OSD
V OL = 0.4V, V OH = 2.4V (Std Drive)
10
mA
I OHD
V OL = 0.4V, V OH = 2.4V (High Drive)
24
mA
±50
mA
Output Current
Short-Circuit Current
CONDITIONS
MIN.
TYP.
MAX.
UNITS
15
mA
3.63
V
0.4
V
At 10MHz, load=15pF
2.25
V DD – 0.4
IS
V
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
(The IC can be programmed for any value in this range.)
SYMBOL
MIN.
F XIN
C L (xtal)
TYP.
MAX.
UNITS
10
30
MHz
5
20
pF
500
W
Maximum Sustainable Drive Level
Operating Drive Level
100
W
Crystal Shunt Capacitance
C0
6
pF
Effective Series Resistance, Fundamental,
10-30MHz
RS
30
Ω
Effective Series Resistance, 3 rd Overtone,
30-50MHz [CO< 4pF, C L =5pF/8pF]
ESR
100/70
Ω
Effective Series Resistance, 3 rd Overtone,
50-65MHz, [CO< 4pF, C L =5pF/8pF]
ESR
60/40
Ω
Effective Series Resistance, 3 rd Overtone,
65-75MHz [CO< 4pF, C L =5pF/8pF
ESR
45/30
Ω
2880 Zanker Rd., San Jose, California 95134
Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 2/14/11 Page 4
PL611-31
Programmable Quick Turn Clock T M
TERMINATING COMPLEMENTARY LVCMOS OUTPUTS
Figure 1 below describes how to terminate the complementary LVCMOS outputs of PhaseLink’s PL611-31
Programmable QTC clock for use with LVPECL or LVDS inputs.
The unique feature of complementary LVCMOS outputs allows great flexibility for board designers. By
standardizing on one termination scheme you can use the PL611-31 for all your LVDS and LVPECL clock
requirements up to 200MHz.
+3.3V
LVCMOS Output
R1
50 ohm line
R2
Input
R3
Complementary
LVCMOS Output
R1
50 ohm line
3.3V
0V
R3
R2
+3.3V
Complementary
Input
LVPECL LVDS
2.35V 1.40V
1.59V 1.10V
Component selection
For LVPECL input For LVDS input
Notes:
Place R1 as close to the LVCMOS outputs as
possible.
R1 = 130 ohm
R2 = 82 ohm
R3 = 130 ohm
Place R2 and R3 as close to the LVPECL/
LVDS inputs as possible.
R1 = 360 ohm
R2 = 130 ohm
R3 = 82 ohm
Figure 1
The above layout allows the PL611-31 to drive either an LVPECL or LVDS input pair by simply changing the value
of R1.
2880 Zanker Rd., San Jose, California 95134
Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 2/14/11 Page 5
PL611-31
Programmable Quick Turn Clock T M
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
MSOP-8L
Symbol
A
A1
A2
B
C
D
E
H
L
e
Dimension in MM
Min.
Max.
--1.10
0.05
0.15
0.81
0.91
0.25
0.40
0.13
0.23
2.90
3.10
2.90
3.10
4.90 BSC
0.445
0.648
0.65 BSC
E
H
D
A2 A
A1
C
e
L
b
SOP-8L
Symbol
A
A1
A2
B
C
D
E
H
L
e
Dimension in MM
Min.
Max.
1.35
1.75
0.10
0.25
1.25
1.50
0.33
0.53
0.19
0.27
4.80
5.00
3.80
4.00
5.80
6.20
0.40
0.89
1.27 BSC
2880 Zanker Rd., San Jose, California 95134
E
H
D
A2 A
A1
C
e
b
Tel (408) 571-1668 Fax (408) 571-1688
L
www.phaselink.com
Rev 2/14/11 Page 6
PL611-31
Programmable Quick Turn Clock T M
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
2880 Zanker Road, San Jose, CA 95134, USA
Tel: (408) 571-1668 Fax: (408) 571-1688
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PL611-31-XXX
X X-R
PART NUMBER
3 DIGIT ID Code *
NONE= TUBE
R=TAPE and REEL
PACKAGE TYPE
M=MSOP-8L
S=SOP-8L
TEMPERATURE
C=COMMERCIAL
I = INDUSTRIAL
* PhaseLink will assign a unique 3-digit ID code for each approved programmed part number.
Part / Order Number
Marking
Package Option
PL611-31-XXXMC
C4XXX
8-Pin MSOP (Tube)
PL611-31-XXXMC-R
C4XXX
8-Pin MSOP (Tape and Reel)
PL611-31-XXXSC
P611-31
XXX
8-Pin SOP (Tube)
PL611-31-XXXSC-R
P611-31
XXX
8-Pin SOP (Tape and Reel)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
2880 Zanker Rd., San Jose, California 95134
Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 2/14/11 Page 7